Method for manufacturing a semiconductor element

Abstract

The present invention discloses a method for fabricating a semiconductor device. First, a gate structure is formed on a substrate. Then, a source / drain region is formed adjacent to the gate structure. A first cleaning process is performed. A first rapid thermal annealing process is performed to remove oxygen atomizations within the substrate. A metal layer is formed on the source / drain region. Finally, a second rapid thermal annealing process is performed to convert the metal layer into a metal silicide.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for improving the high resistance of a radio frequency silicon-on-insulator (RFSOI) device by using a rapid thermal annealing process before forming a metal silicide. Background Art

[0002] In the existing semiconductor industry, polysilicon is widely used in semiconductor devices such as metal-oxide-semiconductor (MOS) transistors as the standard gate fill material of choice. However, as MOS transistors continue to shrink in size, traditional polysilicon gates suffer from problems such as boron penetration, which reduces device performance, and the inevitable depletion effect. This increases the equivalent gate dielectric thickness, reduces gate capacitance, and ultimately leads to a decline in device driving capability. Therefore, the semiconductor industry is experimenting with new gate fill materials, such as using work function metals to replace traditional polysilicon gates as control electrodes that match high-k gate dielectric layers.

[0003] However, in current metal gate transistor fabrication, even when two transistor elements, such as NMOS and / or PMOS elements, are located in adjacent regions, device mismatch can still occur, impacting device performance. Therefore, improving current fabrication processes to address this issue is a critical issue. Summary of the Invention

[0004] The present invention discloses a method for fabricating a semiconductor device. First, a gate structure is formed on a substrate. Then, a source / drain region is formed adjacent to the gate structure. A first cleaning process is performed. A first rapid thermal annealing process is performed to remove oxygen ions within the substrate. A metal layer is formed on the source / drain region. Finally, a second rapid thermal annealing process is performed to convert the metal layer into a metal silicide. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figures 1 to 5 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0006] Description of main component symbols

[0007] 12: Base

[0008] 14: Base

[0009] 16: Trap (capture) layer

[0010] 18: Insulation layer

[0011] 20: Base

[0012] 22: Gate structure

[0013] 24: Gate dielectric layer

[0014] 26: Gate material layer

[0015] 28: Hard mask

[0016] 30: gap wall

[0017] 32: Source / drain region

[0018] 34: offset spacer

[0019] 36: Main side wall

[0020] 38: First rapid thermal annealing process

[0021] 40: Second rapid thermal annealing process

[0022] 42: Metal silicide

[0023] 44: Contact hole etching stop layer

[0024] 46: interlayer dielectric layer

[0025] 48: dielectric layer

[0026] 50: High dielectric constant dielectric layer

[0027] 52: Work function metal layer

[0028] 54: Barrier layer

[0029] 56: Low impedance metal layer

[0030] 58:Metal gate

[0031] 60: Contact plug DETAILED DESCRIPTION

[0032] Please refer to Figures 1 to 5 , Figures 1 to 5 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 1As shown, a substrate 12 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, on which a transistor region, such as a PMOS transistor region or an NMOS transistor region, may be defined. In this embodiment, substrate 12 preferably comprises a SOI substrate, which may include, in detail, a lower substrate 14 formed from a silicon handle wafer, a trap rich layer 16, an insulating layer 18, and an upper substrate 20 also formed from silicon. The trap rich layer 16 preferably comprises polysilicon, and the insulating layer 18 preferably comprises silicon oxide. In this embodiment, the lower substrate 14 is preferably approximately 775 microns thick, the trap rich layer 16 is approximately 1.8 microns thick, the insulating layer 18 is approximately 2000 angstroms thick, and the upper substrate 20 is approximately 550 angstroms thick.

[0033] Then, at least one gate structure 22 or dummy gate may be formed on the substrate 12. In this embodiment, the gate structure 22 may be fabricated using a gate-first process, a gate-last process (a high-k first process), or a gate-last process (a high-k last process) according to fabrication process requirements. Taking the high-k dielectric layer fabrication process of the present embodiment as an example, a gate dielectric layer 24 or dielectric layer, a gate material layer 26 composed of polysilicon, and an optional hard mask 28 can be sequentially formed on the substrate 12. A pattern transfer process is then performed using a patterned photoresist (not shown) as a mask. A portion of the hard mask 28, a portion of the gate material layer 26, and a portion of the gate dielectric layer 24 are removed by a single etching or successive etching steps. The patterned photoresist is then stripped to form a gate structure 22 composed of the patterned gate dielectric layer 24, the patterned gate material layer 26, and the patterned hard mask 28 on the substrate 12.

[0034] Then, at least one spacer 30 is formed on the sidewall of the gate structure 22, and a source / drain region 32 and / or an epitaxial layer (not shown) is formed in the substrate 12 on both sides of the spacer 30. In this embodiment, the spacer 30 can be a single spacer or a composite spacer, for example, it can include an offset spacer 34 and a main spacer 36 in detail. The offset spacer 34 and the main spacer 36 can include the same or different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide nitride. The source / drain region 32 can include different dopants depending on the conductivity type of the transistor to be prepared, for example, it can include P-type dopants or N-type dopants. A first cleaning process is then performed, for example, using diluted hydrofluoric acid (dHF) to remove residues on the surface of the substrate 12. In this embodiment, the time of the first cleaning process is preferably less than 10 seconds or more preferably about 5 seconds.

[0035] Then as Figure 2 As shown, a first rapid thermal annealing process 38 is performed to remove oxygen clusters within the substrate 12 and thereby improve the overall device resistance. Generally, prior to forming a subsequent metal silicide, or more specifically, prior to depositing a metal layer for forming the metal silicide, low-temperature treatments performed at various stages of the manufacturing process, such as at temperatures between 350°C and approximately 500°C, may generate oxygen clusters formed by the accumulation of oxygen in the trap layer 16. This accumulation of oxygen clusters ultimately increases the overall device resistance and affects device performance. Therefore, the present invention preferably performs a first rapid thermal annealing process 38 after forming the source / drain regions 32 and before forming the metal silicide to prevent excessive oxygen clusters from accumulating in the trap layer 16 and causing an increase in resistance. In this embodiment, the temperature of the first rapid thermal annealing process 38 is preferably between 560°C and 700°C.

[0036] It should be noted that, before the first rapid thermal annealing process 38, the present invention may perform one or more additional rapid thermal annealing processes before or after the formation of the source / drain regions 32 and / or the lightly doped drain (not shown) to activate dopants to form the lightly doped drain and / or the source / drain regions 32. For example, the present invention may first utilize an ion implantation process to implant dopants into the substrate 12 on both sides of the gate structure 22 before forming the spacers 30, and perform a rapid thermal annealing process to form the lightly doped drain. Then, after forming the spacers 30, another ion implantation process may be performed to implant dopants into the substrate 12 on both sides of the spacers 30, and perform another rapid thermal annealing process to form the source / drain regions 32. Only then is the first rapid thermal annealing process performed to remove oxygen groups in the substrate 12.

[0037] In other words, the present invention may perform at least two more rapid thermal annealing processes before the first rapid thermal annealing process 38 to respectively form the lightly doped drain and / or source / drain regions 32. In this embodiment, the temperature of the two rapid thermal annealing processes respectively used to form the lightly doped drain and / or source / drain regions 32 is preferably higher than the temperature of the first rapid thermal annealing process 38, such as but not limited to 900 degrees Celsius to 1100 degrees Celsius.

[0038] like Figure 3 As shown, a second cleaning process is then performed to further remove, or more specifically, completely remove, residues or impurities on the surface of the substrate 12. In this embodiment, the etching component used in the second cleaning process preferably includes ammonia and / or carbon trifluoride. A metal layer (not shown) is then sputtered or deposited on the substrate 12 and the gate structure, wherein the metal layer preferably includes a nickel-platinum alloy, but may also include cobalt, titanium, nickel, platinum, palladium, molybdenum, or an alloy thereof. A second rapid thermal annealing process 40 is then performed to react the metal layer with the substrate 12 to form a metal silicide 42, and then the unreacted metal layer is removed.

[0039] Then as Figure 4 As shown, a contact etch stop layer 44 is first formed on the surface of the substrate 12 and the gate structure 22, and an interlayer dielectric layer 46 is then formed on the contact etch stop layer 44. A planarization process is then performed, such as chemical mechanical polishing (CMP), to remove portions of the interlayer dielectric layer 46 and the contact etch stop layer 44 so that the upper surface of the hard mask 28 is flush with the upper surface of the interlayer dielectric layer 36.

[0040] like Figure 5As shown, a metal gate replacement process is then performed to convert the gate structure 22 into a metal gate. For example, a selective dry etching or wet etching process can be performed first, such as using an etching solution such as ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the hard mask 28, gate material layer 26, and even the gate dielectric layer 24 in the gate structure 22 to form a recess (not shown) in the interlayer dielectric layer 46. Thereafter, a selective dielectric layer 48 or gate dielectric layer, a high-k dielectric layer 50, a work function metal layer 52, a barrier layer 54, and a low-resistance metal layer 56 are sequentially formed in the recess. A planarization process is then performed, such as using CMP to remove a portion of the low-resistance metal layer 56, a portion of the barrier layer 54, a portion of the work function metal layer 52, and a portion of the high-k dielectric layer 50 to form the gate structure 22 consisting of the metal gate 58. Taking the metal gate fabricated using the post-high-k dielectric layer fabrication process in this embodiment as an example, the gate structure 22 or metal gate 58 preferably includes a dielectric layer 48 or a gate dielectric layer, a U-shaped high-k dielectric layer 50, a U-shaped work function metal layer 52, a U-shaped barrier layer 54, and a low-resistance metal layer 56.

[0041] In the present embodiment, the high-k dielectric layer 50 includes a dielectric material having a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalum oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalum oxide (SrTiO3), and strontium bismuth tantalum oxide (SrTiO3). tantalate,SrBi2Ta2O9,SBT), lead zirconate titanate (leadzirconate titanate,PbZr x Ti 1-xO3, PZT), barium strontium titanate (barium strontium titanate, Ba x Sr 1- x TiO3, BST), or a combination thereof.

[0042] The work function metal layer 52 is preferably used to adjust the work function of the metal gate, making it suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 52 may be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as, but not limited to, titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide). If the transistor is a P-type transistor, the work function metal layer 52 may be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC). The barrier layer 54 may include, but is not limited to, materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The low-resistance metal layer 56 can be selected from low-resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or a combination thereof.

[0043] A pattern transfer process may then be performed. For example, a patterned mask may be used to remove portions of the interlayer dielectric layer 46 and the contact etch stop layer 44 adjacent to the metal gate 58 to form a plurality of contact holes (not shown) and expose the underlying metal silicide 42. Each contact hole is then filled with a desired metal material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and a low-resistance metal layer selected from a low-resistance material such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or a combination thereof. A planarization process may then be performed, such as chemical mechanical polishing (CMP) to remove portions of the metal material to form contact plugs 60 within each contact hole, electrically connecting to the source / drain regions 32.

[0044] In summary, prior to forming metal silicide, or more specifically, prior to depositing the metal layer used to form the metal silicide, low-temperature treatments performed at various manufacturing stages in conventional wireless RF devices, such as those performed at temperatures between 350°C and approximately 500°C, may generate oxygen clusters or oxygen clumps. This accumulation of oxygen clusters ultimately increases the overall device resistance, thereby impacting device performance. Therefore, the present invention preferably performs a rapid thermal annealing process, preferably between 560°C and 700°C, after forming the source / drain regions and before forming the metal silicide to prevent excessive oxygen cluster accumulation in the trap layer, which could result in increased resistance.

[0045] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: Include: forming a gate structure on a substrate, wherein the substrate comprises a trap layer; forming source / drain regions adjacent to the gate structure; Performing a first cleaning process; performing a first rapid thermal annealing process to remove oxygen clusters in the trap layer of the substrate; forming a metal layer on the source / drain region; as well as converting the metal layer into metal silicide, The first rapid thermal annealing process is performed after the source / drain region is formed and before the metal silicide is formed. The first rapid thermal annealing process is performed at a temperature between 560 degrees Celsius and 700 degrees Celsius.

2. The method of claim 1, wherein the first cleaning process comprises dilute hydrofluoric acid. The method according to claim 1 , wherein the first cleaning process takes less than 10 seconds. 4 . The method according to claim 1 , further comprising performing a second cleaning process after performing the first rapid thermal annealing process.

5. The method of claim 4, wherein the second cleaning process comprises ammonia and carbon trifluoride. 6 . The method according to claim 1 , further comprising performing a second rapid thermal annealing process after forming the metal layer to convert the metal layer into the metal silicide. The method of claim 1 , wherein the metal layer comprises a nickel-platinum alloy.

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