Ceramic thin film substrate for high-reliability thin film hybrid integrated circuit and manufacturing method

Abstract

The present invention relates to a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit and a manufacturing method thereof, comprising sequentially forming a thin film resistor layer, a barrier layer and a thin gold seed crystal layer on the substrate; forming a gold conductive band on the thin gold seed crystal layer; removing the thin gold seed crystal layer; forming a nickel layer in the area to be nickel-plated; covering the pad gold layer on the nickel layer in the pad area; forming a thin film resistor network; and forming a nickel passivation layer. In the present invention, magnetron sputtering, photolithography technology, microelectronic electroplating process, degumming, corrosion technology and heat treatment process technology are used on an alumina ceramic substrate to form a gold conductive band and a nickel-chromium-silicon thin film resistor network respectively, and a nickel-gold burning solder pad and a solder resist layer are superimposed on the gold conductive band. The manufactured thin film substrate has a thick gold layer thickness, high line width accuracy and steep step morphology, which can meet the application requirements of high precision, high frequency and high reliability; the substrate structure is compatible with standard micro-assembly process and can be widely used in the field of thin film hybrid integrated circuits.

Description

Technical Field

[0001] The invention belongs to the technical field of high-reliability thin-film hybrid integrated circuits, and relates to a ceramic thin-film substrate for a high-reliability thin-film hybrid integrated circuit and a manufacturing method thereof. Background Art

[0002] The substrate is the core component of electronic devices. It plays a key role in mechanical support, heat dissipation and electrical conduction. The MCM-D process technology based on thin film technology has the highest assembly density and performance among all forms of MCM components. At the same time, it is also a key basic process technology involved in advanced packaging technology. As electronic products develop towards high density, high speed, high precision, miniaturization and system integration, RF microwave thin film substrates are required to meet the technical requirements of thick gold layer thickness, high line width accuracy, steep step morphology, and process processing requirements compatible with standard micro-assembly technology, which requires the existing RF microwave thin film substrate processing technology to be improved. Summary of the invention

[0003] In view of this, an object of the present invention is to provide a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit and a manufacturing method thereof.

[0004] In order to achieve the above object, the present invention provides the following technical solutions:

[0005] A method for manufacturing a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit comprises the following steps:

[0006] Taking a substrate and cleaning the substrate;

[0007] forming a thin film resistor layer, a barrier layer and a thin gold seed crystal layer in sequence on a substrate;

[0008] forming a gold conduction band on the thin gold seed layer;

[0009] removing the thin gold seed layer exposed on the substrate surface to expose the barrier layer;

[0010] Forming a nickel layer covering the upper end surface of the gold conductive strip and wrapping the side wall of the gold conductive strip in the area to be nickel plated;

[0011] Covering the pad gold layer on the nickel layer in the pad area to form a nickel-thin gold pad; the pad gold layer has a size smaller than the gold conductive strip thereunder;

[0012] removing the barrier layer from the exposed portion of the thin film resistor layer;

[0013] Removing the thin film resistor layer of the exposed portion on the substrate to expose the substrate and form a thin film resistor network;

[0014] The substrate is heat treated to form a nickel passivation layer on the exposed portion of the nickel layer.

[0015] Furthermore, the substrate is an alumina ceramic sheet, and cleaning the substrate comprises the following steps:

[0016] A mixed solution of NH4OH, H2O2 and H2O is used as the first cleaning solution; the substrate is placed in the first cleaning solution and boiled for 5 minutes;

[0017] Take a mixed solution of KCL, H2O2 and H2O as the second cleaning solution; put the substrate into the second cleaning solution and boil for 5 minutes;

[0018] The substrate was rinsed with deionized water, dried, and baked at 150° C. for 1 hour.

[0019] Further, sequentially forming a thin film resistor layer, a barrier layer and a thin gold seed layer on the substrate specifically includes:

[0020] A nickel-chromium-silicon layer is formed on the substrate by magnetron sputtering as a thin film resistor layer, wherein the sheet resistance of the thin film resistor layer is 25 to 150 Ω / □;

[0021] Forming a titanium-tungsten layer as a barrier layer on the thin film resistor layer by magnetron sputtering; the thickness of the barrier layer is 40 to 50 nm;

[0022] A gold layer is formed on the barrier layer by magnetron sputtering as a thin gold seed crystal layer; the thickness of the thin gold seed crystal layer is 120-200 nm.

[0023] Further, forming a gold conduction band on the thin gold seed crystal layer specifically includes:

[0024] A first photoresist is spin-coated on the thin gold seed crystal layer and a pattern of a gold conductive band is photoetched; the first photoresist is a photoresist negative resist, and the thickness of the spin-coated photoresist is 5-6 μm.

[0025] exposing and developing the first photoresist to expose the thin gold seed layer in the gold conduction band region;

[0026] A gold layer with a thickness of 4 to 5.5 μm is electroplated on the thin gold seed crystal layer exposed in the gold conductive band area by using a microelectronics gold electroplating process to form a gold conductive band;

[0027] The first photoresist on the substrate is removed.

[0028] Further, removing the thin gold seed crystal layer exposed on the surface of the substrate to expose the barrier layer includes:

[0029] The electrochemical etching process is adopted to use an acidic solution to corrode the gold layer on the surface of the entire substrate at a corrosion rate of 30 to 40 nm / min; until the thin gold seed crystal layer exposed on the surface of the substrate is completely corroded to expose the barrier layer.

[0030] Furthermore, forming a nickel layer covering the upper end surface of the gold conductive strip in the area to be nickel-plated and wrapping the side wall of the gold conductive strip in the area specifically includes:

[0031] A second photoresist is used to photolithograph a pattern of a region to be nickel plated, wherein the region to be nickel plated includes a region where a gold conductive strip is located below a pad region, and an extended region formed by extending 5.0 to 7.5 μm in a direction where there is no gold conductive strip on the periphery of the region where the gold conductive strip is located and extending 200 to 250 μm along the connected gold conductive strip; the second photoresist is a positive photoresist, and the thickness of the spin-coated photoresist is 5 to 6 μm;

[0032] The upper end surface of the gold conductive strip in the area to be nickel-plated is exposed by exposing and developing the second photoresist, and a gap is formed around the gold conductive strip to expose the side wall of the gold conductive strip; the width of the gap is 5.0 to 7.5 μm;

[0033] A nickel layer is electroplated on the upper end surface and side wall of the exposed gold conductive strip by using a microelectronic nickel electroplating process, wherein the thickness of the nickel layer is 2-4.0 μm.

[0034] Further, the step of covering the nickel layer in the pad area with a gold layer to form a nickel-gold pad specifically includes:

[0035] The third photoresist is used to photoetch the pattern of the pad area on the nickel layer; the third photoresist is a positive photoresist, and the thickness of the spin-coated photoresist is 5-6 μm.

[0036] exposing and developing the third photoresist to expose the nickel layer in the pad area;

[0037] A pad gold layer is covered on the exposed nickel layer by magnetron sputtering to form a nickel-thin gold pad; the pad gold layer thickness is 100-120nm;

[0038] The second photoresist and the third photoresist on the substrate are removed.

[0039] Further, removing the thin film resistor layer of the exposed portion on the substrate to expose the substrate specifically includes:

[0040] A fourth photoresist is used to photolithograph a pattern of a thin film resistor region; the fourth photoresist is a positive photoresist, and the thickness of the spin-coated photoresist is 2 to 3 μm;

[0041] Forming a thin film resistor network by exposing and developing the fourth photoresist to expose the thin film resistor layer outside the thin film resistor region;

[0042] The thin film resistor layer of the exposed portion on the substrate is removed by wet etching to expose the substrate;

[0043] The fourth photoresist on the substrate is removed.

[0044] Furthermore, the substrate is heat-treated under nitrogen protection to generate nickel nitride on the exposed nickel layer to form a nickel passivation layer. The heat treatment temperature is 300±5° C. and the heat treatment time is 30 minutes.

[0045] A ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit comprises a substrate, on which a thin film resistor network is provided, the thin film resistor network is a nickel-chromium-silicon layer with a square resistance of 25-150Ω / □; on the thin film resistor network, a gold conductive strip is provided, and the gold conductive strip is provided with an upper end surface covering the gold conductive strip in the region corresponding to the region to be nickel-plated, and a nickel layer wrapping the side wall of the gold conductive strip in the region; the region to be nickel-plated includes a region below a pad region where the gold conductive strip is located, and an extended region formed by extending 5.0-7.5μm in a direction where there is no gold conductive strip on the basis of the region where the gold conductive strip is located and extending 200-250μm along the connected gold conductive strip; a pad gold layer is provided on the nickel layer in the pad region; and a nickel passivation layer is provided on the nickel layer in the region not covered by the pad gold layer.

[0046] In the present invention, a gold conductive band and a nickel-chromium-silicon thin film resistor network are formed on an alumina ceramic substrate by thin film wiring technology, magnetron sputtering, photolithography, microelectronic electroplating, degumming, corrosion and heat treatment technology, and a nickel-gold welding pad and a solder resist layer are superimposed on the gold conductive band. The thin film substrate produced by this process has a thick gold layer, high line width accuracy and steep step morphology, which can meet the requirements of high-precision, high-frequency and high-reliability applications; the substrate structure is compatible with standard micro-assembly processes such as gold wire bonding, polymer assembly, gold-based solder and tin-based solder welding, and can be widely used in the field of thin film hybrid integrated circuits, especially in the field of radio frequency and microwave circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0048] Figure 1 The present invention is a flow chart of a preferred embodiment of the method for manufacturing a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit.

[0049] Figure 2 It is a schematic cross-sectional view after a thin film resistor layer, a barrier layer and a thin gold seed layer are formed on a substrate.

[0050] Figure 3 It is a cross-sectional schematic diagram after spin coating photoresist on the thin gold seed layer and photolithography of the gold conductive band pattern.

[0051] Figure 4 This is a schematic cross-sectional view of a gold conductive strip formed using a microelectronics gold electroplating process.

[0052] Figure 5 for Figure 4 Schematic diagram of the cross section after removing the photoresist.

[0053] Figure 6 for Figure 5 Schematic diagram of the cross-section after removing the thin gold seed layer exposed on the substrate surface.

[0054] Figure 7 This is a schematic cross-sectional view of the gold conductive strip after the area to be plated with nickel is exposed by photolithography.

[0055] Figure 8 This is a schematic cross-sectional view of a nickel layer formed by selective nickel electroplating.

[0056] Fig. 9 It is a schematic cross-sectional view after the pad area is exposed by photolithography.

[0057] Fig.10 This is a schematic cross-sectional view after sputtering the pad gold layer in the pad area.

[0058] Fig.11 for Fig.10 Schematic diagram of the cross-section after removing the photoresist.

[0059] Fig.12 for Fig.11 Schematic diagram of the structure of the pad area.

[0060] Fig.13 for Fig.11 Schematic diagram of the cross section after etching the barrier layer.

[0061] Fig.14 for Fig.12 The cross-sectional diagram of the thin film resistor pattern formed by photolithography is shown above.

[0062] Fig.15 for Fig.14 Schematic diagram of the cross section after etching away the NiCrSi layer and removing the photoresist.

[0063] Fig.16 for Fig.15 Schematic diagram of the cross section of the metal layer after heat treatment to form a nickel nitride passivation layer.

[0064] In the figure: 1. substrate, 2. thin film resistor layer, 3. barrier layer, 4. thin gold seed layer, 6. gold conductive band, 7. nickel layer, 8. pad gold layer, 9. nickel passivation layer, 11. first photoresist, 12. second photoresist, 13. third photoresist, 14. fourth photoresist, 15. gap. DETAILED DESCRIPTION

[0065] The following describes the implementation methods of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other without conflict.

[0066] like Figure 1 As shown, a preferred embodiment of the method for manufacturing a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit of the present invention comprises the following steps:

[0067] S1, taking a substrate 1 and cleaning the substrate 1. The substrate 1 is preferably an alumina ceramic sheet, and cleaning the substrate 1 may include the following sub-steps:

[0068] S11, taking a mixed solution of NH4OH, H2O2 and H2O as a first cleaning solution; placing the substrate 1 in the first cleaning solution and boiling it for 5 minutes; wherein the volume ratio of each solution is NH4OH:H2O2:H2O=1:2:7.

[0069] S12, taking a mixed solution of KCL, H2O2 and H2O as the second cleaning solution; placing the substrate 1 in the second cleaning solution and boiling it for 5 minutes; wherein the volume ratio of each solution is KCL:H2O2:H2O=1:2:7.

[0070] S13, the substrate 1 is rinsed with deionizer, dried, and baked at 150° C. for 1 hour.

[0071] S2, such as Figure 2 As shown, a thin film resistor layer 2, a barrier layer 3 and a thin gold seed crystal layer 4 are sequentially formed on a substrate 1; specifically, the following sub-steps may be included:

[0072] S21, forming a nickel-chromium-silicon (NiCrSi) layer as a thin film resistor layer 2 on the substrate 1 by magnetron sputtering, wherein the sheet resistance of the thin film resistor layer 2 is 25 to 150 Ω / □;

[0073] S22, forming a titanium tungsten (TiW) layer as a barrier layer 3 on the thin film resistor layer 2 by magnetron sputtering; the thickness of the barrier layer 3 is 40 to 50 nm;

[0074] S23, forming a gold (Au) layer as a thin gold seed crystal layer 4 on the barrier layer 3 by magnetron sputtering; the thickness of the thin gold seed crystal layer 4 is 120-200 nm.

[0075] S3, forming a gold conductive strip 6 on the thin gold seed crystal layer 4; specifically, the step may include the following sub-steps:

[0076] S31, spin-coating a first photoresist 11 on the thin gold seed crystal layer 4 and photolithographically patterning the gold conductive band 6; the first photoresist 11 uses a negative photoresist with a viscosity of 150 cp, the coating speed is 800 rpm, and the spin-coated photoresist has a thickness of 5 to 6 μm.

[0077] S32, exposing and developing the first photoresist 11 to expose the thin gold seed crystal layer 4 in the gold conductive band region, and the cross-sectional shape after exposure and development is as follows: Figure 3 shown.

[0078] S33, using a microelectronic gold electroplating process to electroplate a gold layer with a thickness of 4 to 5.5 μm on the thin gold seed crystal layer 4 exposed in the gold conductive band area, so as to thicken the thin gold seed crystal layer 4 in the gold conductive band area to form a gold conductive band 6; the cross-sectional shape is as follows Figure 4 shown.

[0079] S34, using fuming nitric acid to soak and remove the first photoresist 11 on the substrate 1, and then flushing the substrate 1 for 10 minutes and then drying it; the cross-sectional shape after removing the first photoresist 11 is as follows Figure 5 shown.

[0080] S4, such as Figure 6 As shown, the thin gold seed crystal layer 4 exposed on the surface of the substrate 1 is removed to expose the barrier layer 3; the specific method is:

[0081] The electrochemical etching process is adopted, and the gold layer on the surface of the entire substrate 1 (including the gold layer of the thin gold seed crystal layer 4 and the gold layer of the gold conductive tape 6) is equally etched using an acidic solution at room temperature, and the etching rate is 30-40nm / min; until the exposed thin gold seed crystal layer 4 on the surface of the substrate 1 is completely etched, and the barrier layer 3 is exposed. In this process, the gold layer of the gold conductive tape 6 and the gold layer of the thin gold seed crystal layer 4 will be corroded synchronously, but because the thickness of the gold layer of the gold conductive tape 6 is much greater than the thickness of the gold layer of the thin gold seed crystal layer 4, and the etching rate is slow, the etching process has little effect on the thickness of the gold conductive tape 6. In addition, the thin gold seed crystal layer 4 below the gold conductive tape 6 will not be corroded. Since the thin gold seed crystal layer 4 and the gold conductive tape 6 are both formed by the gold layer, the thin gold seed crystal layer 4 below the gold conductive tape 6 can also compensate for the thickness loss of the gold conductive tape 6.

[0082] S5, forming a nickel (Ni) layer 7 covering the upper end surface of the gold conductive tape 6 and wrapping the side wall of the gold conductive tape 6 in the area to be nickel-plated; specifically, the following sub-steps may be included:

[0083] S51. Use a second photoresist 12 to photolithograph a pattern of the area to be nickel-plated, wherein the area to be nickel-plated includes the area where the gold conductive tape is located below the pad area, and an extended area formed by extending 5.0 to 7.5 μm in the direction where there is no gold conductive tape 6 on the basis of the area where the gold conductive tape is located and extending 200 to 250 μm along the connected gold conductive tape 6; the second photoresist 12 uses a positive photoresist with a viscosity of 60 cp, a coating speed of 800 rpm, and a spin-coated photoresist thickness of 5 to 6 μm.

[0084] S52, exposing and developing the second photoresist 12 to expose the upper end surface of the gold conductive tape 6 in the area to be nickel-plated, and forming a gap 15 around the gold conductive tape 6 in the area to be nickel-plated to expose the side wall of the gold conductive tape 6; the width of the gap 15 is 5.0 to 7.5 μm; the cross-sectional shape after exposure and development is as follows Figure 7 shown.

[0085] S53, using a microelectronic nickel electroplating process, electroplating a nickel layer 7 on the upper end surface and side wall of the exposed gold conductive strip 6, wherein the thickness of the nickel layer 7 is 2-4.0 μm. The cross-sectional shape of the nickel layer 7 is as follows: Figure 8 shown.

[0086] S6, covering the pad gold layer 8 on the nickel layer 7 in the pad area to form a nickel-thin gold pad; the pad gold layer 8 is smaller than the gold conductive strip 6 thereunder; this step may specifically include the following sub-steps:

[0087] S61, using a third photoresist 13 to photoetch a pattern of the pad area on the nickel layer 7; the third photoresist 13 uses a positive photoresist with a viscosity of 60 cp, a coating speed of 800 rpm, and a spin-coated photoresist thickness of 5 to 6 μm.

[0088] S62, exposing and developing the third photoresist 13 to expose the nickel layer 7 in the pad area, and the rest of the nickel layer 7 is covered by the third photoresist 13; the cross-sectional shape after exposure and development is as follows Fig. 9 shown.

[0089] S63, such as Fig.10 As shown, a pad gold layer 8 is covered on the exposed nickel layer 7 by magnetron sputtering to form a nickel thin gold pad; the pad gold layer 8 has a thickness of 100 to 120 nm.

[0090] S64, using acetone and ethanol solution to ultrasonically clean and remove the second photoresist 12 and the third photoresist 13 on the substrate 1, and then flushing the substrate 1 for 10 minutes and then drying it. The cross-sectional shape after removing the second photoresist 12 and the third photoresist 13 on the substrate 1 is as follows: Fig.11 As shown; at this time, the gold layer sputtered onto the third photoresist 13 in step S63 will also be removed after losing the support of the third photoresist 13.

[0091] like Fig.12 As shown, Fig.11 FIG. 1 is a top view of the two pad areas, wherein the dotted line represents the outline of the gold conductive tape 6 covered by the nickel layer 7; it can be seen from the figure that the gold conductive tape 6 below the left pad area is completely wrapped by the nickel layer 7, and in the right pad area, not only the gold conductive tape 6 below is completely wrapped by the nickel layer 7, but also the nickel layer 7 completely wraps a section of the gold conductive tape 6 connected to the nickel thin gold pad, thereby preventing the solder from flowing onto the gold conductive tape 6 around the pad and causing the gold layer of the gold conductive tape 6 to dissolve.

[0092] S7, such as Fig.13 As shown, the barrier layer 3 of the exposed portion on the thin film resistor layer 2 is removed; preferably, wet etching is used to remove the barrier layer 3 of the exposed portion on the thin film resistor layer 2, the etching solution is H2O2, the etching temperature is 40°C, and the etching rate is 250-270nm / min.

[0093] S8, removing the exposed portion of the thin film resistor layer 2 on the substrate 1 to expose the substrate 1; specifically, the following sub-steps may be included:

[0094] S81, using the fourth photoresist 14 to photolithograph the pattern of the thin film resistor area; the fourth photoresist 14 uses a positive photoresist with a viscosity of 20 cp, a coating speed of 800 rpm, and a spin-coated photoresist thickness of 2-3 μm.

[0095] S82, exposing and developing the fourth photoresist 14 to expose the thin film resistor layer 2 outside the thin film resistor area; the cross-sectional shape after exposure and development is as follows Fig.14 shown.

[0096] S83, removing the exposed portion of the thin film resistor layer 2 on the substrate 1 by wet etching to expose the substrate 1, thereby forming a thin film resistor network; the cross-sectional shape after etching is as follows Fig.15 The etching solution is cerium ammonium nitrate and nitric acid etching solution, the etching temperature is room temperature, and the etching rate is 5-7nm / min.

[0097] S84, using acetone and ethanol solution to ultrasonically clean and remove the fourth photoresist 14 on the substrate 1, and then flushing the substrate 1 for 10 minutes and then drying it.

[0098] S9, such as Fig.16As shown, the substrate 1 is heat treated under nitrogen protection, the heat treatment temperature is preferably 300±5°C, and the heat treatment time is preferably 30 minutes, so that nickel nitride is generated on the exposed nickel layer 7 to form a nickel passivation layer 9 (i.e., a nickel nitride layer); that is, a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit is obtained. By passivating the surface of the exposed nickel layer 7, during the soldering process, since the nickel passivation layer 9 and the tin-lead solder are not solderable, the soldering is limited to the pad, avoiding the solder flowing to the gold layer of the gold conductive tape 6 around the pad and causing the gold layer of the gold conductive tape 6 to dissolve, thereby ensuring the integrity, electrical performance and reliability of the metal structure of the substrate 1. In addition, the use of a nickel passivation solder resist is not only simpler than the process of an organic medium (such as polyimide), but also avoids the loss of high-frequency signal transmission caused by the organic medium, which is conducive to high-frequency field applications.

[0099] Through innovative layout design and process design, this embodiment uses thin film wiring technology on an alumina ceramic thin film substrate, and adopts magnetron sputtering and selective microelectronic gold plating technology to strictly limit the gold layer of the gold conduction band 6 to be deposited and thickened within the window formed by the thick photoresist, combined with the arithmetic differential etching process, to form a conduction band with good surface flatness, high line width accuracy and steep step morphology, and the conduction band has good transmission characteristics such as strong oxidation resistance, low resistance and low loss.

[0100] In this embodiment, on the same layer of electroplated nickel layer 7, thin gold is sputtered on the nickel layer 7 in the pad area to form a nickel-thin-gold pad, and the exposed nickel layer 7 is left around the nickel-thin-gold pad and on the gold conductive tape 6 layer connected thereto. Through a heat treatment process, the surface of the exposed nickel layer 7 is passivated, thereby forming a pad with a solder resist function, ensuring the integrity, electrical performance and reliability of the metal structure of the substrate 1 during the welding process. In addition, the nickel passivation solder resist layer process is simple and convenient, and avoids the loss of high-frequency signal transmission caused by organic media, which is conducive to high-frequency field applications.

[0101] The alumina ceramic thin film substrate manufactured by the method of this embodiment is compatible with standard micro-assembly processes such as gold wire bonding, polymer assembly, gold-based solder and tin-based solder welding, and can meet high-precision, high-frequency and high-reliability applications. It can also be promoted and used in other types of thin film substrates (such as aluminum nitride, beryllium oxide, etc.) to meet the high-reliability application requirements of the product.

[0102] like Fig.16As shown, a preferred embodiment of a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit of the present invention includes a substrate 1, on which a thin film resistor network is provided, and the thin film resistor network is a nickel-chromium-silicon layer with a square resistance of 25 to 150Ω / □; on the thin film resistor network, a gold conductive tape 6 is provided, and the thickness of the gold conductive tape 6 is 4 to 5.5μm. The gold conductive tape 6 is provided with a nickel layer 7 covering the upper end surface of the gold conductive tape 6 in the area corresponding to the area to be nickel-plated, and the side wall of the gold conductive tape 6 in the area is wrapped, and the area to be nickel-plated includes the area where the gold conductive tape is located below the pad area, and the extension area formed by extending 5.0 to 7.5μm in the direction where there is no gold conductive tape 6 on the basis of the area where the gold conductive tape is located and extending 200 to 250μm along the connected gold conductive tape 6; the thickness of the nickel layer is 2 to 4.0μm. A pad gold layer 8 is provided on the nickel layer 7 in the pad area, and the thickness of the pad gold layer 8 is 100 to 120nm, and the size of the pad gold layer 8 is smaller than the size of the gold conductive tape 6 below it. A nickel passivation layer 9 is disposed on the nickel layer 7 in the non-pad region, and the nickel passivation layer 9 is preferably nickel nitride.

[0103] In this embodiment, a bare nickel passivation layer 8 is provided around the nickel thin gold pad and on the gold conductive tape 6 layer connected thereto, thereby forming a pad with a solder resist function, ensuring the integrity, electrical performance and reliability of the metal structure of the substrate 1 during the welding process. In addition, the alumina ceramic thin film substrate of this embodiment is compatible with standard micro-assembly technologies, including gold wire bonding, gold-tin eutectic welding, tin-lead solder welding and polymer assembly. The thin film hybrid integrated circuit products assembled using the substrate 1 meet the requirements of GJB2438 "General Specifications for Hybrid Integrated Circuits", and the product reliability level reaches H level.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A method for manufacturing a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit, characterized in that: The following steps are involved: Taking a substrate and cleaning the substrate; forming a thin film resistor layer, a barrier layer and a thin gold seed crystal layer in sequence on a substrate; forming a gold conduction band on the thin gold seed layer; Removing the exposed thin gold seed crystal layer on the surface of the substrate to expose the barrier layer; the exposed thin gold seed crystal layer is the thin gold seed crystal layer not covered with the gold conductive band; A nickel layer covering the upper end surface of the gold conductive tape and wrapping the side wall of the gold conductive tape in the area to be nickel-plated is formed; the area to be nickel-plated includes the area where the gold conductive tape is located below the predetermined pad area, and an extended area formed by extending 5.0 μm to 7.5 μm in the direction where there is no gold conductive tape around the area where the gold conductive tape is located and extending 200 μm to 250 μm along the connected gold conductive tape; Covering the pad gold layer on the nickel layer in the pad area to form a nickel-thin gold pad; the pad gold layer has a size smaller than the gold conductive strip thereunder; Removing the exposed portion of the barrier layer on the thin film resistor layer; the exposed portion of the barrier layer is the barrier layer not covered with the gold conductive band and the nickel layer; The thin film resistor layer of the exposed part on the substrate is removed to expose the substrate and form a thin film resistor network. This step includes: The fourth photoresist is used to photolithograph the pattern of the thin film resistor area; the thin film resistor layer outside the thin film resistor area is exposed by exposing and developing the fourth photoresist to form a thin film resistor network; the thin film resistor layer of the exposed part on the substrate is removed by wet etching to expose the substrate, wherein the thin film resistor layer of the exposed part is the thin film resistor layer not covered by the fourth photoresist and the barrier layer; the fourth photoresist on the substrate is removed; The substrate is heat-treated to form a nickel passivation layer on the exposed nickel layer, wherein the exposed nickel layer is the nickel layer whose surface is not covered with the pad gold layer.

2. The method for manufacturing a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit according to claim 1, characterized in that: The substrate is an alumina ceramic sheet, and cleaning the substrate includes the following steps: A mixed solution of NH4OH, H2O2 and H2O is used as the first cleaning solution; the substrate is placed in the first cleaning solution and boiled for 5 minutes; Take a mixed solution of KCL, H2O2 and H2O as the second cleaning solution; put the substrate into the second cleaning solution and boil for 5 minutes; The substrate was rinsed with deionized water, dried, and baked at 150° C. for 1 hour.

3. The method for manufacturing a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit according to claim 1, characterized in that: The step of sequentially forming a thin film resistor layer, a barrier layer and a thin gold seed crystal layer on a substrate specifically includes: A nickel-chromium-silicon layer is formed on the substrate by magnetron sputtering as a thin film resistor layer, wherein the sheet resistance of the thin film resistor layer is 25 to 150 Ω / □; Forming a titanium-tungsten layer as a barrier layer on the thin film resistor layer by magnetron sputtering; the thickness of the barrier layer is 40 to 50 nm; A gold layer is formed on the barrier layer by magnetron sputtering as a thin gold seed crystal layer; the thickness of the thin gold seed crystal layer is 120-200 nm.

4. The method for manufacturing a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit according to claim 1, characterized in that: The formation of a gold conduction band on the thin gold seed crystal layer specifically includes: Spin-coating a first photoresist on the thin gold seed crystal layer and photolithography a pattern of a gold conductive band; the first photoresist is a photoresist negative resist, and the thickness of the spin-coated photoresist is 5 to 6 μm; exposing and developing the first photoresist to expose the thin gold seed layer in the gold conduction band region; A gold layer with a thickness of 4 to 5.5 μm is electroplated on the thin gold seed crystal layer exposed in the gold conductive band area by using a microelectronics gold electroplating process to form a gold conductive band; The first photoresist on the substrate is removed.

5. The method for manufacturing a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit according to claim 1, characterized in that: Removing the thin gold seed layer exposed on the substrate surface to expose the barrier layer includes: The electrochemical etching process is adopted to use an acidic solution to corrode the gold layer on the surface of the entire substrate at a corrosion rate of 30 to 40 nm / min; until the thin gold seed crystal layer exposed on the surface of the substrate is completely corroded to expose the barrier layer.

6. The method for manufacturing a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit according to claim 1, characterized in that: The nickel layer formed in the area to be nickel plated to cover the upper end surface of the gold conductive strip and the side wall of the gold conductive strip in the area specifically includes: A second photoresist is used to photolithograph a pattern of a region to be nickel plated, wherein the region to be nickel plated includes a region where a gold conductive strip is located below a pad region, and an extended region formed by extending 5.0 to 7.5 μm in a direction where there is no gold conductive strip on the periphery of the region where the gold conductive strip is located and extending 200 to 250 μm along the connected gold conductive strip; the second photoresist is a positive photoresist, and the thickness of the spin-coated photoresist is 5 to 6 μm; The upper end surface of the gold conductive strip in the area to be nickel-plated is exposed by exposing and developing the second photoresist, and a gap is formed around the gold conductive strip to expose the side wall of the gold conductive strip; the width of the gap is 5.0 to 7.5 μm; A nickel layer is electroplated on the upper end surface and side wall of the exposed gold conductive strip by using a microelectronic nickel electroplating process, wherein the thickness of the nickel layer is 2-4.0 μm.

7. The method for manufacturing a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit according to claim 1, characterized in that: Covering the nickel layer in the pad area with a gold layer to form a nickel-thin gold pad specifically includes: A third photoresist is used to photoetch a pattern of the pad area on the nickel layer; the third photoresist is a positive photoresist, and the thickness of the spin-coated photoresist is 5 to 6 μm; exposing and developing the third photoresist to expose the nickel layer in the pad area; A pad gold layer is covered on the exposed nickel layer by magnetron sputtering to form a nickel-thin gold pad; the pad gold layer thickness is 100-120nm; The second photoresist and the third photoresist on the substrate are removed.

8. The method for manufacturing a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit according to claim 1, characterized in that: The fourth photoresist is a positive photoresist, and the thickness of the spin-coated photoresist is 2-3 μm.

9. The method for manufacturing a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit according to claim 1, characterized in that: The substrate is heat-treated under nitrogen protection to generate nickel nitride on the exposed nickel layer to form a nickel passivation layer. The heat treatment temperature is 300±5°C and the heat treatment time is 30 minutes.

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