Deep trench capacitor, semiconductor structure and method of forming the same

Abstract

A deep trench capacitor, a semiconductor structure and a method of forming the same are provided. The method includes forming a deep trench in a substrate and forming a layer stack in the deep trench and over the deep trench, the layer stack including at least three metal electrode plates interleaved with at least two node dielectric layers. A contact level dielectric material layer is formed over the layer stack and a contact via cavity is formed through the contact level dielectric material layer. Depths of the contact via cavities are differentiated by selectively increasing depths of respective subsets of the contact via cavities by performing a combination of at least two processing steps including an etch mask formation process and an etch process. A combination of a dielectric contact via liner and a plate contact via structure can be formed within each of the contact via cavities. The plate contact via structure extending through any of the metal electrode plates can be electrically isolated from such metal electrode plate by the respective dielectric contact via liner.

Description

Technical Field

[0001] Embodiments of the present invention relate to a deep trench capacitor, a semiconductor structure, and a method for forming the same. Background Art

[0002] Capacitors are employed in semiconductor chips for many applications, such as power supply stabilization. Capacitors tend to occupy a large amount of device area, and therefore, capacitors that can provide high capacitance in a small device footprint are desirable. Summary of the Invention

[0003] An embodiment of the present invention provides a deep trench capacitor, comprising: at least one deep trench extending downward from the top surface of a substrate; and a layer stack comprising at least three metal electrode plates interlaced with at least two node dielectric layers, wherein: each layer within the layer stack comprises a corresponding vertical extension portion located within each of the at least one deep trench and a corresponding horizontal extension portion located above the top surface of the substrate; a main electrode assembly comprising at least two main metal electrode plates selected from the at least three metal electrode plates; a complementary electrode assembly comprising at least one complementary metal electrode plate selected from the at least three metal electrode plates; and each layer within the layer stack has a corresponding sidewall contained within a vertical plane, the vertical plane comprising a segment of the outer periphery of the layer stack.

[0004] An embodiment of the present invention provides a semiconductor structure comprising at least one deep trench capacitor located on a substrate, wherein each of the at least one deep trench capacitor comprises: a deep trench extending downward from the top surface of the substrate; a layer stack comprising at least three metal electrode plates interlaced with at least two node dielectric layers; and a plate contact via structure contacting the top surface of a corresponding one of the at least three metal electrode plates, wherein: each layer within the layer stack comprises a corresponding vertical extension portion located within the deep trench and a corresponding horizontal extension portion located above the top surface of the substrate; each interface between the plate contact via structure and the at least three metal electrode plates is located in a horizontal plane, the horizontal plane comprising the top surface of a corresponding one of the at least three metal electrode plates; and wherein each of the plate contact via structures is laterally surrounded by a corresponding dielectric contact via liner having a uniform lateral thickness.

[0005] An embodiment of the present invention provides a method for forming a semiconductor structure, which includes: forming at least one deep trench extending vertically into a substrate; forming a layer stack in and above at least one deep trench, the layer stack including at least three metal electrode plates interlaced with at least two node dielectric layers; forming a contact-level dielectric material layer above the layer stack; forming a contact via cavity through the contact-level dielectric material layer, so that each of the contact via cavities has a bottom surface located above the top layer in the layer stack; selectively increasing the depth of a corresponding subset of the contact via cavities by performing a combination of at least two processing steps including an etch mask formation process and an etching process; and forming a combination of a dielectric contact via liner and a plate contact via structure in each of the contact via cavities. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a vertical cross-sectional view of an exemplary structure after forming a deep trench in a substrate according to an embodiment of the present disclosure.

[0008] Figure 2 is a vertical cross-sectional view of an exemplary structure after forming a layer stack including at least three metal electrode plates interleaved with at least two node dielectric layers according to an embodiment of the present disclosure.

[0009] Figure 3 is a vertical cross-sectional view of the exemplary structure after patterning the layer stack to form vertical sidewalls of the horizontally extending portions of the layer stack according to an embodiment of the present disclosure.

[0010] Figure 4 is a vertical cross-sectional view of an exemplary structure after forming a contact-level dielectric layer according to an embodiment of the present disclosure.

[0011] Figure 5 is a vertical cross-sectional view of an exemplary structure after forming a contact via cavity according to an embodiment of the present disclosure.

[0012] Figures 6A to 6C are sequential vertical cross-sectional views of an exemplary structure during selective vertical extension of contact via cavities according to a first patterning scheme according to an embodiment of the present disclosure.

[0013] Figures 7A to 7Care sequential vertical cross-sectional views of an exemplary structure during selective vertical extension of contact via cavities according to a second patterning scheme according to an embodiment of the present disclosure.

[0014] Figure 8 is a vertical cross-sectional view of an exemplary structure after contact via cavities are selectively vertically extended according to an embodiment of the present disclosure.

[0015] Figure 9 is a vertical cross-sectional view of an exemplary structure after laterally recessing a horizontal portion of a metal electrode plate around each contact via cavity according to an embodiment of the present disclosure.

[0016] Figure 10 is a vertical cross-sectional view of an exemplary structure after a terminal node dielectric etch process according to an embodiment of the present disclosure.

[0017] Figure 11A is a vertical cross-sectional view of an exemplary structure after forming a dielectric contact via liner according to an embodiment of the present disclosure.

[0018] Figure 11B yes Figure 11A A vertical cross-sectional view of an alternative embodiment of the exemplary structure is shown.

[0019] Figure 12 is a vertical cross-sectional view of an exemplary structure after forming a board contact via structure according to an embodiment of the present disclosure.

[0020] Figure 13A is a vertical cross-sectional view of an exemplary structure after forming a metal interconnect structure according to an embodiment of the present disclosure.

[0021] Figure 13B yes Figure 13A A reduced vertical cross-sectional view of the exemplary structure is shown.

[0022] Figure 13C yes Figure 13A A vertical cross-sectional view of an alternative embodiment of the exemplary structure is shown.

[0023] Figure 14 is a vertical cross-sectional view of an exemplary chip assembly including a semiconductor die including a deep trench capacitor according to an embodiment of the present disclosure.

[0024] Figure 15 is a flow chart showing the general processing steps of the method of the present disclosure. DETAILED DESCRIPTION

[0025] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0026] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0027] The present disclosure relates to semiconductor devices, and more particularly to a deep trench capacitor including a self-aligned plate contact via structure and a method of forming the deep trench capacitor.

[0028] Deep trench capacitors can be used as integrated passive devices to provide large capacitance. Deep trench capacitors can be used to stabilize power supplies and as noise filters in handheld devices. If more than two electrode plates are used in a deep trench capacitor, the process window for the contact etching process will be very narrow. The contact etching process can simultaneously etch through different types of layer stacks to provide contact through-hole cavities to each of the electrode plates of the deep trench capacitor. However, for some electrode plates that are not provided with sufficient overlying etch stop material portions, an electrical short circuit to the underlying electrode plate may occur, and / or for some other electrode plates that are provided with too thick overlying etch stop material portions, an electrical open may occur. Since the horizontal portions of the electrode plates are at different heights, providing an etch stop structure with an optimal thickness for each type of electrode plate may be a challenging process and is prone to degradation under process variations.

[0029] In general, the structures and methods of the present disclosure can be used to form deep trench capacitors with reliable electrical contact structures that have reduced electrical opens and shorts. According to embodiments of the present disclosure, process integration schemes can be used to widen the process window for forming electrical contacts to metal electrode plates without electrical opens or shorts.

[0030] Specifically, an interleaved stack of metal electrode plates and node dielectric layers can be formed in deep trenches. The interleaved stack of metal electrode plates can then be patterned using a single etch mask that defines the perimeter of the patterned layer stack. A contact-level dielectric layer can be formed above the patterned layer stack. A vertical through-hole cavity can be formed through the contact-level dielectric layer above the horizontal portion of the patterned layer stack. A combination of masking steps and selective etching processes can be used to selectively extend the vertical through-hole cavity to different vertical extension distances in the vertical direction. A combination of selective etching steps can be used in each selective etching process to selectively etch through the node dielectric layer in sequence relative to the material of the metal electrode plate and then selectively etch through the metal electrode plate relative to the material of the node dielectric layer. The selectivity of the selective etching steps can be high enough to accommodate process variations in the process for forming the interleaved stack. Horizontal portions of the metal electrode plates at different heights can be physically exposed at the bottom of vertically extending contact through-hole cavities having different depths. A plate contact via structure that is laterally insulated from a dielectric contact via liner can be formed in a contact via cavity to provide electrical contact with a metal electrode plate. The dielectric contact via liner can provide electrical isolation between the embedded plate contact via structure and any horizontal portion of the metal electrode plate overlying the metal electrode plate that contacts the embedded plate contact via structure. According to embodiments of the present disclosure, reliable electrical contact between the plate contact via structure and the metal electrode plate can provide higher yield and increased durability of deep trench capacitors.

[0031] Reference Figure 1 , shows an exemplary structure according to an embodiment of the present disclosure, comprising a substrate 8 having a flat top surface. Substrate 8 may comprise a semiconductor material and may have a thickness of at least 10 microns. In one embodiment, substrate 8 may comprise a commercially available semiconductor wafer that may be cut into semiconductor dies after forming the deep trenches. For example, substrate 8 may comprise a semiconductor substrate comprising single crystal silicon and having a thickness ranging from 500 microns to 1,500 microns.

[0032] A deep trench 9 is formed extending vertically into the substrate 8. The deep trench 9 can be formed by forming a patterned etch mask layer on the front surface of the substrate 8. The pattern in the patterned etch mask layer can be transferred to the upper portion of the substrate 8. Before forming the patterned etch mask layer, an optional pad dielectric layer (e.g., a silicon oxide pad layer) can be formed on the front surface (i.e., the top surface) of the substrate 8. In an exemplary embodiment, the pad dielectric layer may include a silicon oxide layer having a thickness in the range of 20 nm to 100 nm. The patterned etch mask layer may include a silicon nitride layer or a borosilicate glass (BSG) layer having a thickness in the range of 200 nm to 600 nm, but different materials and / or smaller or larger thicknesses may also be used for the optional pad dielectric layer and the patterned etch mask layer. The patterned etch mask layer may be formed by depositing a blanket etch mask layer; forming a photoresist layer that is photolithographically patterned over the blanket etch mask layer; and transferring the pattern in the photolithographically patterned photoresist layer through the blanket etch mask layer using an anisotropic etching process (e.g., a reactive ion etching process).

[0033] An anisotropic etching process may be performed to transfer the pattern in the patterned etch mask layer through the upper portion of the substrate 8, thereby forming the deep trenches 9. For example, a reactive ion etching process using a gas combination including HBr, NF3, O2, and SF6 may be used to form the deep trenches 9. The depth of the deep trenches 9 may be in the range of 1 micron to 10 microns. The horizontal cross-sectional shape of each deep trench 9 may have the following shapes: circular, elliptical, rectangular, rounded rectangular, annular with variously shaped inner and outer perimeters, or any two-dimensional shape defining an enclosed volume. An array of deep trenches 9 having the same horizontal cross-sectional shape or different horizontal cross-sectional shapes may be formed in each device region used to form a deep trench capacitor, which is referred to herein as a unit capacitor region. Multiple unit capacitor regions may be provided in the substrate 8.

[0034] The deep trenches 9 may have a corresponding uniform width (e.g., in the case of a circle or rectangle) or a variable width (e.g., in the case of facing sidewalls having lateral undulation). In general, a major portion of each deep trench 9 (e.g., more than 50% of the entire area) may have a width sufficient to accommodate the vertical extensions of all metal electrode plates to be subsequently formed and the vertical extensions of at least two node dielectric layers. For example, the major portion of each deep trench 9 may have a width sufficient to accommodate the vertical extensions of at least three metal electrode plates and the vertical extensions of at least two node dielectric layers. In an illustrative example, the major portion of each deep trench 9 may have a width in the range of 50 nm to 1,000 nm, but smaller or larger widths may also be used.

[0035] The photoresist layer may be removed before the anisotropic etching process for forming the deep trench 9, or the photoresist layer may be consumed during the anisotropic etching process for forming the deep trench 9. The patterned etch mask layer and the optional pad dielectric layer may then be removed, for example, by a corresponding isotropic etching process (e.g., a wet etching process).

[0036] Reference Figure 2 , a dielectric isolation layer 6 may be formed on the physically exposed surface of the semiconductor substrate 8, including the surface of the semiconductor substrate 8 exposed in each deep trench 9. The dielectric isolation layer 6 may include a dielectric material that provides electrical isolation between the deep trench capacitor to be formed later and the substrate 8. For example, the dielectric isolation layer 6 may include silicon oxide, silicon nitride, silicon oxynitride, and / or a dielectric metal oxide. Other suitable materials within the scope of the present disclosure may also be used. In an illustrative example, the dielectric isolation layer 6 may include a silicon oxide layer formed by thermally oxidizing a surface portion of the substrate 8 including silicon. The thickness of the dielectric isolation layer 6 may be in the range of 4 nm to 100 nm, but lesser or greater thicknesses may also be used.

[0037] The alternating layer stack 30 of metal electrode plates (10A, 20A, 10B, 20B) and node dielectric layer 15 can be formed by corresponding conformal deposition processes. Each of the metal electrode plates (10A, 20A, 10B, 20B) can include a metal material. In one embodiment, each metal electrode plate (10A, 20A, 10B, 20B) includes a conductive metal nitride material and / or consists essentially of a conductive metal nitride material, which can be a metal diffusion barrier material. For example, each metal electrode plate (10A, 20A, 10B, 20B) can include a conductive metal nitride material (e.g., TiN, TaN, or WN) and / or can consist essentially of a conductive metal nitride material (e.g., TiN, TaN, or WN). Other suitable materials within the contemplated scope of the present disclosure can also be used. Since the diffusion of metal elements through the node dielectric layer 15 and / or through the dielectric isolation layer 6 may have a harmful effect on the deep trench capacitor, it may be advantageous to use a metal diffusion barrier material for the metal electrode plates (10A, 20A, 10B, 20B). Each metal electrode plate (10A, 20A, 10B, 20B) can be formed by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of each metal electrode plate (10A, 20A, 10B, 20B) can be in the range of 5nm to 50nm, but smaller and larger thicknesses can also be used. In one embodiment, each metal electrode plate (10A, 20A, 10B, 20B) can have the same material composition and the same thickness. In another embodiment, each metal electrode plate (10A, 20A, 10B, 20B) can have the same material composition but different thicknesses. In another embodiment, each metal electrode plate (10A, 20A, 10B, 20B) may have different material compositions and the same thickness. In another embodiment, each metal electrode plate (10A, 20A, 10B, 20B) may have different material compositions and different thicknesses.

[0038] Each of the node dielectric layers 15 may comprise a node dielectric material, which may be a dielectric metal oxide material having a dielectric constant greater than 7.9 (7.9 is the dielectric constant of silicon nitride), i.e., a "high dielectric constant (high-k)" dielectric metal oxide material. For example, the node dielectric layers 15 may comprise a dielectric metal oxide material such as aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, lanthanum oxide, alloys thereof, silicates thereof, and / or layer stacks thereof. In one embodiment, the node dielectric layers 15 may comprise an amorphous aluminum oxide layer, which may then be annealed to a polycrystalline aluminum oxide material after forming the contact via cavity (e.g., after forming the plate contact via structure). Other suitable materials may also be used within the contemplated scope of the present disclosure. Each node dielectric layer 15 may be formed by a conformal deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of each node dielectric layer 15 may range from 1 nm to 20 nm, although smaller and larger thicknesses may also be used. In one embodiment, each node dielectric layer 15 may have the same material composition and the same thickness. In another embodiment, each node dielectric layer 15 may have the same material composition but a different thickness. In yet another embodiment, each node dielectric layer 15 may have a different material composition and the same thickness. In yet another embodiment, each node dielectric layer 15 may have a different material composition and a different thickness.

[0039] The total number of metal electrode plates (10A, 20A, 10B, 20B) may be in the range of 3 to 16 (e.g., from 4 to 8). The total number of node dielectric layers 15 may be one less than the total number of metal electrode plates (10A, 20A, 10B, 20B). Although the present disclosure is described using an embodiment in which the alternating layer stack 30 of metal electrode plates (10A, 20A, 10B, 20B) and node dielectric layers 15 includes four metal electrode plates (10A, 20A, 10B, 20B) and three node dielectric layers 15, embodiments in which a different number of metal electrode plates (10A, 20A, 10B, 20B) and a different number of node dielectric layers 15 may be used within the alternating layer stack 30 are expressly contemplated herein. Generally speaking, the alternating layer stack 30 may include at least three metal electrode plates (10A, 20A, 10B, 20B) interleaved with at least two node dielectric layers 15, and the alternating layer stack 30 may be formed in and above at least one deep trench 9 formed in the substrate 8.

[0040] The metal electrode plates (10A, 20A, 10B, 20B) may be numbered sequentially in the order of deposition. For example, the metal electrode plates (10A, 20A, 10B, 20B) may include a first metal electrode plate 10A, a second metal electrode plate 20A, a third metal electrode plate 10B, a fourth metal electrode plate 20B, and so on. The patterned portion of each odd-numbered metal electrode plate (10A, 10B) may be subsequently used to form a main electrode assembly serving as a main node (i.e., a first node) of a deep trench capacitor, and the patterned portion of each even-numbered metal electrode plate (20A, 20B) may be subsequently used to form a complementary electrode assembly serving as a complementary node (i.e., a second node) of the deep trench capacitor. The total number of metal electrode plates (10A, 20A, 10B, 20B), the thickness of the metal electrode plates (10A, 20A, 10B, 20B) and the width of the deep trench 9 can be selected so that a major portion (i.e., more than 50%) or all of the area of ​​the deep trench 9 can be filled with the alternating layer stack 30.

[0041] A node dielectric material layer 32 may be formed over the alternating layer stack 30. The node dielectric material layer 32 may have the same thickness and composition as one or each of the node dielectric layers 15. An optional dielectric spacer layer 34 may be optionally deposited over the node dielectric material layer 32. The dielectric spacer layer 34 may fill any remaining voids in the deep trenches 9, if such voids exist. Additionally, the dielectric spacer layer 34 may provide a flat, horizontal top surface. In an illustrative example, the dielectric spacer layer 34 may comprise silicon oxide and may have a thickness in the range of 1 nm to 100 nm, although greater thicknesses may also be used. Other suitable materials within the contemplated scope of the present disclosure may also be used. In one embodiment, the dielectric spacer layer 34 may be formed by a conformal deposition process, such as by applying a flowable oxide (FOX) material, or a self-planarizing deposition process, such as spin coating.

[0042] Reference Figure 3 A photoresist layer 130 may be applied over the optional dielectric spacer layer 34 and the node dielectric material layer 32. The photoresist layer 130 may be photolithographically patterned to form an array of discrete patterned portions located within corresponding device regions, referred to herein as unit capacitor regions UC. A one-dimensional array of unit capacitor regions UC or a two-dimensional array of unit capacitor regions UC may be provided. Each unit capacitor region UC may have a region of any two-dimensional shape having a closed perimeter, such as a circle, an ellipse, a polygon, a polygon with rounded corners, or any generally curved two-dimensional shape. In one embodiment, the pattern of the discrete portions of the photoresist layer 130 may be a periodic pattern.

[0043] An anisotropic etching process can be performed to etch through unmasked portions of the optional dielectric spacer layer 34, unmasked portions of the node dielectric material layer 32, and unmasked portions of the alternating layer stack 30 using the patterned photoresist layer 130 as an etch mask. The horizontally extending portions of the optional dielectric spacer layer 34, the horizontally extending portions of the node dielectric material layer 32, and the horizontally extending portions of each layer within the alternating layer stack 30 can be divided into a plurality of discrete patterned portions located within a corresponding unit capacitor region UC. In embodiments where the pattern of the discrete portions of the photoresist layer 130 comprises a periodic pattern, the patterned portions of the optional dielectric spacer layer 34, the patterned portions of the node dielectric material layer 32, and the patterned portions of the alternating layer stack 30 can be arranged into a one-dimensional or two-dimensional array of unit structures. Each unit structure can be located within a corresponding unit capacitor region UC.

[0044] Each unit capacitor region UC includes at least one deep trench 9. An alternating layer stack 30 of metal electrode plates (10A, 20A, 10B, 20B) and node dielectric layers 15 may be provided within each unit capacitor region UC. In an embodiment, the alternating layer stack 30 may include at least three metal electrode plates (10A, 20A, 10B, 20B) interleaved with at least two node dielectric layers 15. Each layer (10A, 20A, 10B, 20B, 15) within the alternating layer stack 30 may include a respective vertically extending portion located within each of the at least one deep trench 9 and a respective horizontally extending portion located above the top surface of the substrate 8.

[0045] The sidewalls 17 of the horizontally extending portions of the layers within the alternating layer stack 30 can be vertical and coincide with the sidewalls of the patterned portions of the photoresist layer 130. Thus, each outer sidewall 17 of the horizontally extending portion of each layer within the alternating layer stack 30 can lie within a corresponding vertical plane. For example, if the horizontally extending portions of all layers within the alternating layer stack 30 have a horizontal cross-sectional shape that is a polygon with N sides (e.g., a rectangle), a set of all sidewalls 17 of the horizontally extending portions of all layers within the alternating layer stack 30 can lie within a plurality of N vertical planes. Alternatively, for example, if the horizontally extending portions of all layers within the alternating layer stack 30 have a circular shape, an elliptical shape, or a two-dimensional shape consisting of a single curved perimeter, the set of all sidewalls 17 of the horizontally extending portions of all layers within the alternating layer stack 30 can lie within a single vertical plane having a curvature in the horizontal plane. Generally speaking, each outer sidewall of the horizontally extending portion of each layer within the alternating layer stack 30 can lie within a corresponding vertical plane within a set of at least one vertical plane that includes the entire outer perimeter of the alternating layer stack 30. The patterned photoresist layer 130 may then be removed, for example, by ashing.

[0046] Reference Figure 4 An etch stop dielectric layer 36 may be formed over each patterned structure including a corresponding alternating layer stack 30, a node dielectric material layer 32, and an optional dielectric spacer layer 34. A contact-level dielectric layer 38 may be deposited over the etch stop dielectric layer 36. The etch stop dielectric layer 36 may comprise a material that provides resistance to etching chemistries used in a subsequent anisotropic etching process to form contact via cavities through the contact-level dielectric layer 38. For example, the etch stop dielectric layer 36 may comprise silicon nitride, and the contact-level dielectric layer 38 may comprise silicon oxide. Other suitable materials within the contemplated scope of the present disclosure may also be used. The horizontal portion of the etch stop dielectric layer 36 may have a uniform thickness that may range from 10 nm to 100 nm, although lesser or greater thicknesses may also be used.

[0047] The top surface of the contact-level dielectric layer 38 can be planarized by forming the contact-level dielectric layer 38 using a self-planarizing process, such as spin coating, or by chemical mechanical planarization. The thickness of the portion of the contact-level dielectric layer 38 overlying the alternating layer stack 30 can range from 100 nm to 1,000 nm, although lesser or greater thicknesses can also be used.

[0048] An etch-stop dielectric layer 36 overlies each alternating layer stack 30. Each horizontally extending portion of each layer (i.e., 10A, 10B, 20A, 20B, 15) within the alternating layer stack 30 may have vertical sidewalls that are vertically coincident with each other, i.e., sidewalls that lie in the same vertical plane. The entire perimeter of the horizontal bottom surface of the etch-stop dielectric layer 36 overlying the alternating layer stack 30 within the unit capacitor region UC may abut the entire upper perimeter of the vertically extending portion of the etch-stop dielectric layer 36. The vertically extending portion of the etch-stop dielectric layer 36 may laterally wrap around and may contact each outer sidewall of each layer within the alternating layer stack 30 that is located below the horizontal bottom surface of the etch-stop dielectric layer 36. In one embodiment, all interfaces between the vertically extending portion of the etch-stop dielectric layer 36 and the outer sidewall of each layer within the alternating layer stack 30 may be vertical.

[0049] A dielectric capping layer 40 may be formed over the top surface of the contact-level dielectric layer 38. The dielectric capping layer 40 may include a different dielectric material than the dielectric material of the contact-level dielectric layer 38. For example, the dielectric capping layer 40 may include silicon oxynitride having a thickness in a range of 10 nm to 100 nm, although different materials and different thicknesses may also be used for the dielectric capping layer 40.

[0050] Reference Figure 5A photoresist layer 170 may be applied over the dielectric cap layer 40. The photoresist layer 170 may be photolithographically patterned to form discrete openings through the photoresist layer 170. At least as many openings as the total number of metal electrode plates (10A, 20A, 10B, 20B) within the alternating layer stack 30 may be formed in the photoresist layer 170 within each region of the unit capacitor region UC. In one embodiment, the total number of openings through the photoresist layer 170 within each region of the unit capacitor region UC may be the same as the total number of metal electrode plates (10A, 20A, 10B, 20B) within the alternating layer stack 30, or may be an integer multiple of the total number of metal electrode plates (10A, 20A, 10B, 20B).

[0051] An anisotropic etching process may be performed to transfer the pattern of openings in photoresist layer 170 through dielectric cap layer 40, contact-level dielectric layer 38, etch-stop dielectric layer 36, and optional dielectric spacer layer 34. Unmasked portions of dielectric cap layer 40, unmasked portions of contact-level dielectric layer 38, unmasked portions of etch-stop dielectric layer 36, and optional unmasked portions of dielectric spacer layer 34 may be etched through using a series of etching steps that selectively etches the dielectric material at the portion of the dielectric material physically exposed at the bottom-most surface of the cavity relative to the underlying dielectric material. The terminal step of the anisotropic etching process that etches dielectric spacer layer 34 (or etch-stop dielectric layer 36 if dielectric spacer layer 34 is omitted) may be selective to the material of node dielectric material layer 32.

[0052] Contact via cavities (41A, 43A, 41B, 43B) may be formed through the stack of dielectric cap layer 40, contact-level dielectric layer 38, etch-stop dielectric layer 36, and optional dielectric spacer layer 34. Each of the contact via cavities (41A, 43A, 41B, 43B) may have a corresponding set of at least one straight sidewall extending vertically from the top surface of dielectric cap layer 40 to the top surface of node dielectric material layer 32. Each straight sidewall of the via cavity (41A, 43A, 41B, 43B) may be vertical or may have a finite taper angle greater than zero. The taper angle of the sidewalls of the via cavities (41A, 43A, 41B, 43B) may be less than 5 degrees and / or may be less than 2 degrees. The via cavities (41A, 43A, 41B, 43B) may have the same depth, which is the sum of the thickness of the dielectric cap layer 40, the thickness of the contact-level dielectric layer 38, the thickness of the etch-stop dielectric layer 36, and the thickness of the optional dielectric spacer layer 34. A portion of the top surface of the node dielectric material layer 32 may be physically exposed at the bottom of each contact via cavity (41A, 43A, 41B, 43B). Each of the contact via cavities (41A, 43A, 41B, 43B) may have a bottom surface located above the topmost layer in the alternating layer stack 30.

[0053] The contact via cavities (41A, 43A, 41B, 43B) may include main node contact via cavities (41A, 43A) and complementary node contact via cavities (41B, 43B). The main node contact via cavities (41A, 43A) may be cavities that are subsequently used to provide electrical contact to components of the main electrode assembly. The main electrode assembly may include at least two main node metal plates, such as a first metal electrode plate 10A and a third metal electrode plate 10B. For example, the main node contact via cavities (41A, 43A) may include: a first contact via cavity 41A (which includes a first subset of contact via cavities), which may then be used to form a plate contact via structure that contacts the corresponding first metal electrode plate 10A; and a third contact via cavity 43A (which includes a third subset of contact via cavities), which may then be used to form a plate contact via structure that contacts the corresponding third metal electrode plate 10B. The complementary node contact via cavities (41B, 43B) can be cavities that can subsequently be used to provide electrical contact to components of a complementary electrode assembly, which includes at least one complementary node metal plate, such as the second metal electrode plate 20A and the fourth metal electrode plate 20B. For example, the complementary node contact via cavities (41B, 43B) can include: a second contact via cavity 41B (which includes a second subset of contact via cavities), which can subsequently be used to form a plate contact via structure that contacts the corresponding second metal electrode plate 10B; and a fourth contact via cavity 43B, which can subsequently be used to form a plate contact via structure that contacts the corresponding fourth metal electrode plate 20B. The photoresist layer 170 can then be removed, for example, by ashing.

[0054] Figures 6A to 6C 1 are sequential vertical cross-sectional views of an exemplary structure during selective vertical extension of contact via cavities (41A, 41B, 43A, 43B) according to a first patterning scheme according to an embodiment of the present disclosure. Generally speaking, the depth of each subset of contact via cavities (41A, 41B, 43A, 43B) can be selectively increased by performing a combination of at least two processing steps including an etch mask formation process and an etch process. Figures 6A to 6C Each of them shows a corresponding combination of processing steps including an etch mask forming process and an etching process.

[0055] Reference Figure 6AA first patterned photoresist layer 171 may be applied over the dielectric cap layer 40 and the contact-level dielectric layer 38. The first patterned photoresist layer 171 may be photolithographically patterned to cover the fourth contact via cavity 43B and not cover the first contact via cavity 41A, the second contact via cavity 41B, or the third contact via cavity 43A. The first patterned photoresist layer 171 may serve as an etch mask for a subsequent etching process, referred to herein as a first etching process. The first etching process etches through the unmasked portion of the node dielectric material layer 32 and the unmasked portion of the metal electrode plate, which may be the fourth metal electrode plate 20B. In one embodiment, each metal electrode plate (10A, 10B, 20A, 20B) may include a conductive metal nitride material, and / or may be essentially composed of a conductive metal nitride material, and each node dielectric layer 15 and node dielectric material layer 32 may include a dielectric metal oxide material having a dielectric constant greater than 7.9, and / or may be essentially composed of a dielectric metal oxide material having a dielectric constant greater than 7.9. In one embodiment, the first etching process may include: a first step of selectively etching the dielectric metal oxide material relative to the conductive metal nitride material; and a second step of selectively etching the conductive metal nitride material relative to the dielectric metal oxide material. The first etching step may include a first anisotropic etching step, wherein the first anisotropic etching step has an etching chemistry that selectively etches the dielectric metal oxide material relative to the conductive metal nitride material. The second etching step may include a second anisotropic etching step, wherein the second anisotropic etching step has a chemistry that selectively etches the conductive metal nitride material relative to the dielectric metal oxide material. The duration of each etching step can be selected so that each of the first contact via cavity 41A, the second contact via cavity 41B, and the third contact via cavity 43A can vertically extend to the top surface of the topmost node dielectric layer 15, which is located in the same horizontal plane as the bottom surface of the fourth metal electrode plate 20B. The first patterned photoresist layer 171 can then be removed, for example, by ashing.

[0056] Reference Figure 6BA second patterned photoresist layer 172 may be applied over the dielectric cap layer 40 and the contact-level dielectric layer 38. The second patterned photoresist layer 172 may be photolithographically patterned to cover the third contact via cavity 43A and the fourth contact via cavity 43B and not cover the first contact via cavity 41A or the second contact via cavity 41B. The second patterned photoresist layer 172 may be used as an etch mask for a subsequent etching process, referred to herein as a second etching process. The second etching process etches through the unmasked portion of the topmost node dielectric layer 15 and the unmasked portion of the metal electrode plate, which may be the third metal electrode plate 20A. In an embodiment where each metal electrode plate (10A, 10B, 20A, 20B) comprises a conductive metal nitride material, and / or consists essentially of a conductive metal nitride material, and each node dielectric layer 15 and node dielectric material layer 32 comprises a dielectric metal oxide material having a dielectric constant greater than 7.9, and / or consists essentially of a dielectric metal oxide material having a dielectric constant greater than 7.9, the second etching process may include: a first step of selectively etching the dielectric metal oxide material relative to the conductive metal nitride material; and a second step of selectively etching the conductive metal nitride material relative to the dielectric metal oxide material. The first etching step may include a first anisotropic etching step having an etching chemistry that selectively etches the dielectric metal oxide material relative to the conductive metal nitride material. The second etching step may include a second anisotropic etching step having an etching chemistry that selectively etches the conductive metal nitride material relative to the dielectric metal oxide material. The duration of each etching step can be selected so that each of the first contact via cavity 41A and the second contact via cavity 41B can extend vertically to the top surface of the intermediate node dielectric layer 15, which is located in the same horizontal plane as the bottom surface of the third metal electrode plate 20A. The second patterned photoresist layer 172 can then be removed, for example, by ashing.

[0057] Reference Figure 6CA third patterned photoresist layer 173 may be applied over the dielectric cap layer 40 and the contact-level dielectric layer 38. The third patterned photoresist layer 173 may be photolithographically patterned to cover the second contact via cavity 41B, the third contact via cavity 43A, and the fourth contact via cavity 43B, while not covering the first contact via cavity 41A. The third patterned photoresist layer 173 may serve as an etch mask for a subsequent etching process, referred to herein as a third etching process. The third etching process etches through the unmasked portion of the intermediate node dielectric layer 15 and the unmasked portion of the metal electrode plate, which may be the second metal electrode plate 10B. In an embodiment where each metal electrode plate (10A, 10B, 20A, 20B) comprises a conductive metal nitride material, and / or consists essentially of a conductive metal nitride material, and each node dielectric layer 15 and node dielectric material layer 32 comprises a dielectric metal oxide material having a dielectric constant greater than 7.9, and / or consists essentially of a dielectric metal oxide material having a dielectric constant greater than 7.9, the third etching process may include: a first step of selectively etching the dielectric metal oxide material relative to the conductive metal nitride material; and a second step of selectively etching the conductive metal nitride material relative to the dielectric metal oxide material. The first etching step may include a first anisotropic etching step having an etching chemistry that selectively etches the dielectric metal oxide material relative to the conductive metal nitride material. The second etching step may include a second anisotropic etching step having an etching chemistry that selectively etches the conductive metal nitride material relative to the dielectric metal oxide material. The duration of each etching step can be selected so that each of the first contact via cavities 41A can extend vertically to the top surface of the bottommost node dielectric layer 15, which is located in the same horizontal plane as the bottom surface of the second metal electrode plate 10B. The third patterned photoresist layer 173 can then be removed, for example, by ashing.

[0058] Figures 7A to 7C 1 is a sequential vertical cross-sectional view of an exemplary structure during selective vertical extension of the contact via cavities (41A, 41B, 43A, 43B) according to a second patterning scheme according to an embodiment of the present disclosure. As described above, the depth of each subset of the contact via cavities (41A, 41B, 43A, 43B) can be selectively increased by performing a combination of at least two processing steps including an etch mask formation process and an etching process. Figures 7A to 7C Each of them shows a corresponding combination of processing steps including an etch mask forming process and an etching process.

[0059] Reference Figure 7AA first patterned photoresist layer 271 may be applied over the dielectric cap layer 40 and the contact-level dielectric layer 38. The first patterned photoresist layer 271 may be photolithographically patterned to cover the second contact via cavity 41B, the third contact via cavity 43A, and the fourth contact via cavity 43B, while not covering the first contact via cavity 41A. The first patterned photoresist layer 271 may serve as an etch mask for a subsequent etching process, referred to herein as a first etching process. The first etching process etches through the unmasked portion of the node dielectric material layer 32 and the unmasked portion of the metal electrode plate, which may be the fourth metal electrode plate 20B. In one embodiment, each metal electrode plate (10A, 10B, 20A, 20B) may include a conductive metal nitride material, and / or may be essentially composed of a conductive metal nitride material, and each node dielectric layer 15 and node dielectric material layer 32 may include a dielectric metal oxide material having a dielectric constant greater than 7.9, and / or may be essentially composed of a dielectric metal oxide material having a dielectric constant greater than 7.9. In such an embodiment, the first etching process may include: a first step of selectively etching the dielectric metal oxide material relative to the conductive metal nitride material. A second step may selectively etch the conductive metal nitride material relative to the dielectric metal oxide material. The first etching step may include a first anisotropic etching step, wherein the first anisotropic etching step has an etching chemistry that selectively etches the dielectric metal oxide material relative to the conductive metal nitride material. The second etching step may include a second anisotropic etching step, wherein the second anisotropic etching step has an etching chemistry that selectively etches the conductive metal nitride material relative to the dielectric metal oxide material. The duration of each etching step may be selected so that each of the first contact via cavities 41A extends vertically to the top surface of the topmost node dielectric layer 15 , which lies in the same horizontal plane as the bottom surface of the fourth metal electrode plate 20B.

[0060] In one embodiment, the first patterned photoresist layer 271 may then be removed, for example, by ashing. In another embodiment, the first patterned photoresist layer 271 may include a trimmable photoresist material that may be isotropically trimmed by a controlled ashing process. In such an embodiment, the second contact via cavity 41B, the third contact via cavity 43A, and the fourth contact via cavity 43B may be geometrically arranged such that the third contact via cavity 43A and the fourth contact via cavity 43B may remain covered by the trimmed portion of the trimmable photoresist material after the trimming process, while the second contact via cavity 41B may become physically exposed (i.e., not covered by the trimmed portion of the trimmable photoresist material). In such an embodiment, the trimmed portion of the trimmable photoresist material may be used as Figure 7B The second patterned photoresist layer 272 is shown in FIG.

[0061] Reference Figure 7B , a second patterned photoresist layer 272 can be provided as a trimmed portion of the trimmable photoresist material. Alternatively, the first patterned photoresist layer 271 can be removed by ashing, and a second photoresist material can be applied over the dielectric cap layer 40 and the contact-level dielectric layer 38. The second photoresist material can be photolithographically patterned to provide a second patterned photoresist layer 272. The second patterned photoresist layer 272 covers the third contact via cavity 43A and the fourth contact via cavity 43B, and does not cover the first contact via cavity 41A or the second contact via cavity 41B. The second patterned photoresist layer 272 can be used as an etch mask for a subsequent etching process, which is referred to herein as a second etching process. The second etching process can etch through the unmasked portion of the node dielectric material layer 32 and the unmasked portion of the topmost node dielectric layer 15, and can then etch through the unmasked portion of the underlying metal electrode plate, which can be the third metal electrode plate 20A for each first contact through-hole cavity 41A or the fourth metal electrode plate 20B for each second contact through-hole cavity 41B. In an embodiment where each metal electrode plate (10A, 10B, 20A, 20B) comprises a conductive metal nitride material, and / or consists essentially of a conductive metal nitride material, and each node dielectric layer 15 and node dielectric material layer 32 comprises a dielectric metal oxide material having a dielectric constant greater than 7.9, and / or consists essentially of a dielectric metal oxide material having a dielectric constant greater than 7.9, the second etching process may include: a first step of selectively etching the dielectric metal oxide material relative to the conductive metal nitride material; and a second step of selectively etching the conductive metal nitride material relative to the dielectric metal oxide material. The first etching step may include a first anisotropic etching step having an etching chemistry that selectively etches the dielectric metal oxide material relative to the conductive metal nitride material. The second etching step may include a second anisotropic etching step having an etching chemistry that selectively etches the conductive metal nitride material relative to the dielectric metal oxide material. The duration of each etching step can be selected so that each of the first contact via cavities 41A extends vertically to the top surface of the middle node dielectric layer 15, which lies in the same horizontal plane as the bottom surface of the third metal electrode plate 20A. Each of the second contact via cavities 41B extends vertically to the top surface of the top node dielectric layer 15, which lies in the same horizontal plane as the bottom surface of the fourth metal electrode plate 20B.

[0062] In an embodiment, the second patterned photoresist layer 272 may then be removed, for example, by ashing. In another embodiment, the second patterned photoresist layer 272 may include a trimmable photoresist material that may be isotropically trimmed by a controlled ashing process. In such an embodiment, the third contact via cavity 43A and the fourth contact via cavity 43B may be geometrically arranged such that the fourth contact via cavity 43B may remain covered by the trimmed portion of the trimmable photoresist material after the trimming process, while the third contact via cavity 43A becomes physically exposed (i.e., not covered by the trimmed portion of the trimmable photoresist material). In this case, the trimmed portion of the trimmable photoresist material may be used as a Figure 7C The third patterned photoresist layer 273 is shown in FIG.

[0063] Reference Figure 7C, the third patterned photoresist layer 273 can be provided as a trimmed portion of the trimmable photoresist material. Alternatively, the second patterned photoresist layer 272 can be removed by ashing, and a third photoresist material can be applied over the dielectric cap layer 40 and the contact-level dielectric layer 38, and the third photoresist material can be photolithographically patterned to provide a third patterned photoresist layer 273. The third patterned photoresist layer 273 can cover the fourth contact via cavity 43B and not cover the first contact via cavity 41A, the second contact via cavity 41B, or the third contact via cavity 43A. The third patterned photoresist layer 273 can be used as an etch mask for a subsequent etching process, which is referred to herein as a third etching process. The third etching process etches through the unmasked portion of the node dielectric material layer 32, the unmasked portion of the topmost node dielectric layer 15 and the unmasked portion of the intermediate node dielectric layer 15, and then etches through the unmasked portion of the underlying metal electrode plate, which may be the second metal electrode plate 10B for each first contact through-hole cavity 41A, the third metal electrode plate 20A for each second contact through-hole cavity 41B, or the fourth metal plate 20B for each third contact through-hole cavity 43A. In an embodiment where each metal electrode plate (10A, 10B, 20A, 20B) comprises a conductive metal nitride material, and / or consists essentially of a conductive metal nitride material, and each node dielectric layer 15 and node dielectric material layer 32 comprises a dielectric metal oxide material having a dielectric constant greater than 7.9, and / or consists essentially of a dielectric metal oxide material having a dielectric constant greater than 7.9, the third etching process may include: a first step of selectively etching the dielectric metal oxide material relative to the conductive metal nitride material; and a second step of selectively etching the conductive metal nitride material relative to the dielectric metal oxide material. The first etching step may include a first anisotropic etching step having an etching chemistry that selectively etches the dielectric metal oxide material relative to the conductive metal nitride material. The second etching step may include a second anisotropic etching step having an etching chemistry that selectively etches the conductive metal nitride material relative to the dielectric metal oxide material. The duration of each etching step can be selected so that each of the first contact via cavities 41A extends vertically to the top surface of the bottom node dielectric layer 15, which lies in the same horizontal plane as the bottom surface of the second metal electrode plate 10A. Each of the second contact via cavities 41B extends vertically to the top surface of the intermediate node dielectric layer 15, which lies in the same horizontal plane as the bottom surface of the third metal electrode plate 20A.Each of the third contact via cavities 43A extends vertically to the top surface of the top node dielectric layer 15, which lies in the same horizontal plane as the bottom surface of the fourth metal electrode plate 20B. The third patterned photoresist layer 273 may then be removed, for example, by ashing.

[0064] Figure 8 An exemplary structure after removal of the third patterned photoresist layer (173, 273) is shown. Although the present disclosure is described using an embodiment in which four metal electrode plates (10A, 10B, 20A, 20B) are used, embodiments in which a different total number of metal electrode plates are used within each alternating layer stack of metal electrode plates and node dielectric layers 15 are expressly contemplated herein. In such an embodiment, multiple groups of contact via cavities may be formed that extend vertically to the top surfaces of different node dielectric layers 15 or the top surfaces of node dielectric material layers 32. Each node dielectric layer 15 within each alternating layer stack and the node dielectric material layer 32 overlying the corresponding alternating layer stack 30 may have a corresponding portion of the top surface that is physically exposed to an overlying contact via cavity (41A, 41B, 43A, 43B).

[0065] Reference Figure 9 , the physically exposed sidewalls of the metal electrode plates (10A, 10B, 20A, 20B) can be selectively laterally recessed relative to the node dielectric layer 15 and the node dielectric material layer 32. For example, if the metal electrode plates (10A, 10B, 20A, 20B) include a metal nitride material and if the node dielectric layer 15 and the node dielectric material layer 32 include a dielectric metal oxide material, a wet etching process can be performed that selectively etches the metal nitride material relative to the dielectric metal oxide material. For example, a wet etching solution including diluted ammonium hydroxide and optionally hydrogen peroxide can be used to selectively laterally recess the physically exposed sidewalls of the metal electrode plates (10A, 10B, 20A, 20B) around each contact via cavity (41A, 41B, 43A, 43B) relative to the dielectric metal oxide material of the node dielectric layer 15 and the node dielectric material layer 32. The lateral recess distance of the isotropic etching process may be in the range of 1 nm to 10 nm, but smaller and larger lateral etch distances may also be used.

[0066] Generally speaking, Figures 6A to 6C or Figures 7A to 7CAt the processing step of, after performing at least two combinations of processing steps to vertically extend the contact through-hole cavity (41A, 41B, 43A, 43B), the physically exposed sidewalls of the horizontally extending portions of the at least three metal electrode plates (10A, 10B, 20A, 20B) can be laterally recessed by selectively isotropically etching the conductive metal nitride material of the at least three metal electrode plates (10A, 10B, 20A, 20B) relative to the dielectric metal oxide material of the node dielectric layer 15. The bottommost metal electrode plate (e.g., the first metal electrode plate 10A) is not physically exposed to the isotropic etchant of the isotropic etching process. Each metal electrode plate other than the bottommost electrode plate has at least one sidewall physically exposed to the isotropic etchant.

[0067] Reference Figure 10 , a terminal node dielectric etching process may be performed. The terminal node dielectric etching process may be an isotropic etching process that isotropically etches the physically exposed portions of the node dielectric layer 15 and the node dielectric material layer 32 around and below each contact via cavity (41A, 41B, 43A, 43B). In one embodiment, the terminal node dielectric etching process may include a wet etching process that selectively etches the dielectric metal oxide material of the node dielectric layer 15 and the node dielectric material layer 32 relative to the conductive metal nitride material of the metal electrode plates (10A, 10B, 20A, 20B). The duration of the terminal node dielectric etch process can be selected so that the etching passes through each portion of the node dielectric layer 15 and the node dielectric material layer 32 located below the contact through-hole cavity (41A, 41B, 43A, 43B) and the top surface of each underlying metal electrode plate (10A, 10B, 20A, 20B) is physically exposed below each contact through-hole cavity (41A, 41B, 43A, 43B).

[0068] The etching chemistry of the terminal node dielectric etching process may be selective with respect to the material of the metal electrode plates (10A, 10B, 20A, 20B) (i.e., the material of the metal electrode plates (10A, 10B, 20A, 20B) is not etched). In such an embodiment, the bottom surface of each contact via cavity (41A, 41B, 43A, 43B) may be flush with the horizontal interface between the top surface of the underlying metal electrode plate (10A, 10B, 20A, 20B) and the bottom surface of one of the node dielectric layer 15 and the node dielectric material layer 32 that contacts the underlying metal electrode plate (10A, 10B, 20A, 20B). In other words, the bottom surface of each contact via cavity (41A, 41B, 43A, 43B) may be located within a horizontal plane that includes the top surface of the corresponding contact via cavity (41A, 41B, 43A, 43B). B) directly below the top surface of the metal electrode plate (10A, 10B, 20A, 20B). The lateral protruding portions of the node dielectric layer 15 and the node dielectric material layer 32 located at the peripheral portion of the contact via cavity (41A, 41B, 43A, 43B) can be removed in parallel during the terminal node dielectric etching process, so that the physically exposed sidewalls of the node dielectric layer 15 and the node dielectric material layer 32 can be roughly aligned with the recessed sidewalls of the metal electrode plate (10A, 10B, 20A, 20B). Therefore, the contact via cavity (41A, 41B, 43A, 43B) can have a bottle-shaped vertical cross-sectional profile, wherein the bottommost portion of the contact via cavity (41A, 41B, 43A, 43B) has a larger lateral dimension than the overlying portion of the contact via cavity (41A, 41B, 43A, 43B) having straight sidewalls.

[0069] Reference Figure 11A A continuous dielectric liner layer may be conformally deposited on the sidewalls of the contact via cavities (41A, 41B, 43A, 43B), on the physically exposed portions of the top surfaces of the metal electrode plates (10A, 10B, 20A, 20B), and on the contact-level dielectric layer 38. The continuous dielectric liner layer comprises a dielectric material (e.g., silicon nitride). Other suitable materials within the contemplated scope of the present disclosure may also be used. The continuous dielectric liner layer may be deposited by a conformal deposition process (e.g., low pressure chemical vapor deposition). The thickness of the continuous dielectric liner layer may be less than 25% (e.g., less than 10% and / or less than 5%) of the lateral dimension (e.g., diameter) of each contact via cavity (41A, 41B, 43A, 43B). For example, the continuous dielectric liner layer may have a thickness in the range of 1 nm to 30 nm, but greater thicknesses may also be used.

[0070] An anisotropic etching process may be performed to remove horizontal portions of the continuous dielectric liner layer. The remaining vertical portions of the continuous dielectric liner layer constitute dielectric contact via liners (51A, 51B, 53A, 53B). The dielectric contact via liners (51A, 51B, 53A, 53B) may include: a first dielectric contact via liner 51A formed in a corresponding one of the first contact via cavities 41A; a second dielectric contact via liner 51B formed in a corresponding one of the second contact via cavities 41B; a third dielectric contact via liner 53A formed in a corresponding one of the third contact via cavities 43A; and a fourth dielectric contact via liner 53B formed in a corresponding one of the fourth contact via cavities 43B. Each dielectric contact via liner (51A, 51B, 53A, 53B) may have a uniform lateral thickness, which may be in the range of 1 nm to 30 nm.

[0071] Each of the dielectric contact via liners (51A, 51B, 53A, 53B) may have a tubular configuration and may include a respective cylindrical inner sidewall and a respective outer sidewall laterally spaced apart from each other by a uniform lateral separation distance (i.e., the thickness of the contact via liner). Each void laterally surrounded by the first dielectric contact via liner 51A is referred to herein as a first void 42A, each void laterally surrounded by the second dielectric contact via liner 51B is referred to herein as a second void 42B, each void laterally surrounded by the third dielectric contact via liner 53A is referred to herein as a third void 44A, and each void laterally surrounded by the fourth dielectric contact via liner 53B is referred to herein as a fourth void 44B, each of the first void 42A, the second void 42B and the third void 44A may have a bulging portion at the bottommost portion, the bulging portion overlying the physically exposed top surface of the corresponding metal electrode plate (10A, 10B, 20A, 20B).

[0072] Each first dielectric contact via liner 51A may contact the sidewalls of the horizontally extending portion of at least two metal electrode plates selected from the at least three metal electrode plates, such as the sidewalls of the second metal electrode plate 10B, the sidewalls of the third metal electrode plate 20A, and the sidewalls of the fourth metal electrode plate 20B. Each second dielectric contact via liner 51B may contact the sidewalls of the horizontally extending portion of at least one metal electrode plate selected from the at least three metal electrode plates, such as the sidewalls of the third metal electrode plate 20A and the sidewalls of the fourth metal electrode plate 20B. Each third dielectric contact via liner 53A may contact the sidewall of the fourth metal electrode plate 20B.

[0073] Reference Figure 11B, the node dielectric layer 15 at the bottom of each of the contact via cavities (41A, 41B, 43A, 43B) can be anisotropically etched to form Figure 9 The exemplary structure shown in derives an alternative embodiment of the exemplary structure. The top surface of the metal electrode plates (10A, 10B, 20A, 20B) is physically exposed at the bottom of each contact via cavity (41A, 41B, 43A, 43B). Figure 11B In the alternative embodiment shown in FIG, the Figure 10 The processing steps are shown. Subsequently, you can execute Figure 11A The process steps shown are to form dielectric contact via liners (51A, 51B, 53A, 53B). Specifically, a continuous dielectric liner layer can be conformally deposited on the sidewalls of the contact via cavities (41A, 41B, 43A, 43B), on the physically exposed portions of the top surfaces of the metal electrode plates (10A, 10B, 20A, 20B), and on the contact-level dielectric layer 38, and the horizontal portions of the continuous dielectric liner layer can be removed by performing an anisotropic etching process. The remaining portions of the continuous dielectric liner layer include the dielectric contact via liners (51A, 51B, 53A, 53B). In one embodiment, the first dielectric contact via liner 51A, the second dielectric contact via liner 51B, and the third dielectric contact via liner 53A may include a corresponding set of at least one annular dielectric edge that protrudes laterally outward toward the laterally recessed surface of the metal electrode plates (10A, 10B, 20A, 20B). The resulting first dielectric contact via liner 51A, the second dielectric contact via liner 51B, the third dielectric contact via liner 53A, and the fourth dielectric contact via liner 53B may provide improved performance to reduce leakage current.

[0074] Reference Figure 12At least one conductive material may be deposited in the unfilled volume of the contact via cavity (41A, 41B, 43A, 43B) (i.e., within the void (42A, 42B, 44A, 44B) laterally surrounded by a respective one of the dielectric contact via liners (51A, 51B, 53A, 53B)). The at least one conductive material may include, for example, a combination of a metal nitride liner material and a metal fill material. For example, a metal nitride liner layer comprising a metal nitride material (e.g., TiN, TaN, and / or WN) may be deposited in the void (42A, 42B, 44A, 44B), and a metal fill material (e.g., W, Cu, Mo, Co, Ru, or alloys or combinations thereof) may fill the remaining volume of the void (42A, 42B, 44A, 44B). Other suitable materials within the contemplated scope of the present disclosure may also be used. Excess portions of the at least one metallic material may be removed from above a horizontal plane including the top surface of the dielectric cap layer 40 by a planarization process, which may use recess etching and / or chemical mechanical planarization.

[0075] Each remaining portion of the at least one conductive material filling the corresponding void (42A, 42B, 44A, 44B) constitutes a plate contact via structure (52A, 52B, 54A, 54B). A combination of a dielectric contact via liner (51A, 51B, 53A, 53B) and a plate contact via structure (52A, 52B, 54A, 54B) may be formed within each of the contact via cavities (41A, 41B, 43A, 43B). Specifically, a combination of a first dielectric contact via liner 51A and a first plate contact via structure 52A may be formed within each first contact via cavity 41A. A combination of a second dielectric contact via liner 51B and a second plate contact via structure 52B may be formed within each second contact via cavity 41B. A combination of a third dielectric contact via liner 53A and a third plate contact via structure 54A may be formed within each third contact via cavity 43A. A combination of a fourth dielectric contact via liner 53B and a fourth plate contact via structure 54B may be formed within each fourth contact via cavity 43B. Each first plate contact via structure 52A contacts the top surface of the first metal electrode plate 10A. Each second plate contact via structure 52B contacts the top surface of the second metal electrode plate 10B. Each third plate contact via structure 54A contacts the top surface of the third metal electrode plate 20A. Each fourth plate contact via structure 54B contacts the top surface of the fourth metal electrode plate 20B.

[0076] In one embodiment, each of the first plate contact via structure 52A, each of the second plate contact via structure 52B, and each of the third plate contact via structure 54A may have a protruding portion, the protruding portion being located below the columnar portion, and the columnar portion having a smaller maximum lateral dimension than the protruding portion. Each columnar portion of the first plate contact via structure 52A, each columnar portion of the second plate contact via structure 52B, and each columnar portion of the third plate contact via structure 54A may have a corresponding straight sidewall, which may be a vertical sidewall or a tapered sidewall. Each protruding portion of the first plate contact via structure 52A, each protruding portion of the second plate contact via structure 52B, and each protruding portion of the third plate contact via structure 54A contacts a corresponding underlying metal electrode plate among the metal electrode plates (10A, 10B, 20A, 20B), which may be the first metal electrode plate 10A, the second metal electrode plate 10B, or the third metal electrode plate 20A.

[0077] Reference Figure 13A and Figure 13B A line-level dielectric layer 60 may be formed over the dielectric cap layer 40. The line-level dielectric layer 60 comprises a dielectric material such as undoped silicate glass or doped silicate glass. The thickness of the line-level dielectric layer 60 may range from 100 nm to 400 nm, although lesser or greater thicknesses may also be used.

[0078] Metal interconnect structures (62, 64) can be formed in the line-level dielectric layer 60, for example, by patterning line trenches through the line-level dielectric layer 60 and filling the line trenches with at least one metal material, such as a combination of a metal nitride liner (e.g., TiN) and a metal filler material (e.g., Cu). Other suitable materials within the contemplated scope of the present disclosure may also be used. Excess portions of the at least one metal material can be removed from a horizontal plane above the top surface of the line-level dielectric layer 60 by, for example, a planarization process (e.g., a chemical mechanical planarization process). The remaining portions of the at least one metal material filling the respective line trenches constitute metal lines (62, 64). The metal lines (62, 64) include: at least one first metal line 62 contacting a respective subset or all of the first plate contact via structure 52A and the third plate contact via structure 54A; and at least one second metal line 64 contacting a respective subset or all of the second plate contact via structure 52B and the fourth plate contact via structure 54B. The at least one first metal line 62 may be formed as a plurality of metal lines, or as a single continuous metal line including a plurality of fingers extending over and contacting each of the first and third plate contact via structures 52A, 54A. Similarly, the at least one second metal line 64 may be formed as a plurality of metal lines, or as a single continuous metal line including a plurality of fingers extending over and contacting each of the second and fourth plate contact via structures 52B, 54B. Each of the first and third plate contact via structures 52A, 54A may be contacted by a corresponding first metal line 62, and each of the second and fourth plate contact via structures 52A, 54B may be contacted by a corresponding second metal line 64. Generally speaking, the metal interconnect structure formed in at least one dielectric material layer may be formed over the board contact via structure (52A, 52B, 54A, 54B).

[0079] In one embodiment, each first metal line 62 and each second metal line 64 may include a pad region having sufficient area for forming a bonding structure (e.g., a solder ball) on the pad region. A passivation dielectric layer 80 may be formed over the line-level dielectric layer 60. The passivation dielectric layer 80 may include a dielectric diffusion barrier material (e.g., silicon nitride). The thickness of the passivation dielectric layer 80 may range from 50 nm to 200 nm, although lesser or greater thicknesses may also be used. The passivation dielectric layer 80 may include an opening in each area of ​​the physically exposed surface of the first metal line 62 or the second metal line 64 where a bonding structure (e.g., a solder ball) will be bonded.

[0080] An exemplary structure may be formed on a semiconductor substrate (e.g., a semiconductor wafer), and then the exemplary structure may be cut into semiconductor dies 100. Each semiconductor die 100 may include at least one deep trench capacitor. Each deep trench capacitor may be formed over a plurality of unit capacitor regions UC, or each deep trench capacitor may be formed over a single unit capacitor region UC. The semiconductor die 100 may be provided as a standalone capacitor die, or may be provided as an integrated semiconductor die including deep trench capacitors and other semiconductor devices (e.g., complementary metal-oxide-semiconductor (CMOS) transistors).

[0081] Reference Figure 13C , showing Figure 13A and Figure 13B Alternative embodiments of the exemplary structures at the processing steps shown. Figure 11B The structure shown then executes Figure 12 、 Figure 13A and Figure 13B The process steps shown are repeated to obtain an alternative embodiment of the exemplary structure.

[0082] Reference Figure 14 , showing Figure 13B Non-limiting exemplary applications of semiconductor die 100 are shown. Semiconductor die 100 can be attached to the land side of a system-on-a-chip (SoC) die 200, which is then bonded to an integrated fan-out package on package (InFO PoP) die 300 via a solder ball array 250. SoC die 200 can be bonded to another module (e.g., a printed circuit board (PCB)) via another solder ball array 150. Deep trench capacitors in semiconductor die 100 can stabilize the power supply system in SoC die 200.

[0083] Reference Figures 1 to 14According to one aspect of the present disclosure, a deep trench capacitor may be provided. The deep trench capacitor may include: at least one deep trench 9 extending downward from the top surface of a substrate 8; and a layer stack 30 including at least three metal electrode plates (10A, 10B, 20A, 20B) interlaced with at least two node dielectric layers 15. Each layer within the layer stack 30 may include a corresponding vertical extension located within each of the at least one deep trench 9 and a corresponding horizontal extension located above the top surface of the substrate 8. The main electrode assembly (10A, 20A, 52A, 54A, 62) includes at least two main metal electrode plates (10A, 20A) selected from the at least three metal electrode plates (10A, 10B, 20A, 20B). The complementary electrode assembly (10B, 20B, 52B, 54B, 64) includes at least one complementary metal electrode plate (10B, 20B) selected from the at least three metal electrode plates (10A, 10B, 20A, 20B). Each layer in the layer stack 30 has a corresponding sidewall (which contacts the etch stop dielectric layer 36) contained within a vertical plane that includes a segment of the outer perimeter of the layer stack 30.

[0084] In some embodiments of the deep trench capacitor, each outer sidewall of the horizontally extending portion of each layer in the layer stack lies within a corresponding vertical plane within a set of at least one vertical plane that includes the entire outer perimeter of the layer stack.

[0085] In some embodiments, the deep trench capacitor further includes an etch stop dielectric layer overlying the layer stack, wherein the entire perimeter of the horizontal bottom surface of the etch stop dielectric layer is adjacent to the entire upper perimeter of the vertically extending portion of the etch stop layer, and the vertically extending portion of the etch stop layer laterally surrounds and contacts each outer side wall of each layer in the layer stack.

[0086] In some embodiments of the deep trench capacitor, all interfaces between the vertically extending portion of the etch stop dielectric layer and the outer sidewalls of each layer in the layer stack are vertical.

[0087] In some embodiments, the deep trench capacitor further includes a plate contact via structure contacting a top surface of a corresponding one of the at least three metal electrode plates.

[0088] In some embodiments of the deep trench capacitor, each interface between the plate contact via structure and the at least three metal electrode plates lies within a horizontal plane including a top surface of a respective one of the at least three metal electrode plates.

[0089] In some embodiments of the deep trench capacitor, each of the plate contact via structures is laterally surrounded by a corresponding dielectric contact via liner having a uniform lateral thickness.

[0090] In some embodiments of the deep trench capacitor, wherein: a first dielectric contact via liner selected from the dielectric contact via liner contacts the sidewalls of the horizontally extending portions of at least two metal electrode plates selected from the at least three metal electrode plates; and a second dielectric contact via liner selected from the dielectric contact via liner contacts the sidewalls of the horizontally extending portions of at least one metal electrode plate selected from the at least three metal electrode plates.

[0091] In some embodiments of the deep trench capacitor, at least two of the plate contact through-hole structures include a protrusion that contacts a corresponding one of the at least three metal electrode plates and is located below a columnar portion, the columnar portion having a smaller maximum lateral dimension than the protrusion.

[0092] In some embodiments of the deep trench capacitor, it also includes: a metal interconnect structure, which is formed in at least one dielectric material layer, and the metal interconnect structure is overlying the plate contact through-hole structure, wherein: the at least two main metal electrode plates are electrically connected to each other through a first subset of the plate contact through-hole structure and a first subset of the metal interconnect structure; and the at least one complementary metal electrode plate includes at least two complementary metal electrode plates electrically connected to each other through a second subset of the plate contact through-hole structure and a second subset of the metal interconnect structure.

[0093] In some embodiments of the deep trench capacitor, wherein: each of the at least three metal electrode plates comprises a conductive metal nitride material; and each of the at least two node dielectric layers comprises a dielectric metal oxide material having a dielectric constant greater than 7.9.

[0094] Various embodiments disclosed herein provide structures and methods for forming deep trench capacitors with reliable electrical contact structures having reduced electrical opens and shorts. The methods disclosed herein for forming deep trench capacitors form electrical contacts to metal electrode plates without electrical opens or shorts. By providing reliable electrical contact between the plate contact via structure and the metal electrode plate, the various embodiments disclosed herein can provide higher yields and enhanced durability of deep trench capacitors during device fabrication.

[0095] In one embodiment, the at least two main metal electrode plates (10A, 20A) are electrically connected to each other through a first subset (52A, 54A) of plate contact via structures (52A, 52B, 54A, 54B) and a first subset (e.g., at least one first metal line 62) of metal interconnect structures (62, 64). The at least one complementary metal electrode plate (10B, 20B) may include at least two complementary metal electrode plates (10B, 20B), and the at least two complementary metal electrode plates (10B, 20B) are electrically connected to each other through a second subset (52B, 54B) of plate contact via structures (52A, 52B, 54A, 54B) and a second subset (e.g., at least one second metal line 64) of metal interconnect structures (62, 64).

[0096] In one embodiment, the plate contact via structures (52A, 52B, 54A, 54B) may contact the top surface of a corresponding one of the at least three metal electrode plates (10A, 10B, 20A, 20B). In one embodiment, each interface between the plate contact via structures (52A, 52B, 54A, 54B) and the at least three metal electrode plates (10A, 10B, 20A, 20B) may be located within a horizontal plane that includes the top surface of a corresponding one of the at least three metal electrode plates (10A, 10B, 20A, 20B). In one embodiment, each of the plate contact via structures (52A, 52B, 54A, 54B) may be laterally surrounded by a corresponding dielectric contact via liner (51A, 51B, 53A, 53B) having a uniform lateral thickness.

[0097] In one embodiment, at least two of the plate contact through-hole structures (52A, 52B, 54A, 54B) (for example, each of the first plate contact through-hole structures 52A, each of the second plate contact through-hole structures 52B, and each of the third plate contact through-hole structures 54A) may have a protrusion that contacts a corresponding one of the at least three metal electrode plates (10A, 10B, 20A, 20B) and is located below a columnar portion having a maximum lateral dimension smaller than that of the protrusion.

[0098] According to another aspect of the present disclosure, a semiconductor structure is provided, comprising at least one deep trench capacitor located on a substrate 8. Each of the at least one deep trench capacitor comprises: a deep trench 9 extending downward from the top surface of the substrate 8; a layer stack 30 comprising at least three metal electrode plates (10A, 10B, 20A, 20B) interleaved with at least two node dielectric layers 15; and a plate contact via structure (52A, 52B, 54A, 54B) contacting the top surface of a respective one of the at least three metal electrode plates (10A, 10B, 20A, 20B). Each layer within the layer stack 30 comprises a respective vertically extending portion located within the deep trench 9 and a respective horizontally extending portion located above the top surface of the substrate 8. Each interface between the plate contact via structure (52A, 52B, 54A, 54B) and the at least three metal electrode plates (10A, 10B, 20A, 20B) lies in a horizontal plane that includes the top surface of a corresponding one of the at least three metal electrode plates (10A, 10B, 20A, 20B). Each of the plate contact via structures (52A, 52B, 54A, 54B) is laterally surrounded by a corresponding dielectric contact via liner (51A, 51B, 53A, 53B) having a uniform lateral thickness.

[0099] In one embodiment, each of the at least one deep trench capacitor may include: a main electrode assembly (10A, 20A, 52A, 54A, 62), including at least two main metal electrode plates (10A, 20A) selected from the at least three metal electrode plates (10A, 10B, 20A, 20B); and a complementary electrode assembly (10B, 20B, 52B, 54B, 64), including at least one complementary metal electrode plate (10B, 20B) selected from the at least three metal electrode plates (10A, 10B, 20A, 20B).

[0100] In one embodiment, at least one deep trench includes a plurality of deep trench capacitors. Main electrode assemblies (10A, 20A, 52A, 54A, 62) of the plurality of deep trench capacitors are electrically connected to each other through a first subset (52A, 54A) of plate contact via structures (52A, 52B, 54A, 54B) and a first subset (e.g., first metal lines 62) of metal interconnect structures (62, 64). Complementary electrode assemblies (10B, 20B, 52B, 54B, 64) of the plurality of deep trench capacitors are electrically connected to each other through a second subset (52B, 54B) of plate contact via structures (52A, 52B, 54A, 54B) and a second subset (e.g., second metal lines 64) of metal interconnect structures (62, 64).

[0101] Reference Figure 15According to an embodiment of the present disclosure, a general method for forming a memory device is provided. Referring to step 1510, at least one deep trench 9 extending vertically into a substrate 8 may be formed. Referring to step 1520, a layer stack 30 including at least three metal electrode plates (10A, 10B, 20A, 20B) interlaced with at least two node dielectric layers 15 may be formed in and above the at least one deep trench 9. Referring to step 1530, a contact-level dielectric material layer 38 may be formed above the layer stack 30. Referring to step 1540, a contact via cavity (41A, 41B, 43A, 43B) may be formed through the contact-level dielectric material layer 38, such that each of the contact via cavities (41A, 41B, 43A, 43B) has a bottom surface located above the topmost layer (e.g., the fourth metal electrode plate 20B) within the layer stack 30. Referring to step 1550, the depth of a corresponding subset of the contact via cavities (41A, 41B, 43A, 43B) can be selectively increased (without increasing the depth of other contact via cavities) by performing at least two processing steps including a combination of an etch mask forming process and an etching process. Referring to step 1560, a combination of a dielectric contact via liner (51A, 51B, 53A, 53B) and a plate contact via structure (52A, 52B, 54A, 54B) can be formed within each of the contact via cavities (41A, 41B, 43A, 43B).

[0102] In some embodiments of the method, each etching process etches through an unmasked portion of a node dielectric layer selected from the at least two node dielectric layers and an unmasked portion of a metal electrode plate selected from the at least three metal electrode plates.

[0103] In some embodiments of the method, wherein: each of the at least three metal electrode plates comprises a conductive metal nitride material; each of the at least two node dielectric layers comprises a dielectric metal oxide material having a dielectric constant greater than 7.9, and wherein each etching process includes: a first step of selectively etching the dielectric metal oxide material relative to the conductive metal nitride material; and a second step of selectively etching the conductive metal nitride material relative to the dielectric metal oxide material.

[0104] In some embodiments, the method further includes performing a terminal node dielectric etching process after performing the combination of at least two of the processing steps, wherein the terminal node dielectric etching process includes a wet etching process that selectively etches the dielectric metal oxide material relative to the conductive metal nitride material.

[0105] In some embodiments of the method, the method further includes, after performing the combination of at least two of the processing steps and before performing the terminal node dielectric etching process, selectively isotropically etching the conductive metal nitride material relative to the dielectric metal oxide material, so that the physically exposed side walls of the horizontal extension portions of the at least three metal electrode plates are recessed in the laterally direction.

[0106] In some embodiments, the method further includes: forming a continuous dielectric liner layer on the sidewalls of the contact through hole cavity and the physically exposed portions of the top surfaces of the at least three metal electrode plates and above the contact-level dielectric material layer; and anisotropically etching the continuous dielectric liner layer, wherein the remaining vertical portion of the continuous dielectric liner layer constitutes the dielectric contact through hole liner, wherein the plate contact through hole structure is formed in the void within the contact through hole cavity after forming the dielectric contact through hole liner.

[0107] In general, the bottom surface of each plate contact via structure (52A, 52B, 54A, 54B) can be self-aligned with a horizontal plane that includes the interface between the underlying metal electrode plate (10A, 10B, 20A, 20B) and one of the overlying node dielectric layer 15 and the node dielectric material layer 32. Therefore, the etching process window for forming the contact via cavity (41A, 41B, 43A, 43B) can be wide and stable. In addition, each plate contact via structure (52A, 52B, 54A, 54B) extending through any metal electrode plate (10A, 10B, 20A, 20B) is electrically isolated from such metal electrode plate (10A, 10B, 20A, 20B) by a corresponding dielectric contact via liner (51A, 51B, 53A, 53B) to prevent lateral electrical shorting. The structures and methods according to various embodiments of the present disclosure may provide reliable deep trench capacitors with high yield during fabrication.

[0108] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A deep trench capacitor, comprising: at least one deep trench extending downward from the top surface of the substrate; as well as a layer stack comprising at least three metal electrode plates interleaved with at least two node dielectric layers; as well as a plate-contact via structure contacting a top surface of a corresponding one of the at least three metal electrode plates, wherein: each layer within the layer stack includes a respective vertically extending portion located within each of the at least one deep trench and a respective horizontally extending portion located above the top surface of the substrate; a main electrode assembly comprising at least two main metal electrode plates selected from the at least three metal electrode plates; a complementary electrode assembly comprising at least one complementary metal electrode plate selected from the at least three metal electrode plates; Each layer in the layer stack has a respective sidewall contained within a vertical plane that includes a segment of an outer perimeter of the layer stack; and The plate contact via structure includes a protruding portion and a columnar portion, the protruding portion contacts a corresponding one of the at least three metal electrode plates and is located below the columnar portion, the columnar portion having a smaller maximum lateral dimension than the protruding portion.

2. The deep trench capacitor of claim 1 , wherein each outer sidewall of the horizontally extending portion of each layer within the layer stack lies within a respective vertical plane within a set of at least one vertical plane that includes the entire outer perimeter of the layer stack.

3. The deep trench capacitor of claim 1 , further comprising an etch stop dielectric layer overlying the layer stack, wherein the entire perimeter of the horizontal bottom surface of the etch stop dielectric layer abuts the entire upper perimeter of a vertically extending portion of the etch stop layer, and the vertically extending portion of the etch stop layer laterally surrounds and contacts each outer sidewall of each layer in the layer stack. 4 . The deep trench capacitor of claim 3 , wherein all interfaces between the vertically extending portions of the etch stop dielectric layer and the outer sidewalls of each layer in the layer stack are perpendicular. 5 . The deep trench capacitor of claim 1 , further comprising a contact-level dielectric layer, the pillar-shaped portion of the plate contact via structure passing through the contact-level dielectric layer.

6. The deep trench capacitor of claim 1, wherein each interface between the plate contact via structure and the at least three metal electrode plates lies within a horizontal plane that includes a top surface of a respective one of the at least three metal electrode plates. 7 . The deep trench capacitor of claim 1 , wherein each of the plate contact via structures is laterally surrounded by a corresponding dielectric contact via liner having a uniform lateral thickness.

8. The deep trench capacitor of claim 7, wherein: A first dielectric contact via liner selected from the dielectric contact via liner contacts a sidewall of a horizontally extending portion of at least two metal electrode plates selected from the at least three metal electrode plates; and A second dielectric contact via liner selected from the dielectric contact via pads contacts a sidewall of a horizontally extending portion of at least one metal electrode plate selected from the at least three metal electrode plates. 9 . The deep trench capacitor of claim 1 , wherein the columnar portion of the plate contact via structure has a vertical sidewall or a tapered sidewall.

10. The deep trench capacitor of claim 1 , further comprising: a metal interconnect structure formed in at least one dielectric material layer, the metal interconnect structure overlying the board contact via structure, wherein: The at least two main metal electrode plates are electrically connected to each other through a first subset of the plate contact via structures and a first subset of the metal interconnect structures; and The at least one complementary metal electrode plate includes at least two complementary metal electrode plates electrically connected to each other through the second subset of the plate contact via structures and the second subset of the metal interconnect structures.

11. The deep trench capacitor of claim 1 , wherein: Each of the at least three metal electrode plates comprises a conductive metal nitride material; and Each of the at least two node dielectric layers includes a dielectric metal oxide material having a dielectric constant greater than 7.

9.

12. A semiconductor structure comprising at least one deep trench capacitor located on a substrate, wherein each of the at least one deep trench capacitor comprises: a deep trench extending downward from the top surface of the substrate; a layer stack comprising at least three metal electrode plates interleaved with at least two node dielectric layers; as well as a plate-contact via structure contacting a top surface of a corresponding one of the at least three metal electrode plates, wherein: Each layer in the layer stack includes a respective vertically extending portion located within the deep trench and a respective horizontally extending portion located above the top surface of the substrate; Each interface between the plate-contact via structure and the at least three metal electrode plates lies within a horizontal plane that includes a top surface of a corresponding one of the at least three metal electrode plates; Each of the board contact via structures is laterally surrounded by a corresponding dielectric contact via liner having a uniform lateral thickness; and The plate contact via structure includes a protruding portion and a columnar portion, the protruding portion contacts a corresponding one of the at least three metal electrode plates and is located below the columnar portion, the columnar portion having a smaller maximum lateral dimension than the protruding portion.

13. The semiconductor structure of claim 12 , wherein each of the at least one deep trench capacitor comprises: a main electrode assembly comprising at least two main metal electrode plates selected from the at least three metal electrode plates; as well as The complementary electrode assembly includes at least one complementary metal electrode plate selected from the at least three metal electrode plates.

14. The semiconductor structure of claim 13, wherein: The at least one deep trench capacitor comprises a plurality of deep trench capacitors; The main electrode assemblies of the plurality of deep trench capacitors are electrically connected to each other through a first subset of the plate contact via structures and a first subset of metal interconnect structures; and The complementary electrode assemblies of the plurality of deep trench capacitors are electrically connected to each other through a second subset of the plate contact vias and a second subset of the metal interconnect structures.

15. A method of forming a semiconductor structure, comprising: forming at least one deep trench extending vertically into the substrate; forming a layer stack in and over the at least one deep trench, the layer stack comprising at least three metal electrode plates interleaved with at least two node dielectric layers; forming a contact-level dielectric material layer over the layer stack; forming contact via cavities through the contact-level dielectric material layer such that each of the contact via cavities has a bottom surface located above a topmost layer within the layer stack; selectively increasing the depth of a corresponding subset of the contact via cavities by performing at least two processing steps in combination including an etch mask forming process and an etching process; as well as A combination of a dielectric contact via liner and a plate contact via structure is formed within each of the contact via cavities, wherein the plate contact via structure includes a protruding portion and a columnar portion, wherein the protruding portion contacts a corresponding one of the at least three metal electrode plates and is located below the columnar portion, and the columnar portion has a smaller maximum lateral dimension than the protruding portion.

16. The method of forming a semiconductor structure according to claim 15, wherein each etching process etches through an unmasked portion of a node dielectric layer selected from the at least two node dielectric layers and an unmasked portion of a metal electrode plate selected from the at least three metal electrode plates.

17. The method for forming a semiconductor structure according to claim 15, wherein: Each of the at least three metal electrode plates comprises a conductive metal nitride material; Each of the at least two node dielectric layers comprises a dielectric metal oxide material having a dielectric constant greater than 7.9, and Each etching process includes: A first step is to etch the dielectric metal oxide material selectively relative to the conductive metal nitride material; and The second step is to selectively etch the conductive metal nitride material relative to the dielectric metal oxide material.

18. The method of forming a semiconductor structure according to claim 17, further comprising performing a terminal node dielectric etch process after performing the combination of at least two of the processing steps, wherein the terminal node dielectric etch process comprises a wet etch process that selectively etches the dielectric metal oxide material relative to the conductive metal nitride material.

19. The method for forming a semiconductor structure according to claim 18 further includes, after performing a combination of at least two of the processing steps and before performing the terminal node dielectric etching process, causing the physically exposed side walls of the horizontal extension portions of the at least three metal electrode plates to be laterally recessed by selectively isotropically etching the conductive metal nitride material relative to the dielectric metal oxide material.

20. The method for forming a semiconductor structure according to claim 15, further comprising: forming a continuous dielectric liner layer on sidewalls of the contact via cavity and on physically exposed portions of the top surfaces of the at least three metal electrode plates and over the contact-level dielectric material layer; as well as anisotropically etching the continuous dielectric liner layer, wherein a remaining vertical portion of the continuous dielectric liner layer constitutes the dielectric contact via liner, The board contact via structure is formed in the void within the contact via cavity after forming the dielectric contact via liner.

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