A power semiconductor module packaging structure

Abstract

The present invention provides a power semiconductor module packaging structure, comprising: a packaging substrate, a packaging case, and a half-bridge power semiconductor module; the packaging case is fixedly connected to the packaging substrate to form an accommodation space; the half-bridge power semiconductor module is disposed in the accommodation space; the half-bridge power semiconductor module includes a paired upper switching tube and a lower switching tube connected in parallel on the packaging substrate, and the upper switching tube and the lower switching tube are disposed opposite to each other in the horizontal direction; the upper switching tube includes a first liner bonded to the substrate, a power semiconductor chip group bonded to the first liner, a main power terminal, and an auxiliary control terminal; the lower switching tube includes a second liner bonded to the substrate, a power semiconductor chip group bonded to the second liner, a main power terminal, and an auxiliary control terminal; the first liner and the second liner are connected through the main power terminal, the auxiliary control terminal, and a module-level bonding wire, and the tops of the main power terminal and the auxiliary control terminal extend out of the packaging case.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a power semiconductor module packaging structure. Background Art

[0002] In the future new generation of power modules for electric vehicles, rail transit, and smart grids, the design of multiple power modules in parallel to form the same bridge arm and then form a multi-phase switch application is gradually popularized in high-power components. This method solves and simplifies the problems such as the electromagnetic balance of chip parallel connection encountered when all chips are simultaneously connected in parallel, and the thermal-mechanical failure encountered in the welding or sintering process of bonding multiple chips or substrates to a large-size substrate or radiator.

[0003] In power electronic energy conversion applications, in order to adapt to high-speed and high-energy switch conversion, the method of connecting multiple power chips in parallel is usually adopted inside the power module to form a single-switch or half-bridge circuit structure. To improve the performance of the multi-chip parallel module, the power module requires a module packaging structure with a low-inductance loop and low electromagnetic interference. When using the same module to meet the application requirements of different power levels, an easy-to-adopt method is to further connect the same modules in parallel to form the same bridge arm, such as 2, 3, 4, or more identical modules are connected in parallel again to form a single bridge arm, and three such bridge arms form a three-phase six-switch power system to improve the overall output power of the power component system.

[0004] In the process of higher-energy power switching where multiple half-bridge modules are connected in parallel to form a bridge arm, the same bridge arm composed of multiple modules works in the on and off states together during the switching energy alternating conversion process of the system. The upper or lower ends of adjacent parallel modules are in the on state or off state at the same time during the working state, and the upper or lower switching tubes of the same bridge arm have the same temperature change, and the thermal coupling coefficient between modules is high. When the upper or lower tubes of the parallel modules work in the same state respectively, the heat dissipation efficiency of the cooling fluid for cooling adjacent multiple switches under high-power conditions will be affected. Due to the thermal coupling effect between modules, the module temperature will rise too fast, which is not conducive to the long-term working reliability of the module. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a power semiconductor module packaging structure to solve the problem that the existing power module cannot achieve long-term reliable operation due to too fast temperature rise.

[0006] Based on the above purpose, the present invention provides a power semiconductor module packaging structure, including: a packaging substrate, a packaging housing, and a half-bridge power semiconductor module; the packaging housing is fixedly connected to the packaging substrate to form an accommodation space; the half-bridge power semiconductor module is arranged in the accommodation space;

[0007] The half-bridge power semiconductor module includes a paired upper switch tube and a lower switch tube arranged in parallel on the packaging substrate, and the upper switch tube and the lower switch tube are arranged opposite to each other in the horizontal direction; the upper switch tube includes a first liner bonded to the substrate, a power semiconductor chip group bonded to the first liner, a main power terminal, and an auxiliary control terminal; the lower switch tube includes a second liner bonded to the substrate, a power semiconductor chip group bonded to the second liner, a main power terminal, and an auxiliary control terminal; the first liner and the second liner are connected through the main power terminal, the auxiliary control terminal, and module-level bonding wires, and the tops of the main power terminal and the auxiliary control terminal extend out of the packaging case.

[0008] In one embodiment, the main power terminal includes a positive DC power terminal, a negative DC power terminal, and an AC power terminal; wherein, the positive DC power terminal and the negative DC power terminal are respectively arranged on the metal layers of the first liner and the second liner, and the bottom pins of the AC power terminal are arranged on the metal layer of the first liner; the positive DC power terminal and the negative DC power terminal are arranged in mirror symmetry so that when the main power terminal conducts currents in different directions, the currents overlap to form a coupled low inductance; the top of the AC power terminal is arranged in mirror symmetry with the tops of the positive DC power terminal and the negative DC power terminal.

[0009] In one embodiment, both the positive DC power terminal and the negative DC power terminal include a mounting portion, a first conductive portion, and a second conductive portion; the mounting portion and the first conductive portion are vertically connected through a first bending portion, and the shape of the first bending portion is adapted to the shape of the packaging case so that the mounting portion extends out of the packaging case; the first conductive portion and the second conductive portion are vertically connected through a second bending portion;

[0010] The second conductive portion of the positive DC power terminal and the second conductive portion of the negative DC power terminal form an overlapping coupling structure; the second conductive portion is provided with a plurality of bent pins, and the plurality of bent pins are respectively bonded to the liner to form a high-conduction current.

[0011] In one embodiment, the AC power terminal includes two AC mounting portions, two AC first bending portions, an AC first conductive portion, and an AC second conductive portion; the two AC mounting portions are respectively connected to the two ends of the AC first conductive portion through the two AC first bending portions so that the two AC mounting portions of the AC power terminal are respectively arranged in mirror symmetry with the mounting portion of the positive DC power terminal and the mounting portion of the negative DC power terminal; the AC first conductive portion and the AC second conductive portion are vertically connected through an AC second bending portion.

[0012] In one embodiment, the auxiliary control terminal includes an auxiliary emitter control terminal and a gate control terminal; the auxiliary emitter control terminal includes a metal terminal and an auxiliary emitter terminal provided below the metal terminal; the gate control terminal includes a metal terminal and a gate terminal provided below the metal terminal; the bottom pins of the auxiliary emitter terminal and the bottom pins of the gate terminal are respectively bonded to two ends of the first liner / second liner on the side away from the main power terminal;

[0013] The gate of the power semiconductor chip group is connected to the bottom pin of the gate terminal through a liner bonding wire, and the emitter of the power semiconductor chip group is connected to the bottom pin of the auxiliary emitter terminal through a liner bonding wire, so as to form a Kevin Contact control loop for the chip by controlling the auxiliary emitter-gate loop of the auxiliary control terminal.

[0014] In one embodiment, the number of the first liners is set to two, and the two first liners are arranged in parallel to form a first liner group; the liner auxiliary control regions and the liner gate control regions of the two first liners are respectively connected through liner pole bonding wires, and the power chip groups are respectively connected through liner pole bonding wires; the switch tube auxiliary control region and the switch tube gate control region are respectively arranged at the ends of the liner auxiliary control region and the liner gate control region close to the two vertical ends of the liner group;

[0015] The gates of the two power semiconductor chip groups of the first liner group are respectively connected to the corresponding liner gate control region and the gate control region of the upper switch tube through liner pole bonding wires; the source / emitter is respectively connected to the corresponding liner auxiliary control region and the auxiliary control region of the upper switch tube through liner pole bonding wires, forming an upper tube switch Kevin Contact control loop.

[0016] In one embodiment, the number of the second liners is set to two, and the two second liners are arranged in parallel to form a second liner group; the liner auxiliary control regions and the liner gate control regions of the two second liners are respectively connected through liner pole bonding wires, and the power chip groups are respectively connected through liner pole bonding wires; the switch tube auxiliary control region and the switch tube gate control region are respectively arranged at the ends of the liner auxiliary control region and the liner gate control region close to the two vertical ends of the liner group;

[0017] The gates of the two power semiconductor chip groups of the second liner group are respectively connected to the corresponding liner gate control region and the gate control region of the upper switch tube through liner pole bonding wires; the source / emitter is respectively connected to the corresponding liner auxiliary control region and the auxiliary control region of the upper switch tube through liner pole bonding wires, forming an upper tube switch Kevin Contact control loop.

[0018] In one embodiment, the power chip group includes a plurality of chips arranged in parallel, and two adjacent chips are connected by chip bonding wires.

[0019] In one embodiment, the number of the power chip groups is set to be a plurality, and the plurality of power chip groups are connected in parallel, and are symmetrically arranged between two adjacent chip groups and connected by chip bonding wires.

[0020] In one embodiment, the main power terminal and the auxiliary control terminal are respectively ultrasonically bonded to the first liner and the second liner.

[0021] As can be seen from the above, in the power semiconductor module packaging structure provided by the present invention, by adopting the layout mode in which the upper switching tube and the lower switching tube are oppositely arranged in the horizontal direction, that is, the upper and lower tube structure with left-right layout. It is possible to take into account the uniform heat dissipation between the upper and lower tubes inside the same module and between the parallel switches of different modules in the case of multi-module parallel connection. Thus, without changing the structure of the external radiator and external components of the module, chip control balance, main current balance, heat distribution balance can be achieved, thermal coupling between modules can be reduced, cooling efficiency can be improved, the long-term working stability of the power module can be improved, and the service life of the module can be extended. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1 It is a schematic structural diagram of a traditional power module in parallel to form a bridge arm;

[0024] Figure 2 It is a schematic structural diagram of a power module in parallel to form a bridge arm according to an embodiment of the present invention;

[0025] Figure 3 It is a schematic overall structural diagram of the power semiconductor module packaging structure according to an embodiment of the present invention;

[0026] Figure 4 It is a schematic structural diagram of the power semiconductor module packaging structure according to an embodiment of the present invention after removing the packaging case;

[0027] Figure 5 It is a schematic diagram of the liner structure according to an embodiment of the present invention;

[0028] Figure 6Schematic diagram of the positive DC power terminal structure according to an embodiment of the present invention;

[0029] Figure 7 Schematic diagram of the negative DC power terminal structure according to an embodiment of the present invention;

[0030] Figure 8 Schematic diagram of the AC power terminal structure according to an embodiment of the present invention;

[0031] Figure 9 Schematic diagram of the power semiconductor chip set and the substrate structure according to an embodiment of the present invention;

[0032] Wherein, packaging substrate - 1; substrate fastening hole - 10; packaging case - 2; positive DC power terminal - 31; positive DC mounting part - 311, straight DC through hole - 310, positive DC first conductive part - 313; positive DC second conductive part - 315; positive DC first bending part - 312; positive DC second bending part - 314; positive DC bend - 316; positive DC pin - 317; negative DC power terminal - 32; negative DC mounting part - 321, negative DC through hole - 320, negative DC first conductive part - 323; negative DC second conductive part - 325; negative DC first bending part - 322; negative DC second bending part - 324; negative DC bend - 326; negative DC pin - 327; AC power terminal - 33; AC mounting part - 331, AC through hole - 330, AC first conductive part - 333; AC second conductive part - 335; AC first bending part - 332; AC second bending part - 334; AC bend - 336; AC pin - 337; power semiconductor chip set - 6; first chip - 61; second chip - 60; first substrate - 41; first substrate ceramic area - 410; positive DC power terminal bonding area - 415; AC power terminal connection wire bonding area - 417; end - 418; second substrate - 40; second substrate ceramic area - 400; negative DC power terminal bonding area - 406; AC power terminal bonding area - 407; auxiliary control terminal - 5, metal terminal - 50, auxiliary collector control terminal - 51, auxiliary emitter control terminal - 52, gate control terminal - 53, power semiconductor chip set - 6; first substrate auxiliary control area - 411; first substrate gate control area - 412; upper switch tube auxiliary control area - 413; upper switch tube gate control area - 414; second substrate auxiliary control area - 401; second substrate gate control area - 402; lower switch tube auxiliary control area - 403; lower switch tube gate control area - 404. Detailed implementation manners

[0033] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0034] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present invention should have the ordinary meanings understood by those of ordinary skill in the art to which this disclosure pertains. The "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "comprising" or "including" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0035] In the long-term research work on the packaging structure of power semiconductor modules, the inventors of the present invention have found that the half-bridge power semiconductor module plays a positive and important role in the performance and reliability of the entire power device. When the same modules are conventionally further paralleled into the same bridge arm to meet the application requirements of different power levels, the method shown in Figure 1 is usually adopted, that is, the upper switching tubes are respectively arranged at the upper ends of the parallel modules, and the lower switching tubes are respectively arranged at the lower ends of the parallel modules. This up-and-down layout of the switching tubes in the module cannot take into account the uniform heat dissipation between the upper and lower tubes of the same module and between the parallel switches of different modules. When the cooling water flow direction is up and down, the heat dissipation conditions between the parallel switches of different modules are the same, while the heat dissipation conditions between the upper and lower tubes of the same module are different; when the cooling water flow direction is left and right, the heat dissipation conditions between the upper and lower tubes of the same module are the same, while the heat dissipation conditions between the parallel switches of different modules are different. Therefore, the conventional semiconductor module is prone to thermal coupling effects, resulting in too fast temperature rise, greatly reducing the use reliability of the module and affecting the service life of the module.

[0036] Starting from challenges in aspects such as electromagnetics, electricity, heat, and mechanics, the inventors propose a new internal layout structure of the left and right switching tubes in the module, and the schematic diagram can be as shown in Figure 2 . Without changing the structure of the external radiator and external components of the module, the thermal coupling effect between the modules is reduced, and the cooling efficiency is improved, enabling the power module to work stably for a long time.

[0037] Please refer to Figure 3 and Figure 5 . An embodiment of the present invention provides a power semiconductor module packaging structure, including: a packaging substrate 1, a packaging case 2, and a half-bridge power semiconductor module; the packaging case 2 is fixedly connected to the packaging substrate 1 to form an accommodation space; the half-bridge power semiconductor module is arranged in the accommodation space.

[0038] The half-bridge power semiconductor module includes a paired upper switch tube and a lower switch tube that are arranged in parallel on the packaging substrate 1, and the upper switch tube and the lower switch tube are arranged opposite to each other in the horizontal direction; the upper switch tube includes a first liner 41 bonded to the substrate, a power semiconductor chip group 6 bonded to the first liner 41, a main power terminal, and an auxiliary terminal; the lower switch tube includes a second liner 40 bonded to the substrate, a power semiconductor chip group 6 bonded to the second liner 40, a main power terminal, and an auxiliary terminal; the first liner 41 and the second liner 40 are connected through the main power terminal, the auxiliary terminal, and module-level bonding wires, and the tops of the main power terminal and the auxiliary terminal extend out of the packaging case 2.

[0039] The power semiconductor module packaging structure provided by the present invention, by adopting a layout method in which the upper switch tube and the lower switch tube are arranged opposite to each other in the horizontal direction, that is, an upper and lower tube structure with a left-right layout. It can take into account the uniform heat dissipation between the upper and lower tubes inside the same module and between the parallel switches of different modules in the case of multi-module parallel connection. When the cooling water flow direction is left-right, all the switch tubes in multi-module parallel connection are switched on and off and other states according to the control signal regularly, and the cooling conditions of the parallel chips in each switch tube are more similar, which is beneficial to the uniform distribution of the junction temperature and the thermal-mechanical stability when multiple semiconductor chips are connected in parallel. Thus, without changing the structure of the external radiator and external components of the module, chip control balance, main current balance, heat distribution balance can be achieved, the thermal coupling between modules can be reduced, the cooling efficiency can be improved, the long-term working stability of the power module can be improved, and the service life of the module can be extended.

[0040] Please refer to Figure 4 , the material of the packaging substrate 1 has good thermal conductivity and strong mechanical properties and is not easily deformed by heat, such as AlSiC aluminum silicon carbide material, MgSiC magnesium silicon carbide material, or copper material. In actual applications, it can be selected according to different application requirements. The packaging substrate 1 can adopt different shapes, such as a plate shape. The packaging substrate 1 can be provided with substrate fastening holes 10. The substrate fastening holes 10 can be specifically arranged at the four ends of the packaging substrate 1. The substrate fastening holes 10 can be specifically in a slotted shape. By respectively arranging slotted substrate fastening holes 10 at the four ends of the substrate, it is convenient for packaging. Among them, the substrate fastening holes 10 are preferably reserved holes directly formed during basic preparation to reduce the packaging cost.

[0041] Please refer to Figure 5 , both the first liner 41 and the second liner 40 are ceramic liners. They can be ceramic liners with high voltage resistance insulation, high heat dissipation efficiency, and high thermal-mechanical reliability. For example, made of aluminum oxide Al 2 O 3, a ceramic liner made of at least one of materials such as aluminum nitride (AlN), silicon nitride (SiN), etc. Conductive metal layers are provided on both the upper and lower surfaces of the ceramic liner. The lower surface of the liner is bonded to the substrate, for example, it can be bonded to the substrate through processes such as welding or silver sintering. The metal layer on the upper surface of the liner completes functions such as conduction and control after considering factors such as electromagnetic current sharing.

[0042] As Figures 3 to 5 shown, the main power terminals include three types of terminals with different functions: a positive DC power terminal 31, a negative DC power terminal 32, and an AC power terminal 33.

[0043] Among them, the positive DC power terminal 31 and the negative DC power terminal 32 are respectively arranged on the metal layers of the first liner 41 and the second liner 40, and the bottom pins of the AC power terminal 33 are arranged on the metal layer of the first liner 41; the positive DC power terminal 31 and the negative DC power terminal 32 are arranged in a mirror-symmetrical manner so that when the main power terminal conducts currents in different directions, the currents overlap to form a coupled low inductance; the top of the AC power terminal 33 is arranged in a mirror-symmetrical manner with the tops of the positive DC power terminal 31 and the negative DC power terminal 32.

[0044] Both the positive DC power terminal 31 and the negative DC power terminal 32 include a mounting part, a first conductive part, and a second conductive part; the mounting part and the first conductive part are vertically connected through a first bending part, and the shape of the first bending part is adapted to the shape of the package housing 2 so that the mounting part extends out of the package housing 2; the first conductive part and the second conductive part are vertically connected through a second bending part. The second conductive parts of the positive DC power terminal 31 and the negative DC power terminal 32 form an overlapping coupling structure; multiple bending pins are provided on the second conductive part, and the multiple bending pins are respectively bonded to the liner to form a high-conduction current.

[0045] Through the simple bending parts and bending pins of the positive DC power terminal 31 and the negative DC power terminal 32 that match the liner structure, high-current conduction can be achieved; combined with the second conductive parts with large current and large area overlap, a magnetic field coupling effect is generated to reduce the effective inductance of the entire module.

[0046] As Figure 6 shown, the positive DC power terminal 31 includes a positive DC mounting part 311, and a straight DC through-hole 310 is provided on the positive DC mounting part 311 for tightly fixing the positive DC power terminal 31 on the package housing 2 to conduct the main current. The positive DC mounting part 311 extends out of the package housing 2.

[0047] Both ends of the positive DC first bending portion 312 are respectively connected to the positive DC mounting portion 311 and the positive DC first conductive portion 313, so that the positive DC mounting portion 311 and the positive DC first conductive portion 313 are vertically connected. The shape of the positive DC mounting portion 311 is adapted to the shape of the encapsulation tube shell 2, so that the positive DC mounting portion 311 horizontally extends out of the encapsulation tube shell 2.

[0048] The positive DC first conductive portion 313 and the positive DC second conductive portion 315 are connected through the positive DC second bending portion 314. The positive DC second bending portion 314 is perpendicular to the positive DC first bending portion 312, so that the positive DC first conductive portion 313 and the positive DC second conductive portion 315 are vertically connected.

[0049] A plurality of positive DC bending pins are arranged near the edge of the first liner on the positive DC second conductive portion 315, and the plurality of positive DC bending pins are respectively bonded on the first liner to form a high-conduction positive DC current. The positive DC bending pins can be set to 4. Among them, the positive DC bending pins include a positive DC bend 316 and a positive DC pin 317.

[0050] As Figure 7 shown, the negative DC power terminal 32 includes a negative DC mounting portion 321, and a negative DC through hole 320 is provided on the negative DC mounting portion 321 for tightly fixing the negative DC power terminal 32 on the encapsulation tube shell 2 to conduct the main current. The negative DC mounting portion 321 extends out of the encapsulation tube shell 2.

[0051] Both ends of the negative DC first bending portion 322 are respectively connected to the negative DC mounting portion 321 and the negative DC first conductive portion 323, so that the negative DC mounting portion 321 and the negative DC first conductive portion 323 are vertically connected. The shape of the negative DC mounting portion 321 is adapted to the shape of the encapsulation tube shell 2, so that the negative DC mounting portion 321 horizontally extends out of the encapsulation tube shell 2. The negative DC first bending portion 322 and the positive DC first bending portion 312 are close to each other and overlap, so that the negative DC first conductive portion 323 and the positive DC first conductive portion 313 are far away from each other.

[0052] The negative DC first conductive portion 323 and the negative DC second conductive portion 325 are connected through the negative DC second bending portion 324. The negative DC second bending portion 324 is perpendicular to the negative DC first bending portion 322, so that the negative DC first conductive portion 323 and the negative DC second conductive portion 325 are vertically connected. The negative DC second conductive portion 325 and the positive DC second conductive portion 315 are close to each other and overlap, resulting in a large-area overlap of positive and negative currents. The area of the negative DC second conductive portion 325 needs to be subjected to electromagnetic analysis with the area of the positive DC second conductive portion 315 to obtain a suitable low-inductance design.

[0053] The negative DC second conductive part 325 is provided with a plurality of negative DC bent pins near the edge of the second lining board. The plurality of negative DC bent pins are respectively bonded to the lining board to form a high-conduction negative DC current. The negative DC bent pins can be set to 4. Among them, the negative DC bent pin includes a negative DC bend 326 and a negative DC pin 327. The negative DC bend 326 and the positive DC bend 316 are close to each other and overlap. The negative DC pin 327 and the positive DC pin 317 are far away from each other.

[0054] As Figure 8 shown, the AC power terminal 33 includes two AC mounting parts 331, two AC first bending parts 332, an AC first conductive part 333 and an AC second conductive part 335. The two AC mounting parts 331 are respectively connected to two ends of the AC first conductive part 333 through the two AC first bending parts 332, so that the two AC mounting parts 331 of the AC power terminal 33 are mirror-symmetrical to the mounting parts of the positive DC power terminal 31 and the mounting parts of the negative DC power terminal 32 respectively. The AC first conductive part 333 and the AC second conductive part 335 are vertically connected through an AC second bending part 334.

[0055] Among them, the two AC mounting parts 331 have the same structure, and the two AC first bending parts 332 have the same structure. An AC through hole 330 is opened on the AC mounting part 331 for fastening the AC power terminal 33 on the packaging tube shell 2 and conducting the main current. The AC mounting part 331 extends out of the packaging tube shell 2.

[0056] The AC first bending part 332 and the AC second bending part 334 are relatively perpendicular, so that the AC first conductive part 333 and the AC second conductive part 335 are vertically connected. The shape of the AC first conductive part 333 is adapted to the shape after the positive DC first conductive part 313 and the negative DC first conductive part 323 are mirror-symmetrical.

[0057] As Figure 4 shown, the power semiconductor chip group 6 is ultrasonically bonded to the middle of the first lining board 41 / second lining board 40 and includes a plurality of chips arranged in parallel. As Figure 9 shown, adjacent two chips arranged in parallel are connected through chip bonding wires to reduce the oscillation and electromagnetic interference caused by the potential difference of the parallel chips due to large current. The plurality can be two or three. An internal resistance is provided inside each of the chips.

[0058] As Figure 5 and Figure 9As shown, in one embodiment, the power semiconductor chip group 6 includes three first chips 61 and two second chips 60 arranged in parallel. Among them, one first chip 61 is provided, and two second chips 60 are provided. The first chip 61 is arranged at a position close to the main power terminal, and the two second chips 60 are arranged on one side of the first chip 61 away from the main power terminal, and the two second chips 60 are arranged adjacent to each other.

[0059] The first chip 61 and the second chip 60 can be selected from silicon carbide Mosfet power chips and IGBT power chips. For example, the first chip 61 is an IGBT power chip, and the second chip 60 is a silicon carbide Mosfet power chip; or the first chip 61 is a silicon carbide Mosfet power chip, and the second chip 60 is an IGBT power chip.

[0060] In one embodiment, the number of the power semiconductor chip groups 6 is set to be multiple, and the multiple power semiconductor chip groups 6 are connected in parallel, and adjacent two power semiconductor chip groups 6 are symmetrically arranged and connected by chip bonding wires, so as to reduce the oscillation and electromagnetic interference caused by the potential difference caused by the large current of the power semiconductor chip groups 6 arranged in parallel.

[0061] Correspondingly, a power semiconductor chip group 6 bonding area, two positive DC power terminal bonding areas 415, and an AC power terminal connection wire bonding area 417 are arranged on the metal layer of the first liner 41, so that the positive DC power terminal 31 and the AC power terminal 33 are connected by bonding wires to form a positive AC current loop. Among them, the two positive DC power terminal bonding areas 415 are symmetrically and spacedly arranged at the end of the first liner 41 close to the second liner 40. The AC power terminal connection wire bonding area 417 is arranged in the interval area between the two positive DC power terminal bonding areas 415. And the AC power terminal connection wire bonding area 417 is in a T shape, and the vertical part of the T shape is close to the power semiconductor chip group 6.

[0062] The power semiconductor chip group 6 is connected to the two ends 418 of the vertical part of the T shape through liner bonding wires, and the AC power terminal connection wire bonding area 417 is bonded to the AC power terminal bonding area of the second liner 40 through a connection wire, so that the power semiconductor chip group 6 and the AC power terminal 33 are connected; cooperating with the positive DC power terminal 31 bonding areas arranged on both sides of the AC power terminal connection wire bonding area 417, the AC power terminal 33 and the positive DC power terminal 31 are connected to form an upper switch tube current path.

[0063] Two negative DC power terminal bonding areas 406 and an AC power terminal bonding area 407 are provided in the metal layer of the second liner 40, so that the negative DC power terminal 32 and the AC power terminal 33 are connected by bonding to form a negative DC current loop. Among them, the two negative DC power terminal bonding areas 406 are symmetrically and spacedly arranged at the end of the second liner 40 close to the first liner 41. The AC power terminal bonding area 407 is arranged in the spaced area between the two negative DC power terminal bonding areas 406.

[0064] The power semiconductor chip set 6 is connected to the two negative DC power terminal bonding areas 406 through liner bonding wires, so that the power semiconductor chip set 6 and the negative DC power terminal 32 form a negative DC connection; cooperating with the AC power terminal bonding area 407 arranged in the spaced area between the two negative DC power terminal bonding areas 406, the negative DC power terminal 32 and the AC power terminal 33 are connected to form a lower switch tube current path.

[0065] As Figure 4 shown, the auxiliary control terminal 5 includes a metal terminal 50 and an auxiliary terminal arranged below the metal terminal 50. The auxiliary terminal and the metal terminal 50 are integrally connected by processes such as laser bonding or welding. Among them, the metal terminal 50 is fixedly connected to the encapsulation case 2 for fixing the auxiliary terminal on the encapsulation case 2, and the top of the metal terminal 50 extends out of the top of the encapsulation housing. The auxiliary terminal can be fastened to the encapsulation case 2 by a nut, and internal threads are provided at the upper end of the metal terminal 50 to avoid sharp ends and possible strong electric field distributions at the tips. The bottom pin of the auxiliary terminal is connected to the first liner 41 / second liner 40 and can be fixed to the metal layer of the first liner 41 / second liner 40 by ultrasonic bonding USW or welding process.

[0066] In one embodiment, the auxiliary control terminal 5 includes an auxiliary collector control terminal 51, an auxiliary emitter control terminal 52, and a gate control terminal 53, which respectively constitute the auxiliary collector, auxiliary emitter, and gate of the half-bridge power semiconductor module. Among them, the auxiliary collector control terminal 51 includes a metal terminal 50 and an auxiliary collector terminal arranged below the metal terminal 50. The auxiliary emitter control terminal 52 includes a metal terminal 50 and an auxiliary emitter terminal arranged below the metal terminal 50. The gate control terminal 53 includes a metal terminal 50 and a gate terminal arranged below the metal terminal 50. The connection of the auxiliary collector is prior art and will not be elaborated here.

[0067] The auxiliary emitter control terminal 52 and the gate control terminal 53 are adjacently arranged in the middle of the metal layer on the first substrate 41 / the second substrate 40. The bottom pins of the auxiliary emitter terminal and the gate terminal are respectively bonded to two ends of the first substrate 41 / the second substrate 40 on the side away from the main power terminal, and the bottom pins of the auxiliary emitter terminal and the gate terminal are arranged in mirror symmetry. The gate of the power semiconductor chip group 6 is connected to the bottom pin of the gate terminal through a substrate bonding wire, and the emitter of the power semiconductor chip group 6 is connected to the bottom pin of the auxiliary emitter terminal through a substrate bonding wire, so as to form a Kevin Contact control loop for the chip by controlling the auxiliary emitter-gate loop of the auxiliary control terminal 5, and realize the balanced control of the chip. By realizing the Kevin Contact control of the power chip in the substrate structure, the effective utilization area of the power chip can be maximized under the simple design of the substrate, and then the Kevin Contact control can be realized for chips of various different sizes, specifications and materials. For example, it can be adapted to different types of silicon-based and wide-bandgap power devices such as high-current silicon-based IGBT chips and new wide-bandgap silicon carbide Mosfet chips.

[0068] Please refer to Figure 5 , an uncovered first substrate ceramic region 410 is provided on the first substrate 41. An uncovered second substrate ceramic region 400 is provided on the second substrate 40. The metal layers of the first substrate 41 and the second substrate 40 respectively include a substrate auxiliary control region, a substrate gate control region, a switch auxiliary control region and a switch gate control region; the substrate auxiliary control region and the substrate gate control region are respectively strip-shaped and arranged at a relative interval, and expansion regions are provided at both ends of the two regions in the vertical direction close to the first substrate 41 / the second substrate 40; the switch auxiliary control region and the switch gate control region are respectively arranged at the ends of the substrate auxiliary control region and the substrate gate control region close to both ends of the substrate in the vertical direction;

[0069] The gates of the power semiconductor chip groups 6 on the first substrate 41 and the second substrate 40 are respectively connected to the gate control region of the corresponding substrate and the gate control region of the switch through substrate pole bonding wires; the source / emitter are respectively connected to the auxiliary control region of the corresponding substrate and the auxiliary control region of the switch through substrate pole bonding wires to form a KevinContact control loop.

[0070] Among them, the metal layer on the upper surface of the first liner 41 includes a first liner auxiliary control area 411, a first liner gate control area 412, an upper switch auxiliary control area 413, and an upper switch gate control area 414; the metal layer on the upper surface of the second liner 40 includes a second liner auxiliary control area 401, a second liner gate control area 402, a lower switch auxiliary control area 403, and a lower switch gate control area 404.

[0071] In one embodiment, please refer to Figure 9 , the number of the first liners 41 is set to two, and the two first liners 41 are connected in parallel to form a first liner group, that is, the upper switch of the half-bridge power semiconductor module. The first liner auxiliary control areas 411 and the first liner gate control areas 412 of the two first liners 41 are respectively connected by liner pole bonding wires, and the power semiconductor chip groups are respectively connected by liner pole bonding wires; the upper switch auxiliary control area 413 and the upper switch gate control area 414 are respectively arranged at the ends of the first liner auxiliary control area 411 and the first liner gate control area 412 close to both ends of the first liner group 41 in the vertical direction.

[0072] The gates of the two power semiconductor chip groups 6 of the first liner group are respectively connected to the corresponding first liner gate control area 412 and the upper switch gate control area 414 by liner pole bonding wires; the source / emitters are respectively connected to the corresponding first liner auxiliary control area 411 and the upper switch auxiliary control area 413 by liner pole bonding wires, forming an upper tube switch Kevin Contact control loop.

[0073] The number of the second liners 40 is set to two, and the two second liners 40 are connected in parallel to form a second liner group, that is, the lower switch of the half-bridge power semiconductor module. The second liner auxiliary control areas 401 and the second liner gate control areas 402 of the two second liners 40 are respectively connected by liner pole bonding wires, and the power semiconductor chip groups are respectively connected by liner pole bonding wires; the lower switch auxiliary control area 403 and the lower switch gate control area 404 are respectively arranged at the ends of the second liner auxiliary control area 401 and the second liner gate control area 402 close to both ends of the liner group 40 in the vertical direction.

[0074] The gates of the two power semiconductor chip groups 6 of the second liner group 40 are respectively connected to the corresponding second liner gate control area 402 and the lower switch gate control area 404 by liner pole bonding wires; the source / emitters are respectively connected to the corresponding second liner auxiliary control area 401 and the lower switch auxiliary control area 403 by liner pole bonding wires, forming a lower tube switch Kevin Contact control loop.

[0075] The power semiconductor module packaging structure provided by the embodiments of the present invention can reduce the thermal resistance of the module during turn-on and turn-off, improve the effective heat dissipation efficiency, and achieve low inductance, low electromagnetic interference and high reliability for long-term applications by means of a new layout of upper and lower switching tubes arranged left and right on a horizontal line, combined with a corresponding new low-inductance busbar structure, and adopting the Kevin Contact type for the chip switching control inside the module. Among them, through the left-right layout of the upper switching tube structure and the lower switching tube structure, it is possible to take into account the uniform heat dissipation between the upper and lower switching tubes inside the same module and between the parallel switches of different modules in the case of multi-module parallel connection. By adopting the simple pre-bent new positive DC power terminal 31, negative DC power terminal 32 and AC power terminal 33 that match the new liner structure, the conduction of high current is ensured, and the large-area overlap of the large current flowing through the positive and negative DC power terminals reduces the effective inductance of the entire module due to the magnetic field coupling effect generated. By adopting the positive DC power terminal 31, negative DC power terminal 32 and AC power terminal 33 with ultrasonic bonding process, the reliability of the power terminals can be improved, and there is stronger ability in terms of resistance to temperature shock and mechanical vibration. By adopting the Kevin Contact control loop in the new liner layout to achieve the balanced control loop for multiple parallel power semiconductor chip groups 6, reducing the inductance of the control loop, reducing the control of electromagnetic interference EMI, and being applicable to chips of various different sizes, specifications and materials. By adopting the auxiliary control terminal 5 directly ultrasonically bonded to the liner, the control PCB board used in traditional modules is saved, the production process is simplified, and the bonding reliability of the auxiliary control terminal 5 is improved.

[0076] Those of ordinary skill in the art should understand that the discussion of any of the above embodiments is only exemplary, and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples; under the concept of the present invention, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the present invention as described above, which are not provided in detail for the sake of brevity.

[0077] In addition, for simplicity of explanation and discussion, and so as not to obscure the present invention, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Further, the devices may be shown in block diagram form in order to avoid obscuring the present invention, and this also takes into account the fact that details of the implementation of these block diagram devices are highly dependent on the platform on which the present invention is to be implemented (i.e., these details should be fully within the understanding of those skilled in the art). In instances in which specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present invention, it will be apparent to those skilled in the art that the present invention may be practiced without such specific details or with variations of such specific details. Accordingly, these descriptions are to be regarded as illustrative rather than restrictive.

[0078] Although the present invention has been described in connection with specific embodiments thereof, many alternatives, modifications, and variations will be apparent to those of ordinary skill in the art based on the foregoing description.

[0079] Embodiments of the present invention are intended to embrace all such alternatives, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included within the protection scope of the present invention.

Claims

1. A power semiconductor module packaging structure, characterized in that, it includes: a packaging substrate, a packaging case, and a half-bridge power semiconductor module; The packaging case is fixedly connected to the packaging substrate to form a receiving space; The half-bridge power semiconductor module is disposed in the receiving space; The half-bridge power semiconductor module includes multiple groups of paired upper switching tubes and lower switching tubes connected in parallel on the packaging substrate, and the upper switching tube and the lower switching tube in each group are oppositely disposed in the horizontal direction; the upper switching tube includes a first liner bonded to the substrate, a power semiconductor chip group bonded to the first liner, a main power terminal, and an auxiliary control terminal; the lower switching tube includes a second liner bonded to the substrate, a power semiconductor chip group bonded to the second liner, a main power terminal, and an auxiliary control terminal; the first liner and the second liner are connected through the main power terminal, the auxiliary control terminal, and a module-level bonding wire, and the tops of the main power terminal and the auxiliary control terminal extend out of the packaging case; The main power terminal includes a positive DC power terminal, a negative DC power terminal, and an AC power terminal; wherein, the positive DC power terminal and the negative DC power terminal are respectively disposed on the metal layers of the first liner and the second liner, and the bottom pins of the AC power terminal are disposed on the metal layer of the first liner; the positive DC power terminal and the negative DC power terminal are arranged in mirror symmetry so that when the main power terminal conducts currents in different directions, the currents overlap to form a coupled low inductance; the top of the AC power terminal is arranged in mirror symmetry with the tops of the positive DC power terminal and the negative DC power terminal; Both the positive DC power terminal and the negative DC power terminal include a mounting portion, a first conductive portion, and a second conductive portion; the mounting portion is vertically connected to the first conductive portion through a first bending portion, and the shape of the first bending portion is adapted to the shape of the packaging case so that the mounting portion extends out of the packaging case; the first conductive portion is vertically connected to the second conductive portion through a second bending portion; The second conductive portion of the positive DC power terminal and the second conductive portion of the negative DC power terminal are in an overlapping coupling structure; the second conductive portion is provided with multiple bending pins, and the multiple bending pins are respectively bonded to the liner to form a high-conducting current; The AC power terminal includes two AC mounting portions, two AC first bending portions, an AC first conductive portion, and an AC second conductive portion; the two AC mounting portions are respectively connected to the two ends of the AC first conductive portion through the two AC first bending portions so that the two AC mounting portions of the AC power terminal are respectively in mirror symmetry with the mounting portion of the positive DC power terminal and the mounting portion of the negative DC power terminal; the AC first conductive portion is vertically connected to the AC second conductive portion through an AC second bending portion.

2. The power semiconductor module packaging structure according to claim 1, characterized in that, The auxiliary control terminals include an auxiliary emitter control terminal and a gate control terminal; the auxiliary emitter control terminal includes a metal terminal and an auxiliary emitter terminal disposed below the metal terminal; the gate control terminal includes a metal terminal and a gate terminal disposed below the metal terminal; the bottom pins of the auxiliary emitter terminal and the bottom pins of the gate terminal are respectively bonded to two ends of the first / second liner on the side away from the main power terminal; The gate of the power semiconductor chip group is connected to the bottom pin of the gate terminal through a liner bonding wire, and the emitter of the power semiconductor chip group is connected to the bottom pin of the auxiliary emitter terminal through a liner bonding wire, so as to form a Kelvin contact control loop for the chip by controlling the auxiliary emitter-gate loop of the auxiliary control terminal.

3. The power semiconductor module packaging structure according to claim 2, characterized in that the number of the first liners is set to two, and the two first liners are arranged in parallel to form a first liner group; the liner auxiliary control regions and the liner gate control regions of the two first liners are respectively connected through liner pole bonding wires, and the power chip groups are respectively connected through liner pole bonding wires; the switch tube auxiliary control region and the switch tube gate control region are respectively disposed at the ends of the liner auxiliary control region and the liner gate control region close to the two vertical ends of the liner group; the gates of the two power semiconductor chip groups of the first liner group are respectively connected to the corresponding liner gate control region and the gate control region of the upper switch tube through liner pole bonding wires; the source / emitter is respectively connected to the corresponding liner auxiliary control region and the auxiliary control region of the upper switch tube through liner pole bonding wires, so as to form an upper tube switch Kelvin contact control loop.

4. The power semiconductor module packaging structure according to claim 2, characterized in that the number of the second liners is set to two, and the two second liners are arranged in parallel to form a second liner group; the liner auxiliary control regions and the liner gate control regions of the two second liners are respectively connected through liner pole bonding wires, and the power chip groups are respectively connected through liner pole bonding wires; the switch tube auxiliary control region and the switch tube gate control region are respectively disposed at the ends of the liner auxiliary control region and the liner gate control region close to the two vertical ends of the liner group; the gates of the two power semiconductor chip groups of the second liner group are respectively connected to the corresponding liner gate control region and the gate control region of the upper switch tube through liner pole bonding wires; the source / emitter is respectively connected to the corresponding liner auxiliary control region and the auxiliary control region of the upper switch tube through liner pole bonding wires, so as to form an upper tube switch Kelvin contact control loop.

5. The power semiconductor module packaging structure according to claim 2, characterized in that the power chip group includes a plurality of chips arranged in parallel, and adjacent two chips are connected through chip bonding wires.

6. The power semiconductor module packaging structure according to claim 5, characterized in that The number of the power chip sets is set to be multiple, the multiple power chip sets are connected in parallel, and adjacent chip sets are symmetrically arranged and connected by chip bonding wires.

7. The power semiconductor module packaging structure according to claim 1, characterized in that the main power terminal and the auxiliary control terminal are respectively ultrasonically bonded to the first liner and the second liner.

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