Memory elements and methods for forming the same

Abstract

A memory device includes a substrate, a wire, a capacitor, a transistor and a contact structure. The wire is located on a peripheral region of the substrate. The capacitor is located on a memory region of the substrate. The transistor is located on and connected to the capacitor, and includes first and second source / drain regions, a channel and a gate structure. The first source / drain region is connected to the capacitor. The gate structure laterally surrounds the channel. The contact structure is located on the peripheral region of the substrate, and includes a bottom portion, a top portion and a middle portion. The bottom portion is connected to the wire. The top portion is connected to the second source / drain region of the transistor. The middle portion is wider than the top portion and the bottom portion, wherein a height of the middle portion of the contact structure is substantially the same as a height of the gate structure of the transistor. Thus, the memory device of the present disclosure can increase a contact area and reduce a resistance, thereby improving a performance of the memory device.

Description

Technical Field

[0001] This disclosure relates to a memory element and a method for forming a memory element. Background Technology

[0002] Semiconductor memory devices can be divided into two categories: volatile memory devices and non-volatile memory devices. Volatile memory cells, such as dynamic random access memory (DRAM) cells, can contain transistors and capacitors. Capacitors can be charged or discharged; these two states are used to represent the two values ​​of a bit, called 0 and 1. Transistors can contain channels and gates, with the channel located between a pair of source / drain regions, and the gate configured to be electrically connected to the source / drain regions via the channel. Summary of the Invention

[0003] The technical specification disclosed herein is a memory element.

[0004] According to some embodiments disclosed herein, a memory element includes a substrate, wires, a capacitor, a transistor, and a contact structure. The substrate has a memory region and a peripheral region. Wires are located on the peripheral region of the substrate. The capacitor is located on the memory region of the substrate. A transistor is located on and connected to the capacitor, and the transistor includes first and second source / drain regions, a channel, and a gate structure. The first source / drain region is connected to the capacitor. The channel is located between the first and second source / drain regions. The gate structure laterally surrounds the channel. The contact structure is located on the peripheral region of the substrate and includes a bottom portion, a top portion, and a middle portion. The bottom portion is connected to the wires. The top portion is connected to the second source / drain region of the transistor. The middle portion is wider than the top and bottom portions, wherein the height of the middle portion of the contact structure is substantially the same as the height of the gate structure of the transistor.

[0005] In some embodiments, the middle portion of the contact structure has a sidewall and a lower surface that contacts the bottom portion of the contact structure, and the angle between the sidewall and the lower surface is between about 135 degrees and about 180 degrees.

[0006] In some implementations, the top portion of the contact structure and the bottom portion of the contact structure are offset from each other in the vertical direction.

[0007] In some implementations, the top portion of the contact structure is substantially aligned with the bottom portion of the contact structure in the vertical direction.

[0008] In some embodiments, the memory element further includes bit lines located on the top portion of the contact structure and the second source / drain region of the transistor, and in contact with the top portion of the contact structure and the second source / drain region of the transistor.

[0009] In some implementations, the extension direction of the bit line is substantially perpendicular to the extension direction of the gate structure of the transistor.

[0010] In some implementations, the middle portion of the contact structure contains the same material as the gate structure of the transistor.

[0011] In some implementations, the lower surface of the middle portion of the contact structure is substantially coplanar with the lower surface of the gate structure of the transistor.

[0012] In some implementations, the upper surface of the middle portion of the contact structure is substantially coplanar with the upper surface of the gate structure of the transistor.

[0013] In some implementations, the width of the middle portion of the contact structure is greater than the width of the gate structure of the transistor.

[0014] In some implementations, an interface is formed between the top portion of the contact structure and the middle portion of the contact structure.

[0015] In some implementations, an interface is formed between the bottom portion of the contact structure and the middle portion of the contact structure.

[0016] In some implementations, the memory element further includes a lower electrode, a dielectric layer, and a upper electrode. The dielectric layer surrounds the lower electrode. The upper electrode covers the dielectric layer and is connected to a first source / drain region of the transistor.

[0017] Another technical aspect disclosed herein is a method for forming memory elements.

[0018] According to some embodiments disclosed herein, a method for forming a memory element includes the following steps: forming a first conductive line on a memory region of a substrate and forming a second conductive line on a peripheral region of the substrate. Forming a capacitor on the first conductive line. Forming a bottom portion of a contact structure on the second conductive line. Forming a first dielectric layer covering the capacitor and the bottom portion of the contact structure. Forming a first opening and a second opening in the first dielectric layer, wherein the first opening is located on the capacitor and the second opening exposes the bottom portion of the contact structure. Filling the first and second openings with a conductive material such that a middle portion of the contact structure is formed in the second opening and a gate material is formed in the first opening. Forming a third opening in the gate material to form a gate structure in the first opening. Forming a gate dielectric layer and a channel in the third opening. Forming a bit line to connect the channel and the contact structure.

[0019] In some implementations, the formation of the first opening and the second opening is performed using a single etching process.

[0020] In some embodiments, the method of forming memory elements further includes forming a second dielectric layer on the gate structure before forming bit lines.

[0021] In some embodiments, the method of forming memory elements further includes forming the top portion of the contact structure in a second dielectric layer.

[0022] In some embodiments, the method of forming a memory element further includes forming a source / drain region in a second dielectric layer and forming bit lines to connect to the source / drain region.

[0023] In some implementations, the middle portion of the contact structure contains the same material as the gate structure.

[0024] In some implementations, the channel is an oxide layer.

[0025] According to the embodiments disclosed above, since the contact structure includes a bottom portion, a top portion, and a middle portion, and the height of the middle portion is substantially the same as the height of the gate structure of the transistor, the contact area can be increased and the resistance can be reduced. As a result, the performance of the memory element can be improved.

[0026] It should be understood that the foregoing general description and the following detailed description are merely examples and are intended to provide further explanation of this disclosure. Attached Figure Description

[0027] The features disclosed herein can be understood from the following detailed description of the embodiments and the accompanying drawings.

[0028] Figure 1 This is a cross-sectional view of a memory element according to some embodiments of this disclosure.

[0029] Figure 2 yes Figure 1 A schematic perspective view of memory elements on a memory region.

[0030] Figures 3 to 12 This is a cross-sectional view of a method for forming a memory element at various stages according to some embodiments of this disclosure.

[0031] Figure 13 This is a cross-sectional view of a memory element according to another embodiment of the present disclosure. Detailed Implementation

[0032] The following describes several embodiments of this disclosure with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit this disclosure. That is, in some embodiments of this disclosure, these practical details are not essential and therefore should not be used to limit this disclosure. In addition, for the sake of simplicity, some conventional structures and components will be shown in the drawings in a simple schematic manner. Furthermore, for the reader's convenience, the dimensions of the components in the drawings are not drawn to scale.

[0033] As used in this disclosure, “around,” “about,” “approximately,” or “substantially” generally means within 20%, 10%, or 5% of a given value or range. The values ​​given in this disclosure are approximate, meaning that the terms “around,” “about,” “approximately,” or “substantially” can be inferred unless explicitly stated otherwise.

[0034] Figure 1 This is a cross-sectional view of a memory element 100 according to some embodiments of this disclosure, and Figure 2 yes Figure 1 A schematic perspective view of memory element 100 on memory region 112. See also... Figure 1 and Figure 2 The memory element 100 includes a substrate 110, wires 124, capacitors 130, transistors 140, and contact structures 150.

[0035] The substrate 110 has a memory region 112 and a peripheral region 114. A conductor 124 is disposed on the peripheral region 114. More specifically, the memory element 100 also includes another conductor 122 located on the memory region 112. In some embodiments, the conductor 124 is connected to a sensor, amplifier, peripheral circuitry, or other electrical components.

[0036] A capacitor 130 is disposed on a memory region 112 of a substrate 110. The capacitor 130 includes a lower electrode 132, a dielectric layer 134, and an upper electrode 136. The lower electrode 132 contacts a conductive line 122. The dielectric layer 134 surrounds the lower electrode 132, and the upper electrode 136 covers the dielectric layer 134 and is separated from the lower electrode 132. In some embodiments, the lower electrode 132 may be column-shaped and extend upward from the conductive line 122.

[0037] A transistor 140 is disposed on and connected to a capacitor 130. The transistor 140 includes a first source / drain region 142 and a second source / drain region 144, a channel 146, and a gate structure 148. The first source / drain region 142 is connected to the capacitor 130. Specifically, the first source / drain region 142 is connected to the upper electrode 136 of the capacitor 130. The channel 146 is disposed between the first source / drain region 142 and the second source / drain region 144. In some embodiments, the first source / drain region 142, the second source / drain region 144, and the channel 146 can be considered as the active area of ​​the transistor 140. The gate structure 148 laterally surrounds the channel 146. In some embodiments, the transistor 140 further includes a gate dielectric layer 147 located between the channel 146 and the gate structure 148 and laterally surrounding the channel 146. In other words, the gate dielectric layer 147 is disposed on the sidewall of the channel 146, and the gate structure 148 is disposed on the sidewall of the gate dielectric layer 147. In some embodiments, the dielectric structure 149 laterally surrounds the gate structure 148.

[0038] like Figure 2 As shown, the character line WL is located between the first source / drain region 142 and the second source / drain region 144. The character line WL surrounds the active region (in Figure 1 A portion of the first source / drain region 142, the second source / drain region 144, and the channel 146 can be considered as a gate structure 148.

[0039] A contact structure 150 is disposed on the peripheral region 114 of the substrate 110. The contact structure 150 includes a bottom portion 152, a top portion 154, and a middle portion 156. The bottom portion 152 is connected to the conductor 124. The top portion 154 is connected to the second source / drain region 144 of the transistor 140. The middle portion 156 is wider than the top portion 154 and the bottom portion 152, wherein the height of the middle portion 156 of the contact structure 150 is substantially the same as the height of the gate structure 148 of the transistor 140. Since the middle portion 156 is wider than the top portion 154 and the bottom portion 152, the contact area can be increased, and the connection between the top portion 154 and the bottom portion 152 can be facilitated, thereby reducing the resistance of the contact structure 150. Therefore, the performance of the memory element 100 can be improved.

[0040] In some embodiments, the middle portion 156 of the contact structure 150 has a sidewall 153, a lower surface 155, and an upper surface 157. The lower surface 155 contacts the bottom portion 152 of the contact structure 150, and the upper surface 157 contacts the top portion 154 of the contact structure 150. The width of the upper surface 157 is substantially greater than the width of the lower surface 155. In some embodiments, the angle θ between the sidewall 153 and the lower surface 155 is greater than about 90 degrees and less than about 180 degrees. For example, the angle θ between the sidewall 153 and the lower surface 155 is between about 135 degrees and about 180 degrees.

[0041] In some embodiments, interface I1 is formed between the top portion 154 and the middle portion 156 of the contact structure 150. Interface I1 is substantially coplanar with the upper surface 157 of the middle portion 156. In some embodiments, interface I2 is formed between the bottom portion 152 and the middle portion 156 of the contact structure 150. Interface I2 is substantially coplanar with the lower surface 155 of the middle portion 156.

[0042] In some embodiments, the lower surface 155 of the middle portion 156 of the contact structure 150 is substantially coplanar with the lower surface 141 of the gate structure 148 of the transistor 140. In some embodiments, the upper surface 157 of the middle portion 156 of the contact structure 150 is substantially coplanar with the upper surface 143 of the gate structure 148 of the transistor 140. That is, the middle portion 156 and the gate structure 148 have substantially the same height.

[0043] In some embodiments, the width of the middle portion 156 of the contact structure 150 is greater than the width of the gate structure 148 of the transistor 140. For example, the middle portion 156 of the contact structure 150 has a maximum width W1 and a minimum width W2, and the gate structure 148 of the transistor 140 has a maximum width W3 and a minimum width W4. The maximum width W1 of the middle portion 156 is greater than the maximum width W3 of the gate structure 148. The minimum width W2 of the middle portion 156 is greater than the minimum width W4 of the gate structure 148. By this configuration, the middle portion 156 can improve the conductivity resistance of the contact structure 150.

[0044] In some embodiments, the top portion 154 and the bottom portion 152 of the contact structure 150 are substantially aligned with each other in the vertical direction D. In some embodiments, the vertical direction D is the extending direction of the bottom portion 152 (or the top portion 154). In some embodiments, the vertical direction D is substantially perpendicular to the extending directions of the wires 122 and 124. In some other embodiments, the top portion 154 and the bottom portion 152 of the contact structure 150 are misaligned (not aligned) with each other in the vertical direction D, such as... Figure 13As shown.

[0045] In some embodiments, the memory element 100 further includes a bit line 160. The bit line 160 is disposed on the top portion 154 of the contact structure 150 and the second source / drain region 144 of the transistor 140, and contacts the top portion 154 of the contact structure 150 and the second source / drain region 144 of the transistor 140. That is, the contact structure 150 is electrically connected to the transistor 140 through the bit line 160. In some embodiments, the extension direction of the bit line 160 is substantially perpendicular to the extension direction of the word line WL (i.e., the gate structure 148) of the transistor 140, such as... Figure 2 As shown. Furthermore, the extension direction of bit line 160 is also substantially perpendicular to the vertical direction D.

[0046] Figures 3 to 12 It is based on some embodiments disclosed herein that are formed at various stages. Figure 1 A cross-sectional view of the method for using memory element 100.

[0047] See Figure 3 A substrate 110 is provided, comprising a memory region 112 and a peripheral region 114. In some embodiments, the substrate 110 comprises elemental semiconductors, compound semiconductors, alloy semiconductors, or combinations thereof. Elemental semiconductors may be, for example, germanium (Ge) or silicon (Si). Compound semiconductors may comprise silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductors may comprise SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0048] Conductors 122 are formed on the memory region 112 of the substrate 110, and conductors 124 are disposed on the peripheral region 114 of the substrate 110. The heights of conductors 122 and 124 are substantially the same. In other words, conductors 122 and 124 are substantially coplanar. Conductors 122 and 124 can be formed in the same process and therefore can contain the same material. For example, a blanket conductive layer is formed on the substrate 110, and a patterning process, such as an etching process, is performed to form conductors 122 and 124 on the substrate 110. Conductors 122 and 124 can be formed by metallization processes, and the aforementioned metal can be, for example, tungsten (W), or other suitable conductive materials.

[0049] In some embodiments, an isolation structure 126 is formed between wires 122 and 124. The isolation structure 126 may be made of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or other suitable materials.

[0050] See Figure 4After forming conductors 122 and 124, a dielectric layer 170 is formed on conductors 122 and 124. Subsequently, a capacitor 130 is formed on the first conductor 122. Specifically, each capacitor 130 includes a lower electrode 132, a dielectric layer 134 surrounding the lower electrode 132, and an upper electrode 136 covering the dielectric layer 134. The lower electrode 132 and the upper electrode 136 can be made of polysilicon or other suitable conductive materials. The dielectric layer 134 can be made of a high-k dielectric material. For example, the high-k material can be selected from metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminates, HfO2, or combinations thereof. In some embodiments, the dielectric layer 170 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable methods. The dielectric layer 170 may be made of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or other suitable materials.

[0051] After the capacitor 130 is formed on the first conductor 122, the bottom portion 152 of the contact structure 150 is formed on the second conductor 124. For example, an opening is formed in the dielectric layer 170 to expose the conductor 124, and the opening is filled with a conductive material. In some embodiments, excess conductive material is removed by performing a planarization process (e.g., CMP process), such that a portion of the conductive material in the opening forms the bottom portion 152 of the contact structure 150. In some embodiments, the bottom portion 152 of the contact structure 150 is made of tungsten, aluminum, copper, or other conductive materials. In some embodiments, the bottom portion 152 of the contact structure 150 is formed before the capacitor 130 is formed on the first conductor 122.

[0052] Subsequently, a dielectric layer 180 is formed, covering the capacitor 130 and the bottom portion 152 of the contact structure 150. In other words, the dielectric layer 180 is formed on the dielectric layer 170. In some embodiments, the dielectric layer 180 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable methods. The dielectric layer 180 can be made of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or other suitable materials. In some embodiments, the dielectric layer 170 and the dielectric layer 180 are made of different materials.

[0053] See Figure 5After forming the dielectric layer 180, a first opening O1 and at least one second opening O2 are formed in the dielectric layer 180, wherein the first opening O1 is located on the capacitor 130, and the second opening O2 exposes the bottom portion 152 of the contact structure 150. In some embodiments, each first opening O1 is narrower than the second opening O2. In some embodiments, the formation of the first opening O1 and the second opening O2 is performed using a single etching process. The dielectric layer 180 is etched using a dry etching or wet etching method to form the first opening O1 and the second opening O2. When using dry etching, the process gas may contain CF4, CHF3, NF3, SF6, Br2, HBr, Cl2, or combinations thereof. A diluent gas, such as N2, O2, or Ar, may optionally be used. When using wet etching, the etching solution (etchant) may contain NH4OH:H2O2:H2O (APM), NH2OH, KOH, HNO3:NH4F:H2O, or similar substances.

[0054] See Figure 5 and Figure 6 Conductive material is filled into the first opening O1 and the second opening O2, such that the middle portion 156 of the contact structure 150 is formed in the second opening O2, and the gate material 190 is formed in the first opening O1. Since the middle portion 156 and the bottom portion 152 of the contact structure 150 are formed using different deposition processes, an interface I2 is formed between the middle portion 156 and the bottom portion 152. In some embodiments, the conductive material (middle portion 156 and gate material 190) comprises a multilayer structure, such as a work function metal layer and a filler metal layer. For example, a work function metal layer is filled into the first opening O1 and the second opening O2, and then a filler metal layer is formed on the work function metal layer. In some embodiments, the conductive material (middle portion 156 and gate material 190) is made of metal, such as tungsten, or other suitable materials. In some embodiments, the middle portion 156 and the bottom portion 152 of the contact structure 150 comprise the same material.

[0055] In some embodiments, after the first opening O1 and the second opening O2 are filled with conductive material, a planarization process (e.g., CMP process) is performed to remove excess conductive material outside the first opening O1 and the second opening O2, such that the upper surface of the middle portion 156 of the contact structure 150 is flush with the gate material 190 (and the subsequently formed gate structure 148, see [reference]). Figure 8 The upper surfaces of ) are essentially coplanar.

[0056] See Figures 5 to 7After forming the intermediate portion 156 of the contact structure 150 and the gate material 190, third openings O3 are formed in the gate material 190 to form gate structures 148 in the first opening O1. In other words, a portion of the gate material 190 is etched until the dielectric layer 170 is exposed. In some embodiments, the intermediate portion 156 of the contact structure 150 and the gate structure 148 contain the same material, such as tungsten or other suitable metal.

[0057] See Figure 7 and Figure 8 Dielectric material 200 is filled in the third opening O3. Specifically, dielectric material 200 is formed on dielectric layer 170 and on the sidewalls of gate structure 148. In some embodiments, dielectric material 200 and dielectric layer 180 are separated by gate structure 148.

[0058] In some embodiments, dielectric material 200 comprises a silicon oxide layer. In other embodiments, dielectric material 200 may optionally comprise a high-k dielectric material, silicon oxynitride, other suitable materials, or combinations thereof. The high-k material may be selected from metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, HfO2, or combinations thereof. Dielectric material 200 may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, other suitable processes, or combinations thereof.

[0059] See Figure 8 and Figure 9 After the dielectric material 200 is formed, a dielectric layer 210 is formed on the intermediate portion 156 of the gate structure 148, dielectric material 200, dielectric layer 180, and contact structure 150. Subsequently, an opening O4 is formed in the dielectric layer 210, dielectric material 200, and dielectric layer 170 to form a gate dielectric layer 147 and expose the upper electrode 136 of the capacitor 130. In other words, the sidewall of the gate dielectric layer 147 away from the gate structure 148 is exposed through the fourth opening O4.

[0060] In some embodiments, the dielectric layer 210 is formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable methods. The dielectric layer 210 may be made of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or other suitable materials.

[0061] See Figure 9 and Figure 10After the fourth opening O4 is formed in the dielectric layer 210, an active region is formed in the fourth opening O4. Specifically, each active region includes a first source / drain region 142, a second source / drain region 144, and a channel 146. The first source / drain region 142 is formed in the dielectric layer 170, the channel 146 is formed on the sidewall of the gate dielectric layer 147, and the second source / drain region 144 is formed in the dielectric layer 210. In some embodiments, such as... Figures 7 to 10 As shown, the gate dielectric layer 147 and the channel 146 are formed in the third opening O3.

[0062] In some implementations, after the active region is formed in the fourth opening O4, a planarization process, such as a CMP process, is performed to remove the excess portion outside the fourth opening O4.

[0063] In some embodiments, the first source / drain region 142, the second source / drain region 144, and the channel 146 comprise the same material. In some embodiments, the first source / drain region 142, the second source / drain region 144, and the channel 146 are oxide layers, and their material differs from that of the gate dielectric layer 147. For example, the first source / drain region 142, the second source / drain region 144, and the channel 146 may comprise silicon, oxide semiconductor, or other suitable materials.

[0064] See Figure 11 After the active regions (first source / drain region 142, second source / drain region 144, and channel 146) are formed, a fifth opening O5 is formed in the dielectric layer 210, exposing the middle portion 156 of the contact structure 150. In some embodiments, the width of the fifth opening O5 is smaller than the width of the upper surface 157 of the middle portion 156 of the contact structure 150. In other words, a portion of the upper surface 157 of the middle portion 156 is exposed, while the remaining portion of the upper surface 157 of the middle portion 156 is covered by the dielectric layer 210.

[0065] See Figure 11 and Figure 12 After the fifth opening O5 is formed in the dielectric layer 210, the top portion 154 of the contact structure 150 is formed in the fifth opening O5, and the bit line 160 is formed on the dielectric layer 210. In some embodiments, the top portion 154 of the contact structure 150 and the bit line 160 can be formed by forming a conductive material in the fifth opening O5 and on the dielectric layer 210, and by patterning the conductive material using a suitable photolithography technique to form the bit line 160.

[0066] In some embodiments, the top portion 154 of the contact structure 150 and the bit line 160 are formed using the same deposition process, resulting in no interface between the top portion 154 and the bit line 160. In other embodiments, the top portion 154 of the contact structure 150 and the bit line 160 are formed using different deposition processes. For example, the top portion 154 of the contact structure 150 is formed in the dielectric layer 210, and then the bit line 160 is formed on the dielectric layer 210 using another deposition process, resulting in an interface between the top portion 154 and the bit line 160. Figure 12 As shown.

[0067] In some embodiments, the top portion 154 of the contact structure 150 and the bit line 160 comprise the same material, such as tungsten, aluminum, copper, or other conductive materials. In some embodiments, the top portion 154 and the bottom portion 152 of the contact structure 150 comprise the same material. Because the top portion 154 and the middle portion 156 of the contact structure 150 are formed using different deposition processes, an interface I1 is formed between the top portion 154 and the middle portion 156.

[0068] Figure 13 This is a cross-sectional view of a memory element 100a according to another embodiment of this disclosure. (See diagram below.) Figure 13 As shown, memory element 100a includes a substrate 110, wires 124, capacitor 130, transistor 140, contact structure 150a, and bit line 160. Figure 13 Memory element 100a and Figure 1 The difference in memory element 100 involves the outline of contact structure 150a. The arrangement of substrate 110, wire 124, capacitor 130, transistor 140, and bit line 160 is similar. Figure 1 The implementation methods shown will not be described in detail here.

[0069] exist Figure 13In the contact structure 150a, a bottom portion 152a, a top portion 154a, and a middle portion 156a are included. The bottom portion 152a is connected to the wire 124. The top portion 154a is connected to the second source / drain region 144 of the transistor 140. The middle portion 156a is wider than the top portion 154a and the bottom portion 152a, wherein the height of the middle portion 156a of the contact structure 150a is substantially the same as the height of the gate structure 148 of the transistor 140. The top portion 154a and the bottom portion 152a of the contact structure 150a are misaligned (disaligned) with each other in the vertical direction D. In some embodiments, the angle θ between the sidewall 153a and the lower surface 155a of the middle portion 156a is greater than about 90 degrees and less than about 180 degrees. For example, the angle θ between the sidewall 153a of the middle portion 156a and the lower surface 155a of the middle portion 156a is between about 135 degrees and about 180 degrees. Figure 13 Other related structural and manufacturing details of the memory element 100a are consistent with Figure 1 The memory element 100 is essentially the same or similar, so it will not be described in detail here.

[0070] While the embodiments have been disclosed in detail above, other embodiments are possible and are not intended to limit the scope of this disclosure. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments disclosed herein.

[0071] Any person skilled in the art may make various changes or substitutions without departing from the spirit and scope of this disclosure, and all such changes or substitutions should be covered within the scope of protection of the claims appended to this disclosure.

[0072] [Symbol Explanation]

[0073] 100: Memory Components

[0074] 100a: Memory element

[0075] 110:Substrate

[0076] 112: Memory area

[0077] 114: Surrounding Area

[0078] 122: Conductor

[0079] 124: Conductor

[0080] 126: Isolation Structure

[0081] 130: Capacitor

[0082] 132: Lower electrode

[0083] 134: Dielectric layer

[0084] 136: Upper electrode

[0085] 140: Transistor

[0086] 141: Lower surface

[0087] 142: First source / drain region

[0088] 143: Upper surface

[0089] 144: Second source / drain region

[0090] 146: Channel

[0091] 147: Gate Dielectric Layer

[0092] 148: Gate Structure

[0093] 149: Dielectric Structure

[0094] 150: Contact Structure

[0095] 150a: Contact structure

[0096] 152: Bottom part

[0097] 152a: Bottom part

[0098] 153: Sidewall

[0099] 153a: Sidewall

[0100] 154: Top section

[0101] 154a: Top part

[0102] 155: Lower surface

[0103] 155a: Lower surface

[0104] 156: Middle section

[0105] 156a: Middle part

[0106] 157: Upper surface

[0107] 160: Bit line

[0108] 170: Dielectric layer

[0109] 180: Dielectric layer

[0110] 190: Gate material

[0111] 200: Dielectric material

[0112] 210: Dielectric layer

[0113] D: Vertical direction

[0114] I1: Interface

[0115] I2: Interface

[0116] O1: Opening

[0117] O2: Opening

[0118] O3: Opening

[0119] O4: Opening

[0120] O5: Opening

[0121] W1: Maximum width

[0122] W2: Minimum width

[0123] W3: Maximum width

[0124] W4: Minimum width

[0125] WL: Character Line

[0126] θ: Angle.

Claims

1. A memory element, comprising: A memory element comprising: a substrate having a memory region and a peripheral region; a conductive line on the peripheral region of the substrate; a capacitor on the memory region of the substrate; a transistor on and connected to the capacitor, the transistor comprising: a first source / drain region and a second source / drain region, wherein the first source / drain region is connected to the capacitor; a channel between the first source / drain region and the second source / drain region; and a gate structure laterally surrounding the channel; a contact structure on the peripheral region of the substrate, the contact structure comprising: a bottom portion connected to the conductive line; a top portion connected to the second source / drain region of the transistor; and an intermediate portion wider than the top portion and the bottom portion, wherein a height of the intermediate portion of the contact structure is substantially the same as a height of the gate structure of the transistor; and a bit line on and contacting the top portion of the contact structure and the second source / drain region of the transistor, wherein the bit line extends from the top portion of the contact structure to the second source / drain region of the transistor, and the top portion of the contact structure and the second source / drain region of the transistor are separated.

2. The memory element of claim 1, wherein the intermediate portion of the contact structure has a sidewall and a lower surface contacting the bottom portion of the contact structure, and an angle between the sidewall and the lower surface is in a range between 135 degrees and 180 degrees.

3. The memory element of claim 1, wherein the top portion of the contact structure and the bottom portion of the contact structure are vertically offset from each other.

4. The memory element of claim 1, wherein the top portion of the contact structure and the bottom portion of the contact structure are substantially aligned in a vertical direction.

5. The memory element of claim 1, wherein an extension direction of the bit line is substantially perpendicular to an extension direction of the gate structure of the transistor.

6. The memory element of claim 1, wherein the intermediate portion of the contact structure and the gate structure of the transistor comprise a same material.

7. The memory element of claim 1, wherein a lower surface of the intermediate portion of the contact structure and a lower surface of the gate structure of the transistor are substantially coplanar.

8. The memory element of claim 1, wherein an upper surface of the intermediate portion of the contact structure and an upper surface of the gate structure of the transistor are substantially coplanar.

9. The memory element of claim 1, wherein a width of the intermediate portion of the contact structure is greater than a width of the gate structure of the transistor.

10. The memory element of claim 1, wherein an interface is formed between the top portion of the contact structure and the intermediate portion of the contact structure.

11. The memory element of claim 1, wherein an interface is formed between the bottom portion of the contact structure and the intermediate portion of the contact structure. further comprising: a lower electrode; 12. The memory element of claim 1, wherein, a dielectric layer surrounding the lower electrode; and a capacitor on the memory region of the substrate; ​ a top portion of the contact structure in the second dielectric layer.

13. A method of forming a memory element, comprising: comprising: forming a first conductive line on a memory region of a substrate and a second conductive line on a peripheral region of the substrate; forming a capacitor on the first conductive line; forming a bottom portion of a contact structure on the second conductive line; forming a first dielectric layer covering the capacitor and the bottom portion of the contact structure; forming a first opening and a second opening in the first dielectric layer, wherein the first opening is on the capacitor and the second opening exposes the bottom portion of the contact structure; filling a conductive material in the first opening and the second opening such that a middle portion of the contact structure is formed in the second opening and a gate material is formed in the first opening; forming a third opening in the gate material to form a gate structure in the first opening; forming a gate dielectric layer and a channel in the third opening; and forming a bit line to connect the channel and the contact structure.

14. The method of claim 13, wherein forming the first opening and the second opening is performed using one etching process. further comprising:

15. The method of claim 13, wherein, forming a second dielectric layer on the gate structure before forming the bit line. further comprising:

16. The method of claim 15, wherein, forming a top portion of the contact structure in the second dielectric layer. further comprising:

17. The method of claim 15, wherein, forming a source / drain region in the second dielectric layer and forming the bit line to connect to the source / drain region.

18. The method of claim 15, wherein the middle portion of the contact structure and the gate structure comprise a same material.

19. The method of claim 15, wherein the channel is an oxide layer. ​

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