Semiconductor memory device

Abstract

An embodiment provides a semiconductor memory device that can be miniaturized. The semiconductor memory device according to the embodiment includes a semiconductor substrate and a memory cell array. The semiconductor substrate includes a first region to a third region that are arranged in sequence in a first direction intersecting with its surface and a second direction intersecting with its surface. The memory cell array includes: a first conductive layer that is laminated in the first direction; a third insulating layer that is provided in the second region and laminated in the first direction; a fourth insulating layer that is provided in the second region and is located between a side surface of the third insulating layer in a third direction intersecting with the first direction and the second direction and a side surface of the first conductive layer in the third direction, and extends in the first direction and the second direction; and a fifth insulating layer that is provided in the second region and is located between a side surface of the third insulating layer in the second direction and a side surface of the first conductive layer in the second direction, and extends in the first direction and the third direction. In the first direction, an end position on the semiconductor substrate side of the fifth insulating layer in the first direction is different from an end position on the semiconductor substrate side of the fourth insulating layer in the first direction.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2020-146444 (filing date: August 31, 2020). This application incorporates the entire content of the base application by reference thereto. Technical Field

[0002] This embodiment relates to a semiconductor memory device. Background Art

[0003] A semiconductor memory device is known, which includes: a semiconductor substrate; a plurality of conductive layers laminated in a direction intersecting the surface of the semiconductor substrate; semiconductor pillars extending in a direction intersecting the surface of the semiconductor substrate and facing these plurality of conductive layers; and a gate insulating film provided between the conductive layer and the semiconductor pillars. Summary of the Invention

[0004] An embodiment provides a semiconductor memory device capable of miniaturization.

[0005] A semiconductor memory device according to one embodiment includes: a semiconductor substrate; and a memory cell array disposed separately from the semiconductor substrate in a first direction intersecting the surface of the semiconductor substrate. The semiconductor substrate includes a first region to a third region arranged in sequence in a second direction intersecting the first direction. The memory cell array includes: a plurality of first conductive layers extending from the first region through the second region to the third region in the second direction and alternately laminated with a plurality of first insulating layers in the first direction; a first semiconductor layer provided in the first region and extending in the first direction and facing the plurality of first conductive layers; a second semiconductor layer provided in the third region and extending in the first direction and facing the plurality of first conductive layers; a plurality of third insulating layers provided in the second region and alternately laminated with a plurality of second insulating layers in the first direction; a first contact portion provided in the second region and extending in the first direction and facing the plurality of third insulating layers, one end in the first direction being closer to the semiconductor substrate than the plurality of first conductive layers and the other end in the first direction being farther from the semiconductor substrate than the plurality of first conductive layers; a fourth insulating layer provided in the second region and located between the side surfaces in a third direction intersecting the first and second directions of the plurality of third insulating layers and the side surfaces in the third direction of the plurality of first conductive layers and extending in the first and second directions; and a fifth insulating layer provided in the second region and located between the side surfaces in the second direction of the plurality of third insulating layers and the side surfaces in the second direction of the plurality of first conductive layers and extending in the first and third directions. The end portion on the semiconductor substrate side in the first direction of the fifth insulating layer is closer to the semiconductor substrate than the end portion on the semiconductor substrate side in the first direction of the fourth insulating layer, or is farther from the semiconductor substrate than the end portion on the semiconductor substrate side in the first direction of the fourth insulating layer. Description of the Drawings

[0006] Figure 1 is a schematic top view of the semiconductor memory device according to the first embodiment.

[0007] Figure 2 is a partial perspective view showing a cut-away of the semiconductor memory device according to the first embodiment.

[0008] Figure 3 is Figure 1 a schematic enlarged cross-sectional view of the portion indicated by A of

[0009] Figure 4 is a schematic cross-sectional view taken along line B-B' of Figure 3 the structure shown and viewed in the direction of the arrow.

[0010] Figure 5 is a schematic cross-sectional view taken along line C-C' of Figure 3 the structure shown and viewed in the direction of the arrow.

[0011] Figure 6 is a schematic cross-sectional view taken along line D-D' of Figure 3 the structure shown and viewed along the direction of the arrow.

[0012] Figure 7 is Figure 6 a schematic enlarged view of the portion indicated by E of

[0013] Figure 8 is a schematic cross-sectional view taken along line F-F' of Figure 3 the structure shown and viewed along the direction of the arrow.

[0014] Figure 9 is Figure 8 an enlarged cross-sectional view of the portion indicated by G of

[0015] Figure 10 is a view showing Figure 8 an enlarged cross-sectional view of another example of the portion indicated by G of

[0016] Figure 11 is a schematic Y-Z cross-sectional view showing the manufacturing method of the semiconductor memory device according to the first embodiment.

[0017] Figure 12 is a schematic X-Z cross-sectional view showing the manufacturing method of the semiconductor memory device according to the first embodiment.

[0018] Figure 13It is a schematic Y-Z cross-sectional view showing a manufacturing method of a semiconductor memory device according to the first embodiment.

[0019] Figure 14 It is a schematic X-Z cross-sectional view showing a manufacturing method of a semiconductor memory device according to the first embodiment.

[0020] Figure 15 It is a schematic X-Z cross-sectional view showing a manufacturing method of a semiconductor memory device according to the first embodiment.

[0021] Figure 16 It is a schematic Y-Z cross-sectional view showing a manufacturing method of a semiconductor memory device according to the first embodiment.

[0022] Figure 17 It is a schematic Y-Z cross-sectional view showing a manufacturing method of a semiconductor memory device according to the first embodiment.

[0023] Figure 18 It is a schematic Y-Z cross-sectional view showing a manufacturing method of a semiconductor memory device according to the first embodiment.

[0024] Figure 19 It is a schematic X-Z cross-sectional view showing a manufacturing method of a semiconductor memory device according to the first embodiment.

[0025] Figure 20 It is a schematic Y-Z cross-sectional view showing a manufacturing method of a semiconductor memory device according to the first embodiment.

[0026] Figure 21 It is a schematic X-Z cross-sectional view showing a manufacturing method of a semiconductor memory device according to the first embodiment.

[0027] Figure 22 It is a schematic enlarged cross-sectional view showing a semiconductor memory device according to the comparative example.

[0028] Figure 23 It is a schematic top view showing a through contact portion structure of a semiconductor memory device according to a modified example.

[0029] Figure 24 It is a schematic top view showing a through contact portion structure of a semiconductor memory device according to a modified example.

[0030] Figure 25 It is a schematic top view showing a through contact portion structure of a semiconductor memory device according to a modified example.

[0031] Figure 26 It is a schematic top view showing a through contact portion structure of a semiconductor memory device according to a modified example.

[0032] Figure 27 is a schematic top view showing the structure of the through-contact portion of the semiconductor memory device according to the modified example.

[0033] Reference numeral description

[0034] 100 semiconductor substrate, 110 conductive layer, 120 semiconductor pillar, 130 gate insulating film, 150 contact portion, 151 through-contact portion. Detailed implementation manners

[0035] Next, the semiconductor memory device according to the implementation manner will be described in detail with reference to the drawings. In addition, the following implementation manners are merely examples and are not intended to limit the present invention.

[0036] In addition, in this specification, a predetermined direction parallel to the surface of the semiconductor substrate is referred to as the X direction, a direction parallel to the surface of the semiconductor substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the surface of the semiconductor substrate is referred to as the Z direction.

[0037] In addition, in this specification, sometimes a direction along a predetermined plane is referred to as the first direction, a direction along the predetermined plane and intersecting the first direction is referred to as the second direction, and a direction intersecting the predetermined plane is referred to as the third direction. These first direction, second direction, and third direction may or may not correspond to a certain direction among the X direction, Y direction, and Z direction.

[0038] In addition, in this specification, expressions such as "upper" and "lower" are based on the semiconductor substrate. For example, the direction away from the semiconductor substrate along the Z direction is referred to as upper, and the direction approaching the semiconductor substrate along the Z direction is referred to as lower. In addition, in the case of expressing the lower surface and the lower end portion with respect to a certain component, it is assumed to mean the surface and the end portion on the semiconductor substrate side of the component, and in the case of expressing the upper surface and the upper end portion, it is assumed to mean the surface and the end portion on the side opposite to the semiconductor substrate of the component. In addition, a plane intersecting the X direction or the Y direction is referred to as a side surface, etc.

[0039] In addition, in this specification, when it is expressed that the first component is "electrically connected" to the second component, it may be that the first component is directly connected to the second component, or the first component is connected to the second component via wiring, semiconductor components, transistors, etc. For example, in the case where three transistors are connected in series, even if the second transistor is in the cut-off (OFF) state, the first transistor is "electrically connected" to the third transistor.

[0040] In addition, in this specification, when it is expressed that the first component is "connected between" the second component and the third component, it sometimes means that the first component, the second component, and the third component are connected in series, and the first component is provided on the current path between the second component and the third component.

[0041] In addition, in this specification, when it is expressed that a circuit or the like "conducts" two wirings or the like, for example, it sometimes means that the circuit or the like includes a transistor or the like, the transistor or the like is provided on the current path between the two wirings, and the transistor or the like is in a conducting (ON) state.

[0042] [First Embodiment]

[0043] Hereinafter, the configuration of the semiconductor storage device according to the first embodiment will be described with reference to the drawings. In addition, the following drawings are schematic drawings, and some configurations may be omitted for the sake of convenience of explanation.

[0044] [Structure]

[0045] Figure 1 is a schematic top view of the semiconductor storage device according to the first embodiment. Figure 2 is a partial perspective view showing the semiconductor storage device according to the first embodiment cut away. Figure 3 is Figure 1 a schematic enlarged cross-sectional view of the portion indicated by A in, showing the configuration in the memory cell array layer. Figure 4 is a schematic cross-sectional view taken along the line B-B' of Figure 3 the structure shown and viewed in the direction of the arrow. Figure 5 is a schematic cross-sectional view taken along the line C-C' of Figure 3 the structure shown and viewed in the direction of the arrow. Figure 6 is a schematic cross-sectional view taken along the line D-D' of Figure 3 the structure shown and viewed in the direction of the arrow. Figure 7 is Figure 6 a schematic enlarged view of the portion indicated by E in. Figure 8 is a schematic cross-sectional view taken along the line F-F' of Figure 3 the structure shown and viewed in the direction of the arrow. Figure 9 is Figure 8 an enlarged cross-sectional view of the portion indicated by G in. Figure 10 is a cross-sectional view showing Figure 8 another example of the portion indicated by G in.

[0046] For example, as Figure 1As shown, the semiconductor memory device according to the first embodiment includes a semiconductor substrate 100. In the illustrated example, four memory cell arrays MCA arranged in the X direction and the Y direction are provided on the semiconductor substrate 100.

[0047] [Structure of the semiconductor memory device]

[0048] For example, as Figure 2 , Figure 4 and Figure 5 shown, the semiconductor memory device according to the first embodiment includes a semiconductor substrate 100, a transistor layer L provided on the semiconductor substrate 100 TR , a wiring layer L provided above the transistor layer L TR , a memory cell array layer L provided above the wiring layer L W1 , and a wiring layer L provided above the memory cell array layer L W1 . MCA And a wiring layer L provided above the memory cell array layer L MCA . W2 .

[0049] [Structure of the semiconductor substrate 100]

[0050] The semiconductor substrate 100 is, for example, a semiconductor substrate formed of P-type silicon (Si) containing a P-type impurity such as boron (B). For example, as Figures 2 - 4 shown, a semiconductor substrate region 100S and an insulating region 100I are provided on the surface of the semiconductor substrate 100.

[0051] [Structure of the transistor layer L TR

[0052] The transistor layer L TR includes a plurality of transistors Tr, electrodes E TR and contact portions C TR etc., which constitute a control circuit for controlling the memory cell array MCA. The transistor Tr is a field effect transistor using the surface of the semiconductor substrate region 100S as a channel region (gate region). The electrode E TR functions as a gate electrode of the transistor Tr. The contact portion C TR extends in the Z direction, and its lower end is connected to the semiconductor substrate 100 and the electrode E TR , and its upper end is connected to the wiring of the wiring layer L W1 .

[0053] [Structure of the wiring layer L W1

[0054] For example, as Figures 2 - 4 shown, the wiring layer L W1 ​​At least one of the configuration in the multiple wiring and memory cell array MCA included and the configuration in the control circuit that controls the memory cell array MCA is electrically connected.

[0055] Wiring layer L W1 Includes a plurality of wirings. These multiple wirings may also include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0056] [Structure of memory cell array layer L MCA

[0057] For example, as Figure 3 shown, in the memory cell array layer L MCA a plurality of memory block groups BLK arranged in the Y direction are provided S and an inter-block structure 160 provided therebetween. In addition, each memory block group BLK S respectively includes two memory blocks BLK arranged in the Y direction, two inter-block structures 161 arranged therebetween and in the X direction, and a via contact portion structure 170 arranged therebetween. In the following description, sometimes the Figure 3 four memory blocks BLK shown are respectively referred to as memory blocks BLK_A to BLK_D.

[0058] [Structure of memory block BLK of memory cell array layer L MCA

[0059] As Figure 3 shown, each memory block BLK includes two memory hole regions R extending in the X direction and arranged in the X direction MH1 , R MH2 , a contact portion region R C and a wiring region R W . The contact portion region R C and the wiring region R W are arranged in the X direction and are provided between the memory hole region R MH1 and the memory hole region R MH2 .

[0060] In memory blocks BLK_B and BLK_C, on the side closer to the memory hole region R MH1 (left side in Figure 3 ) the contact portion region R C is arranged, and on the side closer to the memory hole region R MH2 (right side in Figure 3 ) the wiring region R W is arranged.

[0061] ​​On the other hand, in the storage blocks BLK_A and BLK_D, on the side close to the storage hole region R MH1 (on the left side in Figure 3 ), a wiring region R W is arranged, and on the side close to the storage hole region R MH2 (on the right side in Figure 3 ), a contact portion region R C is arranged.

[0062] [Structure of the storage hole regions R MH1 , R MH2 of the storage block BLK]

[0063] As shown in Figure 3 and Figure 6 , the storage hole regions R MH1 , R MH2 of the storage block BLK each include a plurality of string units SU arranged in the Y direction and an inter-string unit insulating layer 162 such as silicon dioxide (SiO2) provided between two adjacent string units SU in the Y direction.

[0064] For example, as shown in Figure 2 and Figure 6 , the storage hole regions R MH1 , R MH2 of the storage block BLK include a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor columns 120 extending in the Z direction, and a plurality of gate insulating films 130 respectively provided between the plurality of conductive layers 110 and the plurality of semiconductor columns 120.

[0065] The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction. The conductive layer 110 may also include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). In addition, the conductive layer 110 may also include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon dioxide (SiO2) is provided between the plurality of conductive layers 110 arranged in the Z direction.

[0066] A conductive layer 111 is provided below the conductive layer 110. The conductive layer 111 may also include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). In addition, an insulating layer 101 such as silicon dioxide (SiO2) is provided between the conductive layer 111 and the conductive layer 110.

[0067] A conductive layer 112 is provided below the conductive layer 111. The conductive layer 112 includes a semiconductor layer 113 joined to the lower end of the semiconductor pillar 120 and a conductive layer 114 in contact with the lower surface of the semiconductor layer 113. The semiconductor layer 113 may include, for example, polysilicon containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). The conductive layer 114 may include, for example, a metal such as tungsten (W), a conductive layer such as tungsten silicide, or other conductive layers. In addition, an insulating layer 101 such as silicon oxide (SiO2) is provided between the conductive layer 112 and the conductive layer 111.

[0068] The conductive layer 112 functions as a source line.

[0069] The conductive layer 111 functions as a gate electrode of a source-side select transistor, etc. The conductive layer 111 is electrically independent for each memory block BLK.

[0070] In addition, one or more of the lowermost conductive layers 110 among the plurality of conductive layers 110 are electrically independent for each memory block BLK and function as a gate electrode of a source-side select transistor, etc. At that time, the conductive layer 111 may be omitted.

[0071] In addition, the plurality of conductive layers 110 located at positions above it are electrically independent for each memory block BLK and function as word lines, etc.

[0072] In addition, one or more of the conductive layers 110 located at positions above it are electrically independent for each string unit SU and function as a gate electrode of a drain-side select transistor, etc.

[0073] The semiconductor pillars 120 are arranged in a predetermined pattern in the X direction and the Y direction. The semiconductor pillars 120 function as memory cells, etc. The semiconductor pillars 120 are, for example, a semiconductor layer such as polysilicon (Si). For example, as Figure 2 and Figure 6 shown, the semiconductor pillar 120 has a substantially bottomed cylindrical shape, and an insulating layer 125 such as silicon oxide is provided in the central portion.

[0074] The gate insulating film 130 has a substantially bottomed cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120. For example, as Figure 7 shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 laminated between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film 131 and the block insulating film 133 are, for example, insulating films such as silicon oxide (SiO2). The charge storage film 132 is, for example, a film capable of storing charges such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120.

[0075] In addition, an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride is shown in Figure 7 . However, the gate insulating film 130 may also include, for example, a floating gate made of polysilicon containing N-type or P-type impurities.

[0076] [Structure of the contact portion region R of the memory block BLK C

[0077] For example, as shown in Figures 3 - 5 , in the contact portion region R of the memory cell array layer L MCA , a plurality of conductive layers 110 are arranged in the Z direction, similar to the memory hole regions R C , R MH1 , R MH2 . In practice, the number of conductive layers 110 is, for example, several tens to one hundred and several tens, but in Figure 4 and Figure 5 , for ease of understanding, a state in which the memory cell array layer L MCA has eight conductive layers 110 is illustrated.

[0078] In the contact portion region R C , a wiring region R extending in the X direction and a connection region R extending in the X direction are arranged in the Y direction. CW The wiring region R CC is arranged at a position close to the inter-block structure 160, and the connection region R CW is arranged at a position close to the inter-block structure 161. CC

[0079] The wiring region R CW includes a part of the plurality of conductive layers 110 arranged in the Z direction. A part of these conductive layers 110 extends in the X direction along the inter-block structure 160.

[0080] The connection region R CC includes a plurality of contact portions 150 arranged in the X direction and a part of the plurality of conductive layers 110 arranged in the Z direction.

[0081] Each contact portion 150 extends in the Z direction and may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The lower end of each contact portion 150 is connected to one of a part of the plurality of conductive layers 110 arranged in the Z direction.

[0082] ​A part of a plurality of conductive layers 110 arranged in the Z direction respectively includes a connection portion connected to one of the plurality of contact portions 150, and an opening 110a for connecting the other contact portions 150 to the lower conductive layer 110. The width of the opening 110a in the X direction gradually narrows from the upper conductive layer 110 to the lower conductive layer 110, whereby a substantially stepped structure (depression) is formed in the connection region R CC formed ( Figure 4 , Figure 5 ). An insulating layer 140 such as silicon oxide (SiO2) is filled in the substantially stepped structure (depression).

[0083] [Structure of the wiring region R of the memory block BLK W

[0084] The wiring region R W includes a part of a plurality of conductive layers 110 arranged in the Z direction. A part of these conductive layers 110 extends in the X direction along the inter-block structure 160.

[0085] The wiring region R W of the plurality of conductive layers 110 and the plurality of conductive layers 110 in the aforementioned wiring region R CW are connected layer by layer. Therefore, the plurality of conductive layers 110 in the memory hole region R MH1 and the plurality of conductive layers 110 in the memory hole region R MH2 are connected layer by layer via the wiring region R W and the plurality of conductive layers 110 in the wiring region R CW .

[0086] [Structure of the inter-block structure 161 of the memory cell array layer L MCA

[0087] For example, as Figures 2 - 4 shown, the inter-block structure 161 includes a pair of insulating layers 161a, 161a extending in the Z direction and the X direction, and a conductive layer 161b disposed between the insulating layers 161a, 161a. For example, as Figure 2 and Figure 4 shown, the conductive layer 161b is connected to the conductive layer 112 at its lower end.

[0088] For example, as Figure 3 shown, the inter-block structure 161 is provided at a position corresponding to the memory hole region R MH1 , the contact portion region R C and the memory hole region R MH2 between two adjacent memory blocks BLK in the Y direction.

[0089] [Memory cell array layer L MCA ​​Structure of the through-contact portion 170

[0090] As Figure 3 shown, in the Y direction, as described above, the through-contact portion structure 170 is disposed between two memory blocks BLK S constituting a memory block group, for example, between the memory blocks BLK_B and BLK_C. More specifically, for example, it is disposed between the wiring region R W of the memory block BLK_B and the wiring region R W of the memory block BLK_C. In addition, in the X direction, the through-contact portion structure 170 is disposed between two inter-block structures 161 arranged in the X direction.

[0091] The through-contact portion structure 170 includes a pair of stopper insulation layers 171 and 172 that extend in the X direction and are separated in the Y direction, and a pair of stopper insulation layers 173 and 174 that extend in the Y direction and are separated in the X direction. The stopper insulation layers 171, 172, 173, and 174 include, for example, silicon oxide (SiO2), etc. As Figure 4 and Figure 5 shown, the stopper insulation layers 171, 172, 173, and 174 extend in the Z direction from the upper part to the lower part of the memory cell array layer L MCA And the X-direction end edges of the stopper insulation layers 171 and 172 are connected to the Y-direction end edges of the stopper insulation layers 173 and 174. Thus, a four-sided cylindrical structure formed of an insulating layer is formed by the stopper insulation layers 171, 172, 173, and 174.

[0092] In addition, in the Z direction, the lower end positions of the stopper insulation layers 171 and 172 are different from the lower end positions of the stopper insulation layers 173 and 174. For example, as Figure 8 and Figure 9 shown, in the Z direction, sometimes the lower ends of the stopper insulation layers 171 and 172 are located at a position lower than the lower ends of the stopper insulation layers 173 and 174. In addition, for example, as Figure 10 shown, in the Z direction, sometimes the lower ends of the stopper insulation layers 171 and 172 are located at a position higher than the lower ends of the stopper insulation layers 173 and 174.

[0093] In addition, the thickness (Y-direction width) of the stopper insulation layers 171 and 172 is different from the thickness (X-direction width) of the stopper insulation layers 173 and 174. For example, as Figure 3As shown, sometimes the thickness (width in the X direction) of the blocking insulating layers 173 and 174 is thicker than the thickness (width in the Y direction) of the blocking insulating layers 171 and 172. Additionally, for example, sometimes the thickness (width in the X direction) of the blocking insulating layers 173 and 174 is thinner than the thickness (width in the Y direction) of the blocking insulating layers 171 and 172.

[0094] In addition, one end of one of the two inter-block structures 161 arranged in the X direction is connected to the central position in the Y direction of the blocking insulating layer 173, and the other end of the other of the two inter-block structures 161 arranged in the X direction is connected to the central position in the Y direction of the blocking insulating layer 174. Therefore, a storage block group BLK is formed. S The conductive layers 110 of the respective layers stacked in the Z direction included in the two storage blocks BLK that make up a storage block group BLK, for example, the storage blocks BLK_B and BLK_C, are truncated in the Y direction by the inter-block structure 161 and the blocking insulating layers 171, 172, 173, and 174 for each storage block.

[0095] As Figures 3 - 5 shown, inside the four-sided cylindrical structure formed by the blocking insulating layers 171, 172, 173, and 174 and made of an insulating layer, there are provided a first group of a plurality of through contact portions 151 arranged in the X direction, a second group of a plurality of through contact portions 151 arranged in the X direction at positions shifted in the Y direction with respect to the first group of a plurality of through contact portions 151, a plurality of insulating layers 110A arranged in the Z direction, and a part of a plurality of insulating layers 101.

[0096] That is, inside the four-sided cylindrical structure formed by the blocking insulating layers 171, 172, 173, and 174, the insulating layers 101 and the insulating layers 110A are alternately stacked in the Z direction. In addition, each through contact portion 151 extends in the Z direction and penetrates through the plurality of insulating layers 110A and the plurality of insulating layers 101.

[0097] The through contact portion 151 may include, for example, a stacked film of titanium nitride (TiN) and tungsten (W), or may include other materials. The outer peripheral surfaces of the through contact portions 151 are respectively connected to the inner peripheral surfaces of the through holes provided in the plurality of insulating layers 110A and the plurality of insulating layers 101. The insulating layer 110A may be, for example, an insulating layer containing silicon (Si) and nitrogen (N) such as silicon nitride (SiN).

[0098] In addition, as Figure 5 shown, the outer peripheral surface of the upper end portion of the through contact portion structure 170 is covered by the insulating layer 140.

[0099] [Structure of the inter-block structure 160 of the storage cell array layer L MCA

[0100] For example, as Figures 2 - 4 ​As shown, the inter-block structure 160 includes a pair of insulating layers 160a, 160a extending in the Z direction and the X direction, and a conductive layer 160b disposed between the insulating layers 160a, 160a. For example, as Figure 2 and Figure 4 shown, the conductive layer 160b is connected to the conductive layer 112 at the lower end.

[0101] For example, as Figure 3 shown, the inter-block structure 160 includes a portion 160 disposed between two adjacent memory blocks BLK in the Y direction and at a position corresponding to the memory hole regions R MH1 、R MH2 and a portion 160 disposed at a position corresponding to the contact portion region R MH and the wiring region R C and R W . In addition, the inter-block structure 160 includes a portion 160 disposed between the above-mentioned portion 160 C-W and the above-mentioned portion 160 MH and a portion 160 disposed between the above-mentioned portion 160 C-W and the above-mentioned portion 160 C-W and the above-mentioned portion 160 C-W . A

[0102] For example, the above-mentioned portion 160 MH1 is disposed between the memory hole region R of the memory block BLK_A MH1 and the memory hole region R of the memory block BLK_B. This portion 160 MH extends in the X direction. MH

[0103] In addition, for example, the above-mentioned portion 160 W is disposed between the wiring region R of the memory block BLK_A C and the contact portion region R of the memory block BLK_B. This portion 160 C-W extends in the X direction. In addition, the position of this portion 160 C-W in the Y direction is set on one side (for example, C-W below) in the Y direction compared to the position of the above-mentioned portion 160 MH in the Y direction. Therefore, for example, the distance between the position of this portion 160 Figure 3 in the Y direction and the position of the inter-block structure 161 corresponding to the memory block BLK_A in the Y direction is smaller than the distance between the position of the above-mentioned portion 160 C-W in the Y direction and the position of the inter-block structure 161 corresponding to the memory block BLK_A in the Y direction. In addition, the width of this portion 160 MH in the X direction is larger than the width of the portion disposed in the contact portion region R of the memory block BLK_B C-W in the X direction.C is wider in the X direction than the maximum opening 110a.

[0104] In addition, for example, in the contact portion region R of the memory block BLK_A C and the wiring region R of the memory block BLK_B W the above-described portion 160 is provided therebetween C-W . This portion 160 C-W extends in the X direction. In addition, the position of this portion 160 C-W in the Y direction is set on the other side in the Y direction (e.g., MH the upper side) than the position of the above-described portion 160 Figure 3 in the Y direction. Therefore, for example, the distance between the position of this portion 160 C-W in the Y direction and the position of the inter-block structure 161 corresponding to the memory block BLK_A in the Y direction is larger than the distance between the position of the above-described portion 160 MH in the Y direction and the position of the inter-block structure 161 corresponding to the memory block BLK_A in the Y direction. In addition, the width of this portion 160 C-W in the X direction is wider than the width in the X direction of the maximum opening 110a provided in the contact portion region R of the memory block BLK_A C . In addition, for example, between the memory hole region R of the memory block BLK_A MH2 and the memory hole region R of the memory block BLK_B MH2 the above-described portion 160 is provided therebetween MH . This portion 160 MH extends in the X direction. In addition, the position of this portion 160 MH in the Y direction is the same as the position of the above-described portion 160 provided between the memory hole region R of the memory block BLK_A MH1 and the memory hole region R of the memory block BLK_B MH1 in the Y direction. MH

[0105] In addition, for example, the portion 160 A is provided between the above-described portion 160 MH and the portion 160 C-W , or between the above-described portion 160 C-W and the portion 160 C-W , and extends along the direction between the X direction and the Y direction ( Figure 3 the inclined direction) so as to be connected to these portions.

[0106] [Structure of the wiring layer L W2

[0107] For example, as Figure 4 and​Figure 5 As shown, wiring layer L W2 is electrically connected to at least one of the configuration of the plurality of wirings included in the memory cell array MCA and the configuration of the control circuit that controls the memory cell array MCA. For example, the wiring layer L W2 is connected to the conductive layer 110 of the memory cell array layer L via the contact portion 150, or is connected to the transistor Tr, etc. of the transistor layer L via the through contact portion 151 and the wiring of the wiring layer L MCA W1 TR w2 In addition, for example, the plurality of conductive layers 110 are connected to the plurality of transistors Tr of the transistor layer L via the plurality of contact portions 150, the wiring of the wiring layer L w1 TR the wiring of the plurality of through contact portions 151, and the wiring of the wiring layer L

[0108] The wiring layer L W2 The plurality of wirings included may also include a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu). In addition, a part of the plurality of wirings extending in the Y direction included in the wiring layer L functions as a bit line BL( W2 ) Figure 2

[0109] [Manufacturing Method]

[0110] Next, with reference to Figures 11 - 21 , which is a schematic cross-sectional view, a part of the manufacturing method of the semiconductor memory device according to the first embodiment will be described. In addition, Figure 11 , Figure 13 , Figure 16 , Figure 17 , Figure 18 and Figure 20 are Y-Z cross-sectional views corresponding to Figure 4 , Figure 12 , Figure 14 , Figure 15 , Figure 19 and Figure 21 are X-Z cross-sectional views corresponding to Figure 5 .

[0111] [Preparation Step]

[0112] In this manufacturing method, first, the transistor layer L TR and the wiring layer L w1 are formed on the semiconductor substrate 100.

[0113] [First Step: Figure 11 , Figure 12 ​​​​​​

[0114] Reference Figure 11 and Figure 12 Description of the first step

[0115] In the first step, a conductive layer 112 is deposited on the wiring layer L W1 After patterning the position where the through contact portion structure 170 is formed by photolithography, the conductive layer 112 is removed by dry etching such as RIE (Reactive Ion Etching), for example. Then, an insulating layer 101 is deposited in the region where the conductive layer 112 has been removed, and planarization is performed by CMP (Chemical Mechanical Polishing), for example. Then, a plurality of insulating layers 101 and a plurality of insulating layers 110A are alternately formed. The insulating layer 101 and the insulating layer 110A constitute a structure that is alternately stacked in the Z direction. This process is performed by CVD (Chemical Vapor Deposition), for example.

[0116] Next, an insulating layer 140 such as silicon oxide (SiO2) is formed on the stacked multiple insulating layers 101 and the plurality of insulating layers 110A. This process is performed by CVD, for example.

[0117] Next, the portion of the insulating layer 140 corresponding to the connection region R C of the contact portion region R CC ( Figures 3 - 5 ) is removed, and an opening 140a is formed in the insulating layer 140.

[0118] Next, in the portion corresponding to the connection region R C of the contact portion region R CC , a part of the insulating layer 101 and the insulating layer 110A is removed via the opening 140a of the insulating layer 140 to form a substantially stepped structure (recessed portion). This process is performed by forming a resist on the upper surfaces of the alternately formed insulating layer 101 and the insulating layer 110A, and repeatedly removing a part of the insulating layer 101, a part of the insulating layer 110A, and a part of the resist. The processes of removing the insulating layer 101, the insulating layer 110A, and the resist are performed by wet etching or dry etching such as RIE (Reactive Ion Etching), for example.

[0119] [Second step: Figure 13 , Figure 14

[0120] Reference Figure 13 and Figure 14 Description of the second step ​

[0121] In the second step, an insulating layer 140 is filled in a substantially stepped structure (recessed portion) and an opening 140a. This process is performed, for example, by CVD or the like.

[0122] Next, barrier insulating layer grooves 173g and 174g are formed at positions where the barrier insulating layers 173 and 174 are to be formed. The barrier insulating layer grooves 173g and 174g extend in the Z direction and penetrate the insulating layer 101 and the insulating layer 110A. The formation of the barrier insulating layer grooves 173g and 174g is performed, for example, by RIE or the like.

[0123] In addition, portions of the insulating layer 101 and the insulating layer 110A that are laminated in the Z direction and are sandwiched by the barrier insulating layer grooves 173g and 174g extend in the Y direction beyond the positions where the barrier insulating layer grooves 173g and 174g are formed. Therefore, even when the barrier insulating layer grooves 173g and 174g are formed, the portions of the insulating layer 101 and the insulating layer 110A that are sandwiched by the barrier insulating layer grooves 173g and 174g are supported by the portions of the insulating layer 101 and the insulating layer 110A that extend in the Y direction beyond the positions where the barrier insulating layer grooves 173g and 174g are formed, and do not tilt or collapse.

[0124] [Third step: Figure 15

[0125] Refer to Figure 15 The third step will be described.

[0126] In the third step, silicon oxide (SiO2) or the like is filled in the barrier insulating layer grooves 173g and 174g to form the barrier insulating layers 173 and 174. This process is performed, for example, by CVD or the like.

[0127] [Fourth step: Figure 16

[0128] Refer to Figure 16 The fourth step will be described.

[0129] In the fourth step, inter-block structure grooves 160g and 161g are formed at positions where the inter-block structures 160 and 161 are to be formed, and barrier insulating layer grooves 171g and 172g are formed at positions where the barrier insulating layers 171 and 172 are to be formed. The inter-block structure grooves 160g and 161g and the barrier insulating layer grooves 171g and 172g extend in the Z direction and penetrate the insulating layer 101 and the insulating layer 110A. The formation of the inter-block structure grooves 160g and 161g and the barrier insulating layer grooves 171g and 172g is performed, for example, by RIE or the like.

[0130] ​​In addition, in the insulating layers 101 and 110A stacked in the Z direction, the portions sandwiched by the barrier insulating layer grooves 171g and 172g are connected via the barrier insulating layers 173 and 174 to the insulating layers 101 and 110A that extend in the X direction across the positions where the barrier insulating layer grooves 171g and 172g are formed. Therefore, even when the barrier insulating layer grooves 171g and 172g are formed, the portions of the insulating layers 101 and 110A sandwiched by the barrier insulating layer grooves 171g and 172g are supported by the portions of the insulating layers 101 and 110A that extend in the X direction across the positions where the barrier insulating layer grooves 171g and 172g are formed, and do not tilt or collapse.

[0131] [Step 5: Figure 17

[0132] Refer to Figure 17 to describe Step 5.

[0133] In Step 5, silicon oxide (SiO2) or the like is filled in the barrier insulating layer grooves 171g and 172g to form the barrier insulating layers 171 and 172. This process is performed, for example, by CVD or the like.

[0134] Thereby, as described above, the X-direction end edges of the barrier insulating layers 171 and 172 are connected to the Y-direction end edges of the barrier insulating layers 173 and 174, and a four-sided tubular structure made of insulating layers is formed by the barrier insulating layers 171, 172, 173, and 174.

[0135] In addition, since the process of forming the barrier insulating layer grooves 173g and 174g is different from the process of forming the barrier insulating layer grooves 171g and 172g, the lower end positions of the barrier insulating layer grooves 173g and 174g are different from the lower end positions of the barrier insulating layer grooves 171g and 172g in the Z direction. Therefore, in the Z direction, as described above, the lower end positions of the barrier insulating layers 171 and 172 are different from the lower end positions of the barrier insulating layers 173 and 174.

[0136] [Step 6: Figure 18 , Figure 19

[0137] Refer to Figure 18 and Figure 19 to describe Step 6.

[0138] In Step 6, wet etching using a chemical solution such as phosphoric acid is performed via the inter-block structure grooves 160g and 161g to selectively remove the insulating layer 110A.

[0139] ​​Next, a conductive layer 110 is formed on the portion where the insulating layer 110A has been removed. This process is carried out, for example, by forming the conductive layer 110 by CVD or the like via the inter-block structure grooves 160g and 161g. The conductive layer 110 may also include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0140] In addition, the immersion of a chemical solution such as phosphoric acid is blocked by the barrier insulating layers 171, 172, 173, and 174, and the chemical solution such as phosphoric acid does not penetrate into the interior of the quadrilateral cylindrical structure formed by the barrier insulating layers 171, 172, 173, and 174. Therefore, the insulating layer 110A remains without being removed inside the quadrilateral cylindrical structure formed by the barrier insulating layers 171, 172, 173, and 174. As a result, inside the quadrilateral cylindrical structure formed by the barrier insulating layers 171, 172, 173, and 174 in the through contact portion structure 170, a structure in which the insulating layer 101 and the insulating layer 110A are alternately laminated in the Z direction is maintained.

[0141] In addition, in the following description, a process of selectively removing the insulating layer 110A by wet etching or the like and then forming the conductive layer 110 on the portion where the insulating layer 110A has been removed is sometimes referred to as "replace".

[0142] [Step 7: Figure 20 、 Figure 21

[0143] Refer to Figure 20 and Figure 21 to describe Step 7.

[0144] In Step 7, insulating layers 160a and 160a ( Figure 3 、 Figure 4 ) are formed on both side surfaces of the inter-block structure groove 160g, and a conductive layer 160b ( Figure 3 、 Figure 4 ) is formed between the two insulating layers 160a and 160a thus formed to form an inter-block structure 160. Similarly, insulating layers 161a and 161a ( Figure 3 、 Figure 4 ) are formed on both side surfaces of the inter-block structure groove 161g, and a conductive layer 161b ( Figure 3 、 Figure 4 ) is formed between the two insulating layers 161a and 161a thus formed to form an inter-block structure 161.

[0145] In addition, a contact portion 150 is formed in the connection region R C of the contact portion region R CC , and a through contact portion 151 is formed in the through contact portion structure 170.​

[0146] Specifically, at the position in the connection region R C of the contact portion region R CC where the contact portion 150 is formed, for example, a contact hole is formed in the insulating layer 140 by RIE or the like. And, a barrier conductive film such as titanium nitride (TiN) is formed on the inner surface of the contact hole, and then each contact hole is filled with tungsten (W) or the like to form the contact portion 150.

[0147] In addition, at the position in the through-contact portion structure 170 where the through-contact portion 151 is formed, for example, a through-contact hole is formed in the insulating layer 101 and the insulating layer 110A by RIE or the like. And, a barrier conductive film such as titanium nitride (TiN) is formed on the inner surface of the through-contact hole, and then each through-contact hole is filled with tungsten (W) or the like to form the through-contact portion 151.

[0148] [Comparative Example]

[0149] Refer to Figure 22 for the description of the semiconductor memory device related to the comparative example. Figure 22 is corresponding to that of the first embodiment Figure 3 and shows the constitution in the memory cell array layer.

[0150] As Figure 22 shown, in the memory cell array layer L MCA ' of the semiconductor memory device related to the comparative example, a plurality of memory blocks BLK' arranged in the Y direction and an inter-block structure 260 provided therebetween are provided. The inter-block structure 260 extends linearly in the X direction entirely.

[0151] The memory block BLK' includes two memory hole regions R MH1 , R MH2 arranged in the X direction and a contact portion region R C ' and a through-contact portion region R T .

[0152] In the contact portion region R C ', a wiring region R CW ' extending in the X direction and a connection region R CC extending in the X direction are provided. Here, as described above, the inter-block structure 260 related to the comparative example extends linearly in the X direction entirely. Therefore, the width in the Y direction of the wiring region R CW ' related to the comparative example is smaller than the width in the Y direction of the wiring region R CW related to the first embodiment.

[0153] The through-contact portion region R TThere are provided a barrier insulating layer 271 extending in the X and Z directions and a barrier insulating layer 272 extending in the X and Z directions. The two barrier insulating layers 271 and 272 are separated in the Y direction and are disposed opposite to each other.

[0154] Between the barrier insulating layer 271 and the barrier insulating layer 272, an insulating layer 110A (not shown) and an insulating layer 101 (not shown) are alternately stacked in the Z direction. Further, between the barrier insulating layer 271 and the barrier insulating layer 272, there are provided through-contact portions 151 that penetrate the insulating layer 110A (not shown) and the insulating layer 101 (not shown) in the Z direction and are arranged in parallel in the X direction.

[0155] Between the barrier insulating layer 271 and the inter-block structure 260 and between the barrier insulating layer 272 and the inter-block structure 260, a conductive layer 110 (not shown) and an insulating layer 101 (not shown) are alternately stacked in the Z direction.

[0156] The manufacturing method of the semiconductor memory device according to the comparative example is carried out in substantially the same manner as the manufacturing method of the semiconductor memory device according to the first embodiment.

[0157] Here, in the manufacturing process of the semiconductor memory device according to the comparative example, for example, in the replacement process described with reference to Figure 18 and Figure 19 the penetration of a chemical solution such as phosphoric acid into the through-contact portion region R T is prevented by the barrier insulating layers 271 and 272. As a result, as described above, between the barrier insulating layers 271 and 272, the insulating layer 110A (not shown) and the insulating layer 101 (not shown) are maintained in a state of being alternately stacked in the Z direction. In the comparative example, these insulating layers 110A and 101 are used as insulating spacers between the through-contact portions 151.

[0158] Here, in the manufacturing method of the semiconductor memory device according to the comparative example, the insulating layer 110A (not shown) is removed at both ends in the X direction of the barrier insulating layers 271 and 272. Therefore, with respect to the required length in the X direction of the insulating layer 110A (not shown) held between the barrier insulating layers 271 and 272, it is necessary to increase the length in the X direction of the barrier insulating layers 271 and 272. As a result, there is a case where the length in the X direction of the through-contact portion region R T becomes longer, which further hinders the miniaturization of the semiconductor memory device.

[0159] Further, a through-contact portion region R T is provided for each memory block BLK, and therefore, it is necessary to form the through-contact portion region R TAll the components within are arranged between two inter-block structures 260 adjacent in the Y direction, and it is necessary to dispose both of the blocking insulating layers 271 and 272 between two inter-block structures 260 adjacent in the Y direction. Therefore, there is a case where the width in the Y direction of the through contact portion region R T becomes larger, which further hinders the miniaturization of the semiconductor memory device.

[0160] Furthermore, in the comparative example, the inter-block structure 260 extends linearly in the X direction. Therefore, the wiring region R C ' of the contact portion region R CW ' has a narrow width in the Y direction. Therefore, the width in the Y direction of the conductive layer 110 (not shown) included in the wiring region R CW ' becomes narrow, and its resistance becomes high. Therefore, there is a case where the transmission speed of the signal propagating in the conductive layer 110 (not shown) becomes low.

[0161] [Effects of the First Embodiment]

[0162] In the first embodiment, in the replacement process described with reference to Figure 18 and Figure 19 , the immersion of a chemical solution such as phosphoric acid is effectively blocked by the four-sided cylindrical structure formed by the blocking insulating layers 171, 172, 173, and 174. Therefore, the insulating layer 110A disposed inside the above four-sided cylindrical structure is not removed by the chemical solution. As a result, the length of the insulating layer 110A disposed inside the above four-sided cylindrical structure in the X direction can be made the required length. Therefore, in the first embodiment, the length in the X direction of the through contact portion structure 170 including the insulating layer 110A and the blocking insulating layers 171, 172, 173, and 174 can be shortened, and thus the miniaturization of the semiconductor memory device can be achieved.

[0163] In addition, in the first embodiment, each memory block group BLK S , that is, two memory blocks BLK commonly include one through contact portion structure 170. Here, the through contact portion structure 170 according to the first embodiment omits the components corresponding to the inter-block structure 260, the components corresponding to the pair of blocking insulating layers 271 and 272, and the components disposed between the inter-block structure 260 and the blocking insulating layers 271 and 272 compared with the two through contact portion regions R T arranged in the Y direction. That is, the through contact portion structure 170 according to the first embodiment has a smaller width in the Y direction compared with the structure according to the comparative example. Therefore, the miniaturization of the semiconductor memory device can be achieved.

[0164] In addition, the through-contact portion structure 170 according to the first embodiment has a smaller width in the Y direction than the configuration according to the comparative example. Therefore, it is possible to sufficiently increase the width of the wiring region R adjacent to the through-contact portion structure 170 in the Y direction. W Thus, by adjusting the Y-direction position of the above-described portion 160 of the inter-block structure 160 provided between the wiring region R W and the wiring region R CW it is possible to increase the width in the Y direction of both the wiring region R C-W and the wiring region R W and the wiring region R CW in the Y direction. As a result, it is possible to reduce the resistance of the conductive layer 110 included in the wiring region R CW and maintain a high transmission speed of the signal propagating in each conductive layer 110.

[0165] [Other Embodiments]

[0166] Here, other examples of the structure of the barrier insulating layers 171, 172, 173, 174, etc. of the through-contact portion structure 170 and the connection state between the through-contact portion structure 170 and the inter-block structure 161 shown in the first embodiment will be described as the other embodiments.

[0167] In Figure 23 the example shown, the barrier insulating layers 171, 172 have portions 171a, 172a located between the arrangement positions of the barrier insulating layers 173, 174 in the X direction and portions 171b, 172b located more outside in the X direction than the arrangement positions of the barrier insulating layers 173, 174.

[0168] In Figure 24 the example shown, the barrier insulating layers 173, 174 have portions 173a, 174a located between the arrangement positions of the barrier insulating layers 171, 172 in the Y direction and portions 173b, 174b located at positions more outside in the Y direction than the arrangement positions of the barrier insulating layers 171, 172.

[0169] In Figure 25 the example shown, the barrier insulating layers 171, 172 have the above-described portions 171a, 172a, 171b, 172b. In addition, the barrier insulating layers 173, 174 have the above-described portions 173a, 174a, 173b, 174b.

[0170] In Figure 26 the example shown, on one side in the X direction of the plurality of through-contacts 151 included in the through-contact portion structure 170 ( Figure 26On the left side), there are two blocking insulating layers 173 arranged in the X direction. Additionally, on the other side in the X direction of the multiple through-contact portions 151 included in the through-contact portion structure 170 ( Figure 26 On the right side), there are two blocking insulating layers 174 arranged in the X direction. These two blocking insulating layers 173 and the two blocking insulating layers 174 are respectively connected to the blocking insulating layers 171 and 172. Additionally, in Figure 26 In the example of, on one side in the X direction (on the left side in Figure 26 ), the inter-block structure 161 penetrates through one of the blocking insulating layers 173, and on the other side in the X direction (on the right side in Figure 26 ), the inter-block structure 161 penetrates through one of the blocking insulating layers 174.

[0171] In Figure 27 In the example shown, the blocking insulating layer 173 includes a portion 173c provided at one end in the Y direction, a portion 173d provided at the other end in the Y direction, and a portion 173e provided therebetween. Additionally, the width of the portion 173e in the X direction is larger than the width of the portions 173c and 173d in the X direction. Additionally, in Figure 27 In the example shown, the blocking insulating layer 174 includes a portion 174c provided at one end in the Y direction, a portion 174d provided at the other end in the Y direction, and a portion 174e provided therebetween. Additionally, the width of the portion 174e in the X direction is larger than the width of the portions 174c and 174d in the X direction. Additionally, in Figure 27 In the example of, on one side in the X direction (on the left side in Figure 27 ), the end of the inter-block structure 161 is embedded in the above-mentioned portion 173e of the blocking insulating layer 173, and on the other side (on the right side in Figure 27 ), the end of the inter-block structure 161 is embedded in the above-mentioned portion 174e of the blocking insulating layer 174.

[0172] [Other]

[0173] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are included within the scope of the invention described in the claims and its equivalents.

Claims

1. A semiconductor memory device includes: Semiconductor substrate; and a memory cell array which is disposed separately from the semiconductor substrate in a first direction intersecting with the surface of the semiconductor substrate; the semiconductor substrate includes a first region to a third region arranged in sequence in a second direction intersecting with the first direction; the memory cell array includes: a plurality of first conductive layers which extend from the first region through the second region to the third region in the second direction and are alternately stacked with a plurality of first insulating layers in the first direction; a first semiconductor layer which is disposed in the first region, extends in the first direction, and faces the plurality of first conductive layers; a second semiconductor layer which is disposed in the third region, extends in the first direction, and faces the plurality of first conductive layers; a plurality of third insulating layers which are disposed in the second region and are alternately stacked with a plurality of second insulating layers in the first direction; a first contact portion which is disposed in the second region, extends in the first direction, and faces the plurality of third insulating layers, one end in the first direction is closer to the semiconductor substrate than the plurality of first conductive layers, and the other end in the first direction is farther from the semiconductor substrate than the plurality of first conductive layers; a fourth insulating layer which is disposed in the second region, is located between the side surfaces of the plurality of third insulating layers in a third direction intersecting with the first direction and the second direction and the side surfaces of the plurality of first conductive layers in the third direction, and extends in the first direction and the second direction; and a fifth insulating layer which is disposed in the second region, is located between the side surfaces of the plurality of third insulating layers in the second direction and the side surfaces of the plurality of first conductive layers in the second direction, and extends in the first direction and the third direction, an end portion of the fifth insulating layer on the semiconductor substrate side in the first direction is closer to the semiconductor substrate than an end portion of the fourth insulating layer on the semiconductor substrate side in the first direction, or is farther from the semiconductor substrate than the end portion of the fourth insulating layer on the semiconductor substrate side in the first direction.

2. The semiconductor memory device according to claim 1, the semiconductor substrate includes a fourth region to a sixth region arranged in sequence in the second direction, the fourth region is arranged side by side with the first region in the third direction, the fifth region is arranged side by side with the second region in the third direction, the sixth region is arranged side by side with the third region in the third direction, the memory cell array includes: a plurality of second conductive layers which extend from the fourth region through the fifth region to the sixth region in the second direction and are alternately stacked with a plurality of sixth insulating layers in the first direction; a third semiconductor layer which is disposed in the fourth region, extends in the first direction, and faces the plurality of second conductive layers; a fourth semiconductor layer which is disposed in the sixth region, extends in the first direction, and faces the plurality of second conductive layers; and The seventh insulating layer is disposed in the fifth region and extends in the first direction and the second direction. The plurality of second insulating layers, the plurality of third insulating layers, and the fifth insulating layer are disposed throughout the second region and the fifth region. The seventh insulating layer is located between the side surfaces in the third direction of the plurality of third insulating layers and the side surfaces in the third direction of the plurality of second conductive layers. A part of the fifth insulating layer is located between the side surfaces in the second direction of the plurality of third insulating layers and the side surfaces in the second direction of the plurality of second conductive layers.

3. The semiconductor memory device according to claim 1 or 2, The width of the fifth insulating layer in the second direction is different from the width of the fourth insulating layer in the third direction.

4. The semiconductor memory device according to claim 1 or 2, The fifth insulating layer includes: A first portion located on one side in the third direction with respect to the fourth insulating layer; and A second portion located on the other side in the third direction with respect to the fourth insulating layer.

5. The semiconductor memory device according to claim 1 or 2, The fourth insulating layer includes: A third portion located on one side in the second direction with respect to the fifth insulating layer; and A fourth portion located on the other side in the second direction with respect to the fifth insulating layer.

6. The semiconductor memory device according to claim 1 or 2, An eighth insulating layer is provided, which is disposed in the second region, located between the fifth insulating layer and the side surfaces in the second direction of the plurality of first conductive layers, and extends in the first direction and the third direction.

7. The semiconductor memory device according to claim 1 or 2, The semiconductor substrate includes a seventh region provided between the first region and the second region. The memory cell array includes: A plurality of second contact portions disposed in the seventh region, extending in the first direction, and connected to the plurality of first conductive layers; A ninth insulating layer disposed on one side surface in the third direction of the plurality of first conductive layers; and A tenth insulating layer disposed on the other side surface in the third direction of the plurality of first conductive layers. When the distance in the third direction between the ninth insulating layer and the tenth insulating layer in the first region is defined as a first distance, and the distance in the third direction between the ninth insulating layer and the tenth insulating layer in the seventh region is defined as a second distance, the second distance is greater than the first distance.

Images