Array substrate and manufacturing method thereof and display panel

Abstract

The embodiment of the present application provides an array substrate and a preparation method thereof and a display panel. The preparation method of the array substrate includes: sequentially preparing a first active layer, a first inter-gate insulating layer, a first gate electrode and a first capacitor plate on a substrate to form a first preliminary substrate; preparing a first insulating layer on the first preliminary substrate; forming a second active material layer on the first insulating layer; coating a photoresist layer on the second active material layer, and forming a second active layer and a photoresist located on the second active layer; etching the first preliminary substrate with the second active layer and the photoresist to remove a portion of the first insulating layer that is misaligned with the second active layer; stripping the photoresist and continuing to prepare a second inter-gate insulating layer, a second gate electrode, and a second capacitor plate, wherein the second gate electrode and the second active layer are partially overlapped in the thickness direction. The array substrate prepared by the preparation method of the array substrate provided in the present application has the advantages of simple preparation and thin thickness.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to an array substrate and a preparation method thereof, a display panel and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) is an active light-emitting device. Compared with the traditional liquid crystal display (LCD) display method, OLED display technology does not require a backlight and has the characteristic of self-luminescence. OLED uses a thinner organic material film layer and a glass substrate. When an electric current passes through, the organic material will emit light. Therefore, OLED display panels can significantly save electricity, can be made lighter and thinner, can withstand a wider range of temperature changes than LCD display panels, and have a larger viewing angle. OLED display panels are expected to become the next generation of flat-panel display technology after LCD, and are one of the most popular technologies in flat-panel display technology.

[0003] The OLED display panel drives the light-emitting unit to emit light through a transistor (Thin Film Transistor, TFT). The OLED display panel usually includes a switching TFT and a driving TFT. The TFT structure is complex and the film layer stack is relatively thick. Summary of the invention

[0004] The embodiments of the present application provide an array substrate and a method for preparing the same, and a display panel, which are intended to solve the problem of a thick film layer of the display panel.

[0005] An embodiment of the first aspect of the present application provides a method for preparing an array substrate, comprising:

[0006] A first active layer, a first inter-gate insulating layer, a first gate electrode and a first capacitor electrode plate are sequentially prepared on a substrate to form a first preliminary substrate, wherein the first gate electrode and the first capacitor electrode plate are arranged in the same layer, and the first gate electrode and the first active layer are partially overlapped in a thickness direction of the array substrate;

[0007] preparing a first insulating layer on a first preliminary substrate;

[0008] forming a second active material layer on the first insulating layer;

[0009] Coating a photoresist layer on the second active material layer, and exposing and etching to form a second active layer and a photoresist on the second active layer;

[0010] Etching the first preliminary substrate with the second active layer and the photoresist to remove a portion of the first insulating layer that is misaligned with the second active layer;

[0011] The photoresist is stripped off and a second inter-gate insulating layer, a second gate electrode, and a second capacitor plate are continuously prepared to form an array substrate. The second gate electrode and the second active layer are partially overlapped in the thickness direction.

[0012] According to the implementation of the first aspect of the present application, in the step of stripping the photoresist and continuing to prepare the second inter-gate insulating layer, the second gate, and the second capacitor plate to form the array substrate:

[0013] The second gate electrode and the second capacitor electrode plate are prepared on the second inter-gate insulating layer using the same mask plate, and the second gate electrode and the second capacitor electrode plate are arranged in the same layer.

[0014] According to any of the aforementioned embodiments of the first aspect of the present application, in the step of etching the first preliminary substrate with the second active layer and the photoresist to remove a portion of the first insulating layer that is misaligned with the second active layer:

[0015] The first prepared substrate with the second active layer and the photoresist is etched in a dry etching device.

[0016] According to any of the aforementioned embodiments of the first aspect of the present application, in the step of etching the first preliminary substrate with the second active layer and the photoresist to remove a portion of the first insulating layer that is offset from the second active layer: the first preliminary substrate with the second active layer and the photoresist is etched using an etching gas, and the etching gas includes one or more of sulfur hexafluoride, argon, pentafluoroethane, carbon tetrafluoride, and oxygen.

[0017] According to any of the aforementioned embodiments of the first aspect of the present application, the first insulating layer includes a first section and a second section, the first section and the second active layer are overlapped in the thickness direction, and the second section and the second active layer are staggered in the thickness direction.

[0018] In the step of etching the first preliminary substrate with the second active layer and the photoresist to remove a portion of the first insulating layer that is offset from the second active layer: etching the second sub-portion so that the difference in thickness between the first sub-portion and the second sub-portion is

[0019] According to any of the aforementioned embodiments of the first aspect of the present application, the first insulating layer includes a first section and a second section, the first section and the second active layer are overlapped in the thickness direction, and the second section and the second active layer are staggered in the thickness direction.

[0020] In the step of etching the first preliminary substrate with the second active layer and the photoresist to remove a portion of the first insulating layer that is offset from the second active layer: etching the second sub-portion so that the thickness of the second sub-portion is less than or equal to

[0021] According to any of the aforementioned embodiments of the first aspect of the present application, after the step of etching the first preliminary substrate with the second active layer and the photoresist to remove a portion of the first insulating layer that is misaligned with the second active layer, the method further includes:

[0022] The second portion is patterned to form a first via hole, and at least a portion of the first capacitor plate is exposed through the first via hole.

[0023] According to any of the aforementioned implementations of the first aspect of the present application, the first capacitor plate is completely exposed by the first via hole.

[0024] According to any of the aforementioned embodiments of the first aspect of the present application, the first active layer includes a first source region and a first drain region, the second active layer includes a second source region and a second drain region, the first capacitor plate includes a first connection region, and the second capacitor plate includes a second connection region, and the method further includes:

[0025] forming a second insulating layer on the second grid electrode and the second capacitor plate;

[0026] The second insulating layer, the second inter-gate insulating layer, the first insulating layer and the first inter-gate insulating layer are subjected to a hole-opening process to form a plurality of connection holes, wherein the plurality of connection holes include a first connection hole, a second connection hole, a third connection hole and a fourth connection hole, wherein there are two first connection holes, and the first source region and the first drain region are exposed through the first connection holes respectively, the first connection region is exposed through the second connection hole, and the second connection region is exposed through the third connection hole, and there are two fourth connection holes, and the second source region and the second drain region are exposed through the fourth connection holes respectively;

[0027] A third conductive layer is prepared on the second insulating layer to form a first transistor, a first capacitor and a second transistor. The third conductive layer includes a first source, a first drain, a first capacitor line, a second capacitor line, a second source and a second drain. The first source is interconnected with the first source region via a first connection hole, the first drain is interconnected with the first drain region via a first connection hole, the first capacitor line is interconnected with the first capacitor plate via the second connection hole, the second capacitor line is interconnected with the second capacitor plate via the third connection hole, the second source is interconnected with the second source region via a fourth connection hole, and the second drain is connected with the second drain region via a fourth connection hole.

[0028] According to any of the aforementioned embodiments of the first aspect of the present application, the third conductive layer further includes a first signal line, and the first signal line is interconnected with the second gate via a connection hole.

[0029] According to any of the aforementioned embodiments of the first aspect of the present application, the difference between the hole depth of at least one of the first connecting hole, the second connecting hole and the third connecting hole and the hole depth of the fourth connecting hole is

[0030] According to any of the aforementioned embodiments of the first aspect of the present application, the hole depth difference between the first connection hole and the fourth connection hole is

[0031] An embodiment of a second aspect of the present application provides an array substrate for a display panel, wherein the layer structure of the array substrate includes a substrate, a first conductive layer, a second conductive layer, and a third conductive layer sequentially arranged on the substrate, and the array substrate further includes:

[0032] A first transistor comprising a first active layer, a first gate, a first source and a first drain;

[0033] A second transistor comprising a second active layer, a second gate, a second source and a second drain;

[0034] A first capacitor, comprising a first capacitor plate and a second capacitor plate;

[0035] Among them, the first active layer is located between the first conductive layer and the substrate, the first gate and the first capacitor plate are located in the first conductive layer, the second active layer is located between the first conductive layer and the second conductive layer, the second gate and the second capacitor plate are located in the second conductive layer, and the first source, the first drain, the second source and the second drain are located in the third conductive layer.

[0036] According to an implementation of the second aspect of the present application, a first insulating layer is provided between the first conductive layer and the second active layer, the first insulating layer includes a first sub-portion and a second sub-portion, the first sub-portion and the second active layer are overlapped in the thickness direction of the array substrate, and the second sub-portion and the second active layer are staggered in the thickness direction.

[0037] The thickness difference between the first and second sections is and / or, the thickness of the second section is less than or equal to

[0038] According to any of the aforementioned embodiments of the second aspect of the present application, the difference between the distance between the first capacitor plate and the second capacitor plate and the distance between the second gate and the second active layer is

[0039] According to any of the aforementioned embodiments of the second aspect of the present application, the difference between the spacing between the third conductive layer and the first active layer and the spacing between the third conductive layer and the second active layer is

[0040] An embodiment of the third aspect of the present application further provides a display panel, comprising an array substrate according to any one of the above-mentioned embodiments of the second aspect; a light-emitting structure, which is arranged on the array substrate, and the array substrate is used to drive the light-emitting structure to emit light.

[0041] In the preparation method of the array substrate provided in the present application, when a photoresist is coated on the second active material layer and exposed and etched to form a second active layer, before the photoresist on the second active layer is stripped, the first preliminary substrate is etched to remove part of the first insulating layer, and then the optical glue is stripped and the second inter-gate insulating layer, the second gate, and the second capacitor plate are prepared to form the array substrate. On the one hand, the removal of part of the first insulating layer can reduce the thickness of the array substrate; on the other hand, etching the first insulating layer using the photoresist on the second active layer as a mask can simplify the preparation method of the array substrate, so that while the array substrate is thinned, the complexity of the preparation of the array substrate will not be increased. Therefore, the array substrate prepared by the preparation method of the array substrate provided in the present application has the advantages of simple preparation and thin thickness. When the array substrate is used for a display panel, the problem of a thick film layer of the display panel can be solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features.

[0043] Figure 1 It is a structural schematic diagram of an array substrate prepared by a method for preparing an array substrate provided in an embodiment of the first aspect of the present application;

[0044] Figure 2 It is a schematic flow chart of a method for preparing an array substrate provided in an embodiment of the first aspect of the present application;

[0045] Figure 3 It is a process schematic diagram of a method for preparing an array substrate provided in an embodiment of the first aspect of the present application;

[0046] Figures 4 to 16 is a preparation process diagram of a method for preparing an array substrate provided in an embodiment of the first aspect of the present application;

[0047] Fig.17 is a structural schematic diagram of an array substrate provided by an embodiment of the second aspect of the present application;

[0048] Fig.18 It is a structural schematic diagram of a display panel provided in an embodiment of the third aspect of the present application.

[0049] Description of reference numerals:

[0050] 10. Array substrate;

[0051] 01, substrate; 02, first inter-gate insulating layer; 03, first conductive layer; 031, shielding portion; 04, first insulating layer; 04a, first sub-portion; 04b, second sub-portion; 041, first sub-layer; 042, second sub-layer; 05, second inter-gate insulating layer; 06, second conductive layer; 07, second insulating layer; 08, third conductive layer; 081, first signal line; 09, first planarization layer; 010, fourth conductive layer; 011, second planarization layer;

[0052] 100, a first transistor; 110, a first active layer; 111, a first source region; 112, a first channel region; 113, a first drain region; 120, a first gate; 130, a first source electrode; 140, a first drain electrode;

[0053] 200, first capacitor; 210, first capacitor plate; 220, second capacitor plate;

[0054] 300, second transistor; 310, second active layer; 311, second source region; 312, second drain region; 313, second channel region; 320, second gate; 330, second source electrode; 340, second drain electrode;

[0055] 410, first connection hole; 420, second connection hole; 430, third connection hole; 440, fourth connection hole;

[0056] 510, a first capacitor line; 520, a second capacitor line;

[0057] 600, bridge connection;

[0058] 700, pixel electrode;

[0059] 20. Light-emitting structure; 21. Pixel definition layer; 22. Light-emitting unit; 23. Support column; 24. Common electrode. DETAILED DESCRIPTION

[0060] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating examples of the present application. In the accompanying drawings and the following description, at least some of the known structures and technologies are not shown to avoid unnecessary ambiguity in the present application; and, for clarity, the size of some structures may be exaggerated. In addition, the features, structures or characteristics described below may be combined in one or more embodiments in any suitable manner.

[0061] In the description of the present application, it should be noted that, unless otherwise specified, "multiple" means more than two; the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0062] The directional words appearing in the following description are all directions shown in the figures, and do not limit the specific structure of the embodiments of the present application. In the description of the present application, it should also be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0063] At present, low temperature polysilicon (LTPS) transistors and indium gallium zinc oxide (IGZO) transistors have been used in the display market to a certain extent. LTPS transistors and IGZO transistors are used in array substrates of display devices as driving transistors. LTPS transistors and IGZO transistors are collectively referred to as LTPO technology. The transistor technology of the array substrate in LTPO technology combines the two modules of LTPS and IGZO, resulting in a complex transistor structure, thicker film stacking, and a large number of mask plates used in the preparation process, an average of 15-16 mask plates. In addition, due to the obvious difference in film thickness between the via-hole etching process of the LTPS transistor part and the via-hole etching process of the IGZO transistor, on the one hand, the increase in the number of mask plates leads to an increase in preparation costs, and on the other hand, the deep hole etching process has high requirements, which is prone to problems such as product defects and yield loss.

[0064] In order to solve the above technical problems, this application is proposed. In order to better understand this application, Figures 1 to 18 The manufacturing method of the array substrate 10 , the array substrate 10 and the display panel according to the embodiment of the present application are described in detail.

[0065] See also Figure 1 and Figure 2 , Figure 1 The array substrate 10 is formed by the method for preparing the array substrate 10 provided by the embodiment of the first aspect of the present invention. Figure 2A schematic flow chart of a method for preparing an array substrate 10 provided in an embodiment of the first aspect of the present invention.

[0066] like Figure 1 As shown, the array substrate 10 includes a substrate 01, a layer structure of the array substrate 10 disposed on the substrate 01 includes the substrate 01, a first conductive layer 03, a second conductive layer 06 and a third conductive layer 08 sequentially disposed on the substrate 01, and the array substrate 10 also includes: a first transistor 100, including a first active layer 110, a first gate 120, a first source 130 and a first drain 140; a second transistor 300, including a second active layer 310, a second gate 320, a second source 330 and a second drain 340; a first capacitor 200, including a first capacitor plate 210 and a second capacitor plate 220; wherein, the first active layer 110 is located between the first conductive layer 03 and the substrate 01, the first gate 120 and the first capacitor plate 210 are located in the first conductive layer 03, the second active layer 310 is located between the first conductive layer 03 and the second conductive layer 06, the second gate 320 and the second capacitor plate 220 are located in the second conductive layer 06, and the first source 130, the first drain 140, the second source 330 and the second drain 340 are located in the third conductive layer 08.

[0067] Optionally, a first intergate insulating layer 02 is provided between the first active layer 110 and the first conductive layer 03 , a first insulating layer 04 is provided between the first conductive layer 03 and the second active layer 310 , a second intergate insulating layer 05 is provided between the second active layer 310 and the second conductive layer 06 , and a second insulating layer 07 is provided between the second conductive layer 06 and the third conductive layer 08 .

[0068] Optionally, the first transistor 100 is, for example, an LTPS transistor, and the second transistor 300 is, for example, an IGZO transistor.

[0069] like Figure 1 and Figure 2 As shown, the method for preparing the array substrate 10 provided in the embodiment of the present application includes:

[0070] Step S01: A first active layer 110, a first inter-gate insulating layer 02, a first gate electrode 120 and a first capacitor plate 210 are sequentially prepared on a substrate 01 to form a first preliminary substrate. The first gate electrode 120 and the first capacitor plate 210 are arranged in the same layer, and the first gate electrode 120 and the first active layer 110 are partially overlapped in the thickness direction of the display panel.

[0071] Step S02: preparing a first insulating layer 04 on a first preliminary substrate.

[0072] Step S03 : forming a second active material layer on the first insulating layer 04 .

[0073] Step S04 : coating a photoresist layer on the second active material layer, and performing exposure and etching to form a second active layer 310 and a photoresist on the second active layer 310 .

[0074] Step S05 : etching the first preliminary substrate with the second active layer 310 and the photoresist to remove a portion of the first insulating layer 04 that is offset from the second active layer 310 .

[0075] Step S06: stripping the photoresist and continuing to prepare the second inter-gate insulating layer 05, the second gate 320, and the second capacitor plate 220 to form the array substrate 10, wherein the second gate 320 and the second active layer 310 are partially overlapped in the thickness direction.

[0076] In the preparation method of the array substrate 10 provided in the present application, after the first preliminary substrate and the first insulating layer 04 are prepared and formed through steps S01 and S02, a second active material layer is prepared on the first insulating layer 04 through step S03. After photoresist is coated on the second active material layer and exposed and etched to form the second active layer 310 in step S04, the first preliminary substrate is etched through step S05 before the photoresist on the second active layer 310 is stripped in step S06. In step S05, part of the first insulating layer 04 can be removed, and then the optical glue is stripped and the second inter-gate insulating layer 05, the second gate 320, and the second capacitor plate 220 are prepared to form the array substrate 10. On the one hand, in step S05, a portion of the first insulating layer 04 is removed, which can reduce the thickness of the array substrate 10; on the other hand, in step S05, the first insulating layer 04 is etched using the photoresist on the second active layer 310 as a mask, which can simplify the method for preparing the array substrate 10, so that while the array substrate 10 is thinned, the complexity of preparing the array substrate 10 is not increased. Therefore, the array substrate 10 prepared by the method for preparing the array substrate 10 provided by the present application has the advantages of simple preparation and thin thickness. When the array substrate 10 is used for a display panel, the problem of a thick film layer of the display panel can be solved.

[0077] In step S01, the first active layer 110, the first gate electrode 120 and the first capacitor plate 210 may be formed by film formation, coating, exposure and etching processes, and the first insulating layer 04 may be formed by coating. For example, when preparing the first active layer 110, a first active material film layer may be formed on the substrate 01, and then a first photoresist layer may be formed by coating on the first active material film layer, and the first photoresist layer may be exposed to form a patterned first photoresist layer using a mask, and then a portion of the first active material film layer may be etched away to form the first active layer 110 at a designated position. Finally, the first photoresist layer is stripped off, and the first insulating layer 04 is continuously prepared on the first active layer 110, and the first gate electrode 120 and the first capacitor plate 210 are prepared on the first insulating layer 04.

[0078] Optionally, since the first capacitor plate 210 and the first gate 120 are arranged in the same layer, the first capacitor plate 210 and the first gate 120 can be simultaneously prepared using the same mask plate, thereby simplifying the preparation method of the array substrate 10 and improving the preparation efficiency of the array substrate 10.

[0079] Optionally, in the step of preparing the first gate 120 and the first capacitor plate 210, a shielding portion 031 may be prepared, and the orthographic projection of the shielding portion 031 on the substrate 01 and the orthographic projection of the second active layer 310 on the substrate 01 are at least partially overlapped. The shielding portion 031 is capable of shielding light emitted from the bottom toward the second active layer 310.

[0080] After the second inter-gate insulating layer 05 is prepared in step S06, the etched first insulating layer 04 and the second inter-gate insulating layer 05 are still left on the first capacitor plate 210, and the second inter-gate insulating layer 05 is left on the second active layer 310. Since part of the first insulating layer 04 is etched away in step S05, the difference between the sum of the thickness of the first insulating layer 04 and the second inter-gate insulating layer 05 on the first capacitor plate 210 and the thickness of the second inter-gate insulating layer 05 itself is small, so the second gate 320 and the second capacitor plate 220 can be prepared in the same step.

[0081] In some optional embodiments, in step S06, the second gate 320 and the second capacitor plate 220 are prepared on the second inter-gate insulating layer 05 using the same mask plate, and the second gate 320 and the second capacitor plate 220 are arranged on the same layer. This can further simplify the preparation method of the array substrate 10 and improve the preparation efficiency of the array substrate 10.

[0082] In step S05, there are multiple methods for etching the first prepared substrate with the second active layer 310 and the photoresist. Optionally, in step S05: the first prepared substrate with the second active layer 310 and the photoresist is etched in a dry etching device. The dry etching process is mature, and using a dry etching device to etch the first insulating layer 04 can improve the preparation efficiency of the array substrate 10.

[0083] Optionally, in a dry etching device, an etching gas may be selected to etch the first prepared substrate with the second active layer 310 and the photoresist. The etching time and parameters may be adjusted according to the thickness of the first insulating layer 04 to be etched. The etching gas may include one or more of sulfur hexafluoride, argon, pentafluoroethane, carbon tetrafluoride, and oxygen.

[0084] Optionally, the first insulating layer 04 includes a first sublayer 041 and a second sublayer 042 located on the side of the first sublayer 041 away from the substrate 01. The material of the first sublayer 041 is, for example, silicon nitride, and the material of the second sublayer 042 is, for example, silicon nitride or silicon oxide. Then in step S02, the first sublayer 041 and the second sublayer 042 are sequentially prepared on the substrate 01. For example, a high-temperature process can be selected to prepare the first sublayer 041, and a low-temperature process can be selected to prepare the second sublayer 042 after the first sublayer 041 is prepared. When the second active material layer is subsequently prepared on the second sublayer 042, since the second sublayer 042 uses a low-temperature process, the influence of high temperature on the preparation of the second active material layer can be improved.

[0085] The thickness of the first sub-layer 041 is, for example, The thickness of the second sub-layer 042 is, for example, Then the thickness of the first insulating layer 04 before etching in step S05 is That is, the thickness of the unetched first insulating layer 04 between the second inter-gate insulating layer 05 and the second active layer 310 is

[0086] In some optional embodiments, the first insulating layer 04 includes a first sub-portion 04a and a second sub-portion 04b, the first sub-portion 04a and the second active layer 310 are overlapped in the thickness direction, and the second sub-portion 04b and the second active layer 310 are staggered in the thickness direction. That is, the second sub-portion 04b is located between the first inter-gate insulating layer 02 and the second active layer 310, and the thickness of the second sub-portion 04b can be

[0087] In step S05: the second sub-portion 04b is etched so that the thickness difference between the first sub-portion 04a and the second sub-portion 04b is

[0088] In these optional embodiments, the thickness difference between the first subsection 04a and the second subsection 04b is That is, the thickness of the second section 04b etched away is The thickness of the second section 04b is When the thickness of the second section 04b is within the above range, it can avoid damage to the first gate 120 or the first capacitor plate 210 due to excessive etching, and can also avoid the second section 04b being too thick due to insufficient etching, resulting in the second capacitor plate 220 and the second gate 320 being too far apart in the thickness direction and unable to be prepared in the same step.

[0089] In some optional embodiments, in step S05, the second sub-portion 04b may be etched so that the thickness of the second sub-portion 04b is less than or equal to As described above, when the thickness of the second section 04b is within the above range, the etching process will not damage the first gate 120 and the first capacitor plate 210, and the second capacitor plate 220 and the second gate 320 can be manufactured in the same step.

[0090] Optionally, when the first insulating layer 04 includes a first sublayer 041 and a second sublayer 042, and the thickness of the second sub-portion 04b is , it can be determined that the second division 04b includes the first sublayer 041 , and the first division 04a includes the first sublayer 041 and the second sublayer 042 .

[0091] See also Figure 3 , Figure 3 It is a schematic diagram of a process of preparing an array substrate 10 provided in an embodiment of the first aspect of the present invention.

[0092] Optionally, step S05 further includes: patterning the second subsection 04b to form a first via hole, and at least a portion of the first capacitor plate 210 is exposed through the first via hole. For example, the first capacitor plate 210 is completely exposed through the first via hole. The spacing between the second capacitor plate 220 and the first capacitor plate 210 can be further reduced, so that the second inter-gate insulating layer 05 is used as a capacitor dielectric layer between the first capacitor plate 210 and the second capacitor plate 220, thereby improving the performance of the first capacitor plate 210.

[0093] In some optional embodiments, the first active layer 110 includes a first source region 111 and a first drain region 113, the second active layer 310 includes a second source region 311 and a second drain region 312, the first capacitor plate 210 includes a first connection region, the second capacitor plate 220 includes a second connection region, and the method of the array substrate 10 further includes:

[0094] A second insulating layer 07 is formed on the second gate electrode 320 and the second capacitor plate 220;

[0095] The second insulating layer 07, the second inter-gate insulating layer 05, the first insulating layer 04 and the first inter-gate insulating layer 02 are subjected to a hole-opening process to form a plurality of connection holes, the plurality of connection holes include a first connection hole 410, a second connection hole 420, a third connection hole 430 and a fourth connection hole 440, there are two first connection holes 410, the first source region 111 and the first drain region 113 are exposed by the first connection holes 410, the first connection region is exposed by the second connection hole 420, the second connection region is exposed by the third connection hole 430, there are two fourth connection holes 440, the second source region 311 and the second drain region 312 are exposed by the fourth connection holes 440, respectively;

[0096] A third conductive layer 08 is prepared on the second insulating layer 07 to form a first transistor 100, a first capacitor 200 and a second transistor 300. The first source 130 is interconnected with the first source region 111 via a first connection hole 410, the first drain 140 is interconnected with the first drain region 113 via a first connection hole 410, the first capacitor line 510 is interconnected with the first capacitor plate 210 via a second connection hole 420, the second capacitor line 520 is interconnected with the second capacitor plate 220 via a third connection hole 430, the second source 330 is interconnected with the second source region 311 via a fourth connection hole 440, and the second drain 340 is connected to the second drain region 312 via a fourth connection hole 440.

[0097] The first capacitor line 510 is, for example, a power signal line (Vdd line), and the second capacitor line 520 is, for example, a data signal line (data line); or the first capacitor line 510 is a data signal line (data line), and the second capacitor line 520 is a power signal line (Vdd line).

[0098] Optionally, the third conductive layer 08 further includes a first signal line 081, and the first signal line 081 is connected to the second gate 320 via a connection hole. The first signal line 081 is, for example, a scan signal line.

[0099] In some optional embodiments, the difference between the hole depth of at least one of the first connection hole 410, the second connection hole 420 and the third connection hole 430 and the hole depth of the fourth connection hole 440 is The hole depth refers to the extension dimension of the connection hole in the thickness direction of the array substrate 10 .

[0100] In these optional embodiments, when the difference between the hole depth of at least one of the first connection hole 410, the second connection hole 420 and the third connection hole 430 and the hole depth of the fourth connection hole 440 is When the hole depth difference is small, the first connection hole 410, the second connection hole 420, the third connection hole 430 and the fourth connection hole 440 can be prepared in the same process step, which can simplify the preparation process of the array substrate 10 and improve the preparation efficiency of the array substrate 10.

[0101] Optionally, the hole depth difference between the first connection hole 410 and the fourth connection hole 440 is The hole depth difference between the other connection holes and the fourth connection hole 440 is smaller than the hole depth difference between the first connection hole 410 and the fourth connection hole 440, which can ensure that the hole depth difference of the multiple connection holes is small, making it easier to prepare multiple connection holes at one time.

[0102] Below Figure 1 As an example, the array substrate 10 shown in FIG. Figures 4 to 16, an example is given to illustrate a method for preparing an array substrate 10 provided in an embodiment of the first aspect of the present invention. The method for preparing the array substrate 10 includes:

[0103] Step 1: If Figure 4 As shown, a first active layer 110 is prepared on a substrate 01 .

[0104] As described above, the first active layer 110 may be prepared by a method of film formation, coating, exposure and etching, and finally stripping the first photoresist layer.

[0105] Step 2: If Figure 5 As shown, a first inter-gate insulating layer 02 is prepared on the first active layer 110 .

[0106] Step 3: If Figure 6 As shown, a first gate electrode 120 and a first capacitor plate 210 are prepared on the first inter-gate insulating layer 02 .

[0107] The first gate 120 and the first capacitor plate 210 can be prepared by film formation, coating, exposure and etching, and finally stripping the photoresist layer. In the process of exposing the photoresist layer using a mask, the same mask can be used to expose the photoresist, and finally the photoresist is etched and stripped to form the first gate 120 and the first capacitor plate 210. The first gate 120 and the first capacitor plate 210 are prepared and formed by the same process steps, which can simplify the preparation method of the array substrate 10.

[0108] In some embodiments, a shielding portion 031 may also be prepared in step three.

[0109] Step 4: If Figure 7 As shown, a first insulating layer 04 is prepared on the first gate 120 and the first capacitor plate 210 .

[0110] As described above, the first insulating layer 04 may include a first sub-layer 041 and a second sub-layer 042 , and the first sub-layer 041 and the second sub-layer 042 may be prepared in two different process steps.

[0111] Step 5: If Figure 8 As shown, a second active material layer is formed on the first insulating layer 04 .

[0112] Step 6: If Fig. 9 As shown, a photoresist layer is coated on the first active material layer, and then exposed and etched to form a second active layer 310 and a photoresist on the second active layer 310 .

[0113] Step 7: If Fig.10As shown, the first preliminary substrate with the second active layer 310 and the photoresist is etched to remove a portion of the first insulating layer 04 that is offset from the second active layer 310 .

[0114] As described above, the first insulating layer 04 includes a first sub-portion 04a and a second sub-portion 04b. Part of the second sub-portion 04b is removed so that only part of the first sub-layer 041 remains in the second sub-portion 04b. The first sub-portion 04a includes a first sub-layer 041 and a second sub-layer 042.

[0115] Step 8: If Fig.11 As shown, the photoresist is stripped.

[0116] Step 9: If Fig.12 As shown, a second inter-gate insulating layer 05 is prepared on the second active layer 310 .

[0117] A portion of the second inter-gate insulating layer 05 is reused as a capacitor dielectric layer between the first capacitor plate 210 and the second capacitor plate 220 .

[0118] Step 10: Fig.13 As shown, a second gate electrode 320 and a second capacitor plate 220 are prepared on the second inter-gate insulating layer 05 .

[0119] Since the first insulating layer 04 is subjected to etching and thinning treatment, the height difference between the second capacitor plate 220 and the second grid 320 is small. Therefore, the method of film forming, coating, exposure and etching, and finally stripping the photoresist layer can be selected to prepare the second grid 320 and the second capacitor plate 220 in the same process step. In the process of exposing the photoresist layer using a mask plate, the same mask plate can be selected to expose the photoresist, and finally the second grid 320 and the second capacitor plate 220 are formed after etching and stripping the photoresist. The second grid 320 and the second capacitor plate 220 are prepared and formed by the same process step, which can simplify the preparation method of the array substrate 10.

[0120] Step 11: Fig.14 As shown, a second insulating layer 07 is prepared on the second gate electrode 320 and the second capacitor plate 220 substrate.

[0121] Step 12: Fig.15 As shown, the second insulating layer 07 , the second inter-gate insulating layer 05 , the first insulating layer 04 and the first inter-gate insulating layer 02 are subjected to opening processing to form a plurality of connection holes, including a first connection hole 410 , a second connection hole 420 , a third connection hole 430 and a fourth connection hole 440 .

[0122] Step 13: Fig.16As shown, a third conductive layer 08 is prepared on the second insulating layer 07 , and the third conductive layer 08 includes a first source 130 , a first drain 140 , a first capacitor line 510 , a second capacitor line 520 , a second source 330 and a second drain 340 .

[0123] As shown above, the first source 130 is interconnected with the first source region 111 via a first connection hole 410, the first drain 140 is interconnected with the first drain region 113 via a first connection hole 410, the first capacitor line 510 is interconnected with the first capacitor plate 210 via a second connection hole 420, the second capacitor line 520 is interconnected with the second capacitor plate 220 via a third connection hole 430, the second source 330 is interconnected with the second source region 311 via a fourth connection hole 440, and the second drain 340 is connected to the second drain region 312 via a fourth connection hole 440.

[0124] Optionally, in step thirteen, a first signal line 081 is further formed on the third conductive layer 08 .

[0125] Optionally, in some optional embodiments, after step thirteen, a first planarization layer 09 , a fourth conductive layer 010 , a second planarization layer 011 and a pixel electrode 700 are further prepared on the third conductive layer 08 to form an array substrate 10 .

[0126] See also Fig.17 , FIG. 1 is a schematic diagram of the structure of an array substrate 10 provided in an embodiment of the second aspect of the present invention. The array substrate 10 can be prepared by using any of the preparation methods of the array substrate 10 in the first aspect of the present invention.

[0127] like Fig.17 As shown, the layer structure of the array substrate 10 provided by the present invention includes a substrate 01, a first conductive layer 03, a second conductive layer 06 and a third conductive layer 08 sequentially arranged on the substrate 01, and the array substrate 10 also includes: a first transistor 100, including a first active layer 110, a first gate 120, a first source 130 and a first drain 140; a second transistor 300, including a second active layer 310, a second gate 320, a second source 330 and a second drain 340; a first capacitor plate 210, including The first capacitor plate 210 and the second capacitor plate 220; wherein the first active layer 110 is located between the first conductive layer 03 and the substrate 01, the first gate 120 and the first capacitor plate 210 are located in the first conductive layer 03, the second active layer 310 is located between the first conductive layer 03 and the second conductive layer 06, the second gate 320 and the second capacitor plate 220 are located in the second conductive layer 06, and the first source 130, the first drain 140, the second source 330 and the second drain 340 are located in the third conductive layer 08.

[0128] In the array substrate 10 provided in the embodiment of the present invention, the first capacitor plate 210 and the first gate 120 are located in the same first conductive layer 03, so the first capacitor plate 210 and the first gate 120 can be prepared and formed by the same process step, which can simplify the preparation process of the array substrate 10 and improve the preparation efficiency of the array substrate 10. Similarly, the second capacitor plate 220 and the second gate 320 are located in the same second conductive layer 06, so the second capacitor plate 220 and the second gate 320 can be prepared and formed by the same process step, which can simplify the preparation process of the array substrate 10 and improve the preparation efficiency of the array substrate 10. In addition, the first capacitor plate 210 and the first gate 120 are located in the same first conductive layer 03, and the second capacitor plate 220 and the second gate 320 are located in the same second conductive layer 06, which can also reduce the thickness of the array substrate 10.

[0129] Optionally, as described above, the first active layer 110 includes a first source region 111, a first drain region 113, and a first channel region 112, and the second active layer 310 includes a second source region 311, a second drain region 312, and a second channel region 313. The first source electrode 130 is interconnected with the first source region 111, the first drain electrode 140 is interconnected with the first drain region 113, and the first gate electrode 120 and the first channel region 112 are partially overlapped in the thickness direction of the array substrate 10. The second source electrode 330 is interconnected with the second source region 311, the second drain electrode 340 is interconnected with the first drain region 113, and the first gate electrode 120 and the first channel region 112 are partially overlapped in the thickness direction of the array substrate 10.

[0130] In some optional embodiments, a first insulating layer 04 is provided between the first conductive layer 03 and the second active layer 310, the first insulating layer 04 includes a first sub-portion 04a and a second sub-portion 04b, the first sub-portion 04a and the second active layer 310 are overlapped in the thickness direction, and the second sub-portion 04b and the second active layer 310 are staggered in the thickness direction, wherein the thickness difference between the first sub-portion 04a and the second sub-portion 04b is and / or, the thickness of the second section 04b is less than or equal to When the thickness of the second section 04b is within the above range, it can avoid damage to the first gate 120 or the first capacitor plate 210 due to excessive etching, and can also avoid the second section 04b being too thick due to insufficient etching, resulting in the second capacitor plate 220 and the second gate 320 being too far apart in the thickness direction and unable to be prepared in the same step.

[0131] In some optional embodiments, the difference between the distance between the first capacitor plate 210 and the second capacitor plate 220 and the distance between the second gate 320 and the second active layer 310 is

[0132] In these optional embodiments, the second gate inter-insulating layer 05 is between the second gate 320 and the second active layer 310, and the layer structure between the first capacitor plate 210 and the second capacitor plate 220 is the first insulating layer 04 and the second gate inter-insulating layer 05. When the difference between the distance between the first capacitor plate 210 and the second capacitor plate 220 and the distance between the second gate 320 and the second active layer 310 is within the above range, the thickness of the first insulating layer 04 between the first capacitor plate 210 and the second capacitor plate 220 is The first insulating layer 04 has a relatively small thickness, which can effectively reduce the thickness of the array substrate 10 .

[0133] In some optional embodiments, the difference between the distance between the third conductive layer 08 and the first active layer 110 and the distance between the third conductive layer 08 and the second active layer 310 is

[0134] In these optional embodiments, the first inter-gate insulating layer 02, the first insulating layer 04, the second inter-gate insulating layer 05 and the second insulating layer need to be punched to form connection holes so that the first source 130 and the first source region 111, the first drain 140 and the first drain region 113, the first capacitor line 510 and the first capacitor plate 210, and the second capacitor line 520 and the second capacitor plate 220 are connected to each other. The second source 330 and the second source region 311, the second drain region 312 and the second drain 340 are connected to each other. When the difference between the spacing between the third conductive layer 08 and the first active layer 110 and the spacing between the third conductive layer 08 and the second active layer 310 is within the above range, the hole depth difference of each connection hole is within the above range, so that multiple connection holes can be prepared and formed in the same process step, which can simplify the preparation process of the array substrate 10 and improve the preparation efficiency of the array substrate 10.

[0135] Optionally, the array substrate 10 further includes a first planarization layer 09 located on the third conductive layer 08, a fourth conductive layer 010 located on the first planarization layer 09, a second planarization layer 011 located on the fourth conductive layer 010, and a pixel electrode 700 disposed on the first planarization layer 010. A bridge line 600 is disposed in the fourth conductive layer 010, for connecting the third conductive layer 08 and the pixel electrode 700. The array substrate 10 is used to drive the display panel to emit light through the pixel electrode 700.

[0136] See also Fig.18 , Fig.18 It is a structural schematic diagram of a display panel provided in an embodiment of the third aspect of the present application.

[0137] like Fig.18As shown, the display panel provided by the embodiment of the third aspect of the present invention includes: an array substrate 10 of any of the above-mentioned second aspect embodiments; a light-emitting structure 20, which is arranged on the array substrate 10, and the array substrate 10 is used to drive the light-emitting structure 20 to emit light.

[0138] In the display panel provided by the embodiment of the present invention, since the array substrate 10 uses the above-mentioned array substrate 10 , the display panel has the beneficial effects of small thickness and simple manufacturing method.

[0139] Optionally, the light emitting structure 20 includes a pixel definition layer 21, a light emitting unit 22 and a common electrode 24, the pixel definition layer 21 has a pixel opening, the light emitting unit 22 is located at the pixel opening, the common electrode 24 is located at a side of the light emitting unit 22 away from the array substrate 10, and the common electrode 24 and the pixel electrode 700 work together to make the light emitting unit 22 emit light. Optionally, a support column 23 is also provided on the pixel definition layer 21, and the support column 23 is used to support the cover plate and other structures of the display panel.

[0140] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced with equivalents without departing from the scope of the present application. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there are no structural conflicts. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A method for preparing an array substrate, It is characterized in that include: A first active layer, a first inter-gate insulating layer, a first gate and a first capacitor plate are sequentially prepared on a substrate to form a first preliminary substrate, wherein the first gate and the first capacitor plate are arranged in the same layer, and the first gate and the first active layer are partially overlapped in a thickness direction of the array substrate; preparing a first insulating layer on the first preliminary substrate; forming a second active material layer on the first insulating layer; Coating a photoresist layer on the second active material layer, and exposing and etching to form a second active layer and a photoresist on the second active layer; Etching the first preliminary substrate with the second active layer and the photoresist to remove a portion of the first insulating layer that is offset from the second active layer; The photoresist is stripped off and a second inter-gate insulating layer, a second gate electrode, and a second capacitor plate are continuously prepared to form an array substrate, wherein the second gate electrode and the second active layer are partially overlapped in the thickness direction.

2. The method according to claim 1, It is characterized in that In the step of stripping the photoresist and continuing to prepare a second inter-gate insulating layer, a second gate, and a second capacitor plate to form an array substrate: The second gate electrode and the second capacitor electrode plate are prepared on the second inter-gate insulating layer by using the same mask plate, and the second gate electrode and the second capacitor electrode plate are arranged in the same layer.

3. The method according to claim 1, It is characterized in that In the step of etching the first preliminary substrate with the second active layer and the photoresist to remove a portion of the first insulating layer that is offset from the second active layer: The first preliminary substrate with the second active layer and the photoresist is etched in a dry etching device.

4. The method according to claim 3, It is characterized in that In the step of etching the first preliminary substrate with the second active layer and the photoresist to remove a portion of the first insulating layer that is offset from the second active layer: the first preliminary substrate with the second active layer and the photoresist is etched using an etching gas, and the etching gas includes one or more of sulfur hexafluoride, argon, pentafluoroethane, carbon tetrafluoride, and oxygen.

5. The method according to claim 3, It is characterized in that The first insulating layer includes a first section and a second section, the first section and the second active layer are overlapped in the thickness direction, and the second section and the second active layer are staggered in the thickness direction, In the step of etching the first preliminary substrate with the second active layer and the photoresist to remove a portion of the first insulating layer that is offset from the second active layer: etching the second sub-portion so that the difference in thickness between the first sub-portion and the second sub-portion is and / or, etching the second sub-portion so that the thickness of the second sub-portion is less than or equal to 6. The method according to claim 5, It is characterized in that After the step of etching the first preliminary substrate with the second active layer and the photoresist to remove a portion of the first insulating layer that is offset from the second active layer, the method further includes: The second portion is patterned to form a first via hole, and at least a portion of the first capacitor plate is exposed through the first via hole.

7. The method according to claim 6, It is characterized in that The first capacitor plate is completely exposed from the first via hole.

8. The method according to claim 1, It is characterized in that The first active layer includes a first source region and a first drain region, the second active layer includes a second source region and a second drain region, the first capacitor plate includes a first connection region, and the second capacitor plate includes a second connection region, and the method further includes: Preparing a second insulating layer on the second gate and the second capacitor plate; The second insulating layer, the second inter-gate insulating layer, the first insulating layer and the first inter-gate insulating layer are subjected to a hole-opening process to form a plurality of connection holes, wherein the plurality of connection holes include a first connection hole, a second connection hole, a third connection hole and a fourth connection hole, the number of the first connection holes is two, the first source region and the first drain region are exposed by the first connection holes respectively, the first connection region is exposed by the second connection hole, the second connection region is exposed by the third connection hole, the number of the fourth connection holes is two, the second source region and the second drain region are exposed by the fourth connection holes respectively; A third conductive layer is prepared on the second insulating layer to form a first transistor, a first capacitor and a second transistor, the third conductive layer comprising a first source, a first drain, a first capacitor line, a second capacitor line, a second source and a second drain, the first source being interconnected with the first source region via the first connection hole, the first drain being interconnected with the first drain region via the first connection hole, the first capacitor line being interconnected with the first capacitor plate via the second connection hole, the second capacitor line being interconnected with the second capacitor plate via the third connection hole, the second source being interconnected with the second source region via the fourth connection hole, and the second drain being interconnected with the second drain region via the fourth connection hole.

9. The method according to claim 8, It is characterized in that The third conductive layer further includes a first signal line, and the first signal line is connected to the second gate via the connection hole.

10. The method according to claim 8, It is characterized in that The difference between the hole depth of at least one of the first connection hole, the second connection hole and the third connection hole and the hole depth of the fourth connection hole is 11. The method according to claim 8, It is characterized in that The hole depth difference between the first connection hole and the fourth connection hole is 12. An array substrate for a display panel, It is characterized in that The array substrate is prepared and formed by the method according to any one of claims 1 to 11, the layer structure of the array substrate comprises a substrate, a first conductive layer, a second conductive layer and a third conductive layer sequentially arranged on the substrate, and the array substrate further comprises: A first transistor comprising a first active layer, a first gate, a first source and a first drain; A second transistor comprising a second active layer, a second gate, a second source and a second drain; A first capacitor, comprising a first capacitor plate and a second capacitor plate; Among them, the first active layer is located between the first conductive layer and the substrate, the first gate and the first capacitor plate are located in the first conductive layer, the second active layer is located between the first conductive layer and the second conductive layer, the second gate and the second capacitor plate are located in the second conductive layer, and the first source, the first drain, the second source and the second drain are located in the third conductive layer.

13. The array substrate according to claim 12, It is characterized in that A first insulating layer is provided between the first conductive layer and the second active layer, the first insulating layer includes a first sub-portion and a second sub-portion, the first sub-portion and the second active layer are overlapped in a thickness direction of the array substrate, and the second sub-portion and the second active layer are staggered in the thickness direction, The thickness difference between the first section and the second section is: and / or, the thickness of the second section is less than or equal to 14. The array substrate according to claim 12, It is characterized in that The difference between the distance between the first capacitor plate and the second capacitor plate and the distance between the second gate and the second active layer is And / or, the difference between the distance between the third conductive layer and the first active layer and the distance between the third conductive layer and the second active layer is 15. A display panel, It is characterized in that include: The array substrate according to any one of claims 12 to 14; The light emitting structure is arranged on the array substrate, and the array substrate is used to drive the light emitting structure to emit light.

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