semiconductor devices

Abstract

A semiconductor device (1) according to an embodiment includes an oxide semiconductor layer (5). The oxide semiconductor layer (5) includes a metal oxide containing at least one first metal element selected from the group consisting of indium and tin, and at least one second metal element selected from the group consisting of zinc, gallium, aluminum, tungsten, and silicon. The oxide semiconductor layer (5) includes a first region containing at least one anion element selected from the group consisting of fluorine and chlorine in a range of 1 atomic % or more and less than 8 atomic % relative to the metal oxide.

Description

[0001] Citations of Related Applications

[0002] This application claims the benefit of priority based on the prior Japanese Patent Application No. 2020-142583, filed on August 26, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] An embodiment of the present invention relates to a semiconductor device. Background Art

[0004] An oxide semiconductor transistor using an oxide semiconductor in the channel region has the characteristic of low channel leakage current. Such an oxide semiconductor transistor uses, for example, one or more metal oxides containing metal elements such as indium (In), tin (Sn), zinc (Zn), and gallium (Ga). Such metal oxides, for example, having an amorphous structure, have the following characteristics: they have a large band gap and high mobility, but on the contrary, their properties as semiconductors are impaired. Summary of the Invention

[0005] One embodiment provides a semiconductor device capable of improving characteristics of an oxide semiconductor.

[0006] A semiconductor device according to an embodiment is a semiconductor device comprising an oxide semiconductor layer, the oxide semiconductor layer comprising a metal oxide containing at least one first metal element selected from the group consisting of indium and tin, and at least one second metal element selected from the group consisting of zinc, gallium, aluminum, tungsten, and silicon, the oxide semiconductor layer comprising a first region containing at least one anion element selected from the group consisting of fluorine and chlorine in a range of 1 atomic % or more and less than 8 atomic % relative to the metal oxide.

[0007] According to the above configuration, a semiconductor device capable of improving the characteristics of an oxide semiconductor can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0009] Figure 2 This is a diagram showing the formation enthalpies of halides and oxides of representative examples of metal elements in the oxide semiconductor layer of the semiconductor device according to the embodiment.

[0010] Figure 3 This is a table showing the standard electrode potentials of anion elements and oxygen contained in the oxide semiconductor layer of the semiconductor device according to the embodiment.

[0011] Figure 4(A) and (B) are graphs showing the relationship between the gate voltage (Vg) and the drain current (Id) after the heat treatment of the semiconductor device according to the first embodiment.

[0012] Figure 5 (A) to (C) are graphs showing the relationship between the gate voltage (Vg) and the drain current (Id) after heat treatment of a semiconductor device according to a comparative example.

[0013] Figure 6 It is a cross-sectional view showing a modified example of the semiconductor device according to the first embodiment.

[0014] Figure 7 It is a cross-sectional view showing a semiconductor device according to a second embodiment.

[0015] Figure 8 It is a cross-sectional view showing a modified example of the semiconductor device according to the second embodiment.

[0016] Figure 9 (A) to (C) are cross-sectional views showing a first manufacturing step of the semiconductor device according to the second embodiment.

[0017] Figure 10 (A) to (D) are cross-sectional views showing a second manufacturing process of the semiconductor device according to the second embodiment.

[0018] Figure 11 (A) to (D) are cross-sectional views showing a third manufacturing step of the semiconductor device according to the second embodiment.

[0019] Figure 12 (A) to (D) are cross-sectional views showing a fourth manufacturing step of the semiconductor device according to the second embodiment.

[0020] Figure 13 This is a circuit diagram of a semiconductor memory device according to a third embodiment.

[0021] Figure 14 It is a schematic perspective view showing a memory cell of a semiconductor memory device according to a third embodiment.

[0022] Figure 15 FIG. 1 is a schematic cross-sectional view showing a memory cell of a semiconductor memory device according to a third embodiment. DETAILED DESCRIPTION

[0023] The following describes semiconductor devices according to various embodiments with reference to the accompanying drawings. In various embodiments, substantially identical components may be denoted by the same reference numerals, and their descriptions may be partially omitted. The accompanying drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thicknesses of various components, and other aspects may differ from those in actual devices.

[0024] (First embodiment) Figure 1A thin film transistor (TFT) 1 is shown as a semiconductor device according to a first embodiment. The thin film transistor 1 is a bottom-gate oxide semiconductor transistor having an oxide semiconductor layer as a channel layer serving as a channel formation region. Figure 1 The transistor 1 shown includes a substrate 2, a gate electrode 3 serving as a first electrode, a gate insulating film 4, an oxide semiconductor layer 5 serving as a channel layer, a source electrode 6 serving as a second electrode, and a drain electrode 7 serving as a third electrode. The semiconductor device of the embodiment is not limited to a transistor having an oxide semiconductor layer as a channel layer, but can be applied to semiconductor devices having oxide semiconductor layers having various functions.

[0025] Figure 1 In the semiconductor device 1 shown, a gate electrode 3 is provided on a substrate 2, such as a semiconductor substrate, extending in a first direction, which is the surface direction of the substrate 2. A gate insulating film 4 is provided on the substrate 2 so as to cover the gate electrode 3. An oxide semiconductor layer 5, serving as a channel layer, is provided on the gate electrode 3, extending in the first direction via the gate insulating film 4. A portion of the oxide semiconductor layer 5 is arranged so as to face the gate electrode 3 (e.g., by stacking) via the gate insulating film 4. A source electrode 6 is provided on one end (first end) of the oxide semiconductor layer 5 in the first direction in an electrically connected manner, and a drain electrode 7 is provided on the other end (second end) in the first direction in an electrically connected manner.

[0026] The gate electrode 3 includes a metal, a metal compound, a conductive oxide, a semiconductor, or the like. For example, the gate electrode 3 may include at least one element selected from tungsten (W), molybdenum (Mo), copper (Cu), tantalum (Ta), aluminum (Al), or the like. The gate electrode 3 may also include an aluminum alloy primarily composed of aluminum. The gate electrode 3 may also include titanium nitride (TiN) or tantalum nitride (TaN). The gate insulating film 4 includes silicon oxide (SiO) or silicon nitride (SiN). The source electrode 6 and the drain electrode 7 use the same material as the gate electrode 3.

[0027] The oxide semiconductor layer 5 includes a metal oxide containing at least one first metal element selected from the group consisting of indium (In) and tin (Sn) (hereinafter sometimes referred to as the M1 element) and at least one second metal element selected from the group consisting of zinc (Zn), gallium (Ga), aluminum (Al), tungsten (W), and silicon (Si) (hereinafter sometimes referred to as the M2 element). Examples of the metal oxide constituting the oxide semiconductor layer 5 include metal oxides (M1-M2-O) in which at least one second metal element (M2 element) selected from the group consisting of Zn, Ga, Al, W, and Si is contained in one oxide selected from the group consisting of In oxide, Sn oxide, and InSn oxide.

[0028] Specific examples of In oxides containing the M2 element include InZnGaAlWSiO, InZnGaAlWSiO, InGaAlWSiO, InZnAlWSiO, InZnGaWSiO, InZnGaAlWO, InZnGaAlSiO, InAlWSiO, InGaWSiO, InGaAlWO, InGaAlSiO, InZnWSiO, InZnAlWO, InZnAlSiO, InZnGaWO, InZnGaSiO, InZnGaAlO, InWSiO, InAlWO, InAlSiO, InGaWO, InGaSiO, InGaAlO, InZnWO, InZnSiO, InZnAlO, InZnGaO, InZnO, InGaO, InAlO, InSiO, and InWO.

[0029] Specific examples of Sn oxides containing M2 elements include SnZnGaAlWSiO, SnZnGaAlWSiO, SnGaAlWSiO, SnZnAlWSiO, SnZnGaWSiO, SnZnGaAlWO, SnZnGaAlSiO, SnAlWSiO, SnGaWSiO, SnGaAlWO, SnGaAlSiO, SnZnWSiO, SnZnAlWO, SnZnAlSiO, SnZnGaWO, SnZnGaSiO, SnZnGaAlO, SnWSiO, SnAlWO, SnAlSiO, SnGaWO, SnGaSiO, SnGaAlO, SnZnWO, SnZnSiO, SnZnAlO, SnZnGaO, SnZnO, SnGaO, SnAlO, SnSiO, and SnWO.

[0030] Specific examples of InSn oxides containing the M2 element include InSnZnGaAlWSiO, InSnZnGaAlWSiO, InSnGaAlWSiO, InSnZnAlWSiO, InSnZnGaWSiO, InSnZnGaAlWO, InSnZnGaAlSiO, InSnAlWSiO, InSnGaWSiO, InSnGaAlWO, InSnGaAlSiO, InSnZnWSiO, InSnZnAl WO, InSnZnAlSiO, InSnZnGaWO, InSnZnGaSiO, InSnZnGaAlO, InSnWSiO, InSnAlWO, InSnAlSiO, InSnGaWO, InSnG aSiO, InSnGaAlO, InSnZnWO, InSnZnSiO, InSnZnAlO, InSnZnGaO, InSnZnO, InSnGaO, InSnAlO, InSnSiO, InSnWO.

[0031] A metal oxide (M1 oxide) selected from the group consisting of In oxide, Sn oxide, and InSn oxide is known as an oxide semiconductor with higher mobility. These metal oxides preferably have an amorphous structure. By having an amorphous structure of the metal oxide constituting the oxide semiconductor layer 5, the unevenness of the characteristics of the oxide semiconductor layer 5 can be suppressed. In the semiconductor device 1 of the embodiment, in order to improve the characteristics of the metal oxide (M1 oxide), the M1 oxide contains at least one M2 element selected from the group consisting of Zn, Ga, Al, W, and Si. In the semiconductor device 1 of the embodiment, such a metal oxide (M1-M2-O) is applied to the oxide semiconductor layer 5.

[0032] Among the M2 elements, Zn has the effect of promoting stability as an amorphous material. In addition, Ga, Al, W, Si, etc. have a strong bonding force with oxygen, so they help to improve the heat resistance of the M1 oxide. Regarding the heat resistance of the M1 oxide, it is required to suppress the metallization of the M1 oxide after reduction by heat treatment in the manufacturing process of the semiconductor device 1. The content ratio of the M1 element and M2 in M1-M2-O can be appropriately selected according to the characteristics required of the oxide semiconductor layer 5. For example, the content of the M1 element in M1-M2-O can be set to 10 atomic % or more and 40 atomic % or less, and the content of the M2 element can be set to 1 atomic % or more and 30 atomic % or less.

[0033] However, simply adding Ga, Al, W, and Si to the M1 oxide cannot fully improve the heat resistance of the M1 oxide. This aspect is also the same in the oxide formed by adding Zn to the M1 oxide. Therefore, in the semiconductor device 1 of the embodiment, the metal oxide (M1-M2-O) containing the first metal element (M1 element) and the second metal element (M2 element) is made to contain at least one anion element (hereinafter sometimes referred to as A element) selected from the group consisting of fluorine (F) and chlorine (Cl). The anion element (A element) may also be contained in the entire oxide semiconductor layer 5 containing M1-M2-O, or as described below, may be contained only in a part of the region of the oxide semiconductor layer 5. The oxide semiconductor layer 5 only needs to have a region where M1-M2-O contains the A element.

[0034] Fluorine (F) or chlorine (Cl) bonds more strongly to the M1 or M2 element (cation) than oxygen (O). In other words, the F or Cl anion strongly bonds to the M1 or M2 cation, improving the heat resistance of the M1-M2-O structure. Figure 2 As an indicator of the bonding strength between the halogen elements F and Cl and the cations, the formation enthalpy (Δ f H) with the oxides of Ga, In, and Zn (Δ f H) Comparative representation. Figure 2 As the reference element for the halogen elements, namely bromine (Br) and iodine (I), the formation enthalpy (Δ f H) together.

[0035] like Figure 2 As shown, the enthalpy of formation of fluorides (F compounds) or chlorides (Cl compounds) of Ga, In, and Zn is greater than the absolute value of the enthalpy of formation of oxides of Ga, In, and Zn. Based on this, it can be seen that fluorides such as Ga, In, and Zn are more stable than oxides such as Ga, In, and Zn. Therefore, by making M1-M2-O constituting the oxide semiconductor layer 5 contain an appropriate amount of A element (F, Cl), the heat resistance of the oxide semiconductor layer 5 can be improved, and metallization caused by reduction during heat treatment can be suppressed. In this regard, the enthalpy of formation of bromides (Br compounds) or iodides (I compounds) of Ga, In, and Zn is smaller than the absolute value of the enthalpy of formation of oxides of Ga, In, and Zn. Therefore, even if Br or I is contained as a halogen element, the heat resistance of the oxide semiconductor layer 5 cannot be improved.

[0036] Regarding the halogen elements F, Cl, Br, and I, from the viewpoint of the standard electrode potential, which is an indicator of oxidizing power, it is expected that a metal compound of F or Cl is stable, whereas a metal compound of Br or I is unstable. Figure 3 The half-reaction formulas of F, Cl, O, Br, and I and the standard electrode potentials (V vs SHE) based on these half-reaction formulas are shown. Figure 3 As shown, the standard electrode potentials of F and Cl are greater than that of O. In contrast, the standard electrode potentials of Br and I are smaller than that of O. The standard electrode potentials are in the order of F>Cl>O>Br>I, indicating that F and Cl have stronger oxidizing power, while Br and I have weaker oxidizing power. Therefore, it can be seen that the metal compounds of F and Cl are stable and can improve the heat resistance of the oxide semiconductor layer 5. On the other hand, it can be seen that the metal compounds of Br and I are unstable and are not conducive to improving the heat resistance of the oxide semiconductor layer 5.

[0037] The content of F and Cl relative to the M1-M2-O is preferably set to an appropriate range. That is to say, if the content of F and Cl relative to M1-M2-O is too little, the effect of improving the heat resistance by utilizing F and Cl cannot be fully obtained. On the other hand, if the content of F and Cl relative to M1-M2-O is too much, it is easy to form a metal-metal bond that becomes an electron trap, and the carrier electrons are easily deactivated. Therefore, the mobility of the oxide semiconductor is reduced and the on-current is easily reduced. In other words, the characteristics of the oxide semiconductor are reduced. Taking these aspects into consideration, at least one A element of F and Cl is preferably set to a range of 1 atomic % or more and less than 8 atomic % relative to the content of M1-M2-O, and further preferably a range of less than 7 atomic %. By containing an A element in such a range, a higher mobility of the oxide semiconductor can be maintained and the heat resistance can be improved.

[0038] Based on the above aspects, the investigation Figure 1 The relationship between the drain current (Id) and the gate voltage (Vg) (Vg-Id characteristics) of the bottom-gate oxide semiconductor transistor (TFT) shown in FIG. Figure 4 and Figure 5 . Figure 4 In the figure, regarding TFT1, the Vg-Id characteristics when annealed in the composition gas at 380°C and the Vg-Id characteristics when annealed in the composition gas at 400°C are shown respectively. The TFT1 uses InGaZnO as the oxide serving as the base, and an amorphous oxide (A) containing 2.5 atomic % of F and an amorphous oxide (B) containing 5 atomic % of F are used as the oxide semiconductor layer 5. Figure 5In the figure, regarding TFT1, the Vg-Id characteristics when annealed in the composition gas at 380°C and the Vg-Id characteristics when annealed in the composition gas at 400°C are shown respectively. The TFT1 uses InGaZnO as the oxide serving as the base, and an amorphous oxide (A) to which no F is added, an amorphous oxide (B) containing 0.5 atomic % of F, and an amorphous oxide (C) containing 10 atomic % of F are used as the oxide semiconductor layer 5.

[0039] like Figure 4 As shown, an amorphous oxide containing 2.5 atomic % of F ( Figure 4 (A)) and an amorphous oxide containing 5 atomic % of F ( Figure 4 (B)) The TFT1 used as the oxide semiconductor layer 5 obtains the same Vg-Id characteristics when annealed at 400°C as when annealed at 380°C. That is, when annealed at 400°C, the on-current of the TFT1 is maintained. Therefore, as long as the F concentration is 2.5 atomic % or 5 atomic %, the high mobility of the oxide semiconductor layer 5 can be maintained and the heat resistance can be improved. Figure 5 As shown in (C), it was confirmed that when the F concentration reaches 10 atomic % or more, the on-current of TFT1 decreases and the mobility of oxide semiconductor layer 5 decreases. F and Cl that replace O act as donor impurities, generating one carrier electron for each replaced atom. It is estimated that metal-metal bonds will have a carrier electron concentration of 4.7×10 21 cm -3 The above conditions are easy to occur, and in this case, the atomic concentration of F and Cl is about 7 atomic %. Therefore, if the F concentration is within the range of less than 8 atomic %, the same effect as the case of 5 atomic % of F concentration can be expected.

[0040] On the other hand, Figure 5As shown, TFT1 using an amorphous oxide (B) containing 0.5 atomic % of F as the oxide semiconductor layer 5 obtains good Vg-Id characteristics when annealed at 380°C. In contrast, no on-off characteristics can be obtained when annealed at 400°C. This is believed to be because the oxide semiconductor layer 5 is metallized after reduction by heat treatment and loses its semiconductor properties. In view of this, if an oxide semiconductor layer 5 with a F concentration of 1 atomic % is used, then the same effect as an oxide semiconductor layer 5 with a F concentration of 2.5 atomic % can be expected. Due to the similarity in the characteristics of F and Cl, these conditions can also be obtained when M1-M2-O contains Cl instead of F. Therefore, the content of element A relative to M1-M2-O constituting the oxide semiconductor layer 5 is preferably set to 1 atomic % or more and less than 8 atomic %. In addition, when using two elements, F and Cl, as element A, it is preferred to adjust the composition so that the total amount of these elements is within the range of 1 atomic % or more and less than 8 atomic %.

[0041] The metal oxide formed by replacing a part of O in the metal oxide (M1-M2-O) containing the M1 element and the M2 element with the A element preferably satisfies the following composition. That is, in the M1-M2-O formed by replacing a part of O with the A element, the composition formula is: 2 i M 3 j M 4 k M 6 l (O,F,Cl) n )…(1)(where M 2 Zn, M 3 Indicates In, Ga, and Al, M 4 Indicates Sn and Si, M 6 represents W, i represents M 2 The atomic ratio of M 3 The atomic ratio of M 4 The atomic ratio of M 6 When the atomic ratio of (O, F, Cl) is replaced by the A element, it is preferred that M1-M2-O, in which a portion of O is replaced by the A element, has a composition that satisfies the relationship (2i+3j+4k+6l) / 2×0.95<n<(2i+3j+4k+6l) / 2×1.05…(2). This allows stable properties as an oxide semiconductor. Here, O, F, and Cl are anions, O has a valence of -2, and F and Cl have a valence of -1. However, it is assumed that a portion of O is replaced by F and Cl, and F and Cl are calculated as having a valence of -2.

[0042] As described above, by applying M1-M2-O containing the element A, particularly M1-M2-O containing the element A in a range of 1 atomic % or more and less than 8 atomic %, to the oxide semiconductor layer 5 of the TFT 1, it is possible to maintain the inherent high mobility of the M1-M2-O and the high on-current or low leakage current resulting therefrom, and to improve the heat resistance to heat treatment performed during the manufacturing process, for example, heat resistance to heat treatment at 400°C performed during the manufacturing process of a typical semiconductor device. Therefore, it is possible to maintain the on-current based on the high mobility, obtain low leakage current, and improve heat resistance. Based on these conditions, it is possible to provide a semiconductor device such as the oxide semiconductor transistor 1 with improved characteristics, stability, or reproducibility.

[0043] In the oxide semiconductor transistor 1 of the first embodiment, the heat resistance required of the oxide semiconductor layer 5 and the metallization suppression effect obtained thereby may differ depending on the location of the oxide semiconductor layer 5. For example, Figure 6 As shown, since the first region R1 of the oxide semiconductor layer 5 located directly above the gate electrode 3 is a region that can be directly expected to function as a channel region, it is required to prevent metallization caused by heat treatment and function as a high-mobility semiconductor. On the other hand, the second region R2 of the oxide semiconductor layer 5 that is in contact with the source electrode 6 and the third region R3 that is in contact with the drain electrode 7 are sometimes required to reduce the contact resistance (Schottky resistance) with the source electrode 6 or the drain electrode 7 and improve the electrical connection characteristics with the source electrode 6 or the drain electrode 7.

[0044] As described above, sometimes the characteristics required of the regions of the oxide semiconductor layer 5 (e.g., region R1, region R2, and region R3) are different. In view of this aspect, the first region R1 in the oxide semiconductor layer 5, which is located directly above the gate electrode 3, preferably includes M1-M2-O containing the A element, and in particular, M1-M2-O containing the A element in a range of 1 atomic % or more and less than 8 atomic %. On the other hand, in the second region R2 in contact with the source electrode 6 or the third region R3 in contact with the drain electrode 7 in the oxide semiconductor layer 5, in order to reduce the contact resistance with the source electrode 6 or the drain electrode 7, it is preferable to promote metallization by heat treatment. Therefore, the second region R2 and the third region R3 preferably include M1-M2-O that does not contain the A element, for example, M1-M2-O with an A element content of less than 1 atomic %. This promotes metallization by heat treatment in the second region R2 and the third region R3 of the oxide semiconductor layer 5, thereby reducing contact resistance with the source electrode 6 or the drain electrode 7. This allows for providing a semiconductor device such as the oxide semiconductor transistor 1 with further improved characteristics.

[0045] (Second embodiment) Figure 7 A transistor 11 is shown as a semiconductor device according to a second embodiment. The transistor 11 is a vertical transistor, and is a so-called Surrounding Gate Transistor (SGT) in which a gate electrode surrounds a channel layer. Figure 7 The transistor 11 shown includes a substrate 12 , a gate electrode 13 as a first electrode, a gate insulating film 14 , an oxide semiconductor layer 15 as a channel layer, a source electrode 16 as a second electrode, and a drain electrode 17 as a third electrode.

[0046] Figure 7 In the transistor 11 shown, a source electrode 16 is provided on a substrate 12 such as a semiconductor substrate. An oxide semiconductor layer 15 is provided on the source electrode 16 and extends in a first direction intersecting the surface of the substrate 12. The oxide semiconductor layer 15 has a cylindrical shape having a bottom, and the bottom of the cylinder forming the oxide semiconductor layer 15 is in contact with the source electrode 16. The bottom of the cylinder in the oxide semiconductor layer 15 serves as a portion electrically in contact with the source electrode 16. An insulating film 14 is provided along the outer peripheral surface of the cylindrical oxide semiconductor layer 15. The gate electrode 13 is provided along the outer peripheral surface of the cylindrical oxide semiconductor layer 15 with the insulating film 14 interposed therebetween. A drain electrode 17 is provided so as to be electrically connected to the end portion of the cylindrical oxide semiconductor layer 15 on the opposite side of the bottom.

[0047] The gate electrode 13, the source electrode 16, the drain electrode 17, and the insulating film 14 are made of the same materials as those in the first embodiment. The interior of the cylindrical oxide semiconductor layer 15 is filled with an insulating film 18 such as silicon oxide. In addition, instead of the cylindrical oxide semiconductor layer 15, a cylindrical oxide semiconductor layer 15 including an oxide semiconductor can be used. In this structure, the insulating film 18 such as silicon oxide is not filled. The oxide semiconductor layer 15 can be provided so as to extend between the source electrode 16 and the drain electrode 17 along the first direction, that is, the vertical direction of the transistor 11 (the thickness direction when manufacturing each part), thereby forming a vertical transistor.

[0048] The oxide semiconductor layer 15 in the transistor 11 of the second embodiment, similarly to the first embodiment, includes a metal oxide (M1-M2-O) containing at least one first metal element (M1 element) selected from the group consisting of In and Sn, and at least one second metal element (M2 element) selected from the group consisting of Zn, Ga, Al, W, and Si, and further includes a region (first region) containing at least one anion element (A element) selected from the group consisting of F and Cl in the metal oxide. The first region containing the A element may be formed throughout the oxide semiconductor layer 15, as described in detail below, or may be formed only in a portion of the oxide semiconductor layer 15.

[0049] As in the first embodiment, the transistor 11 employing the oxide semiconductor layer 15 including M1-M2-O containing the A element and having the first region can maintain the inherent high mobility of M1-M2-O and the high on-current or low leakage current resulting therefrom, while also improving heat resistance to heat treatments performed during the manufacturing process, such as heat resistance to 400°C heat treatments performed during conventional semiconductor device manufacturing processes. Consequently, it is possible to maintain the on-current resulting from the high mobility, achieve low leakage current, and improve heat resistance. These features can provide a semiconductor device such as the oxide semiconductor transistor 11 with improved characteristics, stability, or reproducibility.

[0050] The first region in the oxide semiconductor layer 15 of the second embodiment preferably contains the A element in a range of 1 atomic % or more and less than 8 atomic % as in the first embodiment. The second region and the third region other than the first region preferably contain the A element in a range of less than 1 atomic % as in the first embodiment. In addition, the metal oxide semiconductor including M1-M2-O containing the A element preferably has a composition satisfying formula (2) when its composition is expressed by formula (1) as in the first embodiment. The other configurations of the oxide semiconductor layer 15 are also the same as in the first embodiment. In addition to the difference in transistors and structure from the first embodiment, the second embodiment has the same constituent materials, etc. of each part and exhibits the same effects as the first embodiment.

[0051] like Figure 8As shown, the transistor 11 of the second embodiment may include an oxide semiconductor layer 15 having a first region R1, a second region R2, and a third region R3. For example, since the first region R1 of the oxide semiconductor layer 15, which faces the gate electrode 13, is expected to function as a channel region, it is required to prevent metallization caused by heat treatment and function as a high-mobility semiconductor. Therefore, the first region R1 of the oxide semiconductor layer 5 preferably includes M1-M2-O containing the A element, and in particular, the M1-M2-O containing the A element in a range of 1 atomic % or more and less than 8 atomic %.

[0052] On the other hand, the second region R2 in the oxide semiconductor layer 15 that is in contact with the source electrode 16 or the third region R3 in contact with the drain electrode 17 is required to reduce the contact resistance (Schottky resistance) with the source electrode 16 or the drain electrode 17 and improve the electrical connection characteristics. Therefore, in order to reduce the contact resistance with the source electrode 16 or the drain electrode 17, the second and third regions R2 and R3 in the oxide semiconductor layer 15 preferably include M1-M2-O with an A content of less than 1 atomic % to promote metallization due to heat treatment. As a result, the second and third regions R2 and R3 of the oxide semiconductor layer 15 can reduce the contact resistance with the source electrode 16 or the drain electrode 17 by promoting metallization due to heat treatment. Based on these circumstances, a semiconductor device such as the oxide semiconductor transistor 11 with further improved characteristics can be provided.

[0053] Figure 8 The transistor 11 shown can be applied, for example, Figure 9 The first manufacturing process shown, Figure 10 The second manufacturing process shown, Figure 11 The third manufacturing process shown, Figure 12 Furthermore, as shown in the example of the manufacturing process below, the second region R2 and the third region R3 of the oxide semiconductor layer 15 can be set in the region R2 in contact with the source electrode 16 and the region R3 in contact with the drain electrode 17, respectively, or only in one of the second region R2 and the third region R3. Figure 8 As described above, the variation of the transistor 11 shown may employ a cylindrical oxide semiconductor layer 15 including an oxide semiconductor in its interior, instead of the cylindrical oxide semiconductor layer 15. In this structure, the insulating film 18 such as silicon oxide is not filled.

[0054] Reference Figure 9 right Figure 8 The first manufacturing step of the transistor 11 shown in FIG. Figure 9The first manufacturing process shown is a manufacturing method in which regions containing less than 1 atomic % of the element A are set in two regions, namely, the region R2 in contact with the source electrode 16 and the region R3 in contact with the drain electrode 17. Figure 9 As shown in FIG. 1A , a source electrode 16, a gate electrode 13, and a gate insulating film 14 are formed on a substrate 12 using the same process as a conventional vertical transistor. Next, a first oxide semiconductor layer 15A comprising M1-M2-O, which forms part of the oxide semiconductor layer 15, is formed along a hollow portion H provided inside the gate insulating film 14. The first oxide semiconductor layer 15A does not contain the A element and contributes to the formation of the second region R2 and the third region R3.

[0055] Next, if Figure 9 As shown in FIG. 2B , a second oxide semiconductor layer 15B including M1-M2-O containing element A is formed on the first oxide semiconductor layer 15A. The second oxide semiconductor layer 15B contains element A within a predetermined range as described above. By stacking the first oxide semiconductor layer 15A and the second oxide semiconductor layer 15B to form the oxide semiconductor layer 15, an oxide semiconductor layer 15 in which the content of element A varies, for example, in a gradient manner can be obtained. For example, in the first region R1 facing the gate electrode 13, the second oxide semiconductor layer 15B primarily functions, so the inherent characteristics of the oxide semiconductor layer 15 can be exhibited. On the other hand, since at least a portion of the first oxide semiconductor layer 15A is present in the region R2 in contact with the source electrode 16 and the region R3 in contact with the drain electrode 17, the contact resistance with the source electrode 16 or the drain electrode 17 can be reduced.

[0056] Then, if Figure 9 As shown in (C), after the insulating film 18 is filled into the hollow portion H remaining inside the second oxide semiconductor layer 15B, the drain electrode 17 is formed, thereby obtaining the transistor 11. Here, as for the insulating film 18 filled into the hollow portion H remaining inside the second oxide semiconductor layer 15B, a silicon oxide film or the like is generally used. For example, the insulating film 18 filled into the hollow portion H may be a silicon oxide film containing at least one A element selected from F and Cl. Alternatively, a silicon oxide film containing F or Cl may be applied through the insulating film 18, so that the F or Cl contained in the insulating film 18 is diffused into the second oxide semiconductor layer 15B. The same is true in the second manufacturing process.

[0057] Reference Figure 10 right Figure 8 The second manufacturing step of the transistor 11 shown in FIG. Figure 10 The second manufacturing process shown is a manufacturing method in which a region containing the A element is set to be less than 1 atomic % in the second region R2 in contact with the source electrode 16. Figure 10 (A) shows that Figure 9 In the same manner as the second manufacturing process shown in FIG. 1 , a source electrode 16, a gate electrode 13, and a gate insulating film 14 are formed on the substrate 12. Then, the hollow portion H provided inside the gate insulating film 14 is filled with a first oxide semiconductor layer 15A comprising M1-M2-O, which becomes part of the oxide semiconductor layer 15. The first oxide semiconductor layer 15A does not contain the A element and contributes to the formation of the second region R2. Then, as shown in FIG. Figure 10 As shown in FIG. 1B , the first oxide semiconductor layer 15A is etched back. The thickness of the remaining portion of the first oxide semiconductor layer 15A is not particularly limited as long as it is within a range sufficient to form the second region R2 in contact with the source electrode 16 .

[0058] Next, if Figure 10 As shown in FIG. 2A , a second oxide semiconductor layer 15B comprising M1-M2-O containing element A is formed within the hollow portion H above the first oxide semiconductor layer 15A. The second oxide semiconductor layer 15B contains element A within the range specified above. By stacking the first oxide semiconductor layer 15A and the second oxide semiconductor layer 15B to form the oxide semiconductor layer 15, a first region R1 facing the gate electrode 13 can be formed in the second oxide semiconductor layer 15B, while a second region R2 in contact with the source electrode 16 can be formed in the first oxide semiconductor layer 15A. This allows the first region R1 to utilize the characteristics of the oxide semiconductor layer 15 while reducing contact resistance with the source electrode 16.

[0059] Then, if Figure 10 As shown in FIG. 1A , the hollow portion H remaining inside the second oxide semiconductor layer 15B is filled with an insulating film 18, and then the drain electrode 17 is formed, thereby obtaining the transistor 11. As shown in the first manufacturing step, the insulating film 18 filling the hollow portion H remaining inside the second oxide semiconductor layer 15B may be a silicon oxide film containing at least one element A selected from F and Cl. Alternatively, a silicon oxide film containing F or Cl may be used through the insulating film 18, so that the F or Cl contained in the insulating film 18 diffuses into the second oxide semiconductor layer 15B.

[0060] Reference Figure 11 right Figure 8 The third manufacturing step of the transistor 11 shown in FIG. Figure 11 The third manufacturing process shown is a manufacturing method for setting a region where the content of the A element is less than 1 atomic % in the third region R3 in contact with the drain electrode 17. First, as shown in FIG. Figure 11 (A) shows that Figure 9In the same manner as the second manufacturing process shown in FIG. 1 , a source electrode 16, a gate electrode 13, and a gate insulating film 14 are formed on the substrate 12. Then, the hollow portion H provided inside the gate insulating film 14 is filled with a second oxide semiconductor layer 15B comprising M1-M2-O containing the A element. Figure 11 As shown in (B), the second oxide semiconductor layer 15B is etched back. The depth of the etch back of the second oxide semiconductor layer 15B is not particularly limited as long as it is within a range sufficient to form the third region R3 in contact with the drain electrode 17.

[0061] Next, if Figure 11 As shown in (C), the first oxide semiconductor layer 15B including M1-M2-O that does not contain the A element is formed in the hollow portion H formed by etching back the second oxide semiconductor layer 15B. By stacking the first oxide semiconductor layer 15A and the second oxide semiconductor layer 15B to form the oxide semiconductor layer 15, the first region R1 adjacent to the gate electrode 13 can be formed in the second oxide semiconductor layer 15B, and the third region R3 in contact with the drain electrode 17 can be formed in the first oxide semiconductor layer 15A. Therefore, the first region R1 can exhibit the characteristics of the oxide semiconductor layer 15 and reduce the contact resistance with the drain electrode 17. Then, as shown in FIG. Figure 11 As shown in (D), the drain electrode 17 is formed on the oxide semiconductor layer 15 , thereby obtaining the transistor 11 .

[0062] Reference Figure 12 right Figure 8 The fourth manufacturing step of the transistor 11 shown in FIG. Figure 12 The fourth manufacturing process shown is a process that combines the second manufacturing process and the third manufacturing process. Figure 10 In the same manner as the step (B), the first oxide semiconductor layer 15A filled in the hollow portion H is etched back ( Figure 12 (A)). Then, if Figure 12 As shown in (B), the hollow portion H on the first oxide semiconductor layer 15A is filled with the second oxide semiconductor layer 15B composed of M1-M2-O containing the A element.

[0063] Next, if Figure 12As shown in (C), the second oxide semiconductor layer 15B is etched back, and a third oxide semiconductor layer 15C including M1-M2-O that does not contain the A element is formed in the hollow portion H formed by the etching back. By stacking the first oxide semiconductor layer 15A, the second oxide semiconductor layer 15B, and the third oxide semiconductor layer 15C to form the oxide semiconductor layer 15, a first region R1 adjacent to the gate electrode 13 can be formed in the second oxide semiconductor layer 15B, and a second region R2 in contact with the source electrode 16 and a third region R3 in contact with the drain electrode 17 can be formed in the first and third oxide semiconductor layers 15A and 15C, respectively. Therefore, the first region R1 can exhibit the characteristics of the oxide semiconductor layer 15, and the contact resistance with the source electrode 16 and the drain electrode 17 can be reduced. Then, as shown in FIG. Figure 12 As shown in (D), the drain electrode 17 is formed on the oxide semiconductor layer 15 , thereby obtaining the transistor 11 .

[0064] In addition, Figure 11 (D) and Figure 12 In (D), the oxide semiconductor layer 15 is shown to be formed in a cylindrical shape, but the third and fourth manufacturing steps may also be applied as follows. Figure 8 By forming the oxide semiconductor layer 15 along the inner surface of the hollow portion H, a structure having the following characteristics can be obtained: Figure 8 In this case, the hollow portion formed inside the oxide semiconductor layer 15 may be filled with the insulating film 18 .

[0065] (Third embodiment) Figure 13 、 Figure 14 ,and Figure 15 A semiconductor memory device according to Embodiment 3 is shown. The semiconductor memory device shown in these figures includes a plurality of memory cell arrays. Figure 13 This is a circuit diagram for explaining an example of the circuit configuration of a memory cell array. Figure 13 The figure shows multiple memory cells MC, multiple word lines WL (word line WLn, word line WLn+1, word line WLn+2, n is an integer), and multiple bit lines BL (bit line BLm, bit line BLm+1, bit line BLm+2, m is an integer).

[0066] A plurality of memory cells MC are arranged in a matrix direction to form a memory cell array. Each memory cell MC includes a memory transistor MTR as a field effect transistor (FET) and a memory capacitor MCP. The gate of the memory transistor MTR is connected to the corresponding word line WL, and one of the source or drain is connected to the corresponding bit line BL. One electrode of the memory capacitor MCP is connected to the other of the source or drain of the memory transistor MTR, and the other electrode is not shown but is connected to a power supply line that supplies a specific potential. The memory cell MC can accumulate charge from the bit line BL to the memory capacitor MCP and save data by switching the memory transistor MTR using the word line WL. The number of the plurality of memory cells MC is not limited to Figure 13 Quantity shown.

[0067] Reference Figure 14 and Figure 15 The following describes an example of the structure of the field effect transistor MTR and the memory capacitor MCP in the memory cell MC. Figure 14 and Figure 15 In the figure, reference numeral 30 denotes a memory capacitor MCP, and reference numeral 51 denotes a field effect transistor (memory transistor) MTR. Figure 14 It is a three-dimensional schematic diagram of the storage unit MC. Figure 15 3 is a schematic cross-sectional view of a memory cell MC. The capacitor 30 is provided above the semiconductor substrate and below the field effect transistor 51, constituting a memory capacitor MCP of the memory cell MC.

[0068] The capacitor 30 is a three-dimensional capacitor such as a cylindrical capacitor or a cylindrical capacitor. Figure 14 and Figure 15 As shown, the three-dimensional capacitor 30 includes a cell electrode 31, an insulating film 32, a plate electrode 33, and a plate electrode 34. The cell electrode 31 functions as the first electrode of the memory capacitor MCP. The insulating film 32 functions as the dielectric layer of the memory capacitor MCP and is provided between the cell electrode 31 and the plate electrode 33. The plate electrode 33 functions as the second electrode of the memory capacitor MCP and is provided opposite the cell electrode 31. The plate electrode 34 is connected to the plate electrode 33. Using this three-dimensional capacitor 30, the area of ​​the memory cell MC can be reduced.

[0069] like Figure 14 and Figure 15 As shown, oxide conductive layer 41 is provided in contact with cell electrode 31. Oxide conductive layer 41 comprises, for example, a metal oxide such as indium-tin-oxide (ITO). Field effect transistor 51 is provided above the semiconductor substrate and above capacitor 30, and constitutes memory transistor MTR of memory cell MC.

[0070] like Figure 14 and Figure 15 As shown, the field effect transistor 51 includes a channel layer 501 comprising an oxide semiconductor such as a metal oxide, and a gate insulating film 502 surrounding the channel layer 501. One end of the channel layer 501 in the Z-axis direction is connected to the wiring 71 via the oxide conductive layer 42 and functions as either the source or the drain of the field effect transistor 51. The other end is connected to the oxide conductive layer 41 and functions as the other of the source or the drain of the field effect transistor 51. In this case, the oxide conductive layer 41 is provided between the cell electrode 31 of the capacitor 30 and the channel layer 501 of the field effect transistor 51 and functions as the other of the source or the drain of the field effect transistor 51. Since the oxide conductive layer 41 comprises the same metal oxide as the channel layer 501 of the field effect transistor 51, the connection resistance between the field effect transistor 51 and the oxide conductive layer 41 can be reduced.

[0071] The channel layer 501 has the same structure as the oxide semiconductor layer (5, 15) in the first and second embodiments. The gate insulating film 502 includes, for example, oxide or oxynitride (for example, silicon oxide). Figure 14 and Figure 15 As shown, the wiring 61 is provided opposite to the channel layer 501 via the gate insulating film 502, and functions as a gate electrode of the field effect transistor 51. Figure 14 As shown, the field effect transistor 51 is a so-called Surrounding Gate Transistor (SGT) in which a gate electrode is arranged to surround a channel layer 501. The SGT can reduce the area of ​​a semiconductor memory device.

[0072] Field-effect transistors with a channel layer composed of an oxide semiconductor have lower off-state leakage current than field-effect transistors formed on a semiconductor substrate. Therefore, for example, data stored in memory cell MC can be retained for a long period of time, reducing the number of refresh operations. Furthermore, field-effect transistors with a channel layer composed of an oxide semiconductor can be formed using a low-temperature process, thus minimizing thermal stress on capacitor 30.

[0073] The wiring 61 includes, for example, a metal, a metal compound, or a semiconductor. The wiring 61 includes, for example, at least one material selected from the group consisting of tungsten (W), titanium (Ti), titanium nitride (TiN), molybdenum (Mo), cobalt (Co), and ruthenium (Ru).

[0074] like Figure 14 and Figure 15As shown, the oxide conductive layer 42 is provided in contact with the channel layer 501 of the field effect transistor 51 and functions as either a source electrode or a drain electrode of the field effect transistor 51. The oxide conductive layer 42 comprises, for example, a metal oxide such as indium-tin-oxide (ITO). Since the oxide conductive layer 42 comprises the same metal oxide as the channel layer 501 of the field effect transistor 51, the connection resistance between the field effect transistor 51 and the oxide conductive layer 42 can be reduced.

[0075] like Figure 14 and Figure 15 As shown, wiring 71 is provided above field effect transistor 51 in contact with oxide conductive layer 42 and is connected to channel layer 501 of field effect transistor 51 via oxide conductive layer 42. Oxide conductive layer 42 functions as either a source electrode or a drain electrode of field effect transistor 51.

[0076] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope and spirit of the invention and within the invention set forth in the claims and their equivalents.

Claims

1. A semiconductor device comprising: an oxide semiconductor layer extending in a first direction and having a first end and a second end opposite to the first end; a first electrode surrounding an outer peripheral surface of the oxide semiconductor layer; an insulating film provided between the first electrode and the outer peripheral surface of the oxide semiconductor layer; a second electrode electrically connected to the first end portion of the oxide semiconductor layer; a third electrode electrically connected to the second end portion of the oxide semiconductor layer; and an insulator extending along the first direction and surrounded by the oxide semiconductor layer; The oxide semiconductor layer includes a metal oxide containing at least one first element selected from the group consisting of indium and tin, and at least one second element selected from the group consisting of zinc, gallium, aluminum, tungsten, and silicon. The oxide semiconductor layer includes a first region containing at least one third element selected from the group consisting of fluorine and chlorine in a range of 1 atomic % or more and less than 8 atomic % relative to the metal oxide, and The insulator contains at least one element selected from the group consisting of fluorine and chlorine. 2 . The semiconductor device according to claim 1 , wherein the oxide semiconductor layer has an amorphous structure. 3 . The semiconductor device according to claim 1 , wherein the oxide semiconductor layer includes a second region in which a content of the third element is less than 1 atomic % relative to the metal oxide.

4. The semiconductor device according to claim 1 or 2, wherein the composition formula: M 2 i M 3 j M 4 k M 6 l (O,F,Cl) n (Where M 2 Zn, M 3 Indicates In, Ga, and Al, M 4 Indicates Sn and Si, M 6 represents W, i represents M 2 The atomic ratio of M 3 The atomic ratio of M 4 The atomic ratio of M 6 When the composition of the first region is represented by the atomic ratio of O, F, and Cl, the first region has a composition that satisfies the relationship of (2i+3j+4k+6l) / 2×0.95<n<(2i+3j+4k+6l) / 2×1.

05.

5. The semiconductor device according to claim 1 , wherein the first region is arranged opposite to the first electrode, and the oxide semiconductor layer includes at least one of a second region electrically connected to the second electrode and having a content of the third element less than 1 atomic % relative to the metal oxide, and a third region electrically connected to the third electrode and having a content of the third element less than 1 atomic % relative to the metal oxide. 6 . The semiconductor device according to claim 1 , further comprising a capacitor electrically connected to the second electrode or the third electrode.

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