Photoelectric conversion structure, manufacturing method thereof, image sensor and electronic device

Abstract

The embodiment of the present invention provides a photoelectric conversion structure, a manufacturing method thereof, an image sensor and an electronic device, including an N-type semiconductor layer, an intrinsic semiconductor layer and a P-type semiconductor layer, wherein the intrinsic semiconductor layer includes an amorphous silicon layer and a polycrystalline silicon layer arranged in layers. The present invention arranges the intrinsic semiconductor layer into a composite structure in which an amorphous silicon layer and a polycrystalline silicon layer are arranged in layers, so that the absorption advantages of the amorphous silicon layer and the polycrystalline silicon layer for light of different wavelengths can be combined, and the light absorption efficiency of the intrinsic semiconductor layer can be effectively improved, so that the intrinsic semiconductor layer can achieve a higher photoelectric conversion capability, thereby improving the external quantum efficiency and sensitivity of the photoelectric conversion structure.

Description

Technical Field

[0001] The present invention relates to the field of photoelectric conversion technology, and in particular to a photoelectric conversion structure, a manufacturing method thereof, an image sensor and an electronic device. Background Art

[0002] At present, the basic devices for circuit realization of mainstream optical sensors in the market are all PIN devices. Optical sensors have extremely high requirements for photoelectric conversion efficiency, that is, the higher the photoelectric conversion efficiency, the better. For PIN devices, the most important film layer affecting the photoelectric conversion efficiency is the I layer in the PIN structure, which is called the intrinsic layer. In order to achieve a higher photoelectric conversion capability, the I layer needs to be thicker. At present, the thickness of the films produced by various manufacturers is basically between 10000A and 13000A. To achieve this thickness, all manufacturers use mature a-Si process technology.

[0003] Due to the limitations of the a-Si process, such as low mobility, in order to achieve accurate and effective photoelectric sensing display, multiple pixels are required to display imaging, so high PPI and high frame rate drive display cannot be achieved. In order to break through this technical barrier, the first solution that comes to mind is to use the low-temperature polycrystalline silicon (LTPS) process. The LTPS process is characterized by the use of laser annealing (ELA) to recrystallize a-Si to form p-Si, achieve high ion mobility, and rely on ion doping technology to achieve N+ / P+ layers, effectively control ion distribution and density, and effectively improve metal contact impedance. PIN devices based on the LTPS process can enhance the signal-to-noise ratio of image sensors, achieve dynamic detection, and have higher integration. However, since the formation of p-Si requires the ELA process, based on this process, it is impossible to form a thicker p-Si layer, which affects the ability to receive and convert photoelectrons. Summary of the invention

[0004] The embodiments of the present invention provide a photoelectric conversion structure, a manufacturing method thereof, an image sensor and an electronic device, so as to improve the photoelectric conversion capability of the photoelectric conversion structure.

[0005] An embodiment of the present invention provides a photoelectric conversion structure, which includes an N-type semiconductor layer, an intrinsic semiconductor layer and a P-type semiconductor layer, wherein the intrinsic semiconductor layer includes an amorphous silicon layer and a polycrystalline silicon layer that are stacked.

[0006] In a possible implementation, in the photoelectric conversion structure provided by an embodiment of the present invention, the N-type semiconductor layer and the P-type semiconductor layer are stacked, the intrinsic semiconductor layer is located between the N-type semiconductor layer and the P-type semiconductor layer, and the amorphous silicon layer and the polycrystalline silicon layer are stacked alternately.

[0007] In a possible implementation, in the photoelectric conversion structure provided by an embodiment of the present invention, the sum of the number of the amorphous silicon layers and the number of the polycrystalline silicon layers is at least 3 layers.

[0008] In a possible implementation, in the photoelectric conversion structure provided by an embodiment of the present invention, the N-type semiconductor layer is disposed in contact with the amorphous silicon layer, and the P-type semiconductor layer is disposed in contact with the amorphous silicon layer.

[0009] In a possible implementation, in the photoelectric conversion structure provided in an embodiment of the present invention, the number of layers of the amorphous silicon layer and the polycrystalline silicon layer are both one layer, the N-type semiconductor layer, the P-type semiconductor layer and the polycrystalline silicon layer are located in the same film layer, and the N-type semiconductor layer and the P-type semiconductor layer are respectively located on opposite sides of the polycrystalline silicon layer, and the amorphous silicon layer is located below the polycrystalline silicon layer.

[0010] In a possible implementation, in the photoelectric conversion structure provided by an embodiment of the present invention, the polycrystalline silicon layer completely wraps the amorphous silicon layer, and the N-type semiconductor layer and the P-type semiconductor layer are not in contact with the amorphous silicon layer.

[0011] In a possible implementation, in the photoelectric conversion structure provided by an embodiment of the present invention, both the N-type semiconductor layer and the P-type semiconductor layer are located on the amorphous silicon layer.

[0012] Correspondingly, an embodiment of the present invention further provides an image sensor, comprising: a substrate, a detection circuit located on the substrate, and a photoelectric conversion structure as described above, which is electrically connected to the detection circuit.

[0013] In a possible implementation, in the image sensor provided by the embodiment of the present invention, the N-type semiconductor layer, the intrinsic semiconductor layer and the P-type semiconductor layer of the photoelectric conversion structure are stacked in sequence, the photoelectric conversion structure is located on the side of the detection circuit away from the substrate, and the N-type semiconductor layer is close to the detection circuit; wherein,

[0014] The photoelectric conversion structure further includes: a first electrode located on a side of the N-type semiconductor layer away from the P-type semiconductor layer, and a second electrode located on a side of the P-type semiconductor layer away from the N-type semiconductor layer;

[0015] The detection circuit includes a signal reading transistor, and the first electrode is electrically connected to a gate of the signal reading transistor.

[0016] In a possible implementation, in the image sensor provided by the embodiment of the present invention, the N-type semiconductor layer and the P-type semiconductor layer of the photoelectric conversion structure are respectively located on opposite sides of the polysilicon layer;

[0017] The detection circuit includes a signal reading transistor, and an active layer of the signal reading transistor is arranged in the same layer as the polysilicon layer.

[0018] In a possible implementation, in the image sensor provided by an embodiment of the present invention, the photoelectric conversion structure further includes: a first electrode and a second electrode which are arranged in the same layer as the source and drain electrodes of the signal reading transistor and are insulated from each other; the first electrode is electrically connected to the N-type semiconductor layer, and the second electrode is electrically connected to the P-type semiconductor layer;

[0019] The first electrode is electrically connected to a gate of the signal reading transistor.

[0020] Correspondingly, an embodiment of the present invention further provides an electronic device, comprising the image sensor as described in any one of the above items.

[0021] Accordingly, an embodiment of the present invention further provides a method for manufacturing a photoelectric conversion structure as described in any one of the above items, comprising:

[0022] An N-type semiconductor layer, an intrinsic semiconductor layer and a P-type semiconductor layer are formed; wherein the intrinsic semiconductor layer comprises an amorphous silicon layer and a polycrystalline silicon layer which are stacked.

[0023] In a possible implementation, in the manufacturing method provided in the embodiment of the present invention, the forming of the N-type semiconductor layer, the intrinsic semiconductor layer and the P-type semiconductor layer specifically includes:

[0024] depositing a first amorphous silicon thin film layer;

[0025] Performing N-type doping on the first amorphous silicon thin film layer to form the N-type semiconductor layer;

[0026] Depositing a second amorphous silicon thin film layer on the N-type semiconductor layer; wherein the thickness of the second amorphous silicon thin film layer is greater than the thickness of the first amorphous silicon thin film layer;

[0027] The second amorphous silicon thin film layer is processed by using an excimer laser annealing process, so that a portion of the second amorphous silicon thin film layer away from the N-type semiconductor layer forms the polycrystalline silicon layer, and a portion of the second amorphous silicon thin film layer close to the N-type semiconductor layer is the amorphous silicon layer;

[0028] Depositing a third amorphous silicon thin film layer on a side of the polysilicon layer away from the N-type semiconductor layer; wherein the thickness of the third amorphous silicon thin film layer is greater than the thickness of the first amorphous silicon thin film layer;

[0029] A P-type doping process is performed on the surface of the third amorphous silicon thin film layer that is away from the N-type semiconductor layer, so that the portion of the third amorphous silicon thin film layer that is away from the N-type semiconductor layer forms the P-type semiconductor layer, and the portion of the third amorphous silicon thin film layer that is close to the N-type semiconductor layer is the amorphous silicon layer.

[0030] In a possible implementation, in the manufacturing method provided in the embodiment of the present invention, the forming of the N-type semiconductor layer, the intrinsic semiconductor layer and the P-type semiconductor layer specifically includes:

[0031] Depositing a first amorphous silicon thin film layer, and patterning the first amorphous silicon thin film layer to form the amorphous silicon layer;

[0032] Depositing a second amorphous silicon thin film layer on the amorphous silicon layer, and treating the second amorphous silicon thin film layer using an excimer laser annealing process to form the polycrystalline silicon thin film layer; wherein the polycrystalline silicon thin film layer completely wraps the amorphous silicon layer;

[0033] Coating a first photoresist layer on the polysilicon thin film layer, and patterning the first photoresist layer to form a first photoresist pattern; wherein the first photoresist pattern exposes one end portion of the polysilicon thin film layer, and the one end portion does not contact the amorphous silicon layer;

[0034] Performing N-type doping on one of the ends to form the N-type semiconductor layer;

[0035] removing the first photoresist pattern;

[0036] Coating a second photoresist layer on the polysilicon thin film layer, and patterning the second photoresist layer to form a second photoresist pattern; wherein the second photoresist pattern exposes another end portion of the polysilicon thin film layer that is arranged opposite to the one end portion, and the other end portion does not contact the amorphous silicon layer;

[0037] Performing P-type doping on the other end to form the P-type semiconductor layer, the remaining polysilicon layer constitutes the polysilicon layer, and the polysilicon layer and the amorphous silicon layer constitute the intrinsic semiconductor layer;

[0038] The second photoresist pattern is removed.

[0039] In a possible implementation, in the manufacturing method provided in the embodiment of the present invention, the forming of the N-type semiconductor layer, the intrinsic semiconductor layer and the P-type semiconductor layer specifically includes:

[0040] Depositing a first amorphous silicon thin film layer, and treating the first amorphous silicon thin film layer using an excimer laser annealing process, so that the first amorphous silicon thin film layer forms the amorphous silicon layer and the polycrystalline silicon thin film layer stacked;

[0041] Coating a first photoresist layer on the polysilicon thin film layer, and patterning the first photoresist layer to form a first photoresist pattern; wherein the first photoresist pattern exposes one end portion of the polysilicon thin film layer;

[0042] Performing N-type doping on one of the ends to form the N-type semiconductor layer located on the amorphous silicon layer;

[0043] removing the first photoresist pattern;

[0044] Coating a second photoresist layer on the polysilicon thin film layer, and patterning the second photoresist layer to form a second photoresist pattern; wherein the second photoresist pattern exposes another end portion of the polysilicon thin film layer that is arranged opposite to the one end portion;

[0045] Performing P-type doping on the other end to form the P-type semiconductor layer located on the amorphous silicon layer, the remaining polycrystalline silicon thin film layer constitutes the polycrystalline silicon layer, and the polycrystalline silicon layer and the amorphous silicon layer constitute the intrinsic semiconductor layer;

[0046] The second photoresist pattern is removed.

[0047] In a possible implementation, in the manufacturing method provided in the embodiment of the present invention, the forming of the N-type semiconductor layer, the intrinsic semiconductor layer and the P-type semiconductor layer specifically includes:

[0048] Depositing a first amorphous silicon thin film layer, and performing thinning processing on opposite sides of the first amorphous silicon thin film layer;

[0049] Using an excimer laser annealing process to process the first amorphous silicon thin film layer after thinning to form a polycrystalline silicon thin film layer and the amorphous silicon layer; wherein the polycrystalline silicon thin film layer completely wraps the amorphous silicon layer;

[0050] Coating a first photoresist layer on the polysilicon thin film layer, and patterning the first photoresist layer to form a first photoresist pattern; wherein the first photoresist pattern exposes one end portion of the polysilicon thin film layer, and the one end portion does not contact the amorphous silicon layer;

[0051] Performing N-type doping on one of the ends to form the N-type semiconductor layer;

[0052] removing the first photoresist pattern;

[0053] Coating a second photoresist layer on the polysilicon thin film layer, and patterning the second photoresist layer to form a second photoresist pattern; wherein the second photoresist pattern exposes another end portion of the polysilicon thin film layer that is arranged opposite to the one end portion, and the other end portion does not contact the amorphous silicon layer;

[0054] Performing P-type doping on the other end to form the P-type semiconductor layer, the remaining polysilicon thin film layer constitutes the polysilicon layer, and the polysilicon layer and the amorphous silicon layer constitute the intrinsic semiconductor layer;

[0055] removing the second photoresist pattern;

[0056] The second photoresist pattern is removed.

[0057] The beneficial effects of the embodiments of the present invention are as follows:

[0058] The embodiment of the present invention provides a photoelectric conversion structure, a manufacturing method thereof, an image sensor and an electronic device, including an N-type semiconductor layer, an intrinsic semiconductor layer and a P-type semiconductor layer, wherein the intrinsic semiconductor layer includes an amorphous silicon layer and a polycrystalline silicon layer arranged in layers. The present invention arranges the intrinsic semiconductor layer into a composite structure in which an amorphous silicon layer and a polycrystalline silicon layer are arranged in layers, so that the absorption advantages of the amorphous silicon layer and the polycrystalline silicon layer for light of different wavelengths can be combined, and the light absorption efficiency of the intrinsic semiconductor layer can be effectively improved, so that the intrinsic semiconductor layer can achieve a higher photoelectric conversion capability, thereby improving the external quantum efficiency and sensitivity of the photoelectric conversion structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 A schematic diagram of a photoelectric conversion structure provided by an embodiment of the present invention;

[0060] Figure 2 A schematic structural diagram of another photoelectric conversion structure provided by an embodiment of the present invention;

[0061] Figure 3 A schematic structural diagram of another photoelectric conversion structure provided by an embodiment of the present invention;

[0062] Figure 4 A schematic structural diagram of another photoelectric conversion structure provided by an embodiment of the present invention;

[0063] Figure 5 This is a schematic diagram comparing the illumination energy-light absorption coefficient of amorphous silicon and polycrystalline silicon;

[0064] Figure 6 A schematic flow chart of a method for manufacturing a photoelectric conversion structure provided by an embodiment of the present invention;

[0065] Figure 7A-7F For the embodiment of the present invention Figure 1 A schematic cross-sectional view of the photoelectric conversion structure after each step shown;

[0066] Figure 8 A schematic flow chart of a method for manufacturing another photoelectric conversion structure provided by an embodiment of the present invention;

[0067] Figure 9A-9I For the embodiment of the present invention Figure 3 A schematic cross-sectional view of the photoelectric conversion structure after each step shown;

[0068] Fig.10 A schematic flow chart of a method for manufacturing another photoelectric conversion structure provided by an embodiment of the present invention;

[0069] Figures 11A-11H For the embodiment of the present invention Figure 4 A schematic cross-sectional view of the photoelectric conversion structure after each step shown;

[0070] Fig.12 A schematic flow chart of a method for manufacturing another photoelectric conversion structure provided by an embodiment of the present invention;

[0071] Figure 13A-13B For the embodiment of the present invention Figure 3 A schematic cross-sectional view of the photoelectric conversion structure after each step shown;

[0072] Fig.14 A schematic diagram of the structure of an image sensor provided by an embodiment of the present invention;

[0073] Fig.15 A schematic diagram of the structure of another image sensor provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0074] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. And in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.

[0075] Unless otherwise defined, the technical terms or scientific terms used in the present invention shall have the usual meanings understood by persons with ordinary skills in the field to which the present invention belongs. The words "include" or "comprise" and the like used in the present invention mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The words "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0076] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, but are only intended to illustrate the content of the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0077] The embodiment of the present invention provides a photoelectric conversion structure, such as Figure 1-Figure 4 As shown, it includes an N-type semiconductor layer 1, an intrinsic semiconductor layer 2 and a P-type semiconductor layer 3, wherein the intrinsic semiconductor layer 2 includes an amorphous silicon layer 21 (a-Si) and a polycrystalline silicon layer 22 (p-Si) which are stacked.

[0078] Specifically, Figure 5 As shown, Figure 5 It is a comparison curve of the light absorption coefficient of a-Si, p-Si, and c-Si under different bands of light (illumination energy), wherein curve A is the illumination energy-light absorption coefficient curve of a-Si, curve B is the illumination energy-light absorption coefficient curve of p-Si, and curve C is the illumination energy-light absorption coefficient curve of c-Si. It can be seen that the light absorption coefficients of a-Si and p-Si are different under different illumination energies. For example, the light absorption coefficient of a-Si is higher in the range greater than 1.8eV, and the light absorption coefficient of p-Si is higher in the range less than 1.8eV. Therefore, the photoelectric conversion structure provided in the embodiment of the present invention, by setting the intrinsic semiconductor layer into a composite structure formed by stacking an amorphous silicon layer and a polycrystalline silicon layer, can combine the absorption advantages of the amorphous silicon layer and the polycrystalline silicon layer for light of different bands respectively, and can effectively improve the light absorption efficiency of the intrinsic semiconductor layer, so that the intrinsic semiconductor layer can achieve a higher photoelectric conversion capability, thereby improving the external quantum efficiency and sensitivity of the photoelectric conversion structure.

[0079] In a specific implementation, in the above-mentioned photoelectric conversion structure provided in the embodiment of the present invention, if Figure 1 and Figure 2As shown, the N-type semiconductor layer 1 and the P-type semiconductor layer 3 are stacked, the intrinsic semiconductor layer 2 is located between the N-type semiconductor layer 1 and the P-type semiconductor layer 3, and the amorphous silicon layer 21 and the polycrystalline silicon layer 22 are stacked alternately, that is, Figure 1 and Figure 2 Each film layer of the photoelectric conversion structure shown is a vertical structure, so that the absorption advantages of the amorphous silicon layer 21 and the polycrystalline silicon layer 22 for light of different wavelengths can be combined to effectively improve the photoelectric conversion capability of the intrinsic semiconductor layer 2 .

[0080] In a specific implementation, in the above-mentioned photoelectric conversion structure provided in the embodiment of the present invention, if Figure 1 and Figure 2 As shown, the sum of the number of amorphous silicon layers 21 and polycrystalline silicon layers 22 is at least 3 layers. Figure 1 As shown, the sum of the number of amorphous silicon layers 21 and polycrystalline silicon layers 22 is 3 layers; Figure 2 As shown, the sum of the number of amorphous silicon layers 21 and polycrystalline silicon layers 22 is 5. Of course, the embodiment of the present invention does not specifically limit the sum of the number of amorphous silicon layers 21 and polycrystalline silicon layers 22. For different numbers of stacked layers, the photoelectric conversion principle and implementation method are the same.

[0081] In a specific implementation, in the above-mentioned photoelectric conversion structure provided in the embodiment of the present invention, if Figure 1 and Figure 2 As shown, the N-type semiconductor layer 1 is arranged in contact with the amorphous silicon layer 21, and the P-type semiconductor layer 3 is arranged in contact with the amorphous silicon layer 21. In this way, when manufacturing the polycrystalline silicon layer 22, a thicker amorphous silicon material film layer can be deposited, and the amorphous silicon material film layer is laser annealed to form a polycrystalline silicon layer 22 of a certain thickness on the surface of the amorphous silicon material film layer, and the remaining part is the amorphous silicon layer 21; when manufacturing the P-type semiconductor layer 3, a thicker amorphous silicon material film layer can be deposited, and the amorphous silicon material film layer is P-type doped to form a P-type semiconductor layer 3 of a certain thickness on the surface of the amorphous silicon material film layer, and the remaining part is the amorphous silicon layer 21.

[0082] In a specific implementation, in the above-mentioned photoelectric conversion structure provided in the embodiment of the present invention, if Figure 3 and Figure 4 As shown, the number of layers of the amorphous silicon layer 21 and the polycrystalline silicon layer 22 are both one layer, the N-type semiconductor layer 1, the P-type semiconductor layer 3 and the polycrystalline silicon layer 22 are located in the same film layer, and the N-type semiconductor layer 1 and the P-type semiconductor layer 3 are located on opposite sides of the polycrystalline silicon layer 22, respectively, and the amorphous silicon layer 21 is located below the polycrystalline silicon layer 22, that is, Figure 3 and Figure 4 The film layers of the photoelectric conversion structure shown are horizontal structures, which can also combine the absorption advantages of the amorphous silicon layer 21 and the polycrystalline silicon layer 22 for light of different wavelengths, and effectively improve the photoelectric conversion capability of the intrinsic semiconductor layer 2 .

[0083] In a specific implementation, in the above-mentioned photoelectric conversion structure provided in the embodiment of the present invention, if Figure 3 As shown, the polysilicon layer 22 completely wraps the amorphous silicon layer 21 , and the N-type semiconductor layer 1 and the P-type semiconductor layer 3 are not in contact with the amorphous silicon layer 21 .

[0084] In a specific implementation, in the above-mentioned photoelectric conversion structure provided in the embodiment of the present invention, if Figure 4 As shown, both the N-type semiconductor layer 1 and the P-type semiconductor layer 3 are located on the amorphous silicon layer 21 .

[0085] Based on the same inventive concept, an embodiment of the present invention further provides a method for manufacturing a photoelectric conversion structure as described above, comprising:

[0086] An N-type semiconductor layer, an intrinsic semiconductor layer and a P-type semiconductor layer are formed; wherein the intrinsic semiconductor layer comprises an amorphous silicon layer and a polycrystalline silicon layer which are stacked.

[0087] The method for manufacturing a photoelectric conversion structure provided in an embodiment of the present invention manufactures a composite structure composed of a stacked amorphous silicon layer and a polycrystalline silicon layer as an intrinsic semiconductor layer. In this way, the absorption advantages of the amorphous silicon layer and the polycrystalline silicon layer for light of different wavelengths can be combined, and the light absorption efficiency of the intrinsic semiconductor layer can be effectively improved, so that the intrinsic semiconductor layer can achieve a higher photoelectric conversion capability, thereby improving the external quantum efficiency and sensitivity of the photoelectric conversion structure.

[0088] In a specific implementation, in the above-mentioned manufacturing method provided in the embodiment of the present invention, an N-type semiconductor layer, an intrinsic semiconductor layer and a P-type semiconductor layer are formed, such as Figure 6 As shown, it may specifically include:

[0089] S601, depositing a first amorphous silicon thin film layer;

[0090] Specifically, Fig. 7A As shown, a first amorphous silicon thin film layer 1' is deposited, and the thickness of the first amorphous silicon thin film layer 1' may be 500 angstroms to 1000 angstroms.

[0091] S602, performing N-type doping on the first amorphous silicon thin film layer to form an N-type semiconductor layer;

[0092] Specifically, Figure 7B As shown, Fig. 7A The first amorphous silicon thin film layer 1 ′ is N-type doped (as indicated by the arrow) to form an N-type semiconductor layer 1 .

[0093] S603, depositing a second amorphous silicon thin film layer on the N-type semiconductor layer; wherein the thickness of the second amorphous silicon thin film layer is greater than the thickness of the first amorphous silicon thin film layer;

[0094] Specifically, Figure 7C As shown, a second amorphous silicon thin film layer 2' is deposited on the N-type semiconductor layer 1; wherein the thickness of the second amorphous silicon thin film layer 2' is greater than 1000 angstroms.

[0095] S604, using an excimer laser annealing process to process the second amorphous silicon thin film layer, so that a portion of the second amorphous silicon thin film layer away from the N-type semiconductor layer forms a polycrystalline silicon layer, and a portion of the second amorphous silicon thin film layer close to the N-type semiconductor layer forms an amorphous silicon layer;

[0096] Specifically, Fig.7D As shown, the second amorphous silicon thin film layer 2' is processed by using an excimer laser annealing process (ELA) so that the portion of the second amorphous silicon thin film layer 2' away from the N-type semiconductor layer 1 forms a polycrystalline silicon layer 22, and the portion of the second amorphous silicon thin film layer 2' close to the N-type semiconductor layer 1 is an amorphous silicon layer 21. Specifically, the second amorphous silicon thin film layer 2' can be partially converted into a polycrystalline silicon layer 22 by controlling the laser energy.

[0097] S605, depositing a third amorphous silicon thin film layer on a side of the polysilicon layer away from the N-type semiconductor layer; wherein the thickness of the third amorphous silicon thin film layer is greater than the thickness of the first amorphous silicon thin film layer;

[0098] Specifically, Fig. 7E As shown, a third amorphous silicon thin film layer 2" is deposited on the side of the polysilicon layer 22 away from the N-type semiconductor layer 1; wherein the thickness of the third amorphous silicon thin film layer 2" is greater than 1000 angstroms.

[0099] S606, performing a P-type doping process on a surface of the third amorphous silicon thin film layer away from the N-type semiconductor layer, so that a portion of the third amorphous silicon thin film layer away from the N-type semiconductor layer forms a P-type semiconductor layer, and a portion of the third amorphous silicon thin film layer close to the N-type semiconductor layer is an amorphous silicon layer;

[0100] Specifically, Figure 7F As shown, a P-type doping process (indicated by the arrow) is performed on the surface of the third amorphous silicon thin film layer 2" that is away from the N-type semiconductor layer 1, so that the portion of the third amorphous silicon thin film layer 2" that is away from the N-type semiconductor layer 1 forms a P-type semiconductor layer 3, and the portion of the third amorphous silicon thin film layer 2" close to the N-type semiconductor layer 1 is an amorphous silicon layer 21. Specifically, the third amorphous silicon thin film layer 2" can be partially converted into a P-type semiconductor layer 3 by controlling the laser energy.

[0101] Therefore, through Figure 7A to Figure 7F The embodiment of the present invention can be made Figure 1 The photoelectric conversion structure shown.

[0102] Specifically, Figure 2The structure shown can be found in Fig. 7E Based on the results shown in the figure, an excimer laser annealing process (ELA) is used to Fig. 7E The third amorphous silicon thin film layer 2" shown is processed so that the portion of the third amorphous silicon thin film layer 2" away from the N-type semiconductor layer 1 forms a polycrystalline silicon layer 22, and the portion of the third amorphous silicon thin film layer 2" close to the N-type semiconductor layer 1 is an amorphous silicon layer 21. Then, a fourth amorphous silicon thin film layer is deposited on the side of the polycrystalline silicon layer 22 away from the N-type semiconductor layer 1; wherein the thickness of the fourth amorphous silicon thin film layer is greater than 1000 angstroms. Finally, a P-type doping process (indicated by the arrow) is performed on the surface of the fourth amorphous silicon thin film layer that is away from the N-type semiconductor layer 1, so that the portion of the fourth amorphous silicon thin film layer that is away from the N-type semiconductor layer 1 forms a P-type semiconductor layer 3, and the portion of the fourth amorphous silicon thin film layer close to the N-type semiconductor layer 1 is an amorphous silicon layer 21. Specifically, the fourth amorphous silicon thin film layer can be partially converted into a P-type semiconductor layer 3 by controlling the laser energy.

[0103] Specifically, Figure 1 The intrinsic semiconductor layer 2 in the example is three layers. Figure 2 The intrinsic semiconductor layer 2 in the example is 5 layers. When the number of the intrinsic semiconductor layer 2 is greater, such as 7 layers, 9 layers, etc., steps S603 and S604 can be repeated.

[0104] In a specific implementation, in the above-mentioned manufacturing method provided in the embodiment of the present invention, an N-type semiconductor layer, an intrinsic semiconductor layer and a P-type semiconductor layer are formed, such as Figure 8 As shown, it may specifically include:

[0105] S801, depositing a first amorphous silicon thin film layer, and patterning the first amorphous silicon thin film layer to form an amorphous silicon layer;

[0106] Specifically, Fig.9A As shown, a first amorphous silicon thin film layer 1' is deposited, a photoresist layer is coated on the first amorphous silicon thin film layer 1', and the photoresist layer is patterned to form a photoresist pattern 10; as shown Fig. 9B As shown, the first amorphous silicon thin film layer 1 ′ is patterned using the photoresist pattern 10 as a mask to form an amorphous silicon layer 21 .

[0107] S802, depositing a second amorphous silicon thin film layer on the amorphous silicon layer, and treating the second amorphous silicon thin film layer using an excimer laser annealing process to form a polycrystalline silicon layer; wherein the polycrystalline silicon layer completely wraps the amorphous silicon layer;

[0108] Specifically, Fig. 9CAs shown, a second amorphous silicon thin film layer 2 ′ is deposited on the amorphous silicon layer 21 , and the second amorphous silicon thin film layer 2 ′ is processed using an excimer laser annealing process (ELA) to form a polycrystalline silicon layer 22 ; wherein the polycrystalline silicon layer 22 completely wraps the amorphous silicon layer 21 .

[0109] S803, coating a first photoresist layer on the polysilicon layer, and patterning the first photoresist layer to form a first photoresist pattern; wherein the first photoresist pattern exposes one end portion of the polysilicon layer, and one end portion is not in contact with the amorphous silicon layer;

[0110] Specifically, Fig.9D As shown, a first photoresist layer is coated on the polysilicon layer 22, and the first photoresist layer is patterned to form a first photoresist pattern 20; wherein the first photoresist pattern 20 exposes one end 221 of the polysilicon layer 22, and one end 221 is not in contact with the amorphous silicon layer 21.

[0111] S804, performing N-type doping on one of the ends to form an N-type semiconductor layer;

[0112] Specifically, Fig.9E As shown, Fig.9D One of the ends 221 is N-type doped (as indicated by the arrow) to form an N-type semiconductor layer 1.

[0113] S805, removing the first photoresist pattern;

[0114] Specifically, Fig.9F As shown, the first photoresist pattern 20 is removed.

[0115] S806, coating a second photoresist layer on the polysilicon layer, and patterning the second photoresist layer to form a second photoresist pattern; wherein the second photoresist pattern exposes another end portion of the polysilicon layer that is arranged opposite to one of the end portions, and the other end portion is not in contact with the amorphous silicon layer;

[0116] Specifically, Figure 9G As shown, a second photoresist layer is coated on the polysilicon layer 22, and the second photoresist layer is patterned to form a second photoresist pattern 30; wherein the second photoresist pattern 30 exposes another end 222 of the polysilicon layer 22 that is arranged opposite to one of the end portions 221, and the other end 222 does not contact the amorphous silicon layer 21.

[0117] S807, performing P-type doping on the other end to form a P-type semiconductor layer, and the remaining polycrystalline silicon layer and the amorphous silicon layer constitute an intrinsic semiconductor layer;

[0118] Specifically, Figure 9HAs shown, the other end 222 is P-type doped (indicated by the arrow) to form a P-type semiconductor layer 3, and the remaining polycrystalline silicon layer 22 and the amorphous silicon layer 21 constitute an intrinsic semiconductor layer 2.

[0119] S808, removing the second photoresist pattern;

[0120] Specifically, Fig.9I As shown, the second photoresist pattern 30 is removed to form Figure 3 The photoelectric conversion structure shown.

[0121] Therefore, through FIG. 9A to FIG. 9I The embodiment of the present invention can be made Figure 3 The photoelectric conversion structure shown.

[0122] In a specific implementation, in the above-mentioned manufacturing method provided in the embodiment of the present invention, an N-type semiconductor layer, an intrinsic semiconductor layer and a P-type semiconductor layer are formed, such as Fig.10 As shown, it may specifically include:

[0123] S1001, depositing a first amorphous silicon thin film layer, and treating the first amorphous silicon thin film layer using an excimer laser annealing process, so that the first amorphous silicon thin film layer forms an amorphous silicon layer and a polycrystalline silicon thin film layer stacked;

[0124] Specifically, Fig.11A As shown, a first amorphous silicon thin film layer 1' is deposited; Fig. 11B As shown, the first amorphous silicon thin film layer 1' is processed by using an excimer laser annealing process (ELA) so that the first amorphous silicon thin film layer 1' forms an amorphous silicon layer 21 and a polycrystalline silicon thin film layer 22' which are stacked.

[0125] S1002, coating a first photoresist layer on the polysilicon thin film layer, and patterning the first photoresist layer to form a first photoresist pattern; wherein the first photoresist pattern exposes one end portion of the polysilicon thin film layer;

[0126] Specifically, Fig. 11C As shown, a first photoresist layer is coated on the polysilicon thin film layer 22', and the first photoresist layer is patterned to form a first photoresist pattern 20; wherein the first photoresist pattern 20 exposes one end 221 of the polysilicon thin film layer 22'.

[0127] S1003, performing N-type doping on one of the ends to form an N-type semiconductor layer located on the amorphous silicon layer;

[0128] Specifically, Fig.11D As shown, Fig. 11COne of the ends 221 is N-type doped (as indicated by the arrow) to form an N-type semiconductor layer 1 located on the amorphous silicon layer 21 .

[0129] S1004, removing the first photoresist pattern;

[0130] Specifically, Fig.11E As shown, the first photoresist pattern 20 is removed.

[0131] S1005, coating a second photoresist layer on the polysilicon thin film layer, and patterning the second photoresist layer to form a second photoresist pattern; wherein the second photoresist pattern exposes another end portion of the polysilicon thin film layer that is arranged opposite to one of the end portions;

[0132] Specifically, Fig.11F As shown, a second photoresist layer is coated on the polysilicon film layer 22' and patterned to form a second photoresist pattern 30; wherein the second photoresist pattern 30 exposes another end 222 of the polysilicon film layer 22' that is arranged opposite to one end 221.

[0133] S1006, performing P-type doping on the other end to form a P-type semiconductor layer located on the amorphous silicon layer, the remaining polycrystalline silicon thin film layer constitutes a polycrystalline silicon layer, and the polycrystalline silicon layer and the amorphous silicon layer constitute an intrinsic semiconductor layer;

[0134] Specifically, Fig.11G As shown, Fig.11F The other end 222 is doped with P type (as shown by the arrow) to form a P type semiconductor layer 3 located on the amorphous silicon 21 layer, and the remaining polycrystalline silicon thin film layer constitutes the polycrystalline silicon layer 22, and the polycrystalline silicon layer 22 and the amorphous silicon layer 21 constitute the intrinsic semiconductor layer 2.

[0135] S1007, removing the second photoresist pattern;

[0136] Specifically, Fig.11H As shown, the second photoresist pattern 30 is removed.

[0137] Therefore, through Figures 11A to 11H The embodiment of the present invention can be made Figure 4 The photoelectric conversion structure shown.

[0138] In a specific implementation, in the above-mentioned manufacturing method provided in the embodiment of the present invention, an N-type semiconductor layer, an intrinsic semiconductor layer and a P-type semiconductor layer are formed, such as Fig.12 As shown, it may specifically include:

[0139] S1201, depositing a first amorphous silicon thin film layer, and performing thinning processing on opposite sides of the first amorphous silicon thin film layer;

[0140] Specifically, Fig.13A As shown, a first amorphous silicon thin film layer 1' is deposited, and the thickness of the first amorphous silicon thin film layer 1' is greater than 1000 angstroms; Fig. 13B As shown, two opposite sides of the first amorphous silicon thin film layer 1' are thinned (by using a photolithography process).

[0141] S1202, using an excimer laser annealing process to process the first amorphous silicon thin film layer after the thinning process to form a polycrystalline silicon layer and an amorphous silicon layer; wherein the polycrystalline silicon layer completely wraps the amorphous silicon layer;

[0142] Specifically, the first amorphous silicon thin film layer 1' after thinning is processed by using an excimer laser annealing process (ELA) to form a polycrystalline silicon thin film layer 22' and an amorphous silicon layer 21; wherein the polycrystalline silicon thin film layer 22' completely wraps the amorphous silicon layer 21, such as Fig. 9C shown.

[0143] S1203, coating a first photoresist layer on the polysilicon thin film layer, and patterning the first photoresist layer to form a first photoresist pattern; wherein the first photoresist pattern exposes one end portion of the polysilicon thin film layer, and one end portion is not in contact with the amorphous silicon layer;

[0144] Specifically, Fig.9D As shown, a first photoresist layer is coated on the polysilicon film layer 22', and the first photoresist layer is patterned to form a first photoresist pattern 20; wherein the first photoresist pattern 20 exposes one end 221 of the polysilicon film layer 22', and one end 221 is not in contact with the amorphous silicon layer 21.

[0145] S1204, performing N-type doping on one of the ends to form an N-type semiconductor layer;

[0146] Specifically, Fig.9E As shown, Fig.9D One of the ends 221 is N-type doped (as indicated by the arrow) to form an N-type semiconductor layer 1.

[0147] S1205, removing the first photoresist pattern;

[0148] Specifically, Fig.9F As shown, the first photoresist pattern 20 is removed.

[0149] S1206, coating a second photoresist layer on the polysilicon thin film layer, and patterning the second photoresist layer to form a second photoresist pattern; wherein the second photoresist pattern exposes another end 222 of the polysilicon thin film layer that is arranged opposite to one of the end portions 221, and the other end 222 is not in contact with the amorphous silicon layer 21;

[0150] Specifically, Figure 9G As shown, a second photoresist layer is coated on the polysilicon thin film layer 22', and the second photoresist layer is patterned to form a second photoresist pattern 30; wherein the second photoresist pattern 30 exposes another end 222 of the polysilicon thin film layer 22' that is arranged opposite to one of the end portions 221, and the other end 222 is not in contact with the amorphous silicon layer 21;

[0151] S1207, performing P-type doping on the other end to form a P-type semiconductor layer, the remaining polysilicon thin film layer constitutes a polysilicon layer, and the polysilicon layer and the amorphous silicon layer constitute an intrinsic semiconductor layer;

[0152] Specifically, Figure 9H As shown, Figure 9G The other end 222 is doped with P type (as indicated by the arrow) to form a P type semiconductor layer 3, and the remaining polycrystalline silicon thin film layer 22' constitutes a polycrystalline silicon layer 22, and the polycrystalline silicon layer 22 and the amorphous silicon layer 21 constitute an intrinsic semiconductor layer 2.

[0153] S1208, removing the second photoresist pattern;

[0154] Specifically, Fig.9I As shown, the second photoresist pattern 30 is removed.

[0155] Therefore, through Fig.13A , Fig. 13B , FIG. 9C to FIG. 9I The embodiment of the present invention can also be made Figure 3 The photoelectric conversion structure shown.

[0156] It should be noted that, in the embodiment of the present invention, the first photoresist pattern and the second photoresist pattern can be removed by an ashing process.

[0157] Based on the same inventive concept, an embodiment of the present invention further provides an image sensor, such as Fig.14 and Fig.15 As shown, it includes: a base substrate 100, a detection circuit 200 located on the base substrate 100, and a photoelectric conversion structure (such as any one of the above items) electrically connected to the detection circuit 200. Fig.14 China-Israel Figure 1 Taking the photoelectric conversion structure shown in the figure as an example, Fig.15 China-Israel Figure 3 As the principle of solving the problem of the image sensor is similar to that of the aforementioned photoelectric conversion structure, the implementation of the image sensor can refer to the implementation of the aforementioned photoelectric conversion structure, and the repeated parts will not be repeated.

[0158] In a specific implementation, in the above-mentioned image sensor provided by the embodiment of the present invention, if Fig.14 As shown, the N-type semiconductor layer 1, the intrinsic semiconductor layer 2 and the P-type semiconductor layer 3 of the photoelectric conversion structure are stacked in sequence, and the photoelectric conversion structure is located on the side of the detection circuit (one of the signal reading transistors 200 is shown, which will be described later) away from the substrate 100, and the N-type semiconductor layer 1 is close to the detection circuit 200; wherein,

[0159] The photoelectric conversion structure further includes: a first electrode 41 located on a side of the N-type semiconductor layer 1 away from the P-type semiconductor layer 3, and a second electrode 42 located on a side of the P-type semiconductor layer 3 away from the N-type semiconductor layer 1;

[0160] The detection circuit includes a signal reading transistor 200 , and the first electrode 41 is electrically connected to a gate 201 of the signal reading transistor 200 .

[0161] Specifically, Fig.14As shown, the image sensor also includes: a buffer layer 300 located between the base substrate 100 and the signal reading transistor 200, a planar layer 400 located on the side of the second electrode 42 away from the base substrate 100, a wiring layer 500 located on the side of the planar layer 400 away from the base substrate 100, and a passivation layer 600 located on the side of the wiring layer 500 away from the base substrate 100; wherein the wiring layer 500 is electrically connected to the second electrode 42 through a via hole penetrating the planar layer 400, and the wiring layer 500 is configured to input a bias voltage to the second electrode 42. The signal reading transistor 200 further includes: an active layer 202 located between the buffer layer 300 and the gate 201, and a source 203 and a drain 204 arranged in the same layer as the first electrode 41. In this way, it is only necessary to change the original patterning pattern when forming the source 203 and the drain 204, and the pattern of the first electrode 41 and the source 203 and the drain 204 can be formed through a single patterning process, without adding a process for preparing the first electrode 41 separately, which can simplify the preparation process flow, save production costs, and improve production efficiency. The image sensor also includes: a gate insulating layer 700 located between the active layer 202 and the gate 201, and an interlayer insulating layer 800 located between the gate 201 and the first electrode 41. The first electrode 41 is electrically connected to the gate 201 through a via hole penetrating the interlayer insulating layer 800, and the source 203 and the drain 204 are electrically connected to the active layer 202 through via holes penetrating the interlayer insulating layer 800 and the gate insulating layer 700. For example, when the image sensor provided by the embodiment of the present invention is applied to fingerprint recognition, during operation, a deflection voltage is loaded to the second electrode 42 through the wiring layer 500, and the photoelectric conversion structure converts the received optical signal into an electrical signal, which is transmitted to the gate 201 of the signal reading transistor 200 through the second electrode 42, thereby controlling the degree of opening of the signal reading transistor 200. The intensity of the optical signal received by the photoelectric conversion structure is different, and the corresponding degree of opening of the signal reading transistor 200 is different, and then the detection signal output by the detected signal reading transistor 200 is different, thereby performing fingerprint recognition.

[0162] In a specific implementation, in the above-mentioned image sensor provided by the embodiment of the present invention, if Fig.15 As shown, the N-type semiconductor layer 1 and the P-type semiconductor layer 3 of the photoelectric conversion structure are respectively located on opposite sides of the polysilicon layer 22;

[0163] The detection circuit includes a signal reading transistor (not shown) and a signal detection transistor 900. The active layer of the signal reading transistor and the active layer 901 of the signal detection transistor 900 are arranged in the same layer as the polysilicon layer 22. In this way, it is only necessary to change the original patterning pattern when forming the active layer 901, and the pattern of the polysilicon layer 22 and the active layer 901 can be formed through a single patterning process, without adding a process for preparing the polysilicon layer 22 separately, which can simplify the preparation process, save production costs, and improve production efficiency. Specifically, after the amorphous silicon layer 21 is formed, an amorphous silicon thin film layer is deposited on the side of the amorphous silicon layer 21 facing away from the substrate 100, and the amorphous silicon thin film layer is patterned to form a first amorphous silicon thin film layer completely wrapping the amorphous silicon layer 21 on the amorphous silicon layer 21, and a second amorphous silicon thin film layer is formed in the area corresponding to the active layer. First, one end of the first amorphous silicon thin film layer and the second amorphous silicon thin film layer is simultaneously doped with N-type, and one end of the first amorphous silicon thin film layer forms an N-type semiconductor layer 1, and one end of the second amorphous silicon thin film layer forms an N-type conductor region 9011; then, the other ends of the first amorphous silicon thin film layer and the second amorphous silicon thin film layer are simultaneously doped with P-type, and the other end of the first amorphous silicon thin film layer forms a P-type semiconductor layer 3, and the other end of the second amorphous silicon thin film layer forms a P-type conductor region 9012, thereby forming an active layer 901.

[0164] In a specific implementation, in the above-mentioned image sensor provided by the embodiment of the present invention, if Fig.15 As shown, the photoelectric conversion structure further includes: a first electrode 41 and a second electrode 42 which are arranged in the same layer as the source-drain electrode of the signal reading transistor and the source-drain electrode (source 903 and drain 904) of the signal detection transistor 900 and are insulated from each other; the first electrode 41 is electrically connected to the N-type semiconductor layer 1, and the second electrode 42 is electrically connected to the P-type semiconductor layer 3;

[0165] The first electrode 41 is electrically connected to the gate of the signal reading transistor (not shown). Specifically, the electrical connection between the first electrode 41 and the gate of the signal reading transistor (not shown) can be achieved by punching and routing.

[0166] Specifically, the film layer having the same function in the signal reading transistor and the signal detecting transistor 900 is arranged in the same layer. Fig.15 The signal detection transistor 900 is used for schematic illustration.

[0167] Specifically, Fig.15As shown, the image sensor further includes: a buffer layer 300 located between the substrate 100 and the signal detection transistor 900, a flat layer 400 located on the side of the second electrode 42 away from the substrate 100, and a passivation layer 600 located on the side of the flat layer 400 away from the substrate 100. The signal reading transistor 200 further includes: an active layer 901 located between the buffer layer 300 and the source-drain electrode (903 and 904), and a gate 902 located between the active layer 902 and the source-drain electrode (903 and 904). The image sensor further includes: a gate insulating layer 700 located between the active layer 901 and the gate 902, and an interlayer insulating layer 800 located between the gate 2902 and the first electrode 41, and the source-drain electrode (903 and 904) is electrically connected to the active layer 901 through a via hole penetrating the interlayer insulating layer 800 and the gate insulating layer 700. For example, when the image sensor provided by the embodiment of the present invention is applied to fingerprint recognition, during operation, by loading a deflection voltage to the second electrode 42, the photoelectric conversion structure converts the received light signal into an electrical signal, which is transmitted to the gate of the signal reading transistor (not shown) through the second electrode 42 to control the degree of opening of the signal reading transistor. The intensity of the light signal received by the photoelectric conversion structure is different, and the corresponding degree of opening of the signal reading transistor is different, and then the detection signal output by the detected signal reading transistor is different, thereby performing fingerprint recognition.

[0168] In summary, the embodiments of the present invention are designed Figure 1 to Figure 4 The several photoelectric conversion structures shown integrate amorphous silicon layers and polycrystalline silicon layers as intrinsic semiconductor layers of the photoelectric conversion structure, combining the absorption advantages of amorphous silicon layers and polycrystalline silicon layers for light of different wavelengths, which can greatly improve the photoelectric conversion efficiency. And combined with the LTPS TFT structure and process, it can realize active image sensors with high external quantum efficiency and large signal volume, as well as active image sensors with high sensitivity and high signal-to-noise ratio.

[0169] Based on the same inventive concept, an embodiment of the present invention further provides an electronic device, including the above-mentioned image sensor provided by an embodiment of the present invention. Since the principle of solving the problem by the electronic device is similar to that of the above-mentioned photoelectric conversion structure, the implementation of the vibration device can refer to the implementation of the above-mentioned photoelectric conversion structure, and the repeated parts will not be repeated.

[0170] The electronic device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the electronic device should be understood by ordinary technicians in the field, and will not be described in detail here, nor should they be used as limitations of the present invention.

[0171] The embodiments of the present invention provide a photoelectric conversion structure, a manufacturing method thereof, an image sensor and an electronic device. By configuring the intrinsic semiconductor layer to be a composite structure composed of amorphous silicon layers and polycrystalline silicon layers, the absorption advantages of the amorphous silicon layer and the polycrystalline silicon layer for light of different wavelengths can be combined, and the light absorption efficiency of the intrinsic semiconductor layer can be effectively improved, so that the intrinsic semiconductor layer can achieve a higher photoelectric conversion capability, thereby improving the external quantum efficiency and sensitivity of the photoelectric conversion structure.

[0172] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0173] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A photoelectric conversion structure, characterized in that: It includes an N-type semiconductor layer, an intrinsic semiconductor layer and a P-type semiconductor layer, wherein the intrinsic semiconductor layer includes an amorphous silicon layer and a polycrystalline silicon layer which are stacked; The number of layers of the amorphous silicon layer and the polycrystalline silicon layer are both one layer, the N-type semiconductor layer, the P-type semiconductor layer and the polycrystalline silicon layer are located in the same film layer, and the N-type semiconductor layer and the P-type semiconductor layer are respectively located on opposite sides of the polycrystalline silicon layer, and the amorphous silicon layer is located below the polycrystalline silicon layer; The polysilicon layer completely wraps the amorphous silicon layer, and the N-type semiconductor layer and the P-type semiconductor layer are not in contact with the amorphous silicon layer.

2. An image sensor, characterized in that: include: A substrate, a detection circuit located on the substrate, and the photoelectric conversion structure according to claim 1 electrically connected to the detection circuit.

3. The image sensor according to claim 2, wherein: The N-type semiconductor layer and the P-type semiconductor layer of the photoelectric conversion structure are respectively located on two opposite sides of the polysilicon layer; The detection circuit includes a signal reading transistor, and an active layer of the signal reading transistor is arranged in the same layer as the polysilicon layer.

4. The image sensor according to claim 3, wherein: The photoelectric conversion structure further includes: a first electrode and a second electrode which are arranged in the same layer as the source and drain electrodes of the signal reading transistor and are insulated from each other; the first electrode is electrically connected to the N-type semiconductor layer, and the second electrode is electrically connected to the P-type semiconductor layer; The first electrode is electrically connected to a gate of the signal reading transistor.

5. An electronic device, characterized in that: Comprising the image sensor as described in any one of claims 2-4.

6. A method for manufacturing the photoelectric conversion structure according to claim 1, characterized in that: include: Depositing a first amorphous silicon thin film layer, and patterning the first amorphous silicon thin film layer to form the amorphous silicon layer; Depositing a second amorphous silicon thin film layer on the amorphous silicon layer, and treating the second amorphous silicon thin film layer using an excimer laser annealing process to form the polycrystalline silicon thin film layer; wherein the polycrystalline silicon thin film layer completely wraps the amorphous silicon layer; Coating a first photoresist layer on the polysilicon thin film layer, and patterning the first photoresist layer to form a first photoresist pattern; wherein the first photoresist pattern exposes one end portion of the polysilicon thin film layer, and the one end portion does not contact the amorphous silicon layer; Performing N-type doping on one of the ends to form the N-type semiconductor layer; removing the first photoresist pattern; Coating a second photoresist layer on the polysilicon thin film layer, and patterning the second photoresist layer to form a second photoresist pattern; wherein the second photoresist pattern exposes another end portion of the polysilicon thin film layer that is arranged opposite to the one end portion, and the other end portion does not contact the amorphous silicon layer; Performing P-type doping on the other end to form the P-type semiconductor layer, the remaining polysilicon layer constitutes the polysilicon layer, and the polysilicon layer and the amorphous silicon layer constitute the intrinsic semiconductor layer; The second photoresist pattern is removed.

7. A method for manufacturing the photoelectric conversion structure according to claim 1, characterized in that: include: Depositing a first amorphous silicon thin film layer, and performing thinning processing on opposite sides of the first amorphous silicon thin film layer; Using an excimer laser annealing process to process the first amorphous silicon thin film layer after thinning to form a polycrystalline silicon thin film layer and the amorphous silicon layer; wherein the polycrystalline silicon thin film layer completely wraps the amorphous silicon layer; Coating a first photoresist layer on the polysilicon thin film layer, and patterning the first photoresist layer to form a first photoresist pattern; wherein the first photoresist pattern exposes one end portion of the polysilicon thin film layer, and the one end portion does not contact the amorphous silicon layer; Performing N-type doping on one of the ends to form the N-type semiconductor layer; removing the first photoresist pattern; Coating a second photoresist layer on the polysilicon thin film layer, and patterning the second photoresist layer to form a second photoresist pattern; wherein the second photoresist pattern exposes another end portion of the polysilicon thin film layer that is arranged opposite to the one end portion, and the other end portion does not contact the amorphous silicon layer; Performing P-type doping on the other end to form the P-type semiconductor layer, the remaining polysilicon thin film layer constitutes the polysilicon layer, and the polysilicon layer and the amorphous silicon layer constitute the intrinsic semiconductor layer; The second photoresist pattern is removed.

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