Memory Controller and Method for Decoding a Memory Device Exiting by Early Hard Decoding

Abstract

The present invention discloses a method and apparatus for decoding. The method includes: receiving a first forward error correction (FEC) block of read values; starting a hard decoding process, wherein the number of parity node failures is identified; and during the hard decoding process, comparing the identified number of parity node failures with a decoding threshold. When the identified number of parity node failures is not greater than the decoding threshold, the hard decoding process is continued. When the identified number of parity node failures is greater than the decoding threshold, the method includes: stopping the hard decoding process before completing the hard decoding process; generating an output indicating that additional reads are needed; receiving one or more additional FEC blocks of read values, mapping the first FEC block of the read values and the additional FEC blocks of the read values into soft input values; and performing a soft decoding process on the soft input values.

Description

Background Art

[0001] Memory controllers such as flash memory controllers use error correction coding to achieve an acceptable uncorrectable bit error rate (UBER). An "FEC block" is a contiguous block of information that contains digital user information or "data" and associated parity information for protecting the original data against bit errors.

[0002] Various algorithms for decoding data encoded with error correction codes are known in the art. Hard decoding algorithms require only a single value as input for each bit of the original forward error correction (FEC) block and only a single read of the stored FEC block.

[0003] When an incorrect address is read or when the data is highly corrupted, it may lead to a severe failure. In some decoding processes, the number of errors in the first layer of check node processing is used to identify a severe failure. More specifically, when an extremely high number of errors is observed at the end of the processing of the first layer of a hard decoding algorithm, it is determined that a severe failure has occurred. When a severe failure is detected, the decoding is aborted. When the decoding process is aborted, the decoding process stops and an error is reported to the host. At this time, an error recovery process such as redundant array of independent disks (RAID) can be used to attempt to recover the stored data.

[0004] As the flash memory device ages, the raw bit error rate (RBER) increases. When a hard decoding algorithm is used for decoding, at a certain point the RBER increases to the extent that the decoder becomes a system bottleneck, thereby reducing the system output rate. More specifically, the time and number of operations required for the hard decoding process to reach the maximum number of iterations and fail, and the time required to reread the data and perform soft decoding become so significant that the throughput of the flash controller decreases. Although this has been described with respect to flash memory devices and flash memory controllers, this problem is relevant to any memory system that exhibits an increasing RBER.

[0005] Accordingly, there is a need for a method and apparatus that will allow decoding and that will reduce the negative impact caused by the increasing RBER in order to prevent or delay the occurrence of reduced throughput due to hard decoding failure. Summary of the Invention

[0006] A method for decoding is disclosed. The method includes receiving, at a hard input decoding circuit, a first forward error correction (FEC) block of read values (where each bit of the first FEC block of read values represents a corresponding bit of a stored FEC block); and initiating a hard decoding process. The hard decoding process includes variable node processing and check node processing of the first FEC block of read values to identify a number of check node failures. During the hard decoding process, the identified number of check node failures is compared with a decoding threshold. When the identified number of check node failures is not greater than the decoding threshold, the hard decoding process continues. When the identified number of check node failures is greater than the decoding threshold, the method further includes: stopping the hard decoding process before completing the hard decoding process; generating an output indicating that additional reads are needed; receiving, at a mapper, the first FEC block of read values and one or more additional FEC blocks of read values (where each bit of each FEC block of the one or more FEC blocks of read values represents a corresponding bit of a stored FEC block); mapping the first FEC block of read values and the additional FEC blocks of read values to soft input values; and performing a soft decoding process on the soft input values to identify decoded FEC blocks.

[0007] The present invention discloses a memory controller. The memory controller includes an input and output circuit; an encoder configured to encode data received at the input and output circuit into FEC blocks; and a write circuit coupled to the encoder. The write circuit is configured to store the FEC blocks on a memory device. A read circuit is configured to read the stored FEC blocks. A hard input decoding circuit is configured to receive a first FEC block of read values (where each bit of the first FEC block of read values represents a corresponding bit of a stored FEC block) and initiate a hard decoding process. The hard decoding process includes variable node processing and check node processing of the first FEC block of read values to identify a number of check node failures. A decoding controller is coupled to the hard input decoding circuit and is configured to compare the identified number of check node failures with a decoding threshold during the hard decoding process. When the identified number of check node failures is greater than the decoding threshold, the decoding controller is operable to generate an output indicating that the hard input decoding circuit will stop processing the error correction code and generate an output indicating that additional reads are needed. In response to the output indicating that the hard input decoding circuit will stop processing the error correction code, the hard input decoding circuit is operable to stop the hard decoding process before completing the hard decoding process. The memory controller further includes a mapper configured to receive the first FEC block of read values and the additional FEC blocks of read values (in response to the generated output indicating that additional reads are needed) and map the first FEC block of read values and the additional FEC blocks of read values into soft input values. A soft input decoding circuit is coupled to the mapper and is configured to perform a soft decoding process on the soft input values to identify decoded FEC blocks.

[0008] The present invention discloses a decoder, which includes a hard input decoding circuit configured to receive a first FEC block of read values (where each bit of the first FEC block of read values represents a corresponding bit of a stored FEC block) and start a hard decoding process. The hard decoding process includes variable node processing and check node processing of the first FEC block of read values to identify the number of check node failures. A decoding controller is coupled to the hard input decoding circuit and is configured to compare the identified number of check node failures with a decoding threshold during the hard decoding process. When the identified number of check node failures is greater than the decoding threshold, the decoding controller is operable to generate an output indicating that the hard input decoding circuit will stop processing the error correction code, and generate an output indicating that additional reads are required. The hard input decoding circuit is operable (in response to the output indicating that the hard input decoding circuit will stop processing the error correction code) to stop the hard decoding process before completing the hard decoding process. The decoder further includes a mapper configured to receive the first FEC block of read values and additional FEC blocks of read values (in response to the generated output indicating that additional reads are required), and map the first FEC block of read values and the additional FEC blocks of read values into soft input values. A soft input decoding circuit is coupled to the mapper and is configured to perform a soft decoding process on the soft input values to identify the decoded FEC blocks.

[0009] Accordingly, the method and apparatus of the present invention provide early hard decoding exit, which moves the processing out of the hard input decoding circuit before completing the hard decoding process, thereby freeing the hard input decoding circuit for performing decoding operations on other FEC blocks. Thus, the workload for decoding is transferred to the soft input decoding circuit, allowing the workload to be balanced based on the number of check node failures. Accordingly, as the RBER increases, the utilization of the soft input decoder increases. Thus, the method and apparatus of the present invention reduce the negative impact caused by the increase in RBER, thereby delaying the occurrence of throughput reduction caused by hard decoding failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present invention will be explained in more detail below with reference to various examples and the drawings, which are shown in the drawings.

[0011] Figure 1 is a block diagram showing a solid state drive (SSD) coupled to a host device according to an example of the present invention.

[0012] Figure 2 shows a method for decoding an FEC block according to an example of the present invention.

[0013] Figure 3 is a diagram showing the effective throughput characteristics of a typical prior art SSD and the theoretical maximum effective throughput improvement achievable by the method and apparatus of the present invention.

[0014] Figure 4 It is a diagram showing a method of receiving user input for controlling the code rate and decoding threshold according to an example of the present invention.

[0015] Figure 5 It is a diagram showing an exemplary hard input decoding circuit, decoding controller, and code information processor according to an example of the present invention.

[0016] Figure 6 It is a graph showing the frame error rate on the vertical axis and the bit error rate (BERin) of the frames received at the decoder on the horizontal axis, which shows the performance of an exemplary SSD according to an example of the present invention.

[0017] Figure 7 It is a graph showing the average number of iterations on the vertical axis and the bit error rate (BERin) of the frames received at the decoder on the horizontal axis, which shows the performance of an exemplary SSD according to an example of the present invention. Detailed Description

[0018] Those of ordinary skill in the art will recognize that the following description is merely illustrative and not limiting in any way. Those skilled in the art will readily think of other examples.

[0019] Figure 1 A solid state drive (SSD) 20 including a flash memory controller 10 and a flash memory device 12 is shown. The flash memory controller 10 includes an input and output (I / O) circuit 2 coupled to an encoder 3. The encoder 3 is coupled to a write circuit 4. A decoder 11 is coupled to a data storage device 6 and a read circuit 5. The decoder 11 includes a hard input decoding circuit 7, a soft input decoding circuit 8, a decoding controller 9, and a mapper 13. The decoding controller 9 is coupled to each hard input decoding circuit in the hard input decoding circuit 7, each soft input decoding circuit in the soft input decoding circuit 8, the I / O circuit 2, and the mapper 13. The mapper 13 is also coupled to the read circuit 5, the data storage device 6, each soft input decoding circuit in the soft input decoding circuit 8, and a register of the decoder 11 that stores soft read values.

[0020] When a write instruction with associated data to be written is received at the I / O circuit 2 from the host device 16, the encoder 3 encodes the received associated data into FEC blocks using an error correction code with a code rate. The code rate (CR) = data / (data + parity), where data is the amount of user data in bits within the FEC block, and parity is the amount of parity bits added to the FEC block.

[0021] The write circuit 4 is configured to store the FEC blocks received from the encoder 3 on the flash memory device 12. The flash memory device 12 can be any type of non-volatile storage device. In this example, the flash memory device 12 is a NAND device (e.g., single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), or more advanced technology. However, alternatively, the flash memory device 12 can be a NOR device. The read circuit 5, in response to a read command received from the host 16, performs a read operation on the flash memory device 12 by sending a command to the flash memory device 12 indicating the type of read to be performed and the address of the information to be read, and receives the read result. The read circuit 5 sends the result from the read operation to the decoder 11. The read result can be stored in a register within the decoder 11 (e.g., a register in one or more hard input decoding circuits 7) or in the data storage device 6.

[0022] A single read of the stored FEC block (commonly referred to as a "hard read") produces a result commonly referred to as a "hard read value" (e.g., the result from a conventional "read" instruction), and the result can be stored in the corresponding register of the decoder 11 in the form of an FEC block, where a single bit of the hard read value (e.g., "0" or "1") represents the corresponding bit of the stored FEC block.

[0023] The hard input decoding circuit 7 is configured to perform processing of an error correction code algorithm on the hard read value, and the soft input decoding circuit 8 is configured to perform processing of an error correction code algorithm on the soft input value, as will be further described below.

[0024] When the iterative processing of the hard input decoding circuit 7 or the soft input decoding circuit 8 is successful (i.e., in the absence of any check node failures), the decoding controller 9 is configured to identify the stored FEC block, remove the parity bits to obtain the initially stored data, and send the initially stored data to the I / O circuit 2 for output to the host device 16.

[0025] A check node is a processing element that verifies the parity status over multiple binary input values. A correct node will report that the parity of the input values has even parity, while an incorrect node will report odd parity. Error correction codes such as, for example, low-density parity-check (LDPC) error correction codes consist of multiple check nodes, and the decoding process operates to force all check nodes to an even state. Thus, the number of failed (odd parity) check nodes within the LDPC decoder indicates the number of error bits that must be corrected.

[0026] In one example, each hard input decoding circuit 7 at Figure 5coupled to the decoding controller 9 in the manner shown, and includes: a first input coupled to receive the FEC block of the read value; a second input coupled to the decoding controller 9 for receiving an early termination signal; a first output coupled to a corresponding input of the decoding controller 9 for outputting an iteration (layer) number signal indicating the number of iterations and / or layers processed during the current hard decoding process; and a second output for outputting a failed check node count signal indicating the number of check node failures in the decoding operation.

[0027] The mapper 13 includes circuitry and processing logic configured to transfer data from the read circuit 5 to registers (e.g., registers in one or more soft input decoding circuits 8) within the decoder 11 while converting the data into a format required by the soft input decoding circuits 8. Each of the soft input decoding circuits 8 is configured to perform a soft decoding process on the soft input values to identify the decoded FEC block.

[0028] In some examples, the hard input decoding circuit 7 is the same as the soft input decoding circuit 8, the only difference being the type of input fed into the decoding circuit. In other examples, the soft input decoding circuits 8 perform calculations using a higher number of significant digits than the calculations performed by the hard input decoding circuit 7. In another implementation, the hard input decoding circuit 7 performs calculations based on log-likelihood ratio (LLR) values and, prior to processing of the first layer or iteration of the error correction code, assigns a value of -8 (e.g., for bit value "1") or +8 (e.g., for bit value "0") to each hard read value in the hard read values.

[0029] Figure 2 A method 100 for decoding an FEC block according to an example of the present invention is shown. The method 100 may be performed by Figure 1 the device. When a read instruction is received (101), a first read of the FEC block stored in a memory (such as on the flash memory device 12 of the SSD 20) is performed (102). A first forward error correction (FEC) block of the read value is received (103) at the hard input decoding circuit, where each bit of the first FEC block of the read value represents the corresponding bit of the stored FEC block.

[0030] A hard decoding process is started (104), which includes variable node processing and check node processing of the first FEC block of the read value to identify the number of check node failures. In one example of the present invention, each hard input decoding circuit 7 is configured to receive the FEC block of the read value (where each bit of the first FEC block of the read value represents the corresponding bit of the stored FEC block) and start a hard decoding process that includes variable node processing and check node processing of the first FEC block of the read value to identify the number of check node failures.

[0031] During the hard decoding process, the number of identified failed check nodes is compared with a decoding threshold (105). In one example, the hard input decoding circuit 7 includes a register indicating the cumulative number of errors in the decoding process, and the hard input decoding circuit 7 can output a failed check node count signal, as described above with respect to Figure 5 the above, indicating the cumulative number of errors. The decoding controller 9 is configured to compare the number of identified failed check nodes with the decoding threshold during the hard decoding process.

[0032] In an example where the error correction code is a single-layer error correction code, the decoding controller 9 is configured to compare the number of identified failed check nodes in the first iteration of the single-layer error correction code with the decoding threshold (105), and is configured to generate an output indicating that the hard input decoding circuit will stop processing the error correction code when the number of identified failed check nodes in the first iteration of the error correction code is greater than the decoding threshold.

[0033] In an example where the error correction code is a multi-layer code, the decoding controller 9 is configured to compare the number of identified failed check nodes in the first iteration of the multi-layer error correction code (e.g., the cumulative number of errors in all layers of the first iteration) with the decoding threshold (105), and is configured to generate an output indicating that the hard input decoding circuit will stop processing the error correction code when the number of identified failed check nodes in the first iteration of the multi-layer error correction code is greater than the decoding threshold.

[0034] In another example where the error correction code is a multi-layer code, the decoding controller 9 is configured to compare the number of identified failed check nodes in the first layer of the first iteration with the decoding threshold (105), and is configured to generate an output indicating that the hard input decoding circuit will stop processing the error correction code when the number of identified failed check nodes in the first layer of the first iteration of the error correction code is greater than the decoding threshold. Alternatively, the layers of subsequent iterations or all layers of a specific subsequent iteration can be compared in step 105.

[0035] When the number of identified failed check nodes is not greater than the decoding threshold (106, 107), the hard decoding process continues (107). The hard decoding process continues until it succeeds (119, 117) or until it fails. The process typically fails when the maximum number of iterations is reached and no stored FEC block is identified. When the hard decoding process fails, soft information is obtained and decoding is performed using the soft information (110 - 115), as described in more detail below.

[0036] The decoding threshold can be changed at different times (120). In one example, the decoding threshold is changed by storing a set of predetermined decoding thresholds at various points in the lifetime of the flash memory device 12 and selecting the predetermined decoding threshold corresponding to the current point in the lifetime of the flash memory device 12. For example, an exemplary flash memory device (e.g., a NAND device having the same design, manufacturing, etc.) can be modeled to obtain a set of predetermined decoding thresholds. The predetermined decoding thresholds can be stored in a look-up table (LUT) 14 of the data storage device 6, and the data storage device is accessed to identify the predetermined decoding threshold corresponding to the type of the flash memory device 12 being used and the current point in the lifetime of the flash memory device 12 (e.g., used under a certain number of program / erase cycles). In one example, the firmware (not shown) of the flash memory controller 10 keeps track of the number of program and erase cycles.

[0037] Optionally, when it is determined that the hard input decoding circuit 7 is full (120, 121), the decoding threshold is changed (120). The decoding controller 9 is configured to monitor the operation of the hard input decoding circuit 7 to determine when the hard input decoding circuit 7 is full. In one example, the decoding threshold starts at a high enough rate such that no hard decoding process stops ( Figure 2 steps 106, 108), and whenever it is determined that the hard input decoding circuit 7 is full, the decoding controller 11 decreases the decoding threshold (e.g., it can be a decremental decrease, e.g., by an increment of 1).

[0038] When the number of identified check node failures is greater than the decoding threshold (106), the hard decoding process is stopped before completion (108) (e.g., before reaching the maximum number of iterations or successfully identifying the stored FEC block), and the stored FEC block is identified using soft information (steps 110 - 115) (117). The decoder - controller 9 is configured to generate an output indicating that the hard input decoding circuit will stop processing the error - correcting code when the number of identified check node failures is greater than the decoding threshold. In response, the corresponding hard input decoding circuit 7 stops the hard decoding process before completing the hard decoding process and does not perform subsequent iterations of the error - correcting code.

[0039] In one example, the decoding controller 9 is configured to send an early termination signal to the hard input decoding circuit 7, as Figure 5 shown. In response to receiving the early termination signal, the hard input decoding circuit 7 is configured to stop the hard decoding process immediately or after completing the layer or iteration being processed.

[0040] When the number of identified failed check nodes is greater than a decoding threshold, an indication (110) is generated that additional reads are needed. The decoder - controller 9 is configured to generate an output (e.g., one or more signals to the read circuit 5) indicating that additional reads are needed when the number of identified failed check nodes is greater than the decoding threshold.

[0041] In response to the output indicating that additional reads are needed, one or more additional reads (111) are performed to obtain one or more additional FEC blocks of read values. The additional reads of step 111 are reads of locations within the flash memory device 12 associated with the memory cells in which the FEC blocks are stored. A read that obtains more information related to a value that has been previously read is commonly referred to as a "soft read", and the information obtained from such a read is referred to as a "soft read value" and is sometimes called "soft information". Thus, the additional reads of step 111 are "soft reads", and they produce "soft read values".

[0042] In one example, the read circuit 5 is configured to perform additional reads (e.g., using a conventional read instruction) of the same address read in step 102 in the flash memory device 12.

[0043] In one example, a first additional read of the stored FEC block is performed to obtain a first additional FEC block of soft read values by sending a first threshold voltage offset read command indicating a negative threshold voltage offset, and a second additional read is performed to obtain a second additional FEC block of soft read values by sending a second threshold voltage offset read command indicating a positive threshold voltage offset. Additionally, a reread instruction can be used to obtain a soft read of the stored FEC block. In yet another example, the flash memory device 12 performs two reads of the stored FEC block (Vt +, Vt -) in response to a reread instruction, and the results of the two reads are XORed together to provide a single set of soft read values output by the flash memory device 12.

[0044] In another example, each bit is read 3 times in exactly the same way. A voting scheme then identifies "strong" inputs (where all 3 reads agree) and weak inputs, where 2 reads are one sign and the third read is the opposite sign. The read values and identifiers are output as the soft read values output by the flash memory device 12.

[0045] The first FEC block of the read value and one or more additional FEC blocks (112) of the read value are received at mapper 13, where each bit of each additional FEC block of the one or more additional FEC blocks of the read value represents a corresponding bit of the stored FEC block. The first FEC block of the read value (e.g., a hard read value) and the additional FEC blocks of the read value (e.g., soft read values) are mapped (113) into soft input values. Mapper 13 is configured to receive the first FEC block of the read value and the additional FEC blocks of the read value in response to an output indicating that additional reads are needed, and is configured to map the first FEC block of the read value and the additional FEC blocks of the read value into soft input values.

[0046] In one example, the mapping process combines multiple reads of a given information bit into a single decoder input value referred to as a "soft input value". The soft input value indicates probabilities (e.g., the probability that the input signal is 1 or 0). In Figure 1 the example shown, mapper 13 identifies the soft input value and provides the identified soft input value to the corresponding soft input decoder circuit 8.

[0047] Table 1 shows an example of different probability values Pn_m for each read condition, where n is the read condition (in this case, the binary value returned from 3 reads), and m is 0 or 1, representing that the real bit is 0 or 1, where Pn_0 + Pn_1 = 1.0.

[0048] Table 1: Soft Mapping Table

[0049] Read Soft Bit 1 Read Soft Bit 2 Read Soft Bit 3 Probability 0 Probability 1 LLR 0 0 0 P0_0 P0_1 LLR_0 0 0 1 P1_0 P1_1 LLR_1 0 1 0 P2_0 P2_1 LLR_2 0 1 1 P3_0 P3_1 LLR_3 1 0 0 P4_0 P4_1 LLR_4 1 0 1 P5_0 P5_1 LLR_5 1 1 0 P6_0 P6_1 LLR_6 1 1 1 P7_0 P7_1 LLR_7

[0050] Probability data (e.g., Pn_m) can be collected during the characterization of the device, where a known sequence is written and then read back using 3 reads. These 3 reads are typically slightly different, i.e., the threshold voltage offset of the read voltage in each case. It should be understood that the characterization process is performed in a test laboratory using a similar device (e.g., the same type of device, the design of the device, and potentially the same production running in a manufacturing facility) before the device is delivered to the customer.

[0051] In one example, the identified probability data is used to calculate a single LLR value (Pn) using the following equation: LLRn = log(Pn_0 / Pn_1).

[0052] In one example, LUT 14 includes an LLR mapping table that includes one or more values representing read results (e.g., columns 1 - 3 of Table 1) and corresponding probability values (e.g., LLR values, such as the LLR_n values shown in Table 1).

[0053] In another example, the soft mapping operation includes identifying a probability value corresponding to a read result through an LLR mapping table stored by an index, and identifying a corresponding LLR value as a soft input value using a first FEC block of the read value and an additional block of the read value.

[0054] Perform a (114) soft decoding process on the soft input value to identify the decoded FEC block. The corresponding soft input decoding circuit 8 is configured to perform a soft decoding process on the soft input value to identify the decoded FEC block. The hard decoding process and the soft decoding process can each perform any error correction code that allows soft data input and processing, such as, for example, Viterbi code, soft output Viterbi algorithm (SOVA) code, Turbo code, or low density parity check (LDPC) code.

[0055] In the case where the soft decoding process in steps 110 - 114 fails (115), further efforts (not shown) can be employed to assist in recovering the FEC block (116). The next steps can be, for example, performing an additional soft read and combining more read information, and then repeating the soft decoding process (114) again to attempt a different mapping of the soft read or, as a last resort, going to RAID.

[0056] The hard read / hard decoding and soft read / soft decoding processes of the present invention that utilize early hard decoding exit move the processing of blocks that may be difficult to decode out of the hard input decoding circuit 7 early in the hard decoding process (before the hard decoding process has reached the maximum number of iterations), thus reducing the number of decoding iterations and freeing up the hard input decoding circuit 7 for performing decoding operations on other FEC blocks.

[0057] Figure 3The line 31 represents the effective throughput distribution of the SSD drive, where the x-axis represents the SSD lifespan, i.e., the age of the solid-state drive 20 measured in read / write cycles, and the y-axis represents the effective throughput. The line segment 31 between A - B and B - C represents an exemplary prior art SSD drive, and the dashed line 32 represents the method and apparatus of the present invention, where the effective throughput is the amount of information read from the drive and passed to the operating system. At the start of the lifespan of the solid-state drive 20, the maximum full bandwidth (FB) of G bytes / s is obtained, which is the maximum read bandwidth of the flash memory device 12 minus some overhead for error correction code parity information. As the solid-state drive ages, it eventually reaches point A, where the hard decoding throughput limit of the hard input decoding circuit 7 is reached. As the RBER further increases due to aging, the effective throughput trend of the prior art SSD follows the solid track line from point A down to point B, where the effective throughput of the system reaches FB / 3 (in this example, for each bit of the stored information, 3 reads from the flash memory device 12 are used to perform soft decoding). Starting from B, the hard decoding engine of the prior art SSD is fully occupied, and the read bandwidth at the flash is also FB / 3. The excess available 2FB / 3 bandwidth (BW) of the SSD is no longer available for the exemplary prior art system. At some point in time after point B, the prior art SSD maintains the throughput at FB / 3 and requires all soft decoding. Point C represents an exemplary point where only soft decoding is used and hard input decoding stops in this embodiment.

[0058] The dashed line 32 extending from A to C is the target effective throughput of the method and apparatus of the present invention, which can theoretically be obtained by adjusting the decoding threshold of the method 100 to balance the number of hard decoding operations and soft decoding operations, such that the maximum effective throughput is obtained at each bit error rate encountered during the lifespan of the SSD 20. The vertical distance between the dashed line 32 and the solid line 31 represents the theoretical maximum improved effective throughput of the method and apparatus of the present invention compared to a conventional prior art SSD.

[0059] In one example of the present invention, at the beginning of the life of the SSD 20, the decoding threshold is set to a high value such that all decoding is performed using standard hard input decoding (e.g., represented by line 31 from the start of life to point A). As the input BER increases, the throughput of the hard decoding engine continues to decrease. At some point, the hard decoding throughput is not sufficient to fully utilize all the available read bandwidth from the flash memory, resulting in a decrease in the utilization of the flash BW. Additionally, at this time, the decoder 11 issues a hard decoder full signal indicating that the hard decoder has become the throughput bottleneck of the system (blocks are ready to be decoded but cannot be processed) and is not utilizing the full available read flash BW from the memory. When this occurs, the decoding threshold is decreased by one such that more difficult FEC blocks will be discarded earlier and will be decoded using the soft decoding process 114 (keeping the effective throughput as close as possible to line 32). This process continues until the decoding threshold reaches the minimum value (e.g., the horizontal line between point B and point C and extending beyond C). As the decoding threshold decreases, more flash BW is used, increasing the effective throughput compared to prior art SSDs until point C is reached, which represents the point at which the method and apparatus of the present invention move to full soft decoding (since there are no points to continue Figure 1 the hard decoding process and comparison of steps 101 - 107 because all blocks to be decoded will have a high enough RBER such that they will require the soft decoding of steps 110 to 115 ( Figure 1 ), and efficiency is obtained by performing only the soft decoding process (steps 110 to 115).

[0060] Figure 4 A method (200) is shown for receiving (201) an initial user input code rate value and an initial threshold control value. The decoding threshold is identified (202) using the code rate value and the threshold control value received in step (201) (or using default values). In one example, simulations are run on a large number of flash memory devices using different code rate values to obtain a decoding threshold base value (DTn) and a scaling value (SCn) for each code rate. The decoding threshold base values are selected such that they provide similar results at each code rate (e.g., approximately the same number of decoding operations are transferred to the soft decoder). In this example, the scaling value for each code rate is different, where the scaling value for each code rate is determined during the simulation such that at each code rate value selected by the user, the amount of change caused by a decrease in the threshold control value is similar. In an exemplary example, the user is able to select a threshold control value (U) from one to ten, and the corresponding decoding threshold (DT) is calculated using the following equation: DT = DTn - U * SCn.

[0061] Figure 5Shows a portion of an exemplary decoder including a hard - input decoding circuit 57, a decoding controller 59, and a code - information processor 58. The decoding controller 59 is coupled to the code - information processor 58 and the hard - input decoding circuit 57. The code - information processor 58 includes logic and / or dedicated circuitry for converting an input code rate into DTn and SCn. In one embodiment, the code - information processor 58 is operable to receive the user input code rate of step 201 and output DTn and SCn for the received code rate. The decoding controller 59 is operable to receive input U, DTn, and SCn and identify the corresponding decoding threshold of step 202.

[0062] The hard - input decoding circuit 57 includes a first input of the FEC block coupled to receive a read value and a second input coupled to the decoding controller 59 for receiving an early - termination signal from the decoding controller 59. The hard - input decoding circuit 57 also outputs a block - status signal (e.g., decoding failure or success, the number of required iterations, and correction statistics (correction zeros and correction ones of the FEC block)). The hard - input decoding circuit 57 includes a first output coupled to a corresponding input of the decoding controller 59 for outputting an iteration (layer) - number signal indicating the number of iterations and / or layers processed during the current hard - decoding process. A second output is coupled to a corresponding input of the decoding controller 59 for outputting a failed - check - node count signal indicating the cumulative number of check - node failures in the decoding operation.

[0063] Now refer to Figure 4 , when all the hard - input decoding circuits 7 are full, an indication (203) is provided to the user. The user, who can be the purchaser of the flash - memory controller 10 in this case, can design their own SSD that includes the flash - memory controller 10, the flash memory 12, and circuitry and / or logic for controlling the operation of the SSD.

[0064] In one example, based on incoming decoding requests and block - status signals from the hard - input decoding circuits 7, the decoding controller 9 is operable to identify when the hard - input decoding circuits 7 are full (e.g., when they are at full capacity and cannot process additional hard - input FEC blocks). When it is determined that the hard - input decoding capacity of the decoder is full (e.g., when all the hard - input decoding circuits 7 are busy), the decoding controller 9 is operable to generate an output to the I / O circuit 2 indicating that the hard - input decoding circuits are full (e.g., a hard - decoder full signal). The I / O circuit 2 then generates a corresponding output to the host 16 indicating that the hard - input decoding circuits are full. In one example, when a request is received for decoding a new FEC block of a hard - read value and the decoding controller 9 determines that all the hard - input decoding circuits 7 are busy, it is operable to generate a hard - decoder full signal.

[0065] Upon receiving a new user input (204) including a new threshold control value, the decoding threshold is updated (202) by identifying a decoded threshold corresponding to the new threshold control value. In one example, the user is allowed to select from more than 100 different code rates. Whenever a new code rate value is received (205), the decoding threshold is updated (202). The new decoding threshold is then stored in one or more of the data storage devices 6, in a register in the decoder 11, and in the hard input decoding circuit 57.

[0066] In one example, at the beginning of life, the decoding threshold is set to a high value such that all decoding is performed using the hard input decoding process. The user monitors the effective throughput of the memory device and when the effective throughput drops below FB, i.e., below full bandwidth, then U is incremented by one setting. Without departing from the scope of the present invention, an increment of one setting is not required and in some embodiments, the increment may be more than one. This will lower the decoding threshold such that difficult FEC blocks will be dropped earlier and then decoding will be performed using the soft input decoding process.

[0067] When a read instruction is received (206) from the host device 16, the hard read / hard decode and soft read / soft decode processes of method 100 with early hard decode exit are performed (207), as described above with respect to method 100, to identify the decoded FEC blocks. Once the decoded FEC blocks are identified (207), the parity bits are removed from the decoded FEC blocks to obtain the initially stored data (208), which is then sent to the input and output circuit 2, which is operable to output the initially stored data to the host device 16.

[0068] Method 200 allows the user to balance the operations between soft input decoding and hard input decoding using the indication (203) that all hard input decoding circuits 7 are full and other information available to the user regarding performance. The user may also allow the default automatic control function of the decoder to control the selection of the threshold control value (in which case the threshold control value is initially set to a high value and decreased each time all hard input decoding circuits 7 are full), as described with respect to steps 120, 121 in method 100.

[0069] Figure 6Shows the frame error rate (FER) of an error correction code at three different code rates CR1, CR2, and CR3 relative to the BER (BERin) of an exemplary frame received at the decoder, where CR1 > CR2 > CR3. In this example, curves 60 - 62 show the performance at CR1, curves 63 - 65 show the performance at CR2, and curves 66 - 68 show the performance at CR3. In this example, CR1, CR2, and CR3 are n - row LDPC error correction codes, where the number of rows in CR1 is less than the number of rows in CR2, and the number of rows in code CR2 is less than the number of rows in CR3. Results for each of the indicated code rates are shown for the prior art situation (equivalent to the decoding threshold being set so high that there is no early exit, shown as "standard"), and exemplary "low decoding threshold" and exemplary "high decoding threshold" are shown in the form of DTnm, where n is L for "low" or H for "high", and n is the code rate number between 1 and 3. More specifically, curves 60, 63, and 66 show the situation where the decoding threshold is set so high that there is no early decoding exit (DT = very high), curves 62, 65, and 68 show the FER at the high decoding threshold, and curves 61, 64, and 67 show the FER at the low decoding threshold (where DT very high > DT high > DT low).

[0070] The prior art decoding operation has the best FER performance because each early exit of the present invention is considered a frame error. A high value of the decoding threshold means that most FEC blocks will be allowed to continue hard decoding because the number of failed check nodes will tend to fall below the high decoding threshold. As the decoding threshold (DT) decreases, we start to degrade the FER curve performance. The purpose of this is to improve the SSD read performance by selectively discarding difficult hard - decoded FEC blocks and converting them into soft - decoded FEC blocks so that they can be easily decoded.

[0071] In one example, the threshold control value U is a 4 - bit value starting from zero, which will Figure 6 the frame error rate of CR1 relative to the BER slowly move from the position of curve 60 towards the position of curve 62, and then move to the position of curve 61 at the highest setting as U increases. Similarly, for CR2, increasing U will move the frame error rate relative to the BER slowly from the position of curve 63 towards the position of curve 65, and then move to the position of curve 64. Additionally, for CR3, changing U will move the frame error rate relative to the BER slowly from the position of curve 66 towards the position of curve 68, and then move to the position of curve 67.

[0072] Figure 7 Shows Figure 6The average number of iterations for the shown codes and code rates versus BERin. More specifically, curves 70, 73, and 76 show cases where the decoding threshold is set so high that there are no early decoding exits (equivalent to prior art systems), curves 72, 75, and 78 show the FER at high decoding thresholds, and curves 71, 74, and 77 show the FER at low decoding thresholds. In the early stages of the life of the flash memory device 12, a low BERin is achieved, where BERin increases as the flash memory device 12 ages. Initially, the hard decoding process (104) successfully decodes all input frames without excessive decoding iterations. However, in the absence of early hard decoding exits, as shown by curves 70, 73, 76, as BERin increases (e.g., as the flash memory device 12 ages), more and more hard decoding processes fail, thus significantly increasing the total number of decoding iterations. Curves 72, 75, and 78 show how the method and apparatus of the present invention reduce the number of iterations at high decoding thresholds. Curves 71, 74, and 77 show how the method and apparatus of the present invention reduce the number of iterations at low decoding thresholds (e.g., fewer iterations of hard decoding, resulting in fewer overall iterations).

[0073] The number of check nodes in any H-matrix and code rate depends on multiple factors, including but not limited to code rate, FEC block size, and the H-matrix of the block. In Figures 6 to 7 the example shown, CR1 = 0.95, CR2 = 0.9, and CR3 = 0.8. Code CR1 has the fewest number of check equations in the code, and the low decoding threshold (DTL1) is 16% of the total number of check nodes, while the high decoding threshold (DTH1) is 20% of the check nodes, and the extremely high decoding threshold (DTstandard) is set to 100% of the check nodes used at CR1. For CR2, DTL2 is 19% of the check nodes in the code; the high decoding threshold (DTH2) is 23% of the check nodes in the code; and the extremely high decoding threshold (DTstandard) is 100% of the check nodes in the code. For CR3, DTL3 is 23% of the check nodes in the code; the high decoding threshold (DTH3) is 27% of the check nodes in the code; and the extremely high decoding threshold (DTstandard) is 100% of the check nodes in the code.

[0074] In one example, to calculate the physical threshold, we can multiply the recommended percentage by the number of check nodes in the H-matrix. For example, for CR1, we may have 2048 check nodes in the H-matrix, and for DTL1, we have a threshold of 16%, so DT1 = 2048 * 0.16 = 327.

[0075] In one example, the flash memory controller 10 is implemented as a single semiconductor die in an integrated circuit. Alternatively, the integrated circuit may include multiple semiconductor dies electrically coupled together, such as a multi-chip module encapsulated in a single integrated circuit package.

[0076] In various examples, the decoder 11 and / or portions of the flash memory controller 10 may be implemented in a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). Those skilled in the art will appreciate that the various functions of the circuit elements may also be implemented as processing steps in a software program. Such software may be used, for example, in a digital signal processor, a network processor, a microcontroller, or a general purpose computer.

[0077] Although examples and applications of the invention have been shown and described, it will be apparent to those skilled in the art that many more modifications are possible without departing from the inventive concepts herein. Accordingly, the invention is not limited except as by the appended claims.

Claims

1. A method for decoding, comprising: receiving, at a hard - input decoding circuit, a first forward error correction (FEC) block of read values, each bit of the first FEC block of read values representing a corresponding bit of a stored FEC block; starting, by the hard - input decoding circuit, a hard - decoding process, the hard - decoding process including variable - node processing and check - node processing of the first FEC block of read values to identify a number of check - node failures; during the hard - decoding process, comparing the identified number of check - node failures with a decoding threshold; when the identified number of check - node failures is not greater than the decoding threshold, continuing, by the hard - input decoding circuit, the hard - decoding process; when the identified number of check - node failures is greater than the decoding threshold: stopping the hard - decoding process before completing the hard - decoding process; generating an output indicating that additional reads are needed; receiving, at a mapper, the first FEC block of read values and one or more additional FEC blocks of read values, each bit of each additional FEC block of the one or more additional FEC blocks of read values representing a corresponding bit of the stored FEC block; mapping the first FEC block of read values and the one or more additional FEC blocks of read values into soft - input values; and performing a soft - decoding process on the soft - input values to identify a decoded FEC block.

2. The method according to claim 1, wherein comparing the identified number of check - node failures with the decoding threshold includes comparing the number of check - node failures in a first iteration of a single - layer error - correcting code with the decoding threshold, and stopping the hard - decoding process includes not performing any subsequent iterations of the single - layer error - correcting code on the first FEC block of read values.

3. The method according to claim 1, wherein the hard - decoding process and the soft - decoding process include performing a multi - layer low - density parity - check (LDPC) error - correcting code.

4. The method according to claim 1, wherein the hard - decoding process and the soft - decoding process include performing an error - correcting code selected from the group consisting of a Viterbi code, a soft - output Viterbi algorithm (SOVA) code, and a Turbo code.

5. The method according to claim 1, wherein comparing the identified number of check - node failures with the decoding threshold further includes comparing the number of failures in a first layer of a first iteration of a multi - layer error - correcting code with the decoding threshold, and wherein stopping the hard - decoding process includes not performing any subsequent iterations of the multi - layer error - correcting code on the first FEC block of read values.

6. The method according to claim 1, further comprising: performing a first read of the stored FEC block by sending a read command from a read circuit of a flash - memory controller to one or more flash - memory devices on which the FEC block is stored, and in response to sending the read command, receiving, at the read circuit, the first FEC block of read values; coupling the first FEC block of read values to the hard - input decoding circuit; and In response to the generated output indicating a need for additional reads, one or more additional reads are performed by sending one or more additional read commands from the read circuit of the flash memory controller to the one or more flash memory devices on which the FEC blocks are stored, and in response to sending the one or more additional read commands, one or more additional FEC blocks of the read values are received.

7. The method according to claim 1, wherein continuing the hard decoding process further comprises continuing the hard decoding process until the hard decoding process has successfully identified the stored FEC block or has failed, and stopping the hard decoding process before completing the hard decoding process further comprises stopping the hard decoding process before the hard decoding process has successfully identified the stored FEC block or has failed.

8. The method according to claim 1, further comprising changing the decoding threshold during the lifetime of the flash memory device to reflect the bit error rate (BER) of the flash memory device.

9. The method according to claim 1, further comprising changing the decoding threshold when the hard input decoding circuit is full.

10. The method according to claim 1, further comprising incrementally decreasing the decoding threshold when the hard input decoding circuit is full.

11. The method according to claim 1, further comprises: generating an output indicating when the hard input decoding circuit is full; receiving user input including a code rate value and a threshold control value; identifying the decoding threshold based on the received code rate value and threshold control value; and storing the identified decoding threshold.

12. A decoder, comprising: a hard input decoding circuit configured to receive a first forward error correction (FEC) block of read values, each bit of the first FEC block of the read values representing a corresponding bit of a stored FEC block, and to begin a hard decoding process that includes variable node processing and check node processing of the first FEC block of the read values to identify the number of check node failures; a decoding controller coupled to the hard input decoding circuit, the decoding controller configured to compare the identified number of check node failures with a decoding threshold during the hard decoding process, generate an output indicating that the hard input decoding circuit will stop processing the error correction code when the identified number of check node failures is greater than the decoding threshold, and generate an output indicating a need for additional reads when the identified number of check node failures is greater than the decoding threshold; wherein in response to the output indicating that the hard input decoding circuit will stop processing the error correction code, the hard input decoding circuit is operable to stop the hard decoding process before completing the hard decoding process; a mapper configured to receive the first FEC block of the read values and additional FEC blocks of the read values in response to the generated output indicating a need for additional reads, and to map the first FEC block of the read values and the additional FEC blocks of the read values into soft input values; and A soft - input decoding circuit, the soft - input decoding circuit being coupled to the mapper, the soft - input decoding circuit being configured to perform a soft - decoding process on the soft - input values to identify decoded FEC blocks from the soft - input values.

13. The decoder according to claim 12, wherein the decoding controller is configured to compare the number of check - node failures identified in a first iteration of a single - layer error - correcting code with the decoding threshold, and is configured to generate an output indicating that the hard - input decoding circuit will stop processing the error - correcting code when the number of check - node failures identified in the first iteration of the error - correcting code is greater than the decoding threshold.

14. The decoder according to claim 12, wherein the decoding controller is configured to compare the number of check - node failures identified in a first layer of a first iteration with the decoding threshold, and is configured to generate an output indicating that the hard - input decoding circuit will stop processing the error - correcting code when the number of check - node failures identified in the first layer of the first iteration of the error - correcting code is greater than the decoding threshold.

15. The decoder according to claim 12, wherein the decoding controller is configured to identify the decoding threshold based on a code - rate value input by a user and a threshold - control value input by the user.

16. The decoder according to claim 15, wherein the decoding controller is configured to identify the decoding threshold by performing a lookup of the input code - rate value and the threshold - control value in a stored look - up table to identify a corresponding decoding threshold.

17. The decoder according to claim 12, wherein the decoding controller is configured to incrementally decrease the decoding threshold when the hard - input decoding circuit is full.

18. The decoder according to claim 12, wherein the hard - decoding process and the soft - decoding process each include performing an error - correcting code selected from the group consisting of Viterbi code, soft - output Viterbi algorithm (SOVA) code, Turbo code, and low - density parity - check (LDPC) code.

19. A memory controller, comprising: an input and output circuit; an encoder configured to encode data received at the input and output circuit into forward error - correction (FEC) blocks; a write circuit coupled to the encoder, the write circuit being configured to store the FEC blocks on a non - volatile storage device; a read circuit configured to read the stored FEC blocks; a hard - input decoding circuit configured to receive a first FEC block of read values, each bit of the first FEC block of read values representing a corresponding bit of the stored FEC block, and start a hard - decoding process, the hard - decoding process including variable - node processing and check - node processing of the first FEC block of read values to identify the number of check - node failures; A decoding controller, the decoding controller being coupled to the hard input decoding circuit, the decoding controller being configured to compare the number of identified check node failures with a decoding threshold during the hard decoding process, and when the number of identified check node failures is greater than the decoding threshold, generate an output indicating that the hard input decoding circuit will stop processing the error correction code, and when the number of identified check node failures is greater than the decoding threshold, generate an output indicating that additional reads are required, wherein in response to the output indicating that the hard input decoding circuit will stop processing the error correction code, the hard input decoding circuit is operable to stop the hard decoding process before completing the hard decoding process; A mapper, the mapper being configured to receive a first FEC block of the read value and an additional FEC block of the read value in response to the generated output indicating that additional reads are required, and being configured to map the first FEC block of the read value and the additional FEC block of the read value into soft input values; and A soft input decoding circuit, the soft input decoding circuit being coupled to the mapper, the soft input decoding circuit being configured to perform a soft decoding process on the soft input values to identify decoded FEC blocks.

20. The memory controller according to claim 19, wherein the decoding controller is configured to incrementally decrease the decoding threshold when the hard input decoding circuit is full.

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