Test Circuit and Method for a Simulated Neural Memory in an Artificial Neural Network

Abstract

The present invention discloses a test circuit and method for simulating a neural memory in a deep learning artificial neural network. The simulated neural memory includes one or more non-volatile memory cell arrays. The test circuit and method can be utilized during sorting tests, qualification tests, and other tests to verify the programming operations of one or more cells.

Description

[0001] Priority Claim

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 876,515, filed on Jul. 19, 2019, titled “Testing Circuitry and Methods for Analog Neural Memory in Artificial Neural Network,” and to U.S. Patent Application No. 16 / 569,611, filed on Sep. 12, 2019, titled “Testing Circuitry and Methods for Analog Neural Memory in Artificial Neural Network.” Technical Field

[0003] The present invention discloses testing circuitry and methods for analog neural memories in deep learning artificial neural networks. The analog neural memories include one or more arrays of non-volatile flash memory cells. Background Art

[0004] Artificial neural networks mimic biological neural networks (the central nervous system of animals, particularly the brain), and are used to estimate or approximate functions that may depend on large numbers of inputs and are generally unknown. Artificial neural networks typically include layers of interconnected “neurons” that exchange messages with each other.

[0005] Figure 1 An artificial neural network is shown, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows and have numerical weights that can be adjusted according to experience. This enables the neural network to adapt to the inputs and learn. Generally, a neural network includes a layer of multiple inputs. There is typically one or more intermediate layers of neurons, and an output layer of neurons that provides the output of the neural network. The neurons at each level make decisions separately or jointly based on the data received from the synapses.

[0006] One of the main challenges in developing artificial neural networks for high-performance information processing is the lack of sufficient hardware technology. In fact, actual neural networks rely on a large number of synapses to achieve high connectivity between neurons, i.e., very high computational parallelism. In principle, such complexity can be achieved by digital supercomputers or clusters of dedicated graphics processing units. However, compared to biological networks, these methods are not only costly but also have mediocre energy efficiency, as biological networks consume less energy mainly due to their execution of low-precision analog computations. CMOS analog circuits have been used in artificial neural networks, but due to the need for a large number of neurons and synapses, most CMOS-implemented synapses are too large.

[0007] The applicant previously disclosed in U.S. Patent Application 15 / 594,439 (published as U.S. Patent Publication 2017 / 0337466) an artificial (analog) neural network that uses one or more non-volatile memory arrays as synapses, which patent application is incorporated herein by reference. The non-volatile memory array operates as an analog neural memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each memory cell of the memory cells includes: spaced-apart source and drain regions formed in a semiconductor substrate, wherein a channel region extends between the source and drain regions; a floating gate disposed over a first portion of the channel region and insulated from the first portion; and a non-floating gate disposed over a second portion of the channel region and insulated from the second portion. Each memory cell of the plurality of memory cells is configured to store a weight value corresponding to a plurality of electrons on the floating gate. The plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs. An array of memory cells used in this manner can be referred to as a vector matrix multiplication (VMM) array.

[0008] Each non-volatile memory cell used in an analog neural memory system must be erased and programmed to maintain a very specific and precise amount of charge (i.e., number of electrons) in the floating gate. For example, each floating gate must maintain one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0009] Precision and accuracy are very important in operations involving a VMM array because each individual memory cell can store one of N different levels, where N can be greater than 2, which is completely different from traditional memory cells where N is always 2. This makes testing an extremely important operation. For example, it is necessary to verify programming operations to ensure that each individual cell or column of cells is accurately programmed to the desired value. Also, it is crucial to identify bad cells or groups of cells so that they can be removed from the set of cells used to store data during the operation of the VMM array.

[0010] What is needed is an improved test circuit and method for a VMM array. SUMMARY OF THE INVENTION

[0011] The present invention discloses a test circuit and method for simulating a neural memory in a deep learning artificial neural network. The simulated neural memory includes one or more non-volatile flash memory cell arrays. The test circuit and method can be utilized during sorting tests, cycling tests, high temperature operating life (HTOL) tests, qualification tests, and other tests, and verify the characteristics and operability of one or more cells.

[0012] One embodiment includes a method for verifying values programmed into a plurality of non-volatile memory cells in an array of simulated neural non-volatile memory cells, where the array is arranged in rows and columns, where each row is coupled to a word line, and each column is coupled to a bit line, and where each word line is selectively coupled to a row decoder, and each bit line is selectively coupled to a column decoder, the method comprising: asserting all word lines in the array by the row decoder; asserting the bit lines in the array by the column decoder; sensing a current received from the bit lines by a sense amplifier; and comparing the current with a reference current to determine whether the non-volatile memory cells coupled to the bit line contain an expected value.

[0013] Another embodiment includes a method for measuring a current consumed by a plurality of non-volatile memory cells in an array of simulated neural non-volatile memory cells, where the array is arranged in rows and columns, where each row is coupled to a word line, and each column is coupled to a bit line, and where each word line is selectively coupled to a row decoder, and each bit line is selectively coupled to a column decoder, the method comprising: asserting all word lines in the array by the row decoder; asserting the bit lines in the array by the column decoder; and measuring the current received from the bit lines.

[0014] Another method includes a method for testing a plurality of simulated neural non-volatile memory cells in a non-volatile memory cell array, where the array is arranged in rows and columns, where each row is coupled to a word line, and each column is coupled to a bit line, and where each word line is selectively coupled to a row decoder, and each bit line is selectively coupled to a column decoder, the method comprising: asserting all word lines in the array by the row decoder; asserting all bit lines in the array by the column decoder; performing a deep programming operation on all non-volatile memory cells in the array; and measuring the total current received from the bit lines.

[0015] Another embodiment includes a method of testing an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, where each row is coupled to a word line and each column is coupled to a bit line, the method comprising: programming a plurality of cells coupled to the bit line; measuring the current consumed by the plurality of cells at K different times and storing the measurement for each of the K different times, where K is an integer; calculating an average value based on the K measurements; and identifying the bit line as a bad bit line if any one of the K measurements is less than the average value by more than a first threshold or greater than the average value by more than a second threshold.

[0016] Another embodiment includes a method of testing an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, where each row is coupled to a word line and each column is coupled to a bit line, the method comprising: programming a plurality of cells coupled to the bit line; measuring the voltage on a control gate line coupled to the control gate terminals of the plurality of cells at K different times and storing the measurement for each of the K different times, where K is an integer; calculating an average value based on the K measurements; and identifying the bit line as a bad bit line if any one of the K measurements is less than the average value by more than a first threshold or greater than the average value by more than a second threshold.

[0017] Another embodiment includes a method of testing an analog neural non-volatile memory cell for storing N different values, where N is an integer, the method comprising: programming the cell to a target value representing one of the N values; verifying that the value stored in the cell is within an acceptable window of values around the target value; repeating the programming step and the read step for each of the N values; and identifying the cell as bad if any of the verification steps indicates that the value stored in the cell is outside the acceptable window of values around the target value.

[0018] Another embodiment includes a method of compensating for leakage in an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, where each row is coupled to a word line and each column is coupled to a bit line, the method comprising: measuring the leakage of a column of non-volatile memory cells coupled to the bit line; storing the measured leakage value; and applying the measured leakage value during a read operation of the column of non-volatile memory cells to compensate for the leakage.

[0019] Another embodiment includes a method of testing selected non-volatile memory cells in an array of analog neural non-volatile memory cells, the method comprising: determining a logarithmic slope factor of a selected non-volatile memory cell while the selected non-volatile memory cell is operating in the subthreshold region; storing the logarithmic slope factor; determining a linear slope factor of the selected non-volatile memory cell while the selected non-volatile memory cell is operating in the linear region; storing the linear slope factor; and utilizing one or more of the logarithmic slope factor and the linear slope factor when programming the selected cell to a target current.

[0020] Another embodiment includes a method of measuring current consumed by a column of non-volatile memory cells in an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line, and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder, and each bit line is selectively coupled to a column decoder, the method comprising: asserting all word lines in the array by the row decoder; asserting the bit lines in the array by the column decoder to select a column of non-volatile memory cells; and measuring the current received from the bit line.

[0021] Another embodiment includes a method of testing an array of analog neural non-volatile memory cells, the method comprising: erasing the non-volatile memory cells in the array by applying a sequence of voltages to the terminals of each of the non-volatile memory cells in the array, wherein the voltages in the sequence of voltages increase over time in a fixed step size; and reading all of the non-volatile memory cells to determine the effect of the erase step.

[0022] Another embodiment includes a method of testing an array of analog neural non-volatile memory cells, the method comprising: programming the non-volatile memory cells in the array by applying a sequence of voltages to the terminals of each non-volatile memory cell in the array, wherein the voltages in the sequence of voltages increase over time in a fixed step size; and reading all of the non-volatile memory cells to determine the effect of the programming step.

[0023] Another embodiment includes a method of testing a plurality of analog neural non-volatile memory cells in a non-volatile memory cell array, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line, and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder, and each bit line is selectively coupled to a column decoder, the method including programming the plurality of non-volatile memory cells to store one of N different values, where N is the number of different levels that can be stored in any non-volatile memory cell; measuring the current consumed by the plurality of non-volatile memory cells; comparing the measured current to a target value; and identifying the plurality of non-volatile memory cells as defective if the difference between the measured value and the target value exceeds a threshold.

[0024] Another embodiment includes a method of testing a plurality of analog neural non-volatile memory cells in a non-volatile memory cell array, wherein the memory array is arranged in rows and columns, wherein each row is coupled to a word line, and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder, and each bit line is selectively coupled to a column decoder, the method including programming a first selection of cells in the plurality of non-volatile memory cells having levels corresponding to the minimum cell current among N levels; programming a second selection of cells in the plurality of non-volatile memory cells having levels corresponding to the maximum cell current among N levels, wherein each cell in the second selection of cells is adjacent to one or more cells in the first selection of cells; measuring the current consumed by the plurality of non-volatile memory cells; comparing the measured current to a target value; and identifying the plurality of non-volatile memory cells as defective if the difference between the measured value and the target value exceeds a threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram showing an artificial neural network of the prior art.

[0026] Figure 2 Showing a split-gate flash memory cell of the prior art.

[0027] Figure 3 Showing another split-gate flash memory cell of the prior art.

[0028] Figure 4 Showing another split-gate flash memory cell of the prior art.

[0029] Figure 5 Showing another split-gate flash memory cell of the prior art

[0030] Figure 6 Showing another split-gate flash memory cell of the prior art.

[0031] Figure 7 Shows a stacked-gate flash memory cell of the prior art.

[0032] Figure 8 Is a schematic diagram showing different levels of an exemplary artificial neural network using one or more non-volatile memory arrays.

[0033] Figure 9 Is a block diagram showing a vector-matrix multiplication system.

[0034] Figure 10 Is a block diagram showing an exemplary artificial neural network using one or more vector-matrix multiplication systems.

[0035] Figure 11 Shows another embodiment of a vector-matrix multiplication system.

[0036] Figure 12 Shows another embodiment of a vector-matrix multiplication system.

[0037] Figure 13 Shows another embodiment of a vector-matrix multiplication system.

[0038] Figure 14 Shows another embodiment of a vector-matrix multiplication system.

[0039] Figure 15 Shows another embodiment of a vector-matrix multiplication system.

[0040] Figure 16 Shows another embodiment of a vector-matrix multiplication system.

[0041] Figure 17 Shows another embodiment of a vector-matrix multiplication system.

[0042] Figure 18 Shows another embodiment of a vector-matrix multiplication system.

[0043] Figure 19 Shows another embodiment of a vector-matrix multiplication system.

[0044] Figure 20 Shows another embodiment of a vector-matrix multiplication system.

[0045] Figure 21 Shows another embodiment of a vector-matrix multiplication system.

[0046] Figure 22 Shows another embodiment of a vector-matrix multiplication system.

[0047] Figure 23 Shows another embodiment of a vector-matrix multiplication system.

[0048] Figure 24 Shows another embodiment of a vector-matrix multiplication system.

[0049] Figure 25 Shows an embodiment of a vector-matrix multiplication system including test control logic components.

[0050] Figure 26 Shows a reference current source.

[0051] Figure 27 Shows a reference sub-circuit for the Figure 26 reference current source.

[0052] Figure 28 Shows a sense amplifier.

[0053] Figure 29A Shows a verification analog-to-digital converter.

[0054] Figure 29B Shows a verification analog-to-digital converter.

[0055] Figure 30 Shows a high-voltage generation circuit.

[0056] Figure 31 Shows an exemplary test algorithm implemented by test control logic components in a vector-matrix multiplication system.

[0057] Figure 32 Shows an embodiment of a bit-line neural read test.

[0058] Figure 33 Shows an embodiment of a bit-line neural measurement test.

[0059] Figure 34 Shows an embodiment of an LSB screen test.

[0060] Figure 35 Shows an embodiment of a bit-line sampling screen test.

[0061] Figure 36 Shows another embodiment of a bit-line sampling screen test.

[0062] Figure 37 Shows an embodiment of a read window check test.

[0063] Figure 38 Shows an embodiment of a read calibration test.

[0064] Figure 39 Shows an embodiment of a read slope test.

[0065] Figure 40 Shows an embodiment of a read neuron identification test.

[0066] Figure 41 Shows an embodiment of a soft erase test.

[0067] Figure 42 Shows an embodiment of a soft program test.

[0068] Figure 43 Shows an embodiment of a verification test.

[0069] Figure 44 Shows an embodiment of a checkerboard verification test. Detailed Description

[0070] The artificial neural network of the present invention utilizes a combination of CMOS technology and a non - volatile memory array.

[0071] Non-volatile memory cell

[0072] Digital non - volatile memories are well known. For example, U.S. Patent 5,029,130 (“the '130 patent”), which is incorporated herein by reference, discloses an array of split - gate non - volatile memory cells, which is a type of flash memory cell. Such memory cells 210 are shown in Figure 2 Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed above and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed above a portion of the source region 14. A word - line terminal 22 (which is typically coupled to a word line) has a first portion disposed above and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion that extends upward and is located above the floating gate 20. The floating gate 20 and the word - line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit - line terminal 24 is coupled to the drain region 16.

[0073] The memory cell 210 is erased by placing a high positive voltage on the word - line terminal 22 (where electrons are removed from the floating gate), which causes electrons on the floating gate 20 to tunnel through an intervening insulator from the floating gate 20 to the word - line terminal 22 via Fowler - Nordheim tunneling.

[0074] The memory cell 210 is programmed by placing a positive voltage on the word - line terminal 22 and a positive voltage on the source region 14 (where electrons are placed on the floating gate). An electron current will flow from the source region 14 (source - line terminal) to the drain region 16. When the electrons reach the gap between the word - line terminal 22 and the floating gate 20, the electrons will accelerate and heat up. Due to the electrostatic attraction from the floating gate 20, some of the heated electrons will be injected onto the floating gate 20 through the gate oxide.

[0075] The memory cell 210 is read by placing a positive read voltage on the drain region 16 and the word line terminal 22 that turns on the portion of the channel region 18 under the word line terminal. If the floating gate 20 is positively charged (i.e., electrons are erased), then the portion of the channel region 18 under the floating gate 20 is also turned on, and current will flow through the channel region 18, which is sensed as the erased state or "1" state. If the floating gate 20 is negatively charged (i.e., programmed with electrons), then the portion of the channel region 18 under the floating gate 20 is mostly or completely turned off, and current will not (or very little current) flow through the channel region 18, which is sensed as the programmed state or "0" state.

[0076] Table 1 shows the typical voltage ranges that can be applied to the terminals of the memory cell 110 for performing read, erase, and program operations:

[0077] Table 1: Figure 2 Operation of the flash memory cell 210

[0078] WL BL SL Read 1 0.5-3V 0.1-2V 0V Read 2 0.5-3V 0-2V 2-0.1V Erase Approximately 11 - 13V 0V 0V Program 1V - 2V 1 - 3μA 9-10V

[0079] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal.

[0080] Figure 3 The memory cell 310 is shown, which is similar to the Figure 2 memory cell 210 but with the addition of a control gate (CG) terminal 28. The control gate terminal 28 is biased at a high voltage (e.g., 10V) during programming, at a low voltage or negative voltage (e.g., 0V / -8V) during erase, and at a low voltage or medium voltage (e.g., 0V / 2.5V) during read. The other terminals are biased similar to Figure 2 that.

[0081] Figure 4 The four-gate memory cell 410 is shown, which includes a source region 14, a drain region 16, a floating gate 20 over a first portion of the channel region 18, a select gate 22 (usually coupled to the word line WL) over a second portion of the channel region 18, a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14. This configuration is described in U.S. Patent 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates except the floating gate 20 are non-floating gates, which means they are electrically connected or can be electrically connected to a voltage source. Programming is performed by hot electrons from the channel region 18 that inject themselves into the floating gate 20. Erase is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0082] Table 2 shows the typical voltage ranges that can be applied to the terminals of memory cell 410 for performing read, erase, and program operations:

[0083] Table 2: Figure 4 Operation of the flash memory cell 410

[0084] WL / SG BL CG EG SL Read 1 0.5-2V 0.1-2V 0-2.6V 0-2.6V 0V Read 2 0.5-2V 0-2V 0-2.6V 0-2.6V 2-0.1V Erase -0.5V / 0V 0V 0V / -8V 8-12V 0V Program 1V 1μA 8-11V 4.5-9V 4.5-5V

[0085] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal.

[0086] Figure 5 Memory cell 510 is shown. Memory cell 510 is similar to Figure 4 memory cell 410, except that it does not include an erase gate EG terminal. Erasure is performed by biasing the substrate 18 to a high voltage and biasing the control gate CG terminal 28 to a low voltage or a negative voltage. Alternatively, erasure is performed by biasing the word line terminal 22 to a positive voltage and biasing the control gate terminal 28 to a negative voltage. Programming and reading are similar to Figure 4 those of

[0087] Figure 6 Trigate memory cell 610 is shown, which is another type of flash memory cell. Memory cell 610 is the same as Figure 4 memory cell 410, except that memory cell 610 does not have a separate control gate terminal. Except for not applying a control gate bias, the erase operation (erasing by using the erase gate terminal) and the read operation are similar to Figure 4 those of

[0088] Table 3 shows the typical voltage ranges that can be applied to the terminals of memory cell 610 for performing read, erase, and program operations:

[0089] Table 3: Figure 6 Operation of the flash memory cell 610

[0090] WL / SG BL EG SL Read 1 0.5-2.2V 0.1-2V 0-2.6V 0V Read 2 0.5-2.2V 0-2V 0-2.6V 2-0.1V Erase -0.5V / 0V 0V 11.5V 0V Program 1V 2 - 3μA 4.5V 7-9V

[0091] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal.

[0092] Figure 7 Stacked gate memory cell 710 is shown, which is another type of flash memory cell. Memory cell 710 is the same as Figure 2The memory cell 210 is similar, except that the floating gate 20 extends over the entire channel region 18, and the control gate terminal 22 (which will be coupled to the word line here) extends over the floating gate 20, separated by an insulating layer (not shown). The erase, program, and read operations operate in a manner similar to that described previously for the memory cell 210.

[0093] Table 4 shows the typical voltage ranges that can be applied to the terminals of the memory cell 710 and the substrate 12 for performing read, erase, and program operations:

[0094] Table 4: Figure 7 Operation of flash memory cell 710

[0095] CG BL SL Substrate Read 1 0-5V 0.1–2V 0-2V 0V Read 2 0.5-2V 0-2V 2-0.1V 0V Erase -8 to -10V / 0V FLT FLT 8 - 10V / 15 - 20V Program 8-12V 3 - 5V / 0V 0V / 3 - 5V 0V

[0096] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal. Optionally, in an array including rows and columns of memory cells 210, 310, 410, 510, 610, or 710, the source line can be coupled to one row of memory cells or two adjacent rows of memory cells. That is, the source line terminal can be shared by memory cells in adjacent rows.

[0097] To utilize a memory array including one of the above types of non-volatile memory cells in an artificial neural network, two modifications are made. First, the circuitry is configured such that each memory cell can be individually programmed, erased, and read without adversely affecting the memory states of other memory cells in the array, as further explained below. Second, continuous (analog) programming of the memory cells is provided.

[0098] Specifically, the memory state of each memory cell in the array (i.e., the charge on the floating gate) can be continuously changed from a fully erased state to a fully programmed state independently and with minimal interference to other memory cells. In another embodiment, the memory state of each memory cell in the array (i.e., the charge on the floating gate) can be continuously changed from a fully programmed state to a fully erased state independently and with minimal interference to other memory cells, and vice versa. This means that the cell storage device is analog or can at least store one of a number of discrete values (such as 16 or 64 different values), which allows for very precise and individual tuning of all the cells in the memory array, and which makes the memory array ideal for storing and fine-tuning the synaptic weights of a neural network.

[0099] The methods and apparatuses described herein can be applied to other non-volatile memory technologies, such as but not limited to SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, charge trapping in nitride), MONOS (Metal-Oxide-Nitride-Oxide-Silicon, metal charge trapping in nitride), ReRAM (Resistive RAM), PCM (Phase Change Memory), MRAM (Magnetic RAM), FeRAM (Ferroelectric RAM), OTP (One-Time Programmable in bilayer or multilayer), and CeRAM (Correlated Electron RAM), etc. The methods and apparatuses described herein can be applied to volatile memory technologies for neural networks, such as but not limited to SRAM, DRAM, and / or volatile synaptic units.

[0100] Neural network using non-volatile memory cell array

[0101] Figure 8 Conceptually illustrated is a non-limiting example of a neural network using a non-volatile memory array of the present embodiment. This example uses the non-volatile memory array neural network for a face recognition application, but any other suitable application can also be implemented using a neural network based on a non-volatile memory array.

[0102] For this example, S0 is the input layer, which is a 32×32 pixel RGB image with 5-bit precision (i.e., three 32×32 pixel arrays, respectively for each color R, G, and B, and each pixel is 5-bit precision). The synapses CB1 from the input layer S0 to the layer C1 apply different sets of weights in some cases and shared weights in other cases, and scan the input image with a 3×3 pixel overlapping filter (kernel), shifting the filter by 1 pixel (or more than 1 pixel as indicated by the model). Specifically, the values of 9 pixels in a 3×3 portion of the image (i.e., called the filter or kernel) are provided to the synapses CB1, where these 9 input values are multiplied by appropriate weights, and after summing the outputs of this multiplication, a single output value is determined and provided by the first synapse of CB1 for a pixel in one of the layers C1 of the generated feature map. Then the 3×3 filter is shifted one pixel to the right within the input layer S0 (i.e., adding the column of three pixels on the right and releasing the column of three pixels on the left), thereby providing the 9 pixel values in this newly positioned filter to the synapses CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process continues until the 3×3 filter scans all three colors and all bits (precision values) of the entire 32×32 pixel image in the input layer S0. Then this process is repeated using different sets of weights to generate different feature maps of C1 until all the feature maps of layer C1 are calculated.

[0103] At layer C1, in this example, there are 16 feature maps, each feature map having 30×30 pixels. Each pixel is a new feature pixel extracted from the product of the input and the kernel, so each feature map is a two-dimensional array. Thus, in this example, layer C1 consists of 16 layers of two-dimensional arrays (remember that the layers and arrays referred to in this text are logical relationships and do not have to be physical relationships, i.e., the arrays do not have to be oriented as physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of a set of sixteen different groups of synaptic weights applied to the filter scan. The C1 feature maps can all relate to different aspects of the same image feature, such as boundary recognition. For example, the first map (generated using the first set of weights, shared for all scans used to generate that first map) may identify circular edges, the second map (generated using a second set of weights different from the first set) may identify rectangular edges, or the aspect ratio of certain features, and so on.

[0104] Before transitioning from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools the values from consecutive non-overlapping 2×2 regions in each feature map. The purpose of the pooling function is to take the mean of neighboring positions (or the max function could also be used) to, for example, reduce the dependence on edge positions and reduce the data size before entering the next stage. At layer S1, there are 16 15×15 feature maps (i.e., sixteen different arrays of 15×15 pixels each feature map). The synapses CB2 from layer S1 to layer C2 scan the maps in S1 using a 4×4 filter, with the filter shifted by 1 pixel. At layer C2, there are 22 12×12 feature maps. Before transitioning from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools the values from consecutive non-overlapping 2×2 regions in each feature map. At layer S2, there are 22 6×6 feature maps. The activation function (pooling) is applied to the synapses CB3 from layer S2 to layer C3, where each neuron in layer C3 is connected via the corresponding synapses of CB3 to each map in layer S2. At layer C3, there are 64 neurons. The synapses CB4 from layer C3 to the output layer S3 fully connect C3 to S3, i.e., each neuron in layer C3 is connected to each neuron in layer S3. The output at S3 includes 10 neurons, and the highest output neuron determines the class. For example, this output can indicate the recognition or classification of the content of the original image.

[0105] Each layer's synapses are implemented using an array or a portion of an array of non-volatile memory cells.

[0106] Figure 9 is a block diagram of a system that can be used for this purpose. The vector-matrix multiplication (VMM) system 32 includes non-volatile memory cells and serves as the synapses between one layer and the next layer (such as Figure 6CB1, CB2, CB3, and CB4 in). Specifically, the VMM system 32 includes a VMM array 33 (including non-volatile memory cells arranged in rows and columns), an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode corresponding inputs to the non-volatile memory cell array 33. The inputs to the VMM array 33 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the VMM array 33. Alternatively, the bit line decoder 36 can decode the output of the VMM array 33.

[0107] The VMM array 33 serves two purposes. First, it stores the weights to be used by the VMM system 32. Second, the VMM array 33 effectively multiplies the inputs with the weights stored in the VMM array 33 and each output line (source line or bit line) sums them to produce an output, which will be used as an input to the next layer or the final layer. By performing the multiplication and addition functions, the VMM array 33 eliminates the need for separate multiplication and addition logic circuits and is also highly efficient due to its in-situ memory computation.

[0108] The output of the VMM array 33 is provided to a differential summing device (such as a summing operational amplifier or a summing current mirror) 38, which sums the output of the VMM array 33 to create a single value for this convolution. The differential summing device 38 is arranged to perform the summation of both positive-weight inputs and negative-weight inputs to output a single value.

[0109] Then the output value of the differential summing device 38 is provided to an activation function circuit 39 after summation, and the activation function circuit corrects the output. The activation function circuit 39 can provide sigmoid, tanh, ReLU functions, or any other non-linear function. The corrected output value of the activation function circuit 39 becomes an element of the feature map as the next layer (e.g., Figure 8 layer C1 in), and then is applied to the next synapse to produce the next feature map layer or the final layer. Thus, in this example, the VMM array 33 constitutes multiple synapses (which receive their inputs from an existing neuron layer or from an input layer such as an image database), and the summing device 38 and the activation function circuit 39 constitute multiple neurons.

[0110] Figure 9The inputs (WLx, EGx, CGx, and optionally BLx and SLx) to the VMM system 32 can be analog levels, binary levels, digital pulses (in which case a pulse - analog converter PAC may be required to convert the pulses to a suitable input analog level), or digital bits (in which case a DAC is provided to convert the digital bits to a suitable input analog level); the outputs can be analog levels, binary levels, digital pulses, or digital bits (in which case an output ADC is provided to convert the output analog level into digital bits).

[0111] Figure 10 A block diagram showing the use of a multi - layer VMM system 32 (here labeled VMM systems 32a, 32b, 32c, 32d, and 32e). As Figure 10 shown, the input (represented as Inputx) is converted from digital to analog by a digital - to - analog converter 31 and provided to the input VMM system 32a. The converted analog input can be voltage or current. The input D / A conversion for the first layer can be done by using a function or a LUT (look - up table) that maps the input Inputx to the appropriate analog levels of a matrix multiplier for the input VMM system 32a. The input conversion can also be done by an analog - to - analog (A / A) converter to convert an external analog input into a mapped analog input to the input VMM system 32a. The input conversion can also be done by a digital - to - digital pulse (D / P) converter to convert an external digital input into one or more digital pulses mapped to the input VMM system 32a.

[0112] The output generated by the input VMM system 32a is provided as an input to the next VMM system (hidden level 1) 32b, which in turn generates an output provided as an input to the next VMM system (hidden level 2) 32c, and so on. Each layer of the VMM system 32 serves as a different layer of synapses and neurons of a convolutional neural network (CNN). Each of the VMM systems 32a, 32b, 32c, 32d, and 32e can be an independent physical system including its respective non - volatile memory array, or multiple VMM systems can utilize different parts of the same non - volatile memory array, or multiple VMM systems can utilize overlapping parts of the same physical non - volatile memory array. Each of the VMM systems 32a, 32b, 32c, 32d, and 32e can also be time - division multiplexed for different parts of its array or neurons. Figure 10 The example shown includes five layers (32a, 32b, 32c, 32d, 32e): an input layer (32a), two hidden layers (32b, 32c), and two fully - connected layers (32d, 32e). Those of ordinary skill in the art will know that this is merely exemplary, and conversely, the system can include more than two hidden layers and more than two fully - connected layers.

[0113] VMM array

[0114] Figure 11 shows a neuron VMM array 1100, which is particularly suitable for Figure 3 the memory cell 310 shown, and serves as the synapse and component of the neuron between the input layer and the next layer. The VMM array 1100 includes a memory array 1101 of non-volatile memory cells and a reference array 1102 of non-volatile reference memory cells (at the top of the array). Alternatively, another reference array can be placed at the bottom.

[0115] In the VMM array 1100, control gate lines (such as control gate line 1103) extend in the vertical direction (so the reference array 1102 is orthogonal to the control gate line 1103 in the row direction), and erase gate lines (such as erase gate line 1104) extend in the horizontal direction. Here, the inputs of the VMM array 1100 are set on the control gate lines (CG0, CG1, CG2, CG3), and the outputs of the VMM array 1100 appear on the source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current placed on each source line (SL0 and SL1 respectively) performs the summation function of all the currents from the memory cells connected to that particular source line.

[0116] As described herein for neural networks, the non-volatile memory cells of the VMM array 1100 (i.e., the flash memory of the VMM array 1100) are preferably configured to operate in the subthreshold region.

[0117] The non-volatile reference memory cells and non-volatile memory cells described herein are biased in weak inversion:

[0118] Ids = Io * e (Vg-Vth) / nVt = w * Io * e (Vg) / nVt ,

[0119] where w = e (-Vth) / nVt

[0120] where Ids is the drain-to-source current; Vg is the gate voltage on the memory cell; Vth is the threshold voltage of the memory cell; Vt is the thermal voltage = k * T / q, where k is the Boltzmann constant, T is the temperature in Kelvin, and q is the electron charge; n is the slope factor = 1 + (Cdep / Cox), where Cdep = the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer; Io is the memory cell current at the gate voltage equal to the threshold voltage, and Io is related to (Wt / L) * u * Cox * (n - 1) * Vt 2Proportional, where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0121] For an I-to-V logarithmic converter that uses a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert an input current Ids into an input voltage Vg:

[0122] Vg = n * Vt * log[Ids / wp * Io]

[0123] Here, wp is the w of the reference memory cell or the peripheral memory cell.

[0124] For an I-to-V logarithmic converter that uses a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert an input current Ids into an input voltage Vg:

[0125] Vg = n * Vt * log[Ids / wp * Io]

[0126] Here, wp is the w of the reference memory cell or the peripheral memory cell.

[0127] For a memory array used as a vector matrix multiplier VMM array, the output current is:

[0128] Iout = wa * Io * e (Vg) / nVt , that is

[0129] Iout = (wa / wp) * Iin = W * Iin

[0130] W = e (Vthp-Vtha) / nVt

[0131] Iin = wp * Io * e (Vg) / nVt

[0132] Here, wa = the w of each memory cell in the memory array.

[0133] The word line or the control gate can be used as the input of the memory cell for the input voltage.

[0134] Alternatively, the non-volatile memory cells of the VMM array described herein can be configured to operate in the linear region:

[0135] Ids = β * (Vgs - Vth) * Vds; β = u * Cox * Wt / L,

[0136] W α (Vgs - Vth),

[0137] meaning that the weight W in the linear region is proportional to (Vgs - Vth)

[0138] A word line, control gate, bit line, or source line can be used as an input to a memory cell operating in the linear region. A bit line or source line can be used as an output of the memory cell.

[0139] For an I-to-V linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor or a resistor operating in the linear region can be used to linearly convert an input / output current into an input / output voltage.

[0140] Alternatively, the memory cells of the VMM array described herein can be configured to operate in the saturation region:

[0141] Ids = 1 / 2 * β * (Vgs - Vth) 2 ; β = u * Cox * Wt / L

[0142] W α (Vgs - Vth) 2 , meaning that the weight W is proportional to (Vgs - Vth) 2 is proportional

[0143] A word line, control gate, or erase gate can be used as an input to a memory cell operating in the saturation region. A bit line or source line can be used as an output of the output neuron.

[0144] Alternatively, the memory cells of the VMM array described herein can be used in all regions or combinations thereof (subthreshold, linear, or saturation regions).

[0145] U.S. Patent Application No. 15 / 826,345 describes Figure 9 other embodiments of the VMM array 33, which is incorporated herein by reference. As described herein, a source line or a bit line can be used as a neuron output (current summation output).

[0146] Figure 12 shows a neuron VMM array 1200, which is particularly suitable for Figure 2The memory cell 210 shown is used as a synapse between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of non-volatile memory cells, a reference array 1201 of first non-volatile reference memory cells, and a reference array 1202 of second non-volatile reference memory cells. The reference arrays 1201 and 1202 arranged along the column direction of the array are used to convert the current inputs flowing into the terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In fact, the first non-volatile reference memory cells and the second non-volatile reference memory cells are diode-connected through a multiplexer 1214 (only partially shown), and the current inputs flow into them. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference microarray matrix (not shown).

[0147] The memory array 1203 serves two purposes. First, it stores the weights to be used by the VMM array 1200 on its corresponding memory cells. Second, the memory array 1203 effectively multiplies the inputs (i.e., the current inputs provided at the terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1201 and 1202 convert into input voltages to be provided to the word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1203, and then sums all the results (memory cell currents) to produce an output on the corresponding bit lines (BL0 - BLN), which will be the input to the next layer or the input to the final layer. By performing the multiplication and addition functions, the memory array 1203 eliminates the need for separate multiplication and addition logic circuits and is also highly efficient. Here, the voltage inputs are provided on the word lines (WL0, WL1, WL2, and WL3), and the outputs appear on the corresponding bit lines (BL0 - BLN) during a read (inference) operation. The current placed on each of the bit lines in BL0 - BLN performs a summing function of the currents from all the non-volatile memory cells connected to that particular bit line.

[0148] Table 5 shows the operating voltages for the VMM array 1200. The columns in the table indicate the voltages placed on the word lines for the selected cells, the word lines for the unselected cells, the bit lines for the selected cells, the bit lines for the unselected cells, the source lines for the selected cells, and the source lines for the unselected cells, where FLT indicates floating, i.e., no voltage is applied. The rows indicate the read, erase, and program operations.

[0149] Table 5: Figure 12 Operation of the VMM array 1200 :

[0150] WL WL - unselected BL BL - unselected SL SL - unselected Read 0.5-3.5V -0.5V / 0V 0.1 - 2V(Ineuron) 0.6V - 2V / FLT 0V 0V Erase Approximately 5 - 13V 0V 0V 0V 0V 0V Program 1V - 2V -0.5V / 0V 0.1 - 3uA Vinh is approximately 2.5V 4-10V 0 - 1V / FLT

[0151] Figure 13Shows a neuron VMM array 1300, which is particularly suitable for Figure 2 the memory cell 210 shown, and serves as the synapse and component of the neuron between the input layer and the next layer. The VMM array 1300 includes a memory array 1303 of non-volatile memory cells, a reference array 1301 of first non-volatile reference memory cells, and a reference array 1302 of second non-volatile reference memory cells. The reference arrays 1301 and 1302 extend in the row direction of the VMM array 1300. The VMM array is similar to the VMM 1000, except that in the VMM array 1300, the word lines extend in the vertical direction. Here, the inputs are set on the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and the outputs appear on the source lines (SL0, SL1) during a read operation. The current placed on each source line performs a summation function of all the currents from the memory cells connected to that particular source line.

[0152] Table 6 shows the operating voltages for the VMM array 1300. The columns in the table indicate the voltages placed on the word lines for the selected cells, the word lines for the unselected cells, the bit lines for the selected cells, the bit lines for the unselected cells, the source lines for the selected cells, and the source lines for the unselected cells. The rows indicate read, erase, and program operations.

[0153] Table 6: Figure 13 Operation of the VMM array 1300

[0154]

[0155] Figure 14 Shows a neuron VMM array 1400, which is particularly suitable for Figure 3The memory cell 310 shown and serves as the synapse and component of the neuron between the input layer and the next layer. The VMM array 1400 includes a memory array 1403 of non-volatile memory cells, a reference array 1401 of first non-volatile reference memory cells, and a reference array 1402 of second non-volatile reference memory cells. The reference arrays 1401 and 1402 are used to convert the current inputs flowing into the terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In fact, the first non-volatile reference memory cells and the second non-volatile reference memory cells are diode-connected through a multiplexer 1412 (only partially shown), where the current inputs flow into them through BLR0, BLR1, BLR2, and BLR3. Each multiplexer 1412 includes a corresponding multiplexer 1405 and a cascode transistor 1404 to ensure a constant voltage on the bit line (such as BLR0) of each of the first non-volatile reference memory cells and the second non-volatile reference memory cells during a read operation. The reference cells are tuned to a target reference level.

[0156] The memory array 1403 serves two purposes. First, it stores the weights to be used by the VMM array 1400. Second, the memory array 1403 effectively multiplies the inputs (the current inputs provided to the terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1401 and 1402 convert into input voltages to be provided to the control gates CG0, CG1, CG2, and CG3) by the weights stored in the memory array, and then sums all the results (cell currents) to produce an output that appears on BL0 - BLN and will be the input to the next layer or the input to the final layer. By performing the multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also highly efficient. Here, the inputs are provided on the control gate lines (CG0, CG1, CG2, and CG3), and the outputs appear on the bit lines (BL0–BLN) during a read operation. The current placed on each bit line performs the summation function of all the currents from the memory cells connected to that particular bit line.

[0157] The VMM array 1400 implements unidirectional tuning for the non-volatile memory cells in the memory array 1403. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be performed, for example, using the precise programming techniques described below. If too much charge is placed on the floating gate (such that an incorrect value is stored in the cell), the cell must be erased, and the sequence of partial programming operations must start over. As shown, two rows sharing the same erase gate (such as EG0 or EG1) need to be erased together (which is called page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

[0158] Table 7 shows the operating voltages for the VMM array 1400. The columns in the table indicate the voltages on the word line for the selected cell, the word line for the unselected cell, the bit line for the selected cell, the bit line for the unselected cell, the control gate for the selected cell, the control gate for the unselected cell in the same sector as the selected cell, the control gate for the unselected cell in a different sector from the selected cell, the erase gate for the selected cell, the erase gate for the unselected cell, the source line for the selected cell, and the source line for the unselected cell. The rows indicate read, erase, and program operations.

[0159] Table 7: Figure 14 Operation of the VMM array 1400

[0160]

[0161]

[0162] Figure 15 shows the neuron VMM array 1500, which is particularly suitable for Figure 3 the memory cell 310 shown, and serves as the synapse and component of the neuron between the input layer and the next layer. The VMM array 1500 includes a memory array 1503 of non-volatile memory cells, a reference array 1501 of first non-volatile reference memory cells, and a reference array 1502 of second non-volatile reference memory cells. The EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1500 is similar to the VMM array 1400, except that the VMM array 1500 implements bidirectional tuning, where each individual cell can be fully erased, partially programmed, and partially erased as needed to achieve the desired charge amount on the floating gate due to the use of separate EG lines. As shown, the reference arrays 1501 and 1502 convert the input current in the terminals BLR0, BLR1, BLR2, and BLR3 into the control gate voltages CG0, CG1, CG2, and CG3 to be applied to the memory cells in the row direction (through the action of the diode-connected reference cells via the multiplexer 1514). The current output (neuron) is in the bit lines BL0 - BLN, where each bit line sums all the currents from the non-volatile memory cells connected to that particular bit line.

[0163] Table 8 shows the operating voltages for the VMM array 1500. The columns in the table indicate the voltages on the word lines for the selected cells, the word lines for the unselected cells, the bit lines for the selected cells, the bit lines for the unselected cells, the control gates for the selected cells, the control gates for the unselected cells in the same sector as the selected cells, the control gates for the unselected cells in a different sector from the selected cells, the erase gates for the selected cells, the erase gates for the unselected cells, the source lines for the selected cells, and the source lines for the unselected cells. The rows indicate the read, erase, and program operations.

[0164] Table 8: Figure 15 Operation of the VMM array 1500

[0165]

[0166]

[0167] Figure 16 shows the neuron VMM array 1600, which is particularly suitable for Figure 2 the memory cell 210 shown, and serves as the synapse and component of the neuron between the input layer and the next layer. In the VMM array 1600, the inputs INPUT0,..., INPUT N are received on the bit lines BL0,... BL N respectively, and the outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on the source lines SL0, SL1, SL2, and SL3 respectively.

[0168] Figure 17 shows the neuron VMM array 1700, which is particularly suitable for Figure 2 the memory cell 210 shown, and serves as the synapse and component of the neuron between the input layer and the next layer. In this example, the inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on the source lines SL0, SL1, SL2, and SL3 respectively, and the outputs OUTPUT0,... OUTPUT N are generated on the bit lines BL0,…, BL N respectively.

[0169] Figure 18 shows the neuron VMM array 1800, which is particularly suitable for Figure 2 the memory cell 210 shown, and serves as the synapse and component of the neuron between the input layer and the next layer. In this example, the inputs INPUT0,…, INPUT M are received on the word lines WL0,…, WL M respectively, and the outputs OUTPUT0,... OUTPUTN are generated on bit lines BL0, …, BL N .

[0170] Figure 19 shows neuron VMM array 1900, which is particularly suitable for Figure 3 memory cell 310 as shown, and serves as the synapse and component of the neuron between the input layer and the next layer. In this example, inputs INPUT0, …, INPUT M are received on word lines WL0, …, WL M respectively, and outputs OUTPUT0, ... OUTPUT N are generated on bit lines BL0, …, BL N .

[0171] Figure 20 shows neuron VMM array 2000, which is particularly suitable for Figure 4 memory cell 410 as shown, and serves as the synapse and component of the neuron between the input layer and the next layer. In this example, inputs INPUT0, …, INPUT n are received on vertical control gate lines CG0, …, CG N respectively, and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0172] Figure 21 shows neuron VMM array 2100, which is particularly suitable for Figure 4 memory cell 410 as shown, and serves as the synapse and component of the neuron between the input layer and the next layer. In this example, inputs INPUT0 to INPUT N are received on the gates of bit line control gates 2901-1, 2901-2 to 2901-(N-1) and 2901-N, which are coupled to bit lines BL0 to BL N respectively. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0173] Figure 22 shows neuron VMM array 2200, which is particularly suitable for Figure 3 memory cell 310 as shown, Figure 5 memory cell 510 as shown and Figure 7 memory cell 710 as shown, and serves as the synapse and component of the neuron between the input layer and the next layer. In this example, inputs INPUT0, …, INPUT M are on word lines WL0, …, WL Mare received on and outputs OUTPUT0, …, OUTPUT N are respectively generated on bit lines BL0, …, BL N thereon.

[0174] Figure 23 shows a neuron VMM array 2300, which is particularly applicable to Figure 3 the memory cell 310 shown, Figure 5 the memory cell 510 shown and Figure 7 the memory cell 710 shown, and serves as the synapse and component of the neuron between the input layer and the next layer. In this example, inputs INPUT0 to INPUT M are received on control gate lines CG0 to CG M thereon. Outputs OUTPUT0, …, OUTPUT N are respectively generated on vertical source lines SL0, …, SL N thereon, where each source line SL i is coupled to the source lines of all memory cells in column i.

[0175] Figure 24 shows a neuron VMM array 2400, which is particularly applicable to Figure 3 the memory cell 310 shown, Figure 5 the memory cell 510 shown and Figure 7 the memory cell 710 shown, and serves as the synapse and component of the neuron between the input layer and the next layer. In this example, inputs INPUT0 to INPUT M are received on control gate lines CG0 to CG M thereon. Outputs OUTPUT0, …, OUTPUT N are respectively generated on vertical bit lines BL0, …, BL N thereon, where each bit line BL i is coupled to the bit lines of all memory cells in column i.

[0176] Test circuit and method

[0177] Figure 25Shows the VMM system 2500. The VMM system 2500 includes a VMM array 2501 (which can be based on any of the previously discussed VMM array designs, such as VMM arrays 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300, and 2400 or other VMM array designs), a low-voltage row decoder 2502, a high-voltage row decoder 2503, a column decoder 2504, a column driver 2505, control logic 2506, a bias circuit 2507, an output circuit block 2508, an input VMM circuit block 2509, an algorithm controller 2510, a high-voltage generator block 2511, an analog circuit block 2515, control logic 2516, and test control logic 2517.

[0178] The input circuit block 2509 serves as an interface to the input terminals from the external input to the memory array 2501. The input circuit block 2509 can include, but is not limited to, a DAC (digital-to-analog converter), a DPC (digital-pulse converter), an APC (analog-pulse converter), an IVC (current-voltage converter), an AAC (analog-analog converter, such as a voltage-voltage scaler), or an FAC (frequency-analog converter). The output circuit block 2508 serves as an interface from the memory array to an external interface (not shown). The output circuit block 2508 can include, but is not limited to, an ADC (analog-to-digital converter), an APC (analog-pulse converter), a DPC (digital-pulse converter), an IVC (current-voltage converter), or an IFC (current-frequency converter). The output circuit block 2508 can include, but is not limited to, an activation function, a normalization circuit, and / or a rescaling circuit.

[0179] The low-voltage row decoder 2502 provides a bias voltage for read and program operations and provides a decoded signal to the high-voltage row decoder 2503. The high-voltage row decoder 2503 provides a high-voltage bias signal for program and erase operations.

[0180] The algorithm controller 2510 provides a control function for the bit lines during program, verify, and erase operations.

[0181] The high-voltage generator block 2511 includes a charge pump 2512, a charge pump regulator 2513, and a high-voltage generation circuit 2514, which provides multiple voltages required for various programming, erasing, program verification, and read operations.

[0182] The test control logic 2517 contains various test control circuits for performing the tests described below with reference to Figures 26 - 31 description.

[0183] Figure 26A reference current source 2600 is shown, which is used during a verification operation after a program operation of one or more non-volatile memory cells, or during other types of tests. For example, the reference current source 2600 can be used for the verification operation of a single non-volatile memory cell, or for the verification operation of a column of non-volatile memory cells (e.g., all cells connected to a specific bit line) or some other grouping of non-volatile memory cells.

[0184] The reference current source 2600 includes a buffer mirror 2601 (the buffer mirror includes a buffer operational amplifier 2602 with an output I REF 2607 and a PMOS transistor 2603), an adjustable bias source 2604, and a two-dimensional array 2605, which includes an array of i rows and j columns of devices 2606, where a specific device 2606 is labeled 2606-(row)(column). Here, various combinations of devices 2606 can be activated, such that the amount of the reference current I REF 2607 output by the buffer mirror 2601 can be adjusted. As shown, there are 16 devices 2606 in the array 2605, and each device can be implemented by a current mirror. The reference current source 2600 basically converts 4 digital inputs into a reference current bias, and the value of the reference current bias is 1 to 16 times of Ibiasunit, where Ibiasunit is provided from the bias source 2604. The reference current source 2600 is basically a thermometer-coded digital-to-current converter, and its buffered output I REF 2607 is a value corresponding to one of 16 levels, and a specific level responds to 4 digital inputs, and this value can be stored by the memory cells in any VMM array discussed previously.

[0185] For example, the bias source 2604 can provide a current Ibiasunit of 1 nA, and this current is mirrored into the devices 2606. Here, the first row consists of devices 2606-11 to 2606-1j, and they are enabled sequentially from left to right, one device 2606 at a time. Then the next row is enabled in a sequential manner from left to right to be added to the first row, which means enabling 5, then 6, then 7, then 8 devices 2606. By enabling the devices 2606 sequentially, the transistor mismatch problem associated with conventional binary decoding can be avoided. The sum of the enabled devices 2606 is then mirrored by the buffer mirror 2601 and output as the current I REF 2607. The bias source 2604 can provide an adjustable range of current Ibiasunit, such as 50 pA / 100 pA / 200 pA / ... / 100 nA. The array 2605 here is shown as a 4×4 array, but it should be understood that the array 2605 can have other sizes, such as 32×32 or 8×32.

[0186] Figure 27 shows a reference sub - circuit 2700, which can be used in any of the devices 2606 in Figure 26 . The reference sub - circuit 2700 includes NMOS transistors 2701 and 2702 configured as shown. Transistor 2702 is a current - mirror - bias transistor that receives current Ibiasunit (discussed above with reference to Figure 26 ), and transistor 2701 is an enabling transistor (to enable the current - mirror - bias transistor 2702 to connect to the output node OUTPUT). The current Ibiasunit is provided, for example, by a diode - connected NMOS transistor (similar to transistor 2702) (not shown).

[0187] Figure 28 shows a sense amplifier 2800 that will be used with a reference current source 2600 during a verification operation after a programming operation of a non - volatile memory cell, a column of non - volatile memory cells, or some other grouping of non - volatile memory cells, or during another type of test. The sense amplifier 2800 receives current I REF 2607, as discussed above with reference to Figure 26 . I REF 2607 can be modeled as a PMOS transistor 2813, where the gate is controlled by VI REF 2814. The sense amplifier 2800 further includes an inverter 2801, a current source 2802 (which is used to limit the current in the inverter 2801), switches 2803 and 2806, a capacitor 2804, and a droop NMOS transistor 2805 (to apply a fixed voltage on the memory bit line). The sense amplifier 2800 receives current I REF 2607 from the reference current source 2600, and this current can be, for example, one of sixteen possible levels to be stored in the non - volatile memory cells of the VMM array. The sense amplifier 2800 is coupled to a cell 2808, which is the non - volatile memory cell whose content is to be verified. When the NMOS transistor 2805 is turned on, the cell 2808 consumes current I CELL . Alternatively, the cell 2808 can be replaced by a column 2809 (for the sake of the drawing, this column will consume a current that will still be referred to as I CELL , which will be the neuron current consumed by the column 2809).

[0188] In an embodiment, I REF2607 starts at the lowest possible value (e.g., the lowest of 16 possible levels that can be stored in cell 2808 or column 2809), and then increases sequentially to each subsequent level for the verification operation. Switch 2806 can be closed to produce an initial state of capacitor 2804 (such as grounding or precharging the voltage to provide offset cancellation). Switch 2803 can be closed to equalize the input and output of inverter 2801, which removes the offset relative to inverter 2801 for comparison during the verification operation. During the verification operation, switches 2806 and 2803 are opened. If I CELL >= I REF 2607, the voltage on node 2810 will decrease, which in turn capacitively couples through capacitor 2804, causing the voltage on node 2811 to decrease, resulting in the inverter output switching to "1", which means the input of inverter 2801 will be a "0" value and the output of inverter 2801 will be a "1" value. If I CELL < I REF 2607, the voltage on node 2810 will increase, which in turn capacitively couples through capacitor 2804, causing the voltage on node 2811 to increase, resulting in the inverter output switching to "0", which means the input of inverter 2801 will switch to a "1" value and the output of inverter 2801 will switch to a "0" value. The value of I REF 2807 at this time corresponds to the value stored in cell 2808.

[0189] Figure 29A Shown is a verification ramp analog-to-digital converter (ADC) 2900 that will be used with reference current source 2600 during the verification operation of non-volatile memory cell 2930 or column 2931 after a program pulse operation, such as to verify whether a memory cell reaches a target current during a weight tuning process or during another type of test, such as to verify trailing memory bits (e.g., outlier bits) in a memory array that fail to meet the cell current requirements. I CELL 2906 is the output current from cell 2930 or column 2931. Verification ADC 2900 converts I CELL 2906 into a series of digital output bits with an output of output 2940, where output 2940 indicates the value stored in cell 2930 or column 2931.

[0190] Verification ADC 2900 includes operational amplifier 2901, adjustable capacitor 2902, operational amplifier 2904, counter 2920, and switches 2908, 2909, and 2910. Adjustable capacitor 2902 pairs I CELL 2906 relative to the current I REFIntegration is performed. During the initialization phase, switch 2908 is closed. The Vout 2903 of operational amplifier 2901 and the input to the inverting input of operational amplifier 2901 will become equal to the value of the reference voltage VREF applied to the non-inverting input of operational amplifier 2901. Thereafter, switch 2908 is opened, and during a fixed time period tref, switch 2910 is closed, and the neuron current I CELL 2906 is integrally increased. During the fixed time period tref, Vout 2903 rises, and its slope reflects I CELL 2906 value. Thereafter, during the time period tmeas, by opening switch 2910 and closing switch 2909, the constant reference current I REF provided by the adjustable current source 2807 is integrally decreased, and during this time period Vout decreases, where tmeas is the time required to integrally decrease Vout to VREF.

[0191] When VOUT 2903 > VREF, the output EC 2905 of operational amplifier 2904 will be high, and vice versa will be low. EC2905 thus generates a pulse, the width of which reflects the time period tmeas, which in turn is proportional to the current I CELL 2906.

[0192] Optionally, the output EC 2905 is input to a counter 2920, which counts the number of received clock pulses 2921 when the output EC2905 is high, and will generate an output 2940, which will be a set of digital bits representing the digital count of the number of clock pulses 2921 that occur when EC 2905 is high, and this number is directly proportional to I CELL 2906, which corresponds to the value stored in cell 2930 or column 2931.

[0193] Figure 29BA verification ramp analog-to-digital converter 2950 is shown, which includes a current source 2953 (representing the received neuron current, Ineu or the current of a single memory cell), a switch 2954, a variable capacitor 2952, and a comparator 2951. The comparator receives, at its non-inverting input, the voltage formed across the variable capacitor 2952 (denoted as Vneu), and receives a configurable reference voltage Vreframp at its inverting input and generates an output Cout. A circuit for clearing the voltage across the variable capacitor 2952 is not shown. Vreframp ramps up (steps) in discrete levels with each comparison clock cycle. The comparator 2951 compares Vneu with Vreframp, and thus when Vneu > Vreframp, the output Cout will be "1", and otherwise will be "0". Therefore, the output Cout will be a pulse, the width of which varies in response to the value of Ineu. A larger Ineu will cause Cout to be "1" for a longer period of time, i.e., a wider pulse of the output Cout. A digital counter 2960 converts the output Cout into a digital output bit DO[n:0] 2970, which reflects the number of clock cycles 2961 during which Cout has a "1" value. Alternatively, the ramp voltage Vreframp is a continuous ramp voltage. A multi-ramp implementation that can reduce the conversion time by using a coarse-fine ramp conversion algorithm. A first coarse reference ramp reference voltage ramps in a fast manner to find the sub-range of each Ineu. Next, a fine reference ramp reference voltage is used for each sub-range separately to convert the Ineu current within the corresponding sub-range. More than two coarse / fine steps or more than two sub-ranges are possible.

[0194] Other ADC architectures can be used as the verification ADC, such as flash ADC, SAR (successive approximation register) ADC, algorithm ADC, pipelined ADC, Σ-Δ ADC, but not limited to.

[0195] Figure 30 The previously referenced Figure 25 An implementation of the high-voltage generation circuit 2511 described previously is shown. The high-voltage generation circuit 2511 can be used with any of the VMM arrays discussed previously. The high-voltage generation circuit 2511 includes a charge pump 2512 and a high-voltage generation circuit 2514. The charge pump 2512 receives an input 3004 and generates a high voltage 3005, which is then provided to high-voltage generators 3002 and 3003. The high-voltage (HV) generator (HVDAC_EG) 3002 is an HV digital-to-analog converter that provides a voltage, denoted as V, in response to digital bits 3006 and the received high voltage 3005. EG3008, such as an incremental voltage, is suitable for being applied to an erase gate terminal of a split-gate flash memory cell. The high voltage generator (HVDAC CGSL) 3003 is an HV digital-to-analog converter that provides voltages in response to digital bits 3007 and the received high voltage 3005, represented as V CG 3009 and V SL 3010, such as an incremental voltage, is suitable for being applied to a control gate terminal and a source line terminal of a split-gate flash memory cell.

[0196] Figure 31 Shows the previously referenced Figure 25 Described VMM system 2500, but shown here in a test configuration. The test control logic component 2517 provides control signals to other components of the VMM system 2500 (shown in Figure 25 but not shown in Figure 31 ), such as the VMM array 2501, row decoder 2502, column decoder 2504, input block 2509, high voltage decoder 2503, column driver 2505, high voltage generation block 2511, analog block 2515, algorithm controller 2510, and output circuit block 2508 to implement one or more test algorithms 3100. The VMM array 2501 receives control signals from the row decoder 2502, thereby asserting one or more rows within the VMM array 2501. The VMM array 2501 provides signals from one or more bit lines to the column decoder 2504, and then the column decoder provides the output from one or more bit lines to the output circuit block 2508. The output circuit block 2508 may include an analog-to-digital converter block (such as the verification ADC 2900 previously referenced in Figure 29A or the verification ramp ADC 2950 previously referenced in Figure 29B ), and the analog-to-digital converter block provides a digital output representing the analog current received by the output circuit block 2508 from the VMM array 2501.

[0197] Table 9 contains exemplary values applied to word lines, control gate lines, erase gate lines, source gate lines, and bit lines within the VMM array 2501 during program, erase, read, and verify operations to be performed on individual memory cells; verifies neuron and read neuron operations performed on selected bit lines coupled to a column of memory cells; and read array operations, thereby reading each bit line, where each bit line is coupled to a column of memory cells.

[0198] Table 9: Exemplary values for operations within VMM array 2501

[0199]

[0200]

[0201] Now, the test algorithm 3100 shown in Figure 31 will be executed and further details of the test type described in further detail in Figures 32 - 44 will be implemented by the test control logic component 2517 and other components of the VMM system 2500.

[0202] Refer to Figure 32 , the bitline neural read test 3101 measures the values in all memory cells simultaneously coupled to the bitlines. That is, the bitline neural read test 3101 reads the neurons in the VMM array. First, the row decoder 2502 asserts all wordlines in the array (step 3201). Second, the bitlines are selected (asserted) by the column decoder 2504 (step 3202). Third, a read is performed on the bitline, for example, by the sense amplifier 2800 that senses the current received from the bitline (step 3203). Fourth, the value of the selected bitline can be determined by comparing the reference current generated by the reference current source 2600 to determine whether the non-volatile memory cells (i.e., neurons) coupled to the selected bitline contain the desired value (step 3204).

[0203] Refer to Figure 33 , the bitline neural measurement test 3102 is similar to the bitline neural read test 3101. The row decoder 2502 asserts all wordlines (step 3301). The bitlines are selected by the column decoder 2504 (step 3302). The current consumed by the bitline during the read operation is measured (step 3303). Here, different from the bitline neural read test 3101, the current from the selected bitline is measured without comparing it with a reference current.

[0204] Refer to Figure 34 , during the LSB screen test 3103, the row decoder 2502 asserts all wordlines (step 3401), and the column decoder 2504 asserts all bitlines (step 3402). Deep programming is performed on all memory cells in the VMM array 2501 (step 3403). Deep programming programs all memory cells beyond the normal program state used for inference reads. It is performed with a longer program timing or a higher program voltage compared to the program timing or program voltage normally used in operation. Then the total current received from all bitlines is measured (step 3404). The total current of the deep programmed array is expected to be much less than the LSB value. Additionally, each individual cell is checked to ensure that the current from the individual cell is also below the LSB value, such as 50 - 100 pA. This type of test is suitable for testing during the manufacturing process to quickly identify defective dies.

[0205] Refer to Figure 35, during the bit line sampling screen test 3104, a memory cell or a group of memory cells is programmed to a specific level, e.g., Lx, where x ranges from 1 to N, and N is the total number of levels that can be stored in the cell (e.g., N = 16) (step 3501). Then the bit line current (meaning the current consumed by a cell or a group of cells in one of the selected bit lines, called I BL ) is measured K times (step 3502). For example, if K = 8, the bit line current is measured 8 times. Then, based on the K measurements in step 3502 (i.e., I BL1 …I BLK ), the average value (I AVG ) is calculated (step 3503).

[0206] Next, for I AVG , each of the K current measurement results I BL1 …I BLK is checked (step 3504). If I BLi (where i ranges from i to K) > (I AVG + threshold 3505) or I BLi < (I AVG – threshold 3506), the bit line is considered defective. Then each cell in the defective bit line is checked, and the defective cell is replaced with a redundant cell (such a cell from a redundant row or redundant column).

[0207] Figure 36 shows another embodiment of the bit line sampling screen test 3104. The voltage V CG is measured by forcing the current Iref into the bit line at K different times (step 3601). For example, the voltage V CG can be scanned until the bit line current matches the fixed Iref, and a specific V CG can be measured and stored. The fixed Iref can be provided by the reference current source 2600, and the operation of verifying whether the bit line current matches the fixed Iref can be performed by the sense amplifier 2800. Then, the average value V CG is calculated from the K different V AVG values. Next, for V AVG , each of the K measured V CG voltages is checked (step 3603). If V CGi (where i ranges from i to K) > (V AVG + threshold 3604) or V CGi < (V AVG - threshold 3605), the bit line is considered defective. Then each cell in the defective bit line is checked, and the defective cell is replaced with a redundant cell (redundant row or column).

[0208] During the read transition point test 3105, coarse and fine read reference current trimming is performed using different levels of Iref in the read operation. The purpose of the read transition point test 3105 is to show whether the selected memory cells can pass a pre-determined current percentage target, such as about 40% of a fully erased cell for an erased cell or about 5% of a fully programmed cell for a programmed cell. This is to ensure that the memory cells are within the main distribution, rather than being trailing memory cells or trailing bits (i.e., statistical outliers), because trailing memory cells or trailing bits can cause potential reliability problems during the operational lifetime.

[0209] Reference Figure 37 , during the read window check test 3107, the test cell is tested to ensure that it can store each of the N possible levels. First, the cell is programmed to a target value representing one of the N values (step 3701). Next, a verify operation is performed to determine whether the value stored in the cell is within an acceptable window 3710 of values around the target value (step 3702). Steps 3701 and 3702 are repeated for each of the N values (step 3703). The acceptable window 3710 can be different for each N value. If any instance of step 3702 being performed indicates that the value stored in the cell is outside the acceptable value window around the target value, the cell is identified as bad. The read window check test 3107 can be performed by the sense amplifier 2800, ADC 2900, ADC 2950, or another component. This can be useful for performing weight tuning on the memory cells. The above has been explained in an embodiment where a fixed window is used for each of the N values centered on a nominal value. It should be understood that in another embodiment, upper and lower thresholds are utilized for each of the N values, and these thresholds need not be the same among all N values and do not exceed this range.

[0210] Reference Figure 38 , during the read calibration test 3108, the leakage of a cell or a group of cells, such as cells coupled to a bit line, is measured (step 3801), the measured leakage (I LEAKAGE ) is stored (step 3802), and the measured leakage value is later used during the read operation to compensate for leakage over various combinations of process / voltage / temperature (PVT) (step 3803). In one embodiment, multiple cells are each programmed with a known value. The word line and control gate line are set to ground, and the bit line is set to a read bias voltage. A sequence of different reference currents is injected into the array, and the resulting data is read out by a sense amplifier such as ADC circuit 2900 or 2950 or sense amplifier 2800. The injected current that produces the best result (compared to the known value programmed into the cell) is stored as I LEAKAGE . Thereafter, ILEAKAGE Applied during the read operation of the same cell, such as by subtracting the stored leakage level from the converted data during the read operation to compensate for leakage occurring within the selected cell.

[0211] Reference Figure 39 , during the read slope test 3109, for two reference currents, namely CG1 at current IR1 and CG2 at current IR2, determine the I-V slope factor of the control gate voltage. The first step is to determine the logarithmic slope factor of the selected non-volatile memory cell when the selected non-volatile memory cell is operating in the subthreshold region (step 3901). The second step is to store the logarithmic slope factor (step 3902). The third step is to determine the linear slope factor of the selected non-volatile memory cell when the selected non-volatile memory cell is operating in the linear region (step 3903). The fourth step is to store the linear slope factor (step 3904). The fifth step is to utilize one or more of the logarithmic slope factor and the linear slope factor when programming the selected cell to a target current (step 3905).

[0212] Reference Figure 40 , during the read neuron identification test 3110, read the neuron (bit line) without checking the value against a desired value. The first step is to measure the current in the bit line and store the measured value (step 4001). The second step is to perform the read virtual neuron test 4010 as described below for a predetermined amount of time, such as the aging time during the identification process. The third step is to measure the current from the bit line (step 4003). The fourth step compares the measured current with the stored measured current from step 4001 (step 4004). If the difference is greater than or less than a certain amount, the bit line is considered a bad bit line.

[0213] The read virtual neuron test 4010 includes a series of steps. The first step is for the row decoder to assert all word lines in the array (step 4011). The second step is for the column decoder to assert all bit lines in the array to select all columns of the non-volatile memory cells (step 4012). The third step is to perform a read operation on the array without checking the read output (read condition) (step 4013). The read virtual neuron test 4010 is used as a read stress on the array for aging purposes.

[0214] Reference Figure 41, during the soft erase test 3111, the entire array or a sector portion is tested to check the erase performance of the memory array. The first step is to erase the non-volatile memory cells in the array by applying a sequence of voltages to the terminals of each non-volatile memory cell in the non-volatile memory cells in the array, where the voltages in the sequence of voltages increase over time with a fixed step size (step 4101). This erases the cells in an incremental manner, for example, by stepping the voltage on the erase gate in a stepped manner between 5 - 12.5 volts, increasing in steps of, for example, 0.5 or 1 volt. Erasing in this way reduces the stress on the memory cells. The second step is to read all the non-volatile memory cells to determine the effect of the erase step (step 4102), for example, by determining that the cell current after the erase in step 4101 is within an acceptable window around the nominal value. Optionally, a durability test can be performed to determine how many program / erase cycles can be sustained, or a background test can be performed to transition the array to an erased state.

[0215] Reference Figure 42 , during the soft program test 3112, the entire array or a row or a cell is tested. The first step is to program the non-volatile memory cells in the array by applying a sequence of voltages to the terminals of each non-volatile memory cell in the array, where the voltages in the sequence of voltages increase over time with a fixed step size (step 4201). In an incremental manner, for example, the cells are programmed with a step difference of 10 mV or 0.3 V or 1 V between 3 - 10 volts to check the program performance of the memory array. Programming in this way reduces the stress on the memory cells. The second step is to read all the non-volatile memory cells to determine the effect of the programming step (step 4202), for example, by determining that the cell current after the programming in step 4201 is within an acceptable window around the nominal value. Optionally, a durability test or a background test can be utilized.

[0216] Reference Figure 43 , a read verification test 3106 can be performed. The first step is to program a plurality of non-volatile memory cells to store one of N different values, where N is the number of different levels that can be stored in any non-volatile memory cell (step 4301). The second step is to measure the current consumed by the plurality of non-volatile memory cells (step 4302). The third step compares the measured current with a target value (step 4303). The fourth step is to store an identification of the plurality of non-volatile memory cells as defective if the difference between the measured value and the target value exceeds a threshold factor (step 4304).

[0217] Reference Figure 44, a checkerboard verification test 3113 can be performed, where the test pattern is implemented using a checkerboard or pseudo-checkerboard pattern, and the sampling levels are measured instead of all possible levels (e.g., 4 levels, L0, Ln, Ln / 4, Ln*3 / 4 instead of all N levels). For example, a pattern can be used to check the worst-case electric field stress within a memory array (meaning one cell is at a high electric field level and adjacent cells are at a low electric field level).

[0218] In one embodiment, the first step is to program a first set of cells in the plurality of non-volatile memory cells whose levels correspond to the minimum cell current among the N levels (step 4401). The second step is to program a second set of cells in the plurality of non-volatile memory cells whose levels correspond to the maximum cell current among the N levels (step 4402). Each cell in the second set of cells is adjacent to one or more cells in the first set of cells. The third step is to measure the current consumed by the plurality of non-volatile memory cells (step 4403). The fourth step is to compare the measured current with a target value (step 4404). The fifth step is to identify the plurality of non-volatile memory cells as defective if the difference between the measured value and the target value exceeds a threshold (step 4405).

[0219] Table 10 contains other exemplary test patterns of the physical array map that can be used during the checkerboard verification test 3113:

[0220] Table 10: Exemplary test patterns

[0221]

[0222]

[0223] The binning test 3114, the final test 3115, the qualification test 3116, and the data retention test 3117 are a test suite that can be performed during the manufacturing and qualification processes of wafers, dies, or packaged devices that include the VMM system disclosed herein.

[0224] Sorting tests 3114 can be performed on the wafers during the manufacturing process. In one embodiment, the sorting tests 3114 include the following test sets: First, relatively fast tests are performed to quickly identify defective wafers or dies, such as soft erase test 3111, soft program test 3112, and various stress mode tests (such as erase gate oxide gox, coupled gate oxide cox, source line oxide sol, reverse interference tunneling rtsts (tunneling from the floating gate to the word line, interference to unselected rows), mass punchthrough mpt (source-to-drain interference of unselected rows), read interference rdist (interference from read conditions)). Second, neural test patterns for the top segment portion and the bottom segment portion are performed, such as LSB screen test 3103 and bit line sampling screen 3104. Compared with the tests performed during the first step, the neural test patterns are more time-consuming, and a period of time is saved due to the identification and screening of defective wafers or dies during the first set of less time-consuming tests.

[0225] Final tests 3115 can be performed on the packaged devices. In one embodiment, the final tests 3115 include the performance of soft erase test 3111 and soft program test 3112. Optionally, test patterns for neural applications can be utilized to reduce the test time instead of a full test, such as testing K out of N levels of M segment portions, or testing all N levels of certain segment portions (such as the top segment portion and the bottom segment portion).

[0226] During qualification tests 3116, virtual bit line read cycles (which are the performance of read operations without actually determining the content of the read data) are performed, and endurance tests are completed by applying soft erase test 3111 and soft program test 3112. Bit line tests are performed instead of individual memory cell tests because bit line reads are used instead of individual memory reads during neural memory applications.

[0227] Data retention test 3117 can include, for example, baking the programmed wafer at a high temperature, such as 250 degrees Celsius, for 24 - 72 hours. In one embodiment, a checkerboard or pseudo-checkerboard test pattern is applied instead of a comprehensive test for digital memory testing. In a neural mode with a read bit line current pattern (instead of each memory cell as done for digital memory), data retention is checked on the bit line current. For example, one query is to check if ΔIBL < + / - p%, where ΔIBL is defined as the difference between the measured bit line current and the desired bit line current. (WholeBLmeas mode, percentage error p% allowed by software neural network modeling for the target accuracy of the neural network). The neural mode of testing ΔIBL is to identify if the bit line output current exceeds or falls below the target, defined herein as a predetermined percentage "p" of the target. Alternatively, each cell can be checked / tested with + / - Δ of the target.

[0228] Other tests can be performed using the hardware and algorithms described herein.

[0229] It should be noted that as used herein, both the terms "above" and "on" inclusively encompass "directly on" (with no intervening material, element, or space therebetween) and "indirectly on" (with intervening material, element, or space therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intervening material, element, or space therebetween) and "indirectly adjacent" (with intervening material, element, or space therebetween), "mounted to" includes "directly mounted to" (with no intervening material, element, or space therebetween) and "indirectly mounted to" (with intervening material, element, or space therebetween), and "electrically coupled to" includes "directly electrically coupled to" (with no intervening material or element electrically connecting the elements together) and "indirectly electrically coupled to" (with intervening material or element electrically connecting the elements together). For example, forming an element "above a substrate" can include directly forming the element on the substrate with no intervening material / element therebetween, and indirectly forming the element on the substrate with one or more intervening material / elements therebetween.

Claims

1. A method for verifying values in a plurality of non-volatile memory cells programmed into an analog neural non-volatile memory cell array, wherein the array is arranged in rows and columns, where each row is coupled to a word line, and each column is coupled to a bit line, and where each word line is selectively coupled to a row decoder, and each bit line is selectively coupled to a column decoder, the method comprising: Asserting all word lines in the array by the row decoder; Asserting bit lines in the array by the column decoder; Sensing a current received from the bit line by a sense amplifier; Generating a reference current by a reference current source, the generating comprising: (i) Receiving a reference current bias; (ii) Receiving a digital input; (iii) Mirroring the reference current bias into a plurality of devices, each of the plurality of devices including a first NMOS transistor and a second NMOS transistor, the first NMOS transistor including a first terminal providing an output current, a second terminal, and a gate receiving an enable signal, the second NMOS transistor including a first terminal coupled to the second terminal of the first NMOS transistor, a second terminal coupled to ground, and a gate receiving the reference current bias; (iv) Enabling one or more of the plurality of devices in response to the digital input by asserting the enable signal for the enabled devices; (v) Mirroring the enabled devices through a buffer mirror to generate the reference current equal to the sum of the output currents generated by the enabled devices; and Comparing the current with the reference current to determine whether the non-volatile memory cell coupled to the bit line contains an expected value.

2. The method according to claim 1, wherein each non-volatile memory cell in the non-volatile memory cell array is a stacked-gate flash memory cell.

3. The method according to claim 1, wherein each non-volatile memory cell in the non-volatile memory cell array is a split-gate flash memory cell.

4. The method according to claim 1, wherein the array is part of a neural network.

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