Fan-out chip packaging method and fan-out chip packaging structure

Abstract

Embodiments of the present invention provide a fan-out chip packaging method and a fan-out chip packaging structure, which relate to the field of semiconductor packaging technology. In the present invention, a chip is mounted on a substrate carrier, and at the same time, a protective carrier with end feet is mounted on the substrate carrier. The protective carrier covers the outside of the chip, and the end feet are respectively arranged on both sides of the chip, thereby playing a supporting role. Moreover, a metal shielding layer is sputtered on the surface of the encapsulant away from the substrate carrier. Compared with the prior art, by setting the protective carrier, the present invention can effectively protect the chip, prevent external dust from falling on the surface and around the chip during the transportation of the packaging structure, and avoid ESD breakdown or defects generated during packaging. At the same time, by setting the protective carrier, combined with the substrate carrier, it can play a good supporting role during the plastic encapsulation process, preventing the encapsulant from warping. And it can achieve the electromagnetic shielding effect of the fan-out packaging structure, and the electromagnetic shielding effect is good.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and more particularly, to a fan-out chip packaging method and a fan-out chip packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, fan-out wafer-level packaging structures are widely used in the semiconductor industry. Generally, the packaging structure involves cutting individual chips from a wafer and then packaging them onto a carrier wafer. The main advantages include high-density integration, small package product size, excellent product performance, fast signal transmission frequency, etc. The fan-out technology mainly enables multi-pin output and a smaller output pin pitch, which is more conducive to product integration.

[0003] However, in highly integrated circuit boards, electronic products need to achieve electromagnetic shielding effects. In fan-out packaging structures, a shielding cover plate is usually directly used to cover the chip. This method has low accuracy and poor electromagnetic shielding effects. In addition, before the shielding cover plate is covered, the chip is directly exposed to the external space and is easily affected by external dust (such as ESD breakdown or packaging defects). In addition, during the fan-out chip packaging process, due to the CTE mismatch of various layer materials, there is an easy problem of plastic package warping. Summary of the Invention

[0004] The objectives of the present invention include, for example, providing a fan-out chip packaging method and a fan-out chip packaging structure that can achieve good electromagnetic shielding effects, avoid plastic package warping, and effectively protect the chip from the influence of external dust.

[0005] Embodiments of the present invention can be implemented as follows:

[0006] In a first aspect, the present invention provides a fan-out chip packaging method, including:

[0007] Mounting a chip on one side surface of a substrate carrier;

[0008] Mounting a protective carrier with end feet on one side surface of the substrate carrier, the protective carrier covering the outside of the chip, and the end feet being arranged on both sides of the chip;

[0009] Forming a potting body by potting on one side surface of the substrate carrier, the potting body being arranged inside and outside the protective carrier and covering the outside of the chip;

[0010] Sputtering a metal shielding layer on the side surface of the potting body away from the substrate carrier;

[0011] Forming a combined wiring layer on the side surface of the potting body away from the metal shielding layer;

[0012] Form solder balls on the side of the combined wiring layer away from the metal shielding layer.

[0013] In an alternative embodiment, the pin is hollow, and the step of forming the metal shielding layer on the surface of the encapsulation body away from the base carrier includes:

[0014] Grind the encapsulation body and the protective carrier until the pins are exposed, so that vias penetrating through to the base carrier are formed in the encapsulation body on both sides of the chip;

[0015] Sputter to form the metal shielding layer on the surface of the encapsulation body and at least part of the vias.

[0016] In an alternative embodiment, the step of forming the combined wiring layer on the side of the encapsulation body away from the metal shielding layer includes:

[0017] Groove the surface of the base carrier on the side away from the metal shielding layer to form a base groove, the base groove penetrates through the base carrier and reaches the chip and the pins;

[0018] Form a base metal layer in the base groove, the base metal layer is electrically connected to both the metal shielding layer and the chip;

[0019] Form a first dielectric layer on the surface of the base carrier on the side away from the metal shielding layer, the first dielectric layer covers the base metal layer;

[0020] Groove the first dielectric layer to form a first groove, the first groove penetrates through the first dielectric layer and reaches the base metal layer;

[0021] Form a first metal layer in the first groove, the first metal layer is electrically connected to the base metal layer;

[0022] Form a second dielectric layer on the surface of the first dielectric layer on the side away from the metal shielding layer, the second dielectric layer covers the first metal layer;

[0023] Groove the second dielectric layer to form a second groove, the second groove penetrates through the second dielectric layer and reaches the first metal layer;

[0024] Form a second metal layer in the second groove, the second metal layer is electrically connected to the first metal layer;

[0025] Wherein, the solder balls are arranged on the second metal layer.

[0026] In an alternative embodiment, before the step of forming a combined wiring layer on a side of the encapsulation body away from the metal shielding layer, the method further includes:

[0027] Peel off the substrate carrier, and expose the chip and the encapsulation body;

[0028] Form a base dielectric layer on a surface of the encapsulation body on a side away from the metal shielding layer, and the base dielectric layer covers the chip.

[0029] In an alternative embodiment, the step of forming a combined wiring layer on a side of the encapsulation body away from the metal shielding layer includes:

[0030] Form a base groove by grooving on a surface of the base dielectric layer on a side away from the metal shielding layer, the base groove penetrates through the base dielectric layer, and penetrates through to the chip and the pins;

[0031] Form a base metal layer in the base groove, and the base metal layer is electrically connected to both the metal shielding layer and the chip;

[0032] Form a first dielectric layer on a surface of the base dielectric layer on a side away from the metal shielding layer, and the first dielectric layer covers the base metal layer;

[0033] Form a first groove by grooving on the first dielectric layer, the first groove penetrates through the first dielectric layer, and penetrates through to the base metal layer;

[0034] Form a first metal layer in the first groove, and the first metal layer is electrically connected to the base metal layer;

[0035] Form a second dielectric layer on a surface of the first dielectric layer on a side away from the metal shielding layer, and the second dielectric layer covers the first metal layer;

[0036] Form a second groove by grooving on the second dielectric layer, the second groove penetrates through the second dielectric layer, and penetrates through to the first metal layer;

[0037] Form a second metal layer in the second groove, and the second metal layer is electrically connected to the first metal layer;

[0038] Wherein, the solder balls are disposed on the second metal layer.

[0039] In an alternative embodiment, the step of forming a second metal layer in the second groove includes:

[0040] Electroplate a conductive metal layer in the second groove;

[0041] Electroplate a conductive column on the conductive metal layer.

[0042] In an alternative embodiment, before the step of mounting the chip on one surface of the substrate carrier, the method further includes:

[0043] Attaching an adhesive layer on one surface of the substrate carrier.

[0044] In an alternative embodiment, after the step of ball mounting on the conductive posts, the method further includes:

[0045] Cutting the encapsulant and the combined wiring layer along the midline of the via hole.

[0046] In a second aspect, the present invention provides a fan-out chip package structure, which is prepared by using the fan-out chip package method according to any one of the foregoing embodiments, and includes:

[0047] A base dielectric layer;

[0048] A chip mounted on the base dielectric layer;

[0049] An encapsulant disposed on the base dielectric layer and covering the chip, and vias are provided on the encapsulant on both sides of the chip;

[0050] A metal shielding layer disposed on one surface of the encapsulant away from the base dielectric layer;

[0051] A combined wiring layer disposed on one surface of the base dielectric layer away from the metal shielding layer;

[0052] Solder balls disposed on one surface of the combined wiring layer away from the metal shielding layer.

[0053] A base groove is provided on the base dielectric layer, the base groove penetrates through the base dielectric layer and extends to the chip and the via hole, and a base metal layer is provided in the base groove, and the base metal layer is electrically connected to both the metal shielding layer and the chip;

[0054] The first dielectric layer covers the base metal layer, and a first groove is provided on the first dielectric layer, the first groove penetrates through the first dielectric layer and extends to the base metal layer, and a first metal layer is provided in the first groove, and the first metal layer is electrically connected to the base metal layer;

[0055] The second dielectric layer covers the first metal layer, and a second groove is provided on the second dielectric layer, the second groove penetrates through the second dielectric layer and extends to the first metal layer, and a second metal layer is provided in the second groove, and the second metal layer is electrically connected to the first metal layer;

[0056] Among them, the solder balls are disposed on the second metal layer.

[0057] The beneficial effects of the embodiments of the present invention include, for example:

[0058] The fan-out chip packaging method and the fan-out chip packaging structure provided by the embodiments of the present invention mount a chip on a substrate carrier, and at the same time mount a protective carrier with pins on the substrate carrier. The protective carrier covers the outside of the chip, and the pins are respectively disposed on both sides of the chip, thereby playing a supporting role. After the protective carrier is mounted, a potting body is formed by potting on the substrate carrier. The potting body is located inside and outside the protective carrier at the same time, and covers the outside of the chip. And, a metal shielding layer is formed by sputtering on one surface of the potting body away from the substrate carrier, and the potting body serves as a sputtering substrate. Then, a combined wiring layer is formed on one surface of the potting body away from the metal shielding layer, and solder balls are formed on one side of the combined wiring layer away from the metal shielding layer. Compared with the prior art, by providing a protective carrier, the present invention can effectively protect the chip, avoid external dust from falling on the surface and around the chip during the transfer process of the packaging structure, and avoid ESD breakdown phenomena or defects generated during packaging (for example: voids, chip surface cracking, etc.). At the same time, by providing a protective carrier, combined with the substrate carrier, it can play a good supporting role during the potting process and avoid warping of the potting body. And, by sputtering on the surface of the potting body to form a metal shielding layer, the electromagnetic shielding effect of the fan-out packaging structure can be realized, and the electromagnetic shielding effect is good. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can be obtained based on these drawings.

[0060] Figure 1 It is a step block diagram of a fan-out chip packaging method provided by the first embodiment of the present invention;

[0061] Figures 2 to 13 It is a process flow diagram of a fan-out chip packaging method provided by the first embodiment of the present invention;

[0062] Figure 14 It is a schematic diagram of a fan-out chip packaging structure provided by the first embodiment of the present invention.

[0063] Icons: 100 - Fan - out chip package structure; 110 - Substrate carrier; 111 - Substrate groove; 113 - Substrate metal layer; 120 - Chip; 121 - Pad; 122 - Adhesive layer; 130 - Encapsulant; 140 - Metal shielding layer; 150 - Composite wiring layer; 151 - First dielectric layer; 152 - First groove; 153 - First metal layer; 154 - Second dielectric layer; 155 - Second groove; 156 - Second metal layer; 160 - Solder ball; 170 - Protection carrier; 171 - Terminal pin; 173 - Via hole. Detailed implementation manners

[0064] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. The components of the embodiments of the present invention usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0065] Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0066] It should be noted that: Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0067] In the description of the present invention, it should be noted that if terms such as "upper", "lower", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the invention is usually placed during use, it is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation of the present invention.

[0068] In addition, terms such as "first", "second", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0069] As disclosed in the background art, for the existing fan-out package structure, in order to achieve the electromagnetic shielding effect, a shielding cover plate is usually adopted. This method undoubtedly has poor accuracy, is difficult to cover the chip, and has a poor shielding effect. In addition, during the process of fan-out wafer chip packaging, due to the mismatch of the CTE of various materials, there is easily a problem of plastic package warping. Moreover, the control of dust fall is extremely strict in fan-out wafer-level chip packaging. Tiny dust is extremely likely to cause ESD breakdown or defects in the package (such as voids, chip surface cracking, etc.) on the chip.

[0070] To solve the above problems, the embodiments of the present invention provide a fan-out chip packaging method and a fan-out chip packaging structure. It should be noted that, without conflict, the features in the embodiments of the present invention can be combined with each other.

[0071] First Embodiment

[0072] Refer to Figure 1 and Figure 14 The fan-out chip packaging method provided in this embodiment is used to prepare a fan-out chip packaging structure 100, which can achieve a good electromagnetic shielding effect, avoid plastic package warping, and effectively protect the chip 120 to avoid the influence of external dust on the chip 120.

[0073] The fan-out chip packaging method provided in this embodiment includes the following steps:

[0074] S1: Mount the chip 120 on one side surface of the base carrier 110.

[0075] Combined with reference to Figure 2 , specifically, take a carrier. Multiple chips 120 can be mounted on the base carrier 110 at the same time, and an adhesive layer 122 needs to be coated on the surface of the base carrier 110 to facilitate bonding the multiple chips 120 to the base carrier 110. Among them, solder pads 121 are provided on all the multiple chips 120, and the solder pads 121 are placed downward, that is, the solder pads 121 on the chip 120 are attached to the base carrier 110. At this time, the adhesive layer 122 can also play a buffering role to ensure that both the surface of the chip 120 and the solder pads 121 can be bonded to the base carrier 110. The adhesive layer 122 can be at least one of a UV adhesive layer, an adhesive, an epoxy resin (Epoxy), and a polyimide (PI).

[0076] In this embodiment, the base carrier 110 can select a substrate, and the substrate can adopt conventional substrate materials such as glass and silicon oxide.

[0077] S2: Mount the protection carrier 170 with end feet 171 on one side surface of the base carrier 110.

[0078] Combined with reference toFigure 3 Specifically, the protective carrier 170 covers the outside of the chip 120, and the end pins 171 are respectively arranged on both sides of the chip 120. After the chip 120 is mounted, the protective carrier 170 is mounted again. The end pins 171 of the protective carrier 170 are attached to the surface of the base carrier 110, and the protective carrier 170 covers the upper part of the chip 120, which can effectively reduce the contamination of the chip 120 by dust falling around the chip 120, and avoid the ESD problem and the process problems (such as chip 120 being crushed and cracked, plastic encapsulation voids, etc.) caused by the dust. The material of the protective carrier 170 can be the same as that of the base carrier 110.

[0079] S3: A encapsulation body 130 is formed by plastic encapsulation on one side surface of the base carrier 110.

[0080] See in conjunction with Figure 4 Specifically, the encapsulation body 130 is arranged on the inner and outer sides of the protective carrier 170 and covers the outside of the chip 120. After the protective carrier 170 is mounted, the bottom structure is protected by the encapsulation body 130. Specifically, the encapsulation material can be filled on both the inner and outer sides of the protective carrier 170 by using a vacuum plastic encapsulation process, and a completely filled encapsulation body 130 is formed after curing. Of course, a conventional injection molding process can also be used here, and a number of flow holes are opened on the top side of the protective carrier 170 to enable the encapsulation material to flow smoothly into the inner side of the protective carrier 170.

[0081] It should be noted that in this embodiment, due to the use of the protective carrier 170 and in combination with the base carrier 110, it can play a good supporting effect during the plastic encapsulation process, thereby effectively avoiding warping of the encapsulation body 130.

[0082] It should also be noted that in other preferred embodiments of the present invention, the plastic encapsulation step can also be omitted. Before directly mounting the protective carrier 170, an adhesive is applied full in the protective carrier 170, and then the protective carrier 170 with the adhesive is mounted on the base carrier 110, so that the glue is covered around the chip 120, and a glue layer is formed after curing, which can also achieve the function of the encapsulation body 130 in this embodiment. The specific scheme thereof will not be described in detail here.

[0083] S4: A metal shielding layer 140 is formed by sputtering on the side surface of the encapsulation body 130 away from the base carrier 110.

[0084] See in conjunction with Figure 5 and Figure 6, specifically, after forming the encapsulation body 130, first grind the encapsulation body 130 and the protection carrier 170 until the end feet 171 are exposed, so that via holes 173 penetrating through to the base carrier 110 are formed on the encapsulation body 130 on both sides of the chip 120. Then, sputter to form a metal shielding layer 140 on the surface of the encapsulation body 130 and at least part of the via holes 173.

[0085] In this embodiment, the top side of the protection carrier 170 can be used as a grinding stop layer, that is, grind to the top side of the protection carrier 170, and preferably grind off the top side of the protection carrier 170 to expose the end feet 171. Here, the end feet 171 adopt a hollow design and are formed with via holes 173. During the process of sputtering to form the metal shielding layer 140, the metal liquid will at least partially fill the via holes 173, so as to form a metal shielding layer 140 on the surface of the encapsulation body 130, and the metal shielding layer 140 extends to the surface of the base carrier 110 through the via holes 173.

[0086] It should be noted that in this embodiment, the via holes 173 can adopt a metallized via hole process, that is, sputter to form a metal shielding layer 140 on the side wall of the sputtered metal shielding layer 140, retaining the structure of the via holes 173, and it can also be recognized in appearance. Here, the via holes 173 can play a role of identification, facilitating the subsequent cutting process.

[0087] In other preferred embodiments of the present invention, the end feet 171 can also be solidly arranged or filled with buffer materials. Before sputtering the metal shielding layer 140, it is necessary to hollow out part of the end feet 171, so as to form via holes 173 on the encapsulation body 130 on both sides of the chip 120, facilitating the grounding of the metal shielding layer 140 in the subsequent process.

[0088] It should be noted that during sputtering, the entire wafer can be used for metal sputtering to form the metal shielding layer 140, which has higher sputtering efficiency and avoids the non-uniformity caused by metal sputtering of single products.

[0089] S5: Form a combined wiring layer 150 on the surface of the encapsulation body 130 away from the metal shielding layer 140.

[0090] Specifically, after forming the metal shielding layer 140, flip the carrier, and form a combined wiring layer 150 on the surface of the carrier away from the metal shielding layer 140, wherein the combined wiring layer 150 is electrically connected to the chip 120.

[0091] In this embodiment, when performing step S5, the following steps can be specifically adopted:

[0092] S51: Open a groove on the surface of the base carrier 110 away from the metal shielding layer 140 to form a base groove 111.

[0093] Refer to Figure 7 , specifically, the base groove 111 penetrates through the base carrier 110 and extends through to the chip 120 and the terminal pin 171. In this embodiment, the base carrier 110 adopts a substrate structure, and a groove is formed on the base carrier 110 by an etching process to form the base groove 111, wherein a part of the area of the base groove 111 extends through to the pad 121 on the chip 120, and a part of the area extends through to the terminal pin 171.

[0094] S52: Form a base metal layer 113 in the base groove 111.

[0095] Refer to Figure 8 , specifically, the base metal layer 113 is electrically connected to both the metal shielding layer 140 and the chip 120. After the base groove 111 is formed, a copper layer is electroplated in the base groove 111 by using the electroplating process again, so as to form the base metal layer 113. The base metal layer 113 can also be prepared by one method of physical vapor deposition process (PVD), chemical vapor deposition process (CVD), sputtering or electroless plating.

[0096] It should be noted that in this embodiment, due to the existence of the via hole 173 and the fact that the base groove 111 extends to the terminal pin 171, that is, extends to the via hole 173, the accumulation of the etching solution in the area of the edge pad 121 during the etching process can be reduced, and the influence of the oxide generated on the edge pad 121 can be avoided, so that the grounding resistance of the edge pad 121 is unstable. At the same time, the base metal layer 113 contacts the metal shielding layer 140 in the terminal pin 171, so as to facilitate the realization of the electromagnetic shielding function.

[0097] It should also be noted that here, due to the existence of the via hole 173 and the metal shielding layer 140 existing in the via hole 173 at the same time, during the actual electroplating process, the metal shielding layer 140 exposed in the base groove 111 in the via hole 173 can be used as an electroplating lead, that is, the metal shielding layer 140 at the terminal pin 171 can be used as an electroplating lead, which is convenient for the electroplating process and ensures the wiring effect. In addition, since the metal shielding layer 140 at the terminal pin 171 is used as an electroplating lead, the micro-etching electroplating lead process required after the traditional wiring process can be avoided, further simplifying the process steps. Among them, the micro-etching process is prone to the risk of over-etching, directly etching onto the pad and causing problems such as too high resistance, which is not conducive to improving the performance of the product.

[0098] S53: Form a first dielectric layer 151 on the surface of the base carrier 110 away from the metal shielding layer 140.

[0099] Specifically, the first dielectric layer 151 covers the base metal layer 113. The first dielectric layer 151 can be formed by spin-coating a dielectric material. Of course, here it can also be obtained by processes such as physical vapor deposition (PVD) and chemical vapor deposition (CVD). The material of the first dielectric layer 151 can be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc.

[0100] S54: A first groove 152 is formed by grooving on the first dielectric layer 151.

[0101] Refer to Figure 9 , specifically, the first groove 152 penetrates through the first dielectric layer 151 and reaches the base metal layer 113. After the first dielectric layer 151 is formed, patterning can be performed on the first dielectric layer 151, and a patterned opening is formed by using an exposure and development process to complete the preparation of the conductive layer pattern. Of course, here the first groove 152 can also be formed by a laser grooving process. It should be noted that here, since the end foot 171 adopts a hollow design and has a via hole 173, it can play a certain buffering role to make the displacement of the first dielectric layer 151 during the patterning or laser grooving process.

[0102] S55: A first metal layer 153 is formed in the first groove 152.

[0103] Refer to Figure 10 , specifically, the first metal layer 153 is electrically connected to the base metal layer 113. The first metal layer 153 is formed by electroplating, that is, the circuit layer is formed. Of course, here the first metal layer 153 can also be prepared by one of physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, or electroless plating. Preferably, both the first metal layer 153 and the base metal layer 113 are copper layers, which have good electrical properties.

[0104] S56: A second dielectric layer 154 is formed on the surface of the first dielectric layer 151 away from the metal shielding layer 140.

[0105] Specifically, the second dielectric layer 154 can be formed by spin-coating a dielectric material again, and the second dielectric layer 154 covers the first metal layer 153. Here the second dielectric layer 154 can also be obtained by processes such as physical vapor deposition (PVD) and chemical vapor deposition (CVD). At the same time, the material of the second dielectric layer 154 is the same as that of the first dielectric layer 151.

[0106] S57: A second groove 155 is formed by grooving on the second dielectric layer 154.

[0107] Refer to Figure 11, wherein the second groove 155 penetrates through the second dielectric layer 154 and extends through to the first metal layer 153. Specifically, after the second dielectric layer 154 is formed, a laser grooving or opening process is performed on the second dielectric layer 154 again to form the second groove 155. Of course, the second groove 155 can also be formed by a conventional etching process here. Since the end pin 171 is designed to be hollow, the displacement generated during the grooving process can be reduced, making the laser grooving more accurate.

[0108] S58: Form a second metal layer 156 in the second groove 155.

[0109] See in conjunction with Figure 12 , wherein the second metal layer 156 is electrically connected to the first metal layer 153. Specifically, after the second groove 155 is formed, electroplating can be used again to electroplate a layer of metal in the second groove 155. Preferably, a conductive metal layer is electroplated in the second groove 155, and a conductive column is electroplated on the conductive metal layer, that is, the second metal layer 156 is a copper column and protrudes from the second dielectric layer 154.

[0110] It should be noted that in other preferred embodiments of the present invention, the metal shielding layer 140 can also be formed together when performing step S58. That is to say, steps S4 and S5 are performed together, and the metal shielding layer 140 is formed together when generating the copper column by the oxidation-reduction reaction of the electroplating bath solution. Therefore, the metal sputtering process is not required at this time, further simplifying the process steps.

[0111] S6: Form solder balls 160 on the side of the combined wiring layer 150 away from the metal shielding layer 140.

[0112] See in conjunction with Figure 13 , specifically, after the combined wiring layer 150 is formed, the solder balls 160 are formed by stencil printing or ball placement methods. The material of the solder balls 160 can be SnAg, SnAgCu, etc. The solder balls 160 can be arranged on the second metal layer 156 here. In this embodiment, the solder balls 160 are arranged on the second metal layer 156, and a conductive metal layer (UBM) is provided at the bottom of the copper column. The welding performance of the solder balls 160 is improved through the UBM layer.

[0113] S7: Cut the encapsulation body 130 and the combined wiring layer 150 along the midline of the via 173.

[0114] See in conjunction with Figure 14, specifically, after the solder balls 160 are formed, a plurality of cutting trace lines can be set on the encapsulation body 130, where the cutting trace lines can be set along the midlines of the plurality of vias 173, that is, each cutting trace line passes through the midline of the via 173, so as to divide the via 173 into two parts, ensuring that the metal shielding layer 140 in each structure can be grounded through the via 173.

[0115] Please continue to refer to Figure 14 , this embodiment also provides a fan-out chip packaging structure 100, which is prepared by the above method. The fan-out chip packaging structure 100 includes a substrate carrier 110, an encapsulation body 130, a chip 120, a metal shielding layer 140, a combined wiring layer 150, and solder balls 160. The chip 120 is mounted on one side surface of the substrate carrier 110, the encapsulation body 130 is disposed on one side surface of the substrate carrier 110 and covers the chip 120, the combined wiring layer 150 is disposed on the other side surface of the substrate carrier 110 and is electrically connected to the chip 120, and the solder balls 160 are disposed on the combined wiring layer 150. The metal shielding layer 140 is disposed on the surface of the encapsulation body 130 and is electrically connected to the combined wiring layer 150 to achieve grounding. Preferably, the metal shielding layer 140 is a copper layer.

[0116] In this embodiment, a solder pad 121 is disposed on one side surface of the chip 120 for mounting, vias 173 are disposed on the encapsulation bodies on both sides of the chip, the combined wiring layer 150 includes a first dielectric layer 151 and a second dielectric layer 154, a substrate metal layer 113 is disposed on the substrate carrier 110, the substrate metal layer 113 is electrically connected to the solder pad 121, a first metal layer 153 is disposed on the first dielectric layer 151, the first metal layer 153 is electrically connected to the substrate metal layer 113, and a second metal layer 156 is disposed on the second dielectric layer 154, the second metal layer 156 is electrically connected to the first metal layer 153. It should be noted that in this embodiment, vias 173 extending to the substrate carrier 110 are disposed on the encapsulation bodies 130 on both sides of the chip 120, and the metal shielding layer 140 extends to the vias 173 and is electrically connected to the substrate metal layer 113 on the substrate carrier 110, so that the metal shielding layer 140 realizes the grounding function.

[0117] In this embodiment, a substrate groove 111 is provided on the substrate dielectric layer. The substrate groove 111 penetrates the substrate dielectric layer and extends through to the chip 120 and the via hole 173. A substrate metal layer 113 is provided in the substrate groove 111. The substrate metal layer 113 is electrically connected to both the metal shielding layer 140 and the chip 120. The first dielectric layer 151 covers the substrate metal layer 113, and a first groove 152 is provided on the first dielectric layer 151. The first groove 152 penetrates the first dielectric layer 151 and extends through to the substrate metal layer 113. A first metal layer 153 is provided in the first groove 152. The first metal layer 153 is electrically connected to the substrate metal layer 113. The second dielectric layer 154 covers the first metal layer 153, and a second groove 155 is provided on the second dielectric layer 154. The second groove 155 penetrates the second dielectric layer 154 and extends through to the first metal layer 153. A second metal layer 156 is provided in the second groove 155. The second metal layer 156 is electrically connected to the first metal layer 153. Among them, the solder ball 160 is provided on the second metal layer 156.

[0118] In summary, this embodiment provides a fan-out chip packaging method and a fan-out chip packaging structure. The chip 120 is mounted on the substrate carrier 110, and at the same time, a protective carrier 170 with terminal pins 171 is mounted on the substrate carrier 110. The protective carrier 170 covers the outside of the chip 120, and the terminal pins 171 are arranged on both sides of the chip 120, thus playing a supporting role. After the protective carrier 170 is mounted, an encapsulant 130 is formed by encapsulation on the substrate carrier 110. The encapsulant 130 is located on both the inside and outside of the protective carrier 170 and covers the outside of the chip 120. And, a metal shielding layer 140 is formed by sputtering on one surface of the encapsulant 130 away from the substrate carrier 110, and the encapsulant 130 serves as the sputtering substrate. Then, a combined wiring layer 150 is formed on one surface of the encapsulant 130 away from the metal shielding layer 140, and solder balls 160 are formed on one side of the combined wiring layer 150 away from the metal shielding layer 140. By setting the protective carrier 170 in this embodiment, the chip 120 can be effectively protected, preventing external dust from falling on the surface and around the chip 120 during the transfer of the packaging structure, and avoiding ESD breakdown or defects in the packaging (such as voids, cracking on the surface of the chip 120, etc.). At the same time, by setting the protective carrier 170 and combining with the substrate carrier 110, a good supporting role can be played during the encapsulation process, preventing the encapsulant 130 from warping. And, by sputtering a metal shielding layer 140 on the surface of the encapsulant 130, the electromagnetic shielding effect of the fan-out packaging structure can be achieved, and the electromagnetic shielding effect is good.

[0119] Second Embodiment

[0120] Please continue to refer to Figures 1 to 14, this embodiment provides a fan-out chip packaging method for fabricating a fan-out chip packaging structure 100. The basic steps and process methods are the same as those in the first embodiment. For the parts not mentioned in this embodiment, reference can be made to the relevant content in the first embodiment.

[0121] The difference between this embodiment and the first embodiment lies in step S5. In this embodiment, before performing step S5, the following steps need to be executed:

[0122] S5a: Peel off the substrate carrier 110 to expose the chip 120 and the encapsulant 130.

[0123] Specifically, in this embodiment, before performing step S1, an adhesive layer 122 needs to be attached to the substrate carrier 110. The adhesive layer 122 is a UV adhesive layer. After performing step S4, the substrate carrier 110 is flipped, and under the irradiation of UV light, the adhesive layer 122 serves as a separation layer, enabling the substrate carrier 110 to be separated from the encapsulant 130.

[0124] It should be noted that since the substrate carrier 110 needs to be peeled off here, the substrate carrier 110 can adopt a carrier with higher structural strength, and there is no need to consider the subsequent grooving and electroplating processes as in the first embodiment.

[0125] S5b: Form a substrate dielectric layer on the surface of the encapsulant 130 on the side away from the metal shielding layer 140.

[0126] Specifically, the substrate dielectric layer (not shown in the figure) covers the chip 120. The substrate dielectric layer can be formed by spin-coating a dielectric material. Of course, here it can also be obtained through processes such as physical vapor deposition (PVD) and chemical vapor deposition (CVD). The material of the substrate dielectric layer can be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc.

[0127] That is to say, in this embodiment, the substrate dielectric layer is used to replace the substrate carrier 110. The advantage is that a dielectric layer with better performance can be selected as the substrate, and the selection of the substrate carrier 110 is also more extensive. For example, a metal carrier can be selected, which has better structural strength.

[0128] In this embodiment, when performing step S5, the following steps can be specifically taken:

[0129] S51: Groove on the surface of the substrate dielectric layer on the side away from the metal shielding layer 140 to form a substrate groove 111.

[0130] Specifically, the base groove 111 penetrates through the base dielectric layer and reaches the chip 120 and the terminal pin 171. In this embodiment, the base groove 111 can be formed by an etching process or a laser grooving process. Part of the area of the base groove 111 reaches the pad 121 on the chip 120, and part of the area reaches the terminal pin 171.

[0131] It should be noted that the subsequent steps S52 - S58 are the same as those in the first embodiment, and details can be referred to the first embodiment.

[0132] Step S52: Form a base metal layer 113 in the base groove 111.

[0133] Specifically, the base metal layer 113 is electrically connected to both the metal shielding layer 140 and the chip 120. That is, the base metal layer 113 is electrically connected to the metal shielding layer 140 through the via hole 173, and the base metal layer 113 is electrically connected to the chip 120 through the pad 121.

[0134] Step S53: Form a first dielectric layer 151 on the surface of the base dielectric layer away from the metal shielding layer 140.

[0135] Specifically, the first dielectric layer 151 covers the base metal layer 113.

[0136] S54: Groove the first dielectric layer 151 to form a first groove 152.

[0137] Specifically, the first groove 152 penetrates through the first dielectric layer 151 and reaches the base metal layer 113.

[0138] S55: Form a first metal layer 153 in the first groove 152.

[0139] Specifically, the first metal layer 153 is electrically connected to the base metal layer 113.

[0140] S56: Form a second dielectric layer 154 on the surface of the first dielectric layer 151 away from the metal shielding layer 140.

[0141] Specifically, the second dielectric layer 154 covers the first metal layer 153.

[0142] S57: Groove the second dielectric layer 154 to form a second groove 155.

[0143] Specifically, the second groove 155 penetrates through the second dielectric layer 154 and reaches the first metal layer 153.

[0144] S58: Form a second metal layer 156 in the second groove 155.

[0145] Specifically, the second metal layer 156 is electrically connected to the first metal layer 153, and the solder ball 160 is disposed on the second metal layer 156.

[0146] This embodiment provides a fan-out chip packaging structure 100, which is formed by using the above method. The fan-out chip packaging structure 100 includes a substrate dielectric layer, an encapsulant 130, a chip 120, a metal shielding layer 140, a combined wiring layer 150, and solder balls 160. The chip 120 is mounted on one side surface of the substrate dielectric layer. The encapsulant 130 is disposed on one side surface of the substrate dielectric layer and covers the chip 120. The combined wiring layer 150 is disposed on the other side surface of the substrate dielectric layer and is electrically connected to the chip 120. The solder balls 160 are disposed on the combined wiring layer 150. The metal shielding layer 140 is disposed on the surface of the encapsulant 130 and is electrically connected to the combined wiring layer 150 to achieve grounding.

[0147] In this embodiment, pads 121 are provided on one side surface of the chip 120 for mounting. The combined wiring layer 150 includes a first dielectric layer 151 and a second dielectric layer 154. A substrate metal layer 113 is provided on the substrate dielectric layer. The substrate metal layer 113 is electrically connected to the pads 121. At the same time, a first metal layer 153 is provided on the first dielectric layer 151. The first metal layer 153 is electrically connected to the substrate metal layer 113. A second metal layer 156 is provided on the second dielectric layer 154. The second metal layer 156 is electrically connected to the first metal layer 153. It should be noted that via holes 173 extending to the substrate dielectric layer are provided on the encapsulant 130 on both sides of the chip 120 in this embodiment. The metal shielding layer 140 extends to the via holes 173 and is electrically connected to the substrate metal layer 113 on the substrate dielectric layer, so that the metal shielding layer 140 realizes the grounding function.

[0148] In summary, this embodiment provides a fan-out chip packaging method and a fan-out chip packaging structure. A chip 120 is mounted on a substrate carrier 110, and a protective carrier 170 having end feet 171 is also mounted on the substrate carrier 110. The protective carrier 170 covers the outside of the chip 120, and the end feet 171 are respectively arranged on both sides of the chip 120, thus playing a supporting role. After the protective carrier 170 is mounted, a molding compound 130 is formed by molding on the substrate carrier 110. The molding compound 130 is located inside and outside the protective carrier 170 at the same time and covers the outside of the chip 120. Moreover, a metal shielding layer 140 is formed by sputtering on the surface of the molding compound 130 away from the substrate carrier 110, and the molding compound 130 serves as a sputtering substrate. Then, the substrate carrier 110 is peeled off to form a substrate dielectric layer, a combined wiring layer 150 is formed on the substrate dielectric layer, and solder balls 160 are formed on the side of the combined wiring layer 150 away from the metal shielding layer 140. By providing the protective carrier 170 in this embodiment, the chip 120 can be effectively protected, preventing external dust from falling on the surface and around the chip 120 during the transportation of the packaging structure, and avoiding ESD breakdown or defects generated during packaging (such as voids, cracking on the surface of the chip 120, etc.). At the same time, by providing the protective carrier 170 and combining it with the substrate carrier 110, a good supporting effect can be achieved during the molding process, preventing the molding compound 130 from warping. Furthermore, by sputtering on the surface of the molding compound 130 to form the metal shielding layer 140, the electromagnetic shielding effect of the fan-out packaging structure can be realized, and the electromagnetic shielding effect is good.

[0149] The fan-out chip packaging method and the fan-out chip packaging structure provided by the embodiments of the present invention mount a chip 120 on a substrate carrier 110, and at the same time mount a protection carrier 170 with end feet 171 on the substrate carrier 110. The protection carrier 170 covers the outside of the chip 120, and the end feet 171 are respectively arranged on both sides of the chip 120, so as to play a supporting role. After the protection carrier 170 is mounted, a package body 130 is formed by plastic encapsulation on the substrate carrier 110. The package body 130 is located inside and outside the protection carrier 170 at the same time, and covers the outside of the chip 120. Moreover, a metal shielding layer 140 is formed by sputtering on one surface of the package body 130 far away from the substrate carrier 110, and the package body 130 serves as a sputtering substrate. Then, a combined wiring layer 150 is formed on one surface of the package body 130 far away from the metal shielding layer 140, and solder balls 160 are formed on one surface of the combined wiring layer 150 far away from the metal shielding layer 140. Compared with the prior art, by setting the protection carrier 170, the present invention can effectively protect the chip 120, avoid external dust from falling on the surface and around the chip 120 during the transportation of the packaging structure, and avoid the ESD breakdown phenomenon or defects generated during packaging (for example: voids, cracking on the surface of the chip 120, etc.). At the same time, by setting the protection carrier 170, combined with the substrate carrier 110, it can play a good supporting role during the plastic encapsulation process and avoid warping of the package body 130. Moreover, by sputtering on the surface of the package body 130 to form the metal shielding layer 140, the electromagnetic shielding effect of the fan-out packaging structure can be realized, and the electromagnetic shielding effect is good.

[0150] As described above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A fan-out chip packaging method, characterized in that, Including: Mounting a chip on one side surface of a base carrier; Mounting a protective carrier with pins on one side surface of the base carrier, the protective carrier covering the outside of the chip, and the pins being disposed on both sides of the chip; Forming an encapsulant by encapsulation molding on one side surface of the base carrier, the encapsulant being disposed inside and outside the protective carrier and covering the outside of the chip; Sputtering a metal shielding layer on one side surface of the encapsulant away from the base carrier; Forming a combined wiring layer on one side surface of the encapsulant away from the metal shielding layer; Forming solder balls on one side of the combined wiring layer away from the metal shielding layer; The pins are hollow, and the step of forming a metal shielding layer on one side surface of the encapsulant away from the base carrier includes: Grinding the encapsulant and the protective carrier until the pins are exposed, so that via holes penetrating through to the base carrier are formed on the encapsulant on both sides of the chip; Sputtering the metal shielding layer on the surface of the encapsulant and at least part of the via holes; 2. The fan-out chip packaging method according to claim 1, wherein The step of forming a combined wiring layer on one side of the encapsulant away from the metal shielding layer includes: Forming a base groove by grooving on one side surface of the base carrier away from the metal shielding layer, the base groove penetrating through the base carrier and reaching the chip and the pins; Forming a base metal layer in the base groove, the base metal layer being electrically connected to both the metal shielding layer and the chip; Forming a first dielectric layer on one side surface of the base carrier away from the metal shielding layer, the first dielectric layer covering the base metal layer; Forming a first groove by grooving on the first dielectric layer, the first groove penetrating through the first dielectric layer and reaching the base metal layer; Forming a first metal layer in the first groove, the first metal layer being electrically connected to the base metal layer; Forming a second dielectric layer on one side surface of the first dielectric layer away from the metal shielding layer, the second dielectric layer covering the first metal layer; Forming a second groove by grooving on the second dielectric layer, the second groove penetrating through the second dielectric layer and reaching the first metal layer; Forming a second metal layer in the second groove, the second metal layer being electrically connected to the first metal layer; Wherein, the solder balls are disposed on the second metal layer; 3. The fan-out chip packaging method according to claim 1, wherein Before the step of forming a combined wiring layer on one side of the encapsulant away from the metal shielding layer, the method further includes: Peeling off the base carrier to expose the chip and the encapsulant; Forming a base dielectric layer on one side surface of the encapsulant away from the metal shielding layer, the base dielectric layer covering the chip; 4. The fan-out chip packaging method according to claim 3, wherein The step of forming a combined wiring layer on one side of the encapsulant away from the metal shielding layer includes: Forming a base groove by grooving on one side surface of the base dielectric layer away from the metal shielding layer, the base groove penetrating through the base dielectric layer and reaching the chip and the pins; Forming a base metal layer in the base groove, the base metal layer being electrically connected to both the metal shielding layer and the chip; A first dielectric layer is formed on the surface of the base dielectric layer away from the metal shielding layer, and the first dielectric layer covers the base metal layer; A first groove is formed by grooving on the first dielectric layer, and the first groove penetrates through the first dielectric layer and reaches the base metal layer; A first metal layer is formed in the first groove, and the first metal layer is electrically connected to the base metal layer; A second dielectric layer is formed on the surface of the first dielectric layer away from the metal shielding layer, and the second dielectric layer covers the first metal layer; A second groove is formed by grooving on the second dielectric layer, and the second groove penetrates through the second dielectric layer and reaches the first metal layer; A second metal layer is formed in the second groove, and the second metal layer is electrically connected to the first metal layer; Wherein, the solder ball is disposed on the second metal layer.

5. The fan-out chip packaging method according to claim 2 or 4, characterized in that, The step of forming the second metal layer in the second groove includes: Electroplating a conductive metal layer in the second groove; Electroplating a conductive column on the conductive metal layer.

6. The fan-out chip packaging method according to claim 1, wherein, After the step of forming the solder ball on the surface of the combined wiring layer away from the metal shielding layer, the method further includes: Cutting the encapsulation body and the combined wiring layer along the midline of the via hole.

7. The fan-out chip packaging method according to claim 1, wherein Before the step of mounting the chip on one surface of the base carrier, the method further includes: Attaching an adhesive layer on one surface of the base carrier.

8. A fan-out chip packaging structure, which is prepared by using the fan-out chip packaging method described in any one of claims 1-7, and is characterized in that, Comprising: A base dielectric layer; A chip mounted on the base dielectric layer; An encapsulation body disposed on the base dielectric layer and covering the chip and the protection carrier, and via holes are provided on the encapsulation body on both sides of the chip; A metal shielding layer disposed on the surface of the encapsulation body away from the base dielectric layer; A combined wiring layer disposed on the surface of the base dielectric layer away from the metal shielding layer; A solder ball disposed on the surface of the combined wiring layer away from the metal shielding layer.

9. The fan-out chip package structure according to claim 8, wherein, The combined wiring layer includes a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed on the side of the base dielectric layer away from the metal shielding layer, and the second dielectric layer is disposed on the side of the first dielectric layer away from the metal shielding layer; A base groove is provided on the base dielectric layer, the base groove penetrates through the base dielectric layer and reaches the chip and the via hole, and a base metal layer is disposed in the base groove. The base metal layer is electrically connected to both the metal shielding layer and the chip at the same time; The first dielectric layer covers the base metal layer, and a first groove is provided on the first dielectric layer. The first groove penetrates through the first dielectric layer and reaches the base metal layer, and a first metal layer is disposed in the first groove. The first metal layer is electrically connected to the base metal layer; The second dielectric layer covers the first metal layer, and a second groove is provided on the second dielectric layer. The second groove penetrates through the second dielectric layer and reaches the first metal layer, and a second metal layer is disposed in the second groove. The second metal layer is electrically connected to the first metal layer; Wherein, the solder ball is disposed on the second metal layer.

Images