A packaging structure and method for reducing switch parasitic inductance and improving dynamic performance

Abstract

The present invention discloses a packaging structure and method for reducing switch parasitic inductance and improving dynamic performance. The method steps are as follows: 1) Weld the drain of the switch die (2) to the drain pad on the top plate; 2) Perform gold ball array (7) bonding at the source and gate positions of the switch die (2); 3) Weld the dielectric plate (4) to the top plate; 4) Fill the gap between the switch die (2) and the dielectric plate (4); 5) Fill a solder mask layer between the gate pad and the source pad on the top plate; 6) Weld the dielectric plate (4) and the pad substrate (5). The device includes a top plate, a switch die (2), a dielectric plate (4), and a welding substrate (5); the present invention can effectively reduce the switch parasitic inductance and improve the switch dynamic characteristics.

Description

Technical Field

[0001] The present invention relates to the field of nanosecond pulse generators, and specifically to a packaging structure and method for reducing switch parasitic inductance and improving dynamic performance. Background Art

[0002] The performance of switches is a core component in the development of nanosecond pulse generators. Existing commercial switches are mostly applied to conventional power electronics applications and are difficult to meet the increasing requirements of nanosecond pulse generators in terms of parasitic inductance control and dynamic performance optimization. The generation of nanosecond pulses subjects the switches to high voltage and current stresses with transient changes. At the same time, the transient electromagnetic field caused by the rapidly changing voltage and current also has a huge impact on the pulse characteristics generated by the switches. Therefore, developing a switch with extremely low parasitic inductance and improved dynamic performance has become the most urgent issue for improving the performance of nanosecond pulse generators. Summary of the Invention

[0003] The purpose of the present invention is to provide a packaging method for reducing switch parasitic inductance and improving dynamic performance, including the following steps:

[0004] 1) Print solder on the top plate drain pad.

[0005] 2) Solder the switch die drain to the top plate drain pad.

[0006] In step 2), the switch die drain is soldered to the top plate drain pad using solder paste.

[0007] 3) Perform gold ball array bonding at the source and gate positions of the switch die.

[0008] In step 3), a gold ball array is arranged on the source and gate of the switch die respectively using a gold wire bonder.

[0009] 4) Print solder on the dielectric plate.

[0010] 5) Solder the dielectric plate to the top plate.

[0011] In step 5), the dielectric plate is soldered to the top plate using solder paste.

[0012] 6) Fill the gap between the switch die and the dielectric plate.

[0013] The material used to fill the gap between the switch die and the dielectric plate includes silicone gel.

[0014] 7) Fill the solder mask layer between the top plate gate pad and the top plate source pad.

[0015] 8) Print solder on the pad substrate.

[0016] 9) Solder the dielectric plate and the pad substrate.

[0017] In step 9), the dielectric plate and the pad substrate are soldered using solder paste.

[0018] The soldering method includes a reflow soldering process.

[0019] The package structure obtained by using a packaging method that reduces the switch parasitic inductance and improves the dynamic performance includes a top plate, a switch die, a dielectric plate, and a soldering substrate.

[0020] The top plate includes a heat dissipation ceramic substrate and a heat dissipation copper foil substrate. The heat dissipation copper foil substrate covers the upper surface and the lower surface of the heat dissipation ceramic substrate respectively.

[0021] The top plate includes a top plate drain pad, a top plate gate pad, and a top plate source pad. A solder mask layer is filled between the top plate gate pad and the top plate source pad.

[0022] The drain of the switch die is soldered on the top plate drain pad.

[0023] A gold ball array is arranged on the gate and source of the switch die.

[0024] The drain lead of the switch die is led out through the pad substrate, and the source lead is connected to the top plate through a connection via, so that the source lead and the drain bus realize symmetric output in the upper and lower layers.

[0025] The vector direction of the area where the switch die is located is distributed in concentric circles, and the left and right sides are arranged counterclockwise and clockwise in opposite directions respectively.

[0026] One surface of the dielectric plate is soldered to the top plate, and the other surface is soldered to the pad substrate.

[0027] A number of connection vias are formed on the dielectric plate.

[0028] The gate and source of the pad substrate adopt a wiring design with Kelvin gate and source connections.

[0029] The pad substrate has pins.

[0030] The package structure further includes solder paste for soldering the drain of the switch die and the top plate drain pad, the dielectric plate and the top plate, and the dielectric plate and the pad substrate.

[0031] The package structure further includes silicone gel for filling the gap between the switch die and the dielectric plate.

[0032] The technical effect of the present invention is beyond doubt. The present invention proposes a method for stacking multiple layers of printed circuit boards and laminating and packaging switch wafer dies.

[0033] The present invention proposes and verifies a packaging process for dissimilar metal welding and temperature gradient welding based on a gold ball array.

[0034] The present invention proposes and verifies a board-level switch package and its pin design device, and the experimental results prove that the device can effectively reduce the parasitic inductance of the switch and improve the switching dynamic characteristics. Description of the Drawings

[0035] Figure 1 It is a schematic diagram of the internal structure of a very low parasitic inductance stacked structure;

[0036] Figure 2 It is an exploded view of each layer of the stacked package structure; Figure 2 (a) is the overall exploded view; Figure 2 (b) is the sectional exploded view;

[0037] Figure 3 It is the packaging process of a very low parasitic inductance stacked package;

[0038] Figure 4 It is the circuit wiring diagram of the pad substrate; Figure 4 (a) is the pad substrate design with direct gate-source connection; Figure 4 (b) is the pad substrate design with Kelvin gate-source connection;

[0039] Figure 5 It is the model establishment in Maxwell 3D; Figure 5 (a) is the magnetic field calculation spatial region; Figure 5 (b) is the switch model analysis;

[0040] Figure 6 It is the spatial variation of the magnetic field of the stacked package during the pulse formation process; Figure 6 (a), Figure 6 (b), Figure 6 (c), Figure 6 (d), Figure 6 (e), Figure 6 (f), Figure 6 (g), Figure 6 (h), Figure 6 (i) is the spatial variation of the magnetic field of the stacked package during the pulse formation process at t = 0ns, t = 1ns, t = 2ns, t = 5ns, t = 50ns, t = 95ns, t = 98ns, t = 99ns, t = 100ns;

[0041] Figure 7 It is the magnetic flux density vector distribution of the stacked package during the pulse flat-top stage; Figure 7 (a) is the magnetic flux density vector and intensity distribution; Figure 7 (b) is the magnetic flux density vector distribution on the cross-section;

[0042] Figure 8Current density distribution of the stacked package in the pulse flat-top stage; Figure 8 (a) Package pin surface - bottom; Figure 8 (b) Package top;

[0043] Figure 9 Mesh generation of the thermal simulation model; Figure 9 (a) Computational grid for natural cooling; Figure 9 (b) Computational grid for forced cooling;

[0044] Figure 10 Thermal simulation results of natural cooling; Figure 10 (a) Temperature distribution on the stacked package housing (5 MHz); Figure 10 (b) Temperature distribution on the internal cross-section of the package (5 MHz); Figure 10 (c) Temperature distribution on the stacked package housing (50 kHz); Figure 10 (d) Temperature distribution on the internal cross-section of the package (50 kHz);

[0045] Figure 11 Thermal simulation results of forced cooling; Figure 11 (a) Temperature distribution on the stacked package housing (cooling device hidden); Figure 11 (b) Temperature distribution on the internal cross-section of the package;

[0046] Figure 12 Fluid velocity and distribution in the forced-cooling cold plate;

[0047] Figure 13 Thermal simulation results of forced cooling (burst pulse output mode); Figure 13 (a) Temperature distribution on the stacked package housing; Figure 13 (b) Temperature distribution on the internal cross-section of the package;

[0048] Figure 14 Double-pulse test results of TO-263 package at rated current; Figure 14 (a) U gs Test waveform; Figure 14 (b) U ds Test waveform; Figure 14 (c) i d Test waveform; Figure 14 (d) P loss Test waveform;

[0049] Figure 15 Comparison waveforms of double-pulse tests of TO-263 and PoP packages at rated current of 36 A; Figure 15 (a) U gs Comparison waveform; Figure 15 (b) U ds Comparison waveform; Figure 15(c) is for i d Comparison waveform; Figure 15 (d) is for P loss Comparison waveform;

[0050] Figure 16 It is the comparison waveform of double-pulse test for TO-263 and PoP packages when the limit pulse current is 90A; Figure 16 (a) is for U gs Comparison waveform; Figure 16 (b) is for U ds Comparison waveform; Figure 16 (c) is for i d Comparison waveform; Figure 16 (d) is for P loss Comparison waveform;

[0051] In the figure: switch die 2, solder paste 3, dielectric board 4, soldering substrate 5, heat dissipation ceramic substrate 11, heat dissipation copper sheet substrate 12, connection via 42, pin 6, copper layer of dielectric board 41, power current direction A, gold ball array 7. Specific implementation mode

[0052] The present invention will be further described below in conjunction with embodiments, but it should not be understood that the above-mentioned subject scope of the present invention is limited to the following embodiments. Without departing from the above-mentioned technical idea of the present invention, various substitutions and changes made according to the common general knowledge and customary means in the art should be included within the protection scope of the present invention.

[0053] Embodiment 1:

[0054] See Figure 3 , a packaging method for reducing switch parasitic inductance and improving dynamic performance, comprising the following steps:

[0055] 1) Printing solder on the top plate drain pad.

[0056] 2) Welding the drain of the switch die 2 on the top plate drain pad.

[0057] In step 2, the drain of the switch die 2 is welded on the top plate drain pad by using the solder paste 3. The switch die 2 includes GaN switch die, Si switch die, SiC switch die, SiCMOSFET wafer, etc.

[0058] 3) Bonding the gold ball array 7 at the source and gate positions of the switch die 2.

[0059] In step 3, the gold ball array is arranged on the source and gate of the switch die 2 respectively by using a gold wire bonder.

[0060] 4) Printing solder on the dielectric board 4.

[0061] 5) Weld the dielectric plate 4 to the top plate.

[0062] In step 5, the dielectric plate 4 is welded to the top plate using solder paste 3. The dielectric plate 4 includes substrates such as a PCB board and a ceramic substrate.

[0063] 6) Fill the gap between the switch die 2 and the dielectric plate 4.

[0064] The material used to fill the gap between the switch die 2 and the dielectric plate 4 includes silicone gel.

[0065] 7) Fill a solder mask layer between the top plate gate pad and the top plate source pad.

[0066] 8) Print solder on the pad substrate 5.

[0067] 9) Weld the dielectric plate 4 to the pad substrate 5.

[0068] In step 9, the dielectric plate 4 is welded to the pad substrate 5 using solder paste 3.

[0069] The welding method includes a reflow soldering process.

[0070] Example 2:

[0071] A packaging method for reducing the parasitic inductance of a switch and improving the dynamic performance, including the following steps:

[0072] In the first step, the proposed structure starts packaging from the top plate. Now, solder is printed on the top plate drain pad. In the second step, the switch die drain is soldered to the top plate using solder paste. In the third step, a gold ball array bonding is performed on the existing process parts. The diameter of the gold balls is 38 μm. Using a gold wire bonder, gold ball arrays are arranged on the two source and gate electrodes of the wafer respectively. The number of gold balls in the array is directly related to the size of the pad. The arrangement principle is to arrange the gold balls as densely as possible. The fourth and fifth steps are to effectively weld and combine the intermediate layer with the top plate. However, due to processing technology limitations and the positioning of the strong field distribution area in the electromagnetic field simulation, in the sixth step, silicone gel needs to be filled in the gap between the wafer and the intermediate layer. This gap filling not only plays a strengthening role but also can effectively suppress the air breakdown caused by strong field distortion. At the same time, since the source and gate are connected in a flip-chip manner, compared with using an aluminum wire bonding wire pulled outwards, the gap of the external connection pad is directly reduced to the minimum value. Since the solder is solder paste, it will inevitably cause some solder creeping or form solder balls and solder beads in the non-welding area. From the above electromagnetic field simulation, the wafer area is the position where the magnetic field strength of the entire package is the strongest and the distortion is the most severe. In addition to filling silicone gel in the gap in the sixth step, a certain solder mask layer design should also be provided at the gate-source pad position. Therefore, in the seventh step, a small amount of solder mask layer is filled between the gate and source electrodes. Finally, the eighth and ninth steps perform the welding of the pad substrate.

[0073] Example 3:

[0074] See Figure 1 and Figure 2 , a package structure prepared by a packaging method for reducing switch parasitic inductance and improving dynamic performance, includes a top plate, a switch die 2, a dielectric plate 4, and a solder substrate 5.

[0075] The top plate includes a heat dissipation ceramic substrate 11 and a heat dissipation copper foil substrate 12. The heat dissipation copper foil substrate 12 covers the upper surface and the lower surface of the heat dissipation ceramic substrate 11 respectively.

[0076] The top plate includes a top plate drain pad, a top plate gate pad, and a top plate source pad. A solder mask layer is filled between the top plate gate pad and the top plate source pad.

[0077] The drain of the switch die 2 is soldered on the top plate drain pad.

[0078] A gold ball array 7 is arranged on the gate and the source of the switch die 2.

[0079] The drain lead of the switch die 2 is led out through the solder substrate 5, and the source lead is connected to the top plate through a connection via, so that the source lead and the drain bus realize symmetric output of upper and lower layers.

[0080] The vector direction of the area where the switch die 2 is located is distributed in concentric circles, and the left and right sides are arranged counterclockwise and clockwise in opposite directions respectively.

[0081] One surface of the dielectric plate 4 is soldered to the top plate, and the other surface is soldered to the solder substrate 5.

[0082] A number of connection vias 42 are formed on the dielectric plate 4.

[0083] The outer surface of the dielectric plate 4 is a dielectric plate copper skin layer 41.

[0084] The gate and source of the solder substrate 5 adopt a wiring design with Kelvin gate and source connections.

[0085] The solder substrate 5 has pins 6.

[0086] The package structure further includes a solder paste 3 for soldering the drain of the switch die 2 to the top plate drain pad, the dielectric plate 4 to the top plate, and the dielectric plate 4 to the solder substrate 5.

[0087] The package structure further includes a silicone gel for filling the gap between the switch die 2 and the dielectric plate 4.

[0088] See Figure 3 , the power current direction of the package structure prepared by the packaging method for reducing switch parasitic inductance and improving dynamic performance is along the arrow direction indicated by A.

[0089] Example 4:

[0090] The packaged structure prepared by a packaging method for reducing switch parasitic inductance and improving dynamic performance, the main structure is shown in Embodiment 3, wherein, the source connection of the packaged structure adopts Kelvin source connection.

[0091] The core of Kelvin connection is to intentionally design the parasitic difference between the low-power loop and the high-power loop to minimize the coupling effect of the high-power loop on the low-power loop, thereby making the high-power loop and the low-power loop independent of each other to improve the driving efficiency and the anti-interference ability of the low-power loop. Therefore, in this embodiment, Kelvin connection design is carried out in the stacked package structure design. Thanks to the adaptability and simplicity in PCB design and processing, Figure 4 is the wiring diagram of the pad substrate. Figure 4 (a) and Figure 4 (b) are respectively the wiring designs of direct gate and source connections and the wiring designs of Kelvin gate and source connections. It can be seen that Figure 4 in (b), Figure 4 the copper cladding with the same width as the high-power source wiring in (a) is modified to a copper wire with a width of 20 mil. Similarly, the gate copper rectangular connection method is modified to a 20 mil copper wire connection.

[0092] In this embodiment, the source part connecting the wafer chip to the negative input pin of the gate drive is defined as L s.gate , and the gate part connecting the wafer chip to the positive input pin of the gate drive is defined as L g.gate . Import the proposed pad substrate circuit into Ansys Q3D to obtain the data shown in Table 1. Therefore, under the premise of keeping the parasitic inductance of the high-power loop less than 1 nH, the proposed stacked package structure changes the parasitic inductance difference between the high- and low-power loops through the Kelvin gate-source connection method, improving the switching dynamic performance.

[0093] Table 1 Extraction parameters of parasitic inductance of gate drive gate-source pins of pad substrate

[0094]

[0095] Embodiment 5:

[0096] The electromagnetic field simulation experiment of the packaging method and the packaged structure for reducing switch parasitic inductance and improving dynamic performance is as follows:

[0097] The extremely low parasitic inductance stacked package proposed in this embodiment has the advantages of extremely low parasitic inductance, Kelvin source connection, flip-chip pads, and compact structure. The overall size is only 10mm * 10mm * 0.8mm. In the application environment of nanosecond short pulse generators, faster voltage and current rise times are often pursued. At this time, in addition to the electrical parameter distortion caused by high-speed di / dt and du / dt inside the switch, it is also subjected to a violently changing electromagnetic field. The distribution and emission of the electromagnetic field not only depend on the intensity of the emission source but also vary greatly due to differences in structural design. The violent change of the electromagnetic field will not only restrict the dynamic characteristics of the switch itself but also have a huge impact on the normal operation of the peripheral circuit. Therefore, the switch package applied in the nanosecond short pulse generator needs to perform transient electromagnetic field simulation under the operating conditions. In this section, the electromagnetic simulation software ANSYS Electronics Desktop is used to study the transient field distribution characteristics of the proposed package.

[0098] Thanks to the highly integrated platform advantage of ANSYS Electronics Desktop, in this embodiment, the three-dimensional package model in SolidWorks can be directly imported into Maxwell 3D and Q3DExtractor to obtain an electromagnetic field simulation geometric model consistent with the actual package. Figure 3 .10 is the simulation model established for the proposed package in ANSYS Electronics. In this embodiment, it is known that the electromagnetic field is a radiation field, which is not only distributed on the package but also has a field distribution in the spatial structure. Therefore Figure 5 (a) is the electromagnetic field calculation area in the simulation. In addition, in order to more realistically reflect the pulse formation situation, in the excitation setting, in this embodiment, the waveform definition function of ANSYS Electronics is used to set a pulse current with a pulse width of 100 ns, pulse rise and fall times of 3 ns (10% - 90%) as the excitation, where the pulse current amplitude is 90 A (the limit pulse current in the manual of the proposed switch is 90 A).

[0099] After the above parameter settings, Figure 6It is the scalar distribution state of the magnetic field during the application of the excitation pulse on the stacked package. First, it can be clarified that the magnetic field distribution in the proposed package is non-uniform but symmetric, and the pulse rise and fall times are consistent with the establishment and decay of the magnetic field. The rise time and fall time of the excitation pulse are both 3 ns. Therefore, from 0 ns to 5 ns, it can be seen that the magnetic field intensity diffuses spatially, the acting intensity increases continuously, and it gradually decreases as the acting range expands. During the 50-ns pulse flat-top stage, it can be seen that the output pin area of the package and the area vertically below it are the concentrated areas of the magnetic field intensity, and the strongest distribution is in the SiCMOSFET wafer layout area. Therefore, in the design of the power loop and the drive loop, this magnetic field concentration area should be avoided to prevent the spatial interference of the sudden magnetic field on the low-voltage circuit. Moreover, additional insulation measures are required at the wafer edge to avoid insulation failure caused by extremely non-uniform field distortion. From 95 ns to 100 ns is the pulse fall stage, and the magnetic field intensity gradually decreases. The magnetic fields on the left and right sides centered on the wafer are symmetrically distributed, and both increase and decrease equivalently. Therefore, special attention should be paid to the layout of the external circuit traces of the switch source electrode when guiding the packaging process.

[0100] Through the intensity analysis of the magnetic field, the magnetic field distribution law of the proposed package during the pulse formation process can be obtained. The power loop can effectively improve the negative mutual inductance and reduce the parasitic inductance of the loop by designing the current direction in the opposite direction within a limited space through structural design, thereby improving the pulse dynamic characteristics. Therefore, in this embodiment, the magnetic field vector distribution of the proposed stacked package is analyzed. Figure 7 It is the distribution diagram during the pulse flat-top stage. Generally speaking, as Figure 7 (a) The vector directions in the wafer area are distributed in concentric circles, and are arranged counterclockwise and clockwise in the opposite direction on the left and right sides respectively. However, when the proposed package is installed in the actual circuit, the routing design of the main loop can directly realize the power loop output through the bottom layer of the pad. And the magnetic field intensities on both sides are much smaller than those in the middle side, and the main intensity is only concentrated in the SiCMOSFET wafer part. Therefore, the drain trace can be led out through the Top layer where the pad is located, and the source electrode is symmetrically output from the upper and lower layers of the drain bus directly through the PCB via to the Bottom layer, finally reducing the wiring difficulty and facilitating the reduction of the power parasitic inductance.

[0101] Finally, the current density distribution also has a direct impact on the design of the peripheral circuit. When the current density concentration area of the high-power loop is close to the low-power loop, it will inevitably have a fatal impact on the signal transmission of the low-power loop. Figure 8 The current density distributions are shown respectively from the pin output surface and the top of the stacked package. According to Figure 8 (a) of the pin distribution, in this embodiment, it can be found that the current density of the proposed package is mainly distributed in the pin area of the high-power loop, while the distribution in the low-power area where the gate signal is distributed is very small. It should be noted that in this section, Figure 4The direct source pin in (a) is simulated and analyzed to make all stacked structures closer to the general operating conditions.

[0102] Then, this embodiment obtains Figure 9 the thermal simulation model mesh division shown in the figure. To further confirm the cooling device parameters, this embodiment establishes a natural cooling model as Figure 9 shown in (a). At this time, the mesh size in the three-dimensional space is less than one fortieth of the calculation area, and at the same time, it is required that the mesh thickness is not less than 4 layers. As can be seen from Figure 9 (a), the vertical mesh is greater than 7 layers, and the number of meshes is 3.5 million. And the forced cooling power required for the same heating power is further discussed. Figure 9 (b) is the thermal simulation mesh division model including the forced cooling device. Considering the compact space limitation, this embodiment uses a water-cooled plate as the forced cooling device. The size of the cold plate in the figure is quite different from the size of the switch. The continuous area mesh will cause non-convergence or inability to calculate due to the sparse mesh in the switch area. At the same time, there is fluid and the fluid belongs to high-density fins. In Figure 9 (b), 4 discontinuous mesh regions are divided in the mesh division, so that the number of meshes in the switch area is greater than 250,000.

[0103] Embodiment 6:

[0104] Thermal management analysis experiment of the packaging method and packaging structure for reducing switch parasitic inductance and improving dynamic performance is as follows:

[0105] The Ansys Icepak thermal simulation software is used to conduct thermal characteristic simulation research on the proposed stacked packaging. First, the simulation conditions are defined as the switch rated current (36 A), continuous high repetition frequency (5 MHz), fixed pulse width (100 ns). The output power in its stable operating state is 42.12 W, which is set as the power heat source and added to the SiC MOSFET wafer. The simulation parameters in Ansys Icepak are set as shown in Table 2.

[0106] Table 2 Thermal simulation setting parameters

[0107]

[0108] First, the natural cooling mode is discussed. The switch is fixed on the PCB substrate, and the SiC MOSFET wafer transfers heat outward as the heat source. The simulation type is steady-state thermal field simulation, that is, the simulation duration is set to 1000 seconds and the simulation step size is 1 second. After simulation calculation, the junction temperature T j = 180 °C; the package case temperature T a = 170 °C; the center temperature of the PCB substrate T PCB = 175 °C. The switch simulation temperature in the natural cooling mode is as Figure 3 .29 shows.Figure 10 (a) is the temperature contour map of the stacked package housing. The entire switch is between 169°C and 180°C. At this time, the switch can no longer operate normally, and the temperature of the entire PCB substrate area exceeds 155°C. From Figure 10 (b), it can be seen from inside the package that the temperature is the highest in the vertical area of the chip wafer, with an average of over 178°C. And Figure 10 (c) and Figure 10 (d) are for operation at a repetition frequency of 50 kHz. It can be found that although there is only natural cooling as the only heat transfer path, after continuous operation for 1000 s, the temperature of the switch wafer is only 65°C. At this time, it can operate directly under appropriate air convection conditions without an external heat dissipation device.

[0109] The previous introduction shows that air-cooled heat dissipation is difficult to meet the requirements of the high-repetition-frequency pulse generator for a compact structure design, and natural convection heat dissipation is difficult to achieve a fast enough cooling speed and heat transfer. The liquid cooling device completes high-speed and high-power heat transfer within a vertical space of 13 mm. Figure 11 This is the thermal simulation result when the liquid cooling device is in operation in the continuous operation mode. Figure 11 (a) is the surface temperature simulation result. After simulation calculation, the junction temperature T j = 47°C; the package housing temperature T a = 28°C; Figure 11 (a) is the cross-sectional temperature simulation result. The temperature at the center of the PCB substrate T PCB = 38°C. At the same time, the temperature in the area where the SiCMOSFET wafer is located at the center of the switch is less than 45°C. It can be said that the switch temperature has stabilized at the ambient temperature, and the heat dissipation solution can meet the actual requirements for continuous and stable operation. Figure 12 This is the distribution of the liquid and the flow velocity distribution in the cold plate. The diameter of the fluid pipeline is 4 mm, and the initial flow velocity is set at 3 m / s. At the same time, it should also be noted that after continuous operation for 1000 s, the temperature of the periphery of the PCB substrate still reaches 90°C. This also means that for the power bus substrate of the pulse generator, a whole-machine thermal management design needs to be carried out, and materials with lower thermal resistance are also required for the substrate medium.

[0110] The nanosecond pulse generator operates in a burst mode in quite a number of applications. Although the frequency of the output pulses is still very high, there are a limited number of them. At this time, the overall operating frequency of the pulse generator is much lower than the repetition frequency of the output pulses. In this mode, after simulation calculation, the junction temperature T j = 34°C; the package housing temperature T a = 33°C; the temperature at the center of the PCB substrate T PCB= 34 °C. After continuous operation for 1000 s, the temperature stabilizes at around 34 °C. From the above simulation results, it can be concluded that the proposed extremely low parasitic inductance hybrid packaging structure can achieve stable operation by natural heat dissipation or simple air convection at a lower frequency of 50 kHz and in burst operation mode. When operating at a repetition frequency of 5 MHz, stable operation can only be achieved by relying on a forced liquid cooling device.

[0111] Example 7:

[0112] Verification experiments on packaging methods and packaging structures for reducing switching parasitic inductance and improving dynamic performance are as follows:

[0113] In this example, the dynamic characteristic differences between the proposed stacked packaging PoP and the commercially available wafer low parasitic inductance packaging TO-263 are comprehensively evaluated under rated current and ultimate pulse current conditions. To control the constant current comparison, this example adjusts the charging voltage by fixing the charging time to achieve constant current comparison. Key attention is paid to the comparison and analysis of the gate-source voltage U gs , drain-source voltage U ds , loop current i d and switching on-off loss P loss to comprehensively evaluate the dynamic advantages of the proposed PoP packaging. Figure 13 is the typical double-pulse test parameters measured for the TO-263 package switch under rated current conditions. Figure 13 In Figure 13 (a), Figure 13 (b), Figure 13 (c), Figure 13 (d) respectively represent the gate-source voltage U gs , drain-source voltage U ds , loop current i d and switching on-off loss P loss . Its circuit function is the same as described in the previous section. After the first pulse is charged for 2 μs, the switch is turned off, and then it is turned on again after a 200 ns interval. The turn-on time is 300 ns. Figure 13 (c) intuitively reflects the above process. Figure 14 is the comparison of the dynamic parameters of the TO-263 and PoP packages at rated current. Figure 15 is the comparison of the dynamic parameters of the TO-263 and PoP packages at a rated current of 36 A. To be able to intuitively show the switching dynamic characteristics, this example focuses the time axis of the test waveform on the test waveform of the switch operating under a certain current load. Figure 14 (a) The driving voltage waveform shows that PoP can improve the rise time of the driving voltage and has smaller positive oscillations in the falling stage. Of course, due to the negative voltage driving circuit used in this section, the oscillations of the driving voltage after both turn-offs do not exceed the switching threshold voltage.Figure 14 From the switching loss waveform of (d), it can be seen that PoP has no obvious advantage in the peak power of turn-on loss, while the peak power of turn-off loss is significantly reduced, only 50% of that of TO-263.

[0114] The further comparison and evaluation results are shown in Table 3. It can be seen that there is no obvious difference in the voltage turn-on and turn-off times of the switches of the two packages. The PoP package is only slightly better than the TO-263 package in terms of voltage turn-on and turn-off times. This is because the powerful driving ability of the self-made ultra-fast gate driver GaN_E-Driver has made the turn-on and turn-off speeds of the proposed switch close to the limit. However, in terms of improving the loop current, thanks to the extremely low loop parasitic inductance of PoP, the current rise speed of PoP has increased by 32.7%, and the current fall speed has increased by 71.4%. This advantage is directly reflected in the switching loss. The turn-on loss of PoP is 13.5%, and the turn-off loss is reduced by 33.7%. At the same time, the bus voltage has reached 950V, which is close to the limit voltage of the switch, 1000V. At this time, the switching characteristics have strong guiding significance for the design of pulse generators pursuing high power density.

[0115] Table 3 Parameter comparison between TO-263 and PoP packages at a rated current of 36A

[0116]

[0117] The rated current has certain guiding significance, but higher power density undoubtedly puts higher requirements on the dynamic characteristics of the switch under large current conditions. Since PoP has a minimalist design for the parasitic inductance of the package, the laminated package with extremely low parasitic inductance should have more prominent advantages under large current conditions. Figure 16 This is the comparison result of the dynamic characteristic tests of PoP and TO-263 under the condition of the limit current of 90A mentioned in the CPM3-1000-0065B manual. First, in Figure 16 the driving voltage of (a), due to the integrated Kelvin source connection and the special parasitic inductance design of the gate loop in the PoP package, not only does it show a faster U gs rise time and a shorter switch Miller plateau duration under the limit current condition, but also there is no serious voltage oscillation after the switch is turned off. In Figure 16 the loop current i d in the comparison diagram, PoP shows faster rise and fall times. Of course, due to the reduction of parasitic inductance, its oscillation damping is also reduced, and it also shows a relatively serious overshoot. Figure 16 the switching loss P lossIt can also be found in the comparison that PoP has a smaller peak value in the peak value of the switching loss power during the turn-off process, but it is basically the same as that of TO-263 during the turn-on process. Compared with the switching loss under the rated current condition, PoP has negative power at a larger current, which is due to the LC network in the power loop and the improvement of PoP on di / dt, forming negative power in the energy conversion process. In this embodiment, the absolute value of the negative power is accumulated when calculating the switching loss.

[0118] Table 4 details the comparison and evaluation results of the dynamic characteristics of TO-263 and PoP under the condition of the limit pulse current. At this time, PoP can still maintain a fast voltage turn-on and turn-off speed and is always slightly better than TO-263. In terms of the loop current speed, PoP has increased the current turn-on speed by 48% and the current turn-off speed by 50%. It can be said that PoP has more excellent dynamic characteristics than TO-263 under the limit current condition and can play a greater role in application scenarios with high power density requirements such as pulse power. Moreover, the excellent dynamic characteristics of PoP further reduce the switching loss. The turn-on loss is reduced from 285.8 μJ to 129.5 μJ, a reduction of 54.6%. The turn-off loss has always been the main source of switching loss in pulse power applications. PoP can effectively improve the turn-off speed and reduce the turn-off loss compared with traditional packages. The experimental results show that PoP reduces the turn-off loss by 62.8% compared with TO-263.

[0119] Table 4 Parameter Comparison between TO-263 and PoP Packages at the Limit Pulse Current of 90A

[0120]

Claims

1. A packaging method for reducing switch parasitic inductance and improving dynamic performance, characterized in that, It includes the following steps: 1) Print solder on the top plate drain pad; 2) Weld the drain of the switch die (2) to the top plate drain pad; 3) Bond the gold ball array (7) at the source and gate positions of the switch die (2); 4) Print solder on the dielectric plate (4); 5) Weld the dielectric plate (4) to the top plate; 6) Fill the gap between the switch die (2) and the dielectric plate (4); 7) Fill the solder mask layer between the top plate gate pad and the top plate source pad; 8) Print solder on the pad substrate (5); 9) Weld the dielectric plate (4) and the pad substrate (5).

2. The packaging method for reducing the parasitic inductance of a switch and improving the dynamic performance according to claim 1, wherein: In step 2), the drain of the switch die (2) is welded to the top plate drain pad by using solder paste (3); In step 5), the dielectric plate (4) is welded to the top plate by using solder paste (3); In step 9), the dielectric plate (4) is welded to the pad substrate (5) by using solder paste (3).

3. The packaging method for reducing the parasitic inductance of a switch and improving the dynamic performance according to claim 1, wherein: In step 3), the gold ball array is arranged on the source and gate of the switch die (2) respectively by using a gold wire bonder.

4. A packaging method for reducing switch parasitic inductance and improving dynamic performance according to claim 1, characterized in that: The welding method includes a reflow soldering process.

5. The packaging method for reducing switch parasitic inductance and improving dynamic performance according to claim 1, wherein: The material for filling the gap between the switch die (2) and the dielectric plate (4) includes silicone gel.

6. The packaged structure prepared by the packaging method for reducing the parasitic inductance of the switch and improving the dynamic performance according to any one of claims 1 to 5, characterized in that: It includes a top plate, a switch die (2), a dielectric plate (4), and a welding substrate (5); The top plate includes a top plate drain pad, a top plate gate pad, and a top plate source pad; a solder mask layer is filled between the top plate gate pad and the top plate source pad; The drain of the switch die (2) is welded to the top plate drain pad; The gold ball array (7) is arranged on the gate and source of the switch die (2); The drain lead of the switch die (2) is led out through the pad substrate (5), and the source lead is connected to the top plate through the connection via hole (42), so that the source lead and the drain bus realize upper and lower layer symmetric output; One surface of the dielectric plate (4) is welded to the top plate, and the other surface is welded to the pad substrate (5); A plurality of connection via holes (42) are formed on the dielectric plate (4); The gate and source of the pad substrate (5) adopt a wiring design with Kelvin gate and source connections; The pad substrate (5) has pins (6).

7. The packaging structure obtained by the packaging method for reducing the parasitic inductance of a switch and improving the dynamic performance according to claim 6, wherein: The top plate includes a heat dissipation ceramic substrate (11) and a heat dissipation copper skin substrate (12); the heat dissipation copper skin substrate (12) covers the upper surface and the lower surface of the heat dissipation ceramic substrate (11) respectively.

8. The packaged structure obtained by the packaging method for reducing the parasitic inductance of the switch and improving the dynamic performance according to claim 6, characterized in that: It also includes solder paste (3) for welding the drain of the switch die (2) to the top plate drain pad, the dielectric plate (4) to the top plate, and the dielectric plate (4) to the pad substrate (5).

9. The packaged structure prepared by the packaging method for reducing the parasitic inductance of a switch and improving the dynamic performance according to claim 6, wherein: It also includes silicone gel for filling the gap between the switch die (2) and the dielectric plate (4).

10. The package structure obtained by the package method for reducing switch parasitic inductance and improving dynamic performance according to claim 6, wherein: The vector direction of the area where the switch die (2) is located is concentric circle distribution, and the left and right sides are arranged counterclockwise and clockwise in reverse respectively.

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