Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: forming a second dielectric layer on the surface of a first dielectric layer, the top surface of a gate structure, and the top surface of a plug; forming a first opening in the second dielectric layer to expose the surface of the first dielectric layer, wherein the first opening exposes at least two top surfaces of the gate structure or at least two top surfaces of the plug; forming a first initial conductive structure in the first opening; and etching a portion of the first initial conductive structure until the surface of the first dielectric layer is exposed to form a discrete first conductive structure, wherein the first conductive structure is located on the top surface of the gate structure or the top surface of the plug. The first initial conductive structure has a larger dimension perpendicular to the extension direction of the gate structure, thereby reducing the difficulty of the etching process for forming the first initial conductive structure, and the second opening ensures that adjacent first conductive structures are isolated from each other, thereby increasing the process window.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the continuous advancement of integrated circuit manufacturing technology, the requirements for integrated circuit integration and performance are becoming increasingly stringent. To increase integration and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density within integrated circuits is increasing. This development has resulted in insufficient surface area on the wafer to produce the required interconnects.

[0003] The connection plugs within the transistor structure include connection plugs located on the surface of the gate structure, used to connect the gate structure to external circuits; and connection plugs located on the surface of the source and drain doped regions, used to connect the source or drain region of the transistor to external circuits. To further meet the demand for higher integration, further area savings can be achieved by transferring the connection plugs from the gate structure in the isolation region to the gate structure in the active region.

[0004] However, the performance of semiconductor structures formed in the prior art still needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a first dielectric layer and a plurality of gate structures are formed on the substrate, source-drain doped regions are formed in the substrate on both sides of the gate structures, and plugs are formed on the top surfaces of the source-drain doped regions, and the first dielectric layer is located on the surfaces of the gate structures, the source-drain doped regions, and the plugs; forming a second dielectric layer on the surfaces of the first dielectric layer, the top surfaces of the gate structures, and the top surfaces of the plugs; forming a first opening in the second dielectric layer to expose the surface of the first dielectric layer, and the first opening exposes the top surfaces of at least two gate structures, at least two plugs, or the top surfaces of adjacent gate structures and plugs; forming a first initial conductive structure in the first opening; etching a portion of the first initial conductive structure until the surface of the first dielectric layer is exposed to form a discrete first conductive structure, wherein the first conductive structure is located on the top surface of the gate structure or the top surface of the plug.

[0007] Optionally, the method for forming the first opening includes: forming a first patterned layer on the surface of the second dielectric layer, the first patterned layer exposing a portion of the surface of the second dielectric layer; using the first patterned layer as a mask, etching the second dielectric layer until the top surface of the gate structure or the top surface of the plug is exposed, thereby forming the first opening in the second dielectric layer.

[0008] Optionally, a first stop layer is further provided on the surface of the first dielectric layer, and the second dielectric layer is located on the surface of the first stop layer.

[0009] Optionally, a material of the first stop layer includes silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride oxide, or silicon nitride oxide.

[0010] Optionally, the top surface of the gate structure has a first protective layer; the method for forming the first opening also includes: using the first patterned layer as a mask, etching the second dielectric layer to expose the top surface of the first stop layer; etching the first stop layer and the first protective layer located on the top surface of the gate structure until the top surface of the gate structure is exposed, forming the first opening in the second dielectric layer.

[0011] Optionally, the top surface of the first protective layer is flush with the top surface of the first dielectric layer; the material of the first protective layer includes: silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride or silicon oxynitride.

[0012] Optionally, the top surface of the plug has a second protective layer; the method for forming the first opening also includes: using the first patterned layer as a mask, etching the second dielectric layer to expose the top surface of the first stop layer; etching the first stop layer and the first protective layer located on the top surface of the plug until the top surface of the plug is exposed, thereby forming the first opening in the second dielectric layer.

[0013] Optionally, the top surface of the second protective layer is flush with the top surface of the first dielectric layer; the material of the second protective layer includes: silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride or silicon oxynitride.

[0014] Optionally, the method for forming a first initial conductive structure in the first opening includes: forming a first conductive material film in the first opening and on the surface of the second dielectric layer, the first conductive material film filling the first opening; flattening the first conductive material film until the surface of the second dielectric layer is exposed, and forming the first initial conductive structure in the first opening.

[0015] Optionally, along an extension direction perpendicular to the gate structure, the first conductive structure has a first size, a spacing between adjacent first conductive structures is a second size, and the second size is greater than the first size.

[0016] Optionally, the method for etching the first initial conductive structure includes: forming a second patterned layer on the surface of the second dielectric layer and the surface of the first initial conductive structure, the second patterned layer exposing a portion of the surface of the first initial conductive structure; using the second patterned layer as a mask, etching the first initial conductive structure until the surface of the first dielectric layer is exposed, and forming a discrete first conductive structure in the second dielectric layer.

[0017] Optionally, it also includes: after forming the first initial conductive structure and before forming the second patterned layer, forming a second stop layer on the surface of the second dielectric layer and the surface of the first initial conductive structure; the material of the second stop layer includes: silicon oxide, silicon carbide, silicon nitride, silicon carbide, silicon boron nitride, silicon carbon nitride or silicon nitride oxide.

[0018] Optionally, the method further includes: forming an isolation layer between adjacent first conductive structures.

[0019] Optionally, there is a second opening between adjacent first conductive structures; the method for forming the isolation layer includes: forming an isolation material film in the second opening and on the surface of the second dielectric layer, and the isolation material film fills the second opening; flattening the isolation material film until the surface of the second dielectric layer is exposed, and forming the isolation layer in the second opening.

[0020] Optionally, the method further includes: forming a second conductive structure located on a top surface of the plug or gate structure in the second dielectric layer.

[0021] Optionally, the method for forming the second conductive structure includes: forming a third patterned layer on the surface of the second dielectric layer, the third patterned layer exposing a portion of the surface of the second dielectric layer; using the third patterned layer as a mask, etching the second dielectric layer until the top surface of the plug or the top surface of the gate structure is exposed, and forming a third opening in the second dielectric layer; forming a second conductive material film in the third opening and on the surface of the second dielectric layer, the second conductive material film filling the third opening; and planarizing the second conductive material film until the surface of the second dielectric layer is exposed, thereby forming the second conductive structure.

[0022] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0023] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a first initial conductive structure is first formed, and then the first initial conductive structure is etched to form a discrete first conductive structure. Since the first initial conductive structure is not only located on the top surfaces of at least two gate structures, at least two plug top surfaces, or adjacent gate structure top surfaces and plug top surfaces, but also on the top surface of the first dielectric layer therebetween, the first initial conductive structure has a larger dimension perpendicular to the extension direction of the gate structure, thereby reducing the difficulty of the etching process for forming the first initial conductive structure. Furthermore, by etching the first initial conductive structure to form a discrete first conductive structure, an isolation layer is subsequently formed between adjacent first conductive structures to isolate the first conductive structure, which is beneficial for increasing the process window. In summary, this is beneficial for improving the performance of the formed semiconductor structure.

[0024] Furthermore, by etching the first initial conductive structure, the first initial conductive structure is formed into a first conductive structure. Along the extension direction perpendicular to the gate structure, the spacing between adjacent first conductive structures is greater than the size of the first conductive structure, that is, the distance between the adjacent first conductive structures is large, so that the size of the formed first conductive structure meets the process requirements while the process difficulty of etching the first initial conductive structure is low, which is conducive to improving the performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 2 It is a structural schematic diagram of each step of a conventional method for forming a semiconductor structure;

[0026] Figures 3 to 14 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention;

[0027] Figures 15 to 19 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0028] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0029] First, the reasons why the performance of the existing semiconductor structure is poor are described in detail with reference to the accompanying drawings. Figures 1 to 2 The present invention is a structural schematic diagram of each step of a conventional method for forming a semiconductor structure.

[0030] Please refer to Figure 1A substrate 100 is provided, wherein a first dielectric layer 120 and a plurality of gate structures 110 are formed on the substrate 100. Source-drain doped regions 130 are formed in the substrate 100 on both sides of the gate structures 110, and plugs 140 are formed on the surfaces of the source-drain doped regions 130. The first dielectric layer 120 is located on the gate structures 110, the source-drain doped regions 130, and the plug surfaces 140. A second dielectric layer 150 is formed on the surface of the first dielectric layer 120.

[0031] Please refer to Figure 2 , a second opening (not shown in the figure) is formed in the second dielectric layer 150 , wherein the second opening exposes the top surface of the gate structure 110 ; and a second conductive structure 170 is formed in the second opening.

[0032] In the above method, the gate structure 110 is electrically connected to the peripheral circuit via the second conductive structure 170 .

[0033] However, as the integration requirements of integrated circuits gradually increase, not only are the critical dimensions of each gate structure 110 becoming smaller, but the distance between adjacent gate structures 110 is also becoming closer. If the size of the second conductive structure 170 formed on the gate structure 110 is large, due to the small distance between adjacent gate structures 110, the spacing between the second conductive structures 170 on the gate structures 110 that are closer is too small, which can easily lead to bridging between adjacent second conductive structures 170, resulting in poor performance of the formed semiconductor structure. If the size of the second conductive structure 170 formed on the gate structure 110 is small, although it is beneficial to increase the spacing between the second conductive structures 170 on adjacent gate structures 110, forming a second opening that is too small often exceeds the limit of the existing photolithography process, resulting in poor morphology of the second conductive structure 170 or even failure to form.

[0034] To address the aforementioned technical issues, an embodiment of the present invention provides a method for forming a semiconductor structure. This method involves first forming a first initial conductive structure and then etching the first initial conductive structure to form a discrete first conductive structure. The first initial conductive structure has a larger dimension perpendicular to the gate structure's extension direction, reducing the difficulty of the etching process for forming the first initial conductive structure. Furthermore, the second opening ensures isolation between adjacent first conductive structures, facilitating an increase in the process window. In summary, this method is beneficial for improving the performance of the resulting semiconductor structure.

[0035] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Figures 3 to 141 is a schematic structural diagram of each step of a method for forming a semiconductor structure in an embodiment of the present invention.

[0037] Please refer to Figure 3 A substrate 200 is provided, on which a first dielectric layer 220 and a plurality of gate structures 210 are provided. Source-drain doped regions 230 are provided in the substrate 200 on both sides of the gate structures 210, and plugs 240 are provided on the top surfaces of the source-drain doped regions 230. The first dielectric layer 220 is located on the surfaces of the gate structures 210, the source-drain doped regions 230, and the plugs 240.

[0038] In this embodiment, the substrate 200 is single crystal silicon. In other embodiments, the substrate may be made of semiconductor materials such as single crystal germanium, silicon germanium, gallium arsenide, or a semiconductor-on-insulator structure.

[0039] The gate structure 210 includes a gate dielectric layer (not shown) and a gate layer (not shown) located on the surface of the gate dielectric layer. The gate dielectric layer is made of silicon oxide or a high-K dielectric material. The gate electrode layer is made of polysilicon or metal.

[0040] The material of the plug 240 includes cobalt, copper, tungsten, aluminum, titanium or tantalum. In this embodiment, the material of the plug 240 is tungsten.

[0041] The material of the first dielectric layer 220 includes silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride oxide, or silicon oxynitride. In this embodiment, the material of the first dielectric layer 220 is silicon oxide.

[0042] In this embodiment, a first stop layer 221 is further formed on the surface of the first dielectric layer 220 .

[0043] The first stop layer 221 serves as an indicator stop layer for subsequent etching processes.

[0044] The material of the first stop layer 221 includes silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride or silicon oxynitride. In this embodiment, the material of the first stop layer 221 is silicon nitride.

[0045] In this embodiment, the top surface of the gate structure 210 further has a first protection layer 211 .

[0046] The first protection layer 211 is used to protect the top surface of the gate structure 210 , reducing the impact of subsequent processes, and is beneficial to the performance of the gate structure 210 .

[0047] The top surface of the first protective layer 211 is flush with the top surface of the first dielectric layer 220. The material of the first protective layer 211 includes silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride, or silicon oxynitride. In this embodiment, the material of the first protective layer 211 is silicon nitride.

[0048] In other embodiments, the top surface of the gate structure may not have the first protection layer.

[0049] In this embodiment, the top surface of the plug 240 further has a second protective layer 241 .

[0050] The second protection layer 241 is used to protect the top surface of the plug 240 , reducing the impact of subsequent processes, and improving the performance of the plug 240 .

[0051] The top surface of the second protective layer 241 is flush with the top surface of the first dielectric layer 220. The material of the second protective layer 241 includes silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride oxide, or silicon oxynitride. In an embodiment, the material of the second protective layer 241 is silicon carbide.

[0052] Please refer to Figure 4 A second dielectric layer 250 is formed on the surface of the first dielectric layer 220 , the top surface of the gate structure 210 , and the top surface of the plug 240 .

[0053] The second dielectric layer 250 provides support for the subsequent formation of the first initial conductive structure.

[0054] Specifically, the second dielectric layer 250 is formed on the surface of the first stop layer 221 .

[0055] The material of the second dielectric layer 250 is different from that of the first stop layer 221 .

[0056] The material of the second dielectric layer 250 includes silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride oxide, or silicon oxynitride. In this embodiment, the second dielectric layer 250 and the first dielectric layer 220 are made of the same material, silicon oxide.

[0057] Please refer to Figure 5 and Figure 6 , Figure 6 for Figure 5In a top view along the Y direction, a third patterned layer 251 is formed on the surface of the second dielectric layer 250, and the third patterned layer 251 exposes a portion of the surface of the second dielectric layer 250. Using the third patterned layer 251 as a mask, the second dielectric layer 250 is etched until the top surface of the plug 240 is exposed, thereby forming a third opening 260 in the second dielectric layer 250.

[0058] The third opening 260 provides space for subsequently forming a second conductive structure.

[0059] In this embodiment, the third opening 260 exposes the top surface of the plug 240 , so that the second conductive structure subsequently formed in the third opening 260 is located on the top surface of the plug 240 .

[0060] In other embodiments, the third opening exposes the top surface of the gate structure, so that the second conductive structure subsequently formed in the third opening is located on the top surface of the gate structure.

[0061] In this embodiment, specifically, the second dielectric layer 250 is etched using the third patterned layer 251 as a mask to expose the top surface of the first stop layer 221; the first stop layer 221 and the first protective layer 241 located on the top surface of the plug 240 are etched until the top surface of the plug 240 is exposed, thereby forming the third opening 260 in the second dielectric layer 250.

[0062] In this embodiment, after forming the third opening 260 , the process further includes: removing the third patterned layer 251 .

[0063] Next, a first opening is formed in the second dielectric layer 250 to expose the surface of the first dielectric layer 250 , and the first opening exposes at least two gate structure 210 surfaces, at least two top surfaces of the plugs 240 , or adjacent gate structure 210 top surfaces and plug 240 top surfaces.

[0064] In this embodiment, after forming the third opening 260 in the second dielectric layer 250 to expose the top surface of the plug 240, a first opening is formed in the second dielectric layer 250 to expose the surface of the first dielectric layer 220, and the first opening exposes the top surfaces of at least two gate structures 210. For the specific process of forming the first opening, please refer to Figures 6 and 7 .

[0065] Please refer to Figure 7 A first patterned layer 252 is formed on the surface of the second dielectric layer 250 , and the first patterned layer 252 exposes a portion of the surface of the second dielectric layer 250 .

[0066] The first patterned layer 252 provides a mask for subsequently forming a first opening.

[0067] Specifically, the first patterned layer 252 is formed in the third opening 260 and on the surface of the second dielectric layer 250 , and the first patterned layer 252 exposes the surface of the second dielectric layer 250 on adjacent gate structures 210 and on the first dielectric layer 220 between adjacent gate structures 210 .

[0068] Please refer to Figure 8 and Figure 9 , Figure 9 for Figure 8 In a top view along the Y direction, the second dielectric layer 250 is etched using the first patterned layer 252 as a mask until the top surface of the gate structure 210 is exposed, thereby forming the first opening 280 in the second dielectric layer 250 .

[0069] The first opening 280 provides a space for subsequently forming a first initial conductive structure.

[0070] Specifically, the first opening 280 exposes the top surfaces of adjacent gate structures 210 and the surface of the first dielectric layer 220 between adjacent gate structures 210 .

[0071] In this embodiment, specifically, the second dielectric layer 250 is etched using the first patterned layer 252 as a mask to expose the top surface of the first stop layer 221; the first stop layer 221 and the first protective layer 211 located on the top surface of the gate structure 210 are etched until the top surface of the gate structure 210 is exposed, and the first opening 280 is formed in the second dielectric layer 250.

[0072] In another embodiment, the first opening exposes at least two gate structure top surfaces and a top surface of a plug located between the gate structures.

[0073] In yet another embodiment, the first opening exposes at least two plug top surfaces and a top surface of the gate structure located between the plugs.

[0074] In this embodiment, the first opening 280 exposes the top surfaces of the two gate structures 210 .

[0075] In other embodiments, the first opening exposes one or more gate structure tops.

[0076] When the first opening exposes a top surface of the gate structure, the first opening also exposes more than one top surface of the plug.

[0077] Since the first opening 280 is not only located on the top surface of the adjacent gate structure 210, but also on the surface of the first dielectric layer 220 between the adjacent gate structures 210, the first opening 280 is larger in size along the extension direction perpendicular to the gate structure 210, which reduces the difficulty of the etching process for forming the first opening 280, thereby reducing the difficulty of subsequently forming the first initial conductive structure in the first opening 280.

[0078] In this embodiment, after the first opening 280 is formed, the first patterned layer 252 is removed.

[0079] In this embodiment, since the first patterned layer 252 is still filled in the third opening 260 , the third opening 260 is exposed after the first patterned layer 252 is removed.

[0080] Please refer to Figure 10 , a first initial conductive structure 291 is formed in the first opening 280 .

[0081] The method for forming the first initial conductive structure 291 in the first opening 280 includes: forming a first conductive material film (not shown in the figure) in the first opening 280 and on the surface of the second dielectric layer 250, so that the first conductive material film completely fills the first opening 280; planarizing the first conductive material film until the surface of the second dielectric layer 250 is exposed, thereby forming the first initial conductive structure 291 in the first opening 280.

[0082] Since the first initial conductive structure 291 is not only located on the top surfaces of at least two gate structures 210, the top surfaces of at least two plugs 240, or the top surfaces of adjacent gate structures 210 and plugs 240, but also located on the top surface of the first dielectric layer 220 therebetween, the first initial conductive structure 291 has a larger dimension along the direction perpendicular to the extension direction of the gate structure 210, thereby reducing the difficulty of the etching process for forming the first initial conductive structure 291.

[0083] In this embodiment, after forming the first opening 280 , the method further includes forming a second conductive structure 270 in the third opening 260 .

[0084] The method for forming the second conductive structure 270 includes: forming a second conductive material film (not shown in the figure) in the third opening 260 and on the surface of the second dielectric layer 250, so that the second conductive material film completely fills the third opening 260; and planarizing the second conductive material film until the surface of the second dielectric layer 250 is exposed to form the second conductive structure 270.

[0085] In this embodiment, the first conductive material film and the second conductive material film are formed by the same deposition process, and after the planarization process, the first initial conductive structure 291 and the second conductive structure 270 are formed in the same process, thereby simplifying the process steps and improving production efficiency.

[0086] In other embodiments, the first opening is formed before the third opening is formed.

[0087] Next, a portion of the first initial conductive structure 291 is etched until the surface of the first dielectric layer 220 is exposed to form a discrete first conductive structure. The first conductive structure is located on the top surface of the gate structure 210. For a specific process of etching the first initial conductive structure, please refer to Figures 11 to 12 .

[0088] Please refer to Figure 11 A second patterned layer 254 is formed on the surface of the second dielectric layer 250 and the surface of the first initial conductive structure 291 , and the second patterned layer 254 exposes a portion of the surface of the first initial conductive structure 291 .

[0089] The second patterned layer 254 provides a mask for subsequent etching of the first initial conductive structure 291 .

[0090] In this embodiment, after forming the first initial conductive structure 291 and before forming the second patterned layer 254, it also includes: forming a second stop layer 253 on the surface of the second dielectric layer 250 and the surface of the first initial conductive structure 291, and the second patterned layer 254 is located on the surface of the second stop layer 253.

[0091] The second stop layer 253 serves as an indicator stop layer for subsequent etching processes.

[0092] The material of the second stop layer 253 includes silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride oxide, or silicon nitride oxide. In this embodiment, the material of the second stop layer 253 is silicon nitride. In other embodiments, the second stop layer may not be formed.

[0093] Please refer to Figure 12 Using the second patterned layer 254 as a mask, the first initial conductive structure 291 is etched until the surface of the first dielectric layer 220 is exposed, thereby forming a discrete first conductive structure 292 in the second dielectric layer 250 .

[0094] It should be noted that the process of etching the first initial conductive structure 291 is an over-etching process to ensure that the metal material residue in the second opening 293 caused by etching the first initial conductive structure 291 can be fully removed, thereby improving the performance of the formed semiconductor structure.

[0095] In this embodiment, the first conductive structures 292 are all located on the gate structure 210 .

[0096] In another embodiment, the first conductive structures are all located on the plugs.

[0097] In yet another embodiment, one of the first conductive structures is located on the gate structure, and another of the first conductive structures is located on the plug.

[0098] Along an extending direction perpendicular to the gate structure 210 , the first conductive structures 292 have a first size W1 , and a spacing between adjacent first conductive structures 292 is a second size W2 , and the second size W2 is greater than the first size W1 .

[0099] By etching the first initial conductive structure 291, the first initial conductive structure 291 is formed into a first conductive structure 292. Along the extension direction perpendicular to the gate structure 210, the spacing between adjacent first conductive structures 292 is greater than the size of the first conductive structure 292, that is, the distance between adjacent first conductive structures 292 is large, so that the size of the formed first conductive structure 292 meets the process requirements, and the process difficulty of etching the first initial conductive structure 291 is low, which is conducive to improving the performance of the formed semiconductor structure.

[0100] Specifically, there is a second opening 293 between adjacent first conductive structures 292 , and the second opening 293 exposes the surface of the first dielectric layer 220 .

[0101] In this embodiment, after forming the first conductive structure 292 , the method further includes: removing the first patterned layer 252 and the second stop layer 253 .

[0102] Next, after forming the first conductive structure 292, the process further includes: forming an isolation layer between adjacent first conductive structures 292. For details on the process of forming the isolation layer, please refer to Figure 13 and Figure 14 .

[0103] Please refer to Figure 13 and Figure 14 , Figure 14 for Figure 13 In the top view along the Y direction, at the second opening 293 ( Figure 12 An isolation material film (not shown in the figure) is formed inside the second dielectric layer 250 and on the surface of the second dielectric layer 250, and the isolation material film fills the second opening 293; the isolation material film is planarized until the surface of the second dielectric layer 250 is exposed, and the isolation layer 295 is formed in the second opening 293.

[0104] By forming an isolation layer 295 in the second opening 293 , adjacent first conductive structures 292 are electrically isolated from each other.

[0105] The material of the isolation layer 295 includes silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride oxide, or silicon oxynitride. In this embodiment, the material of the isolation layer 295 is silicon oxide.

[0106] Since the second opening 293 is relatively large in size and has a relatively small depth-to-width ratio, it is beneficial for the material forming the isolation layer 295 to be fully filled in the second opening 293 , thereby improving the performance of the formed semiconductor structure.

[0107] Figures 15 to 19 This is a cross-sectional structural diagram of the formation process of a semiconductor structure according to another embodiment of the present invention. The difference between this embodiment and the above embodiment is that the positions of the first conductive structure and the second conductive structure are different. Therefore, this embodiment continues to explain the formation process of the semiconductor structure based on the above embodiment. Figure 4 Continue to refer to Figure 15 .

[0108] Please refer to Figure 15 A third patterned layer 351 is formed on the surface of the second dielectric layer 250, and the third patterned layer 351 exposes a portion of the surface of the second dielectric layer 250. The second dielectric layer 250 is etched using the third patterned layer 251 as a mask until the top surface of the plug gate structure 210 is exposed, thereby forming a third opening 310 in the second dielectric layer 250.

[0109] The third opening 310 provides space for subsequently forming a second conductive structure.

[0110] In this embodiment, the third opening 310 exposes the top surface of the gate structure 210 , so that the second conductive structure subsequently formed in the third opening 310 is located on the top surface of the gate structure 210 .

[0111] Next, after forming the third opening 310 in the second dielectric layer 250 to expose the top surface of the gate structure 210 , a first opening is formed in the second dielectric layer 250 to expose the surface of the first dielectric layer 220 , and the first opening exposes the top surfaces of at least two plugs 240 .

[0112] Please refer to Figure 16 A first opening 320 is formed in the second dielectric layer 250 to expose the surface of the first dielectric layer 220 , and the first opening 320 exposes the top surface of the plug 240 .

[0113] Specifically, the first opening 320 exposes the top surfaces of two adjacent plugs 240 .

[0114] In this embodiment, the first opening 320 further exposes the top surface of the gate structure 210 between the plugs 240 .

[0115] In this embodiment, the first opening 320 exposes the top surfaces of the two plugs 240 .

[0116] In other embodiments, the first opening exposes one or more than three plug top surfaces. When the first opening exposes one plug top surface, the first opening also exposes more than one gate structure top surfaces.

[0117] The method for forming the first opening 320 includes: forming a first patterned layer (not shown in the figure) on the surface of the second dielectric layer 250, wherein the first patterned layer exposes a portion of the surface of the second dielectric layer 250; using the first patterned layer as a mask, etching the second dielectric layer 250 until the top surface of the plug 240 is exposed, thereby forming the first opening 320 in the second dielectric layer 250.

[0118] Please refer to Figure 17 , a first initial conductive structure 330 is formed in the first opening 320 .

[0119] The method for forming the first preliminary conductive structure 330 is the same as the method for forming the first preliminary conductive structure 291 in the above embodiment, and will not be repeated here.

[0120] It should be noted that, in this embodiment, the first initial conductive structure 330 is located on the top surfaces of adjacent plugs 240 and the surface of the first dielectric layer 220 between adjacent plugs 240 .

[0121] In this embodiment, after forming the first opening 320 , the method further includes: forming a second conductive structure 340 in the third opening 310 .

[0122] The method for forming the second conductive structure 340 is the same as the method for forming the second conductive structure 270 in the above embodiment, and will not be repeated here.

[0123] It should be noted that, in this embodiment, the second conductive structure 340 is located on the top surface of the gate structure 210 .

[0124] Please refer to Figure 18 , a portion of the first initial conductive structure 330 is etched until the surface of the first dielectric layer 220 is exposed, thereby forming a discrete first conductive structure 350 , which is located on the top surface of the plug 240 .

[0125] The method of etching a portion of the first initial conductive structure 330 is the same as the method of etching a portion of the first initial conductive structure 291 in the above embodiment, and will not be repeated here.

[0126] Please refer to Figure 19 , an isolation layer 370 is formed between adjacent first conductive structures 350 .

[0127] The isolation layer 370 is formed in the same manner as the isolation layer 295 in the above embodiment, and will not be further described herein.

[0128] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a first dielectric layer and a plurality of gate structures, the substrate has source and drain doped regions on both sides of the gate structures, and the top surfaces of the source and drain doped regions have plugs, and the first dielectric layer is located on the surfaces of the gate structures, the source and drain doped regions, and the plugs; forming a second dielectric layer on the surface of the first dielectric layer, the top surface of the gate structure, and the top surface of the plug; forming a first opening in the second dielectric layer to expose a surface of the first dielectric layer, wherein the first opening exposes at least two top surfaces of the gate structures, at least two top surfaces of the plugs, or adjacent top surfaces of the gate structures and the plugs; forming a first initial conductive structure in the first opening; A portion of the first initial conductive structure is etched until the surface of the first dielectric layer is exposed to form a discrete first conductive structure, where the first conductive structure is located on a top surface of the gate structure or a top surface of the plug.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the first opening includes: forming a first patterned layer on the surface of the second dielectric layer, the first patterned layer exposing a portion of the surface of the second dielectric layer; using the first patterned layer as a mask, etching the second dielectric layer until the top surface of the gate structure or the top surface of the plug is exposed, thereby forming the first opening in the second dielectric layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: A first stop layer is further provided on the surface of the first dielectric layer, and the second dielectric layer is located on the surface of the first stop layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The material of the first stop layer includes silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride oxide or silicon nitride oxide.

5. The method for forming a semiconductor structure according to claim 3, wherein: The top surface of the gate structure has a first protective layer; the method for forming the first opening also includes: using the first patterned layer as a mask, etching the second dielectric layer to expose the top surface of the first stop layer; etching the first stop layer and the first protective layer located on the top surface of the gate structure until the top surface of the gate structure is exposed, forming the first opening in the second dielectric layer.

6. The method for forming a semiconductor structure according to claim 5, wherein: The top surface of the first protective layer is flush with the top surface of the first dielectric layer; the material of the first protective layer includes: silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride or silicon oxynitride.

7. The method for forming a semiconductor structure according to claim 3, wherein: The top surface of the plug has a second protective layer; the method for forming the first opening also includes: using the first patterned layer as a mask, etching the second dielectric layer to expose the top surface of the first stop layer; etching the first stop layer and the first protective layer located on the top surface of the plug until the top surface of the plug is exposed, thereby forming the first opening in the second dielectric layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: The top surface of the second protective layer is flush with the top surface of the first dielectric layer; the material of the second protective layer includes: silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride or silicon oxynitride.

9. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming a first initial conductive structure in the first opening includes: forming a first conductive material film in the first opening and on the surface of the second dielectric layer, the first conductive material film filling the first opening; flattening the first conductive material film until the surface of the second dielectric layer is exposed, and forming the first initial conductive structure in the first opening.

10. The method for forming a semiconductor structure according to claim 1, wherein: Along a direction perpendicular to the extension direction of the gate structure, the first conductive structure has a first size, a spacing between adjacent first conductive structures is a second size, and the second size is greater than the first size.

11. The method for forming a semiconductor structure according to claim 1, wherein: The method for etching the first initial conductive structure includes: forming a second patterned layer on the surface of the second dielectric layer and the surface of the first initial conductive structure, the second patterned layer exposing a portion of the surface of the first initial conductive structure; using the second patterned layer as a mask, etching the first initial conductive structure until the surface of the first dielectric layer is exposed, thereby forming a discrete first conductive structure in the second dielectric layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: Also includes: After forming the first initial conductive structure and before forming the second patterned layer, forming a second stop layer on the surface of the second dielectric layer and the surface of the first initial conductive structure; The material of the second stop layer includes silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride oxide, or silicon nitride oxide.

13. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: An isolation layer is formed between adjacent first conductive structures.

14. The method for forming a semiconductor structure according to claim 13, wherein: There is a second opening between adjacent first conductive structures; The method for forming the isolation layer includes: forming an isolation material film in the second opening and on the surface of the second dielectric layer, wherein the isolation material film fills the second opening; flattening the isolation material film until the surface of the second dielectric layer is exposed, and forming the isolation layer in the second opening.

15. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: A second conductive structure is formed in the second dielectric layer and located on a top surface of the plug or gate structure.

16. The method for forming a semiconductor structure according to claim 15, wherein: The method for forming the second conductive structure includes: forming a third patterned layer on the surface of the second dielectric layer, the third patterned layer exposing a portion of the surface of the second dielectric layer; etching the second dielectric layer using the third patterned layer as a mask until the top surface of the plug or the top surface of the gate structure is exposed, thereby forming a third opening in the second dielectric layer; forming a second conductive material film in the third opening and on the surface of the second dielectric layer, wherein the second conductive material film completely fills the third opening; and planarizing the second conductive material film until the surface of the second dielectric layer is exposed, thereby forming the second conductive structure.

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