Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, a gate structure, a gate cap layer located on the top of the gate structure, source-drain doped regions in the substrate located on both sides of the gate structure, and a bottom dielectric layer located on the substrate at the side of the gate structure; forming a source-drain interconnection layer penetrating the bottom dielectric layer at the top of the source-drain doped region, the top surface of the source-drain interconnection layer and the adjacent gate cap layer forming a groove for forming a source-drain cap layer; ion doping the sidewall of the gate cap layer through the groove, suitable for improving the etching selectivity between the source-drain cap layer and the gate cap layer; after ion doping, forming a source-drain cap layer in the groove; forming a top dielectric layer covering the gate cap layer and the source-drain cap layer; forming a source-drain contact hole penetrating the top dielectric layer and the source-drain cap layer; and forming a source-drain plug in the source-drain contact hole. The embodiment of the present invention reduces the probability of short circuit or breakdown between the source-drain plug and the adjacent gate structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve integration and reduce costs, the key dimensions of components are constantly decreasing, and the circuit density inside the integrated circuit is increasing. This development makes it impossible for the wafer surface to provide enough area to make the required interconnection lines.

[0003] In order to meet the needs of interconnection lines after the critical dimensions are reduced, the conduction between different metal layers or between a metal layer and a substrate is currently achieved through an interconnection structure. The interconnection structure includes interconnection lines and contact plugs formed in contact openings. The contact plugs are connected to semiconductor devices, and the interconnection lines realize the connection between the contact plugs, thereby forming a circuit. The contact plugs in the transistor structure include gate contact plugs located on the gate structure, which are used to realize the connection between the gate structure and the external circuit, and also include source and drain contact plugs located on the source and drain doping regions, which are used to realize the connection between the source and drain doping regions and the external circuit.

[0004] At present, in order to further reduce the area of ​​transistors, the contact over active gate (COAG) process has been introduced. Compared with the traditional gate contact plug located above the gate structure in the isolation area, the COAG process can place the gate contact plug above the gate structure in the active area (AA), thereby further saving the chip area.

[0005] However, the current COAG process still has great challenges, and short circuits or breakdowns are easily caused between the source and drain plugs and the adjacent gate structures. Summary of the invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to reduce the probability of short circuit or breakdown between the source-drain plug and the adjacent gate structure.

[0007] In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, a gate structure is formed on the substrate, a gate cap layer is formed on the top of the gate structure, source and drain doped regions are formed in the substrate on both sides of the gate structure, a bottom dielectric layer covering the source and drain doped regions is formed on the substrate on the sides of the gate structure and the gate cap layer; forming a source and drain interconnection layer that penetrates the bottom dielectric layer on the top of the source and drain doped regions and contacts the source and drain doped regions, the top surface of the source and drain interconnection layer is lower than the top surface of the bottom dielectric layer, and the top surface of the source and drain interconnection layer is Adjacent gate capping layers form a groove, and the groove is used to form a source-drain capping layer; through the groove, ion doping is performed on the side wall of the gate capping layer, which is suitable for improving the etching selectivity between the source-drain capping layer and the gate capping layer; after ion doping, a source-drain capping layer is formed in the groove; a top dielectric layer covering the gate capping layer and the source-drain capping layer is formed on the bottom dielectric layer; a source-drain contact hole is formed that penetrates the top dielectric layer and the source-drain capping layer to expose the source-drain interconnection layer; and a source-drain plug in contact with the source-drain interconnection layer is formed in the source-drain contact hole.

[0008] Correspondingly, an embodiment of the present invention also provides a semiconductor structure, comprising: a substrate; a gate structure located on the substrate; a gate cap layer located on the top of the gate structure; a source-drain doped region located in the substrate on both sides of the gate structure; a bottom dielectric layer located on the substrate on the sides of the gate structure and the gate cap layer; a source-drain interconnection layer penetrating the bottom dielectric layer at the top of the source-drain doped region and contacting the source-drain doped region, the top surface of the source-drain interconnection layer being lower than the top surface of the bottom dielectric layer; a source-drain cap layer located on the top of the source-drain interconnection layer; wherein the sidewalls of the gate cap layer have doped ions, and the doped ions are suitable for improving the etching selectivity between the source-drain cap layer and the gate cap layer; a top dielectric layer located on the bottom dielectric layer and covering the gate cap layer and the source-drain cap layer; a source-drain plug penetrating the source-drain cap layer and the top dielectric layer at the top of the source-drain interconnection layer and contacting the source-drain interconnection layer.

[0009] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0010] In the method for forming a semiconductor structure provided by an embodiment of the present invention, in the step of forming the source-drain interconnection layer, the groove surrounded by the source-drain interconnection layer and the adjacent gate cap layer is used to form the source-drain cap layer. After the source-drain interconnection layer is formed, the side wall of the gate cap layer is ion-doped through the groove, which is suitable for improving the etching selectivity between the source-drain cap layer and the gate cap layer. Therefore, in the step of forming a source-drain contact hole penetrating the top dielectric layer and the source-drain cap layer, since the source-drain cap layer and the gate cap layer have a higher etching selectivity, it is beneficial to reduce the probability of causing mis-etching to the gate cap layer, and therefore it is beneficial to ensure the protective effect of the gate cap layer on the gate structure and improve the cross-section controllability of the source-drain contact hole. Accordingly, after the source-drain plug is formed in the source-drain contact hole, it is beneficial to reduce the probability of short circuit (Short) or breakdown between the source-drain plug and the adjacent gate structure, thereby improving the performance and production yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 4 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0012] Figures 5 to 15 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0013] As can be seen from the background technology, the current COAG process still has great challenges, and short circuits or breakdowns are easily caused between the source and drain plugs and the adjacent gate structures. The reasons why the COAG process has great challenges are now analyzed in combination with a method for forming a semiconductor structure.

[0014] Figures 1 to 4 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1 , providing a substrate (not shown), a gate structure 1 is formed on the substrate, a gate cap layer 2 is formed on the top of the gate structure 1, source-drain doped regions 3 are formed in the substrate on both sides of the gate structure 1, a bottom dielectric layer (not shown) covering the source-drain doped regions 3 is formed on the substrate on the sides of the gate structure 1 and the gate cap layer 2, a source-drain interconnection layer 4 in contact with the source-drain doped regions 3 is formed in the bottom dielectric layer on the top of the source-drain doped regions 3, and a source-drain cap layer 5 is formed on the top of the source-drain interconnection layer 4.

[0016] refer to Figure 2 , a top dielectric layer 6 is formed on the bottom dielectric layer to cover the gate cap layer 2 and the source / drain cap layer 5 .

[0017] refer to Figure 3 , forming a gate plug 7 penetrating the gate cap layer 2 and the top dielectric layer 6 and contacting the gate structure 1; forming a source-drain plug 8 penetrating the source-drain cap layer 5 and the top dielectric layer 6 and contacting the source-drain doped region 3.

[0018] The gate cap layer 2 is used to protect the top of the gate structure 1 during the process of forming the source-drain plug 8; the source-drain cap layer 5 is used to protect the top of the source-drain doped layer 4 during the process of forming the gate plug 7.

[0019] However, in the current process, it is difficult to simultaneously ensure that the process of etching the gate cap layer 2 has a high etching selectivity to the source-drain cap layer 5, and the process of etching the source-drain cap layer 5 has a high etching selectivity to the gate cap layer 2. For example, in the etching process of etching the top dielectric layer 6 and the source-drain cap layer 5 to form source-drain contact holes, it is difficult to achieve a high selectivity between the source-drain cap layer 5 and the gate cap layer 2, which makes it easy for the etching process to cause mis-etching of the gate cap layer 2, and then the etched cross-sectional morphology is easy to lose control, such as Figure 4 As shown, the source-drain plug 8 and the gate structure 1 are easily short-circuited or broken down (eg Figure 4 This can cause device failure and reduce manufacturing yield.

[0020] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, a gate structure is formed on the substrate, a gate cap layer is formed on the top of the gate structure, source and drain doped regions are formed in the substrate on both sides of the gate structure, a bottom dielectric layer covering the source and drain doped regions is formed on the substrate on the sides of the gate structure and the gate cap layer; forming a source and drain interconnection layer that penetrates the bottom dielectric layer on the top of the source and drain doped regions and contacts the source and drain doped regions, the top surface of the source and drain interconnection layer is lower than the top surface of the bottom dielectric layer, and the top surface of the source and drain interconnection layer is The surface of the substrate and the adjacent gate cap layer form a groove, wherein the groove is used to form a source-drain cap layer; through the groove, ion doping is performed on the side wall of the gate cap layer, which is suitable for improving the etching selectivity between the source-drain cap layer and the gate cap layer; after ion doping, a source-drain cap layer is formed in the groove; a top dielectric layer covering the gate cap layer and the source-drain cap layer is formed on the bottom dielectric layer; a source-drain contact hole is formed that penetrates the top dielectric layer and the source-drain cap layer to expose the source-drain interconnection layer; and a source-drain plug in contact with the source-drain interconnection layer is formed in the source-drain contact hole.

[0021] In the method for forming a semiconductor structure provided by an embodiment of the present invention, in the step of forming the source-drain interconnection layer, the groove surrounded by the source-drain interconnection layer and the adjacent gate cap layer is used to form the source-drain cap layer. After the source-drain interconnection layer is formed, the side wall of the gate cap layer is ion-doped through the groove, which is suitable for improving the etching selectivity between the source-drain cap layer and the gate cap layer. Therefore, in the step of forming a source-drain contact hole penetrating the top dielectric layer and the source-drain cap layer, since the source-drain cap layer and the gate cap layer have a higher etching selectivity, it is beneficial to reduce the probability of causing mis-etching to the gate cap layer, and therefore it is beneficial to ensure the protective effect of the gate cap layer on the gate structure and improve the cross-section controllability of the source-drain contact hole. Accordingly, after the source-drain plug is formed in the source-drain contact hole, it is beneficial to reduce the probability of short circuit (Short) or breakdown between the source-drain plug and the adjacent gate structure, thereby improving the performance and production yield of the semiconductor structure.

[0022] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0023] Figures 5 to 15 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0024] refer to Figure 5 , providing a substrate (not shown), a gate structure 110 is formed on the substrate, a gate cap layer 120 is formed on the top of the gate structure 110, source and drain doped regions 130 are formed in the substrate on both sides of the gate structure 110, and a bottom dielectric layer 140 covering the source and drain doped regions 130 is formed on the substrate on the sides of the gate structure 110 and the gate cap layer 120.

[0025] The substrate is used to provide a process platform for subsequent processes. In this embodiment, the substrate is a planar substrate, and the substrate is a silicon substrate. In other embodiments, the substrate can also be a three-dimensional substrate, for example: the substrate includes a substrate and a fin protruding from the substrate.

[0026] The gate structure 110 is used as a device gate to control the opening or closing of the conductive channel when the device is working. In this embodiment, the gate structure 110 is a metal gate structure, and the gate structure 110 is formed by forming a high k last metal gate last process.

[0027] The gate cap layer 120 is used to protect the top of the gate structure 110 during the subsequent formation of the source-drain interconnection layer and the source-drain plug, thereby reducing the probability of damage to the gate structure 110 and short circuit problems between the gate structure 110 and the source-drain interconnection layer or the source-drain plug.

[0028] Subsequently, a source-drain cap layer is formed on the top of the source-drain interconnection layer to protect the top of the source-drain interconnection layer. Therefore, the gate cap layer 120 is made of a material having etching selectivity with the source-drain cap layer, the bottom dielectric layer 140 and the subsequent top dielectric layer, so as to ensure that the gate cap layer 120 can protect the gate structure 110. In this embodiment, the material of the gate cap layer 120 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. As an example, the material of the gate cap layer 120 is silicon nitride.

[0029] The source-drain doping region 130 is used to provide a carrier source when the device is working. When forming an NMOS device, the source-drain doping region 130 is doped with N-type ions; when forming a PMOS device, the source-drain doping region 130 is doped with P-type ions.

[0030] The bottom dielectric layer 140 is used to isolate adjacent devices. The material of the bottom dielectric layer 140 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon nitride oxide. In this embodiment, the material of the bottom dielectric layer 140 is silicon oxide.

[0031] It should be noted that, in this embodiment, sidewalls 150 are also formed on the sidewalls of the gate structure 110 and the gate cap layer 120 , the source and drain doping regions 130 are located in the substrate on both sides of the gate structure 110 and the sidewalls 150 , and the bottom dielectric layer 140 covers the sidewalls of the sidewalls 150 .

[0032] The sidewall 150 is used to define the formation position of the source-drain doped region 130. The sidewall 150 is located on the sidewall of the gate structure 110 and is also used to protect the sidewall of the gate structure 110. In addition, a source-drain interconnection layer is subsequently formed that penetrates the bottom dielectric layer 140 and contacts the source-drain doped region 130. The sidewall 150 is located between the source-drain interconnection layer and the gate structure 110 and is also used to isolate the source-drain interconnection layer from the gate structure 110.

[0033] In this embodiment, the material of the spacer 150 is a low-k dielectric material or an ultra-low-k dielectric material, which is beneficial to reducing the effective capacitance between the source-drain interconnection layer and the gate structure 110 .

[0034] refer to Figure 6 to Figure 7, forming a source-drain interconnection layer 160 that penetrates the bottom dielectric layer 140 on the top of the source-drain doped region 130 and contacts the source-drain doped region 130, the top surface of the source-drain interconnection layer 160 is lower than the top surface of the bottom dielectric layer 140, and the top surface of the source-drain interconnection layer 160 and the adjacent gate cap layer 120 form a groove 100, and the groove 100 is used to form a source-drain cap layer.

[0035] The source-drain interconnection layer 160 is in contact with the source-drain doped region 130 , and is used to realize electrical connection between the source-drain doped region 130 and an external circuit or other interconnection structure.

[0036] The groove 100 is used to provide a space for the subsequent formation of a source / drain capping layer.

[0037] In this embodiment, in the step of forming the source-drain interconnection layer 160 , the sidewall 150 is located between the source-drain interconnection layer 160 and the gate structure 110 or the gate cap layer 120 , and the groove 100 is surrounded by the sidewall 150 and the top surface of the source-drain interconnection layer 160 .

[0038] In this embodiment, the material of the source-drain interconnection layer 160 is copper. Copper has a low resistivity, which is beneficial to improving the signal delay of the back-end RC and increasing the processing speed of the chip. It is also beneficial to reduce the resistance of the source-drain interconnection layer 160, and correspondingly reduces power consumption. In other embodiments, the material of the source-drain interconnection layer can also be a conductive material such as tungsten or cobalt.

[0039] In this embodiment, the steps of forming the source-drain interconnection layer 160 include: Figure 6 As shown, a source-drain interconnect material layer 155 is formed that penetrates the bottom dielectric layer 140 at the top of the source-drain doped region 130; Figure 7 As shown, a portion of the source-drain interconnect material layer 155 is etched back, and the remaining source-drain interconnect material layer 155 is used as the source-drain interconnect layer 160 .

[0040] The process of forming the source-drain interconnection material layer 155 includes one or more of a chemical vapor deposition process, a physical vapor deposition process and an electrochemical plating process. The process of etching back a portion of the thickness of the source-drain interconnection material layer 155 includes a dry etching process.

[0041] Combined with reference Figure 8 In this embodiment, the method for forming the semiconductor structure further includes: after forming the groove 100 , forming a liner layer 170 at the bottom of the groove 100 .

[0042] In the subsequent step of ion doping the sidewalls of the gate cap layer 120 , the liner layer 170 is used to protect the source-drain interconnection layer 160 , thereby preventing adverse effects on the source-drain interconnection layer 160 , for example, preventing ion doping from affecting the resistivity of the source-drain interconnection layer 160 .

[0043] In this embodiment, in the step of forming the liner layer 170, the liner layer 170 is also formed on the sidewall of the groove 100. The liner layer 170 is also located on the sidewall of the groove 100. In the step of ion doping the sidewall of the gate cap layer 120, ions can also be doped into the liner layer 170 located on the sidewall of the groove 100, and the etching selectivity of the liner layer 170 and the source-drain cap layer can be correspondingly improved, so that in the subsequent step of forming the source-drain contact hole penetrating the top dielectric layer and the source-drain cap layer, it is beneficial to reduce the etching rate of the liner layer 170. The liner layer 170 is located between the gate cap layer 120 and the source-drain cap layer, and the probability of mis-etching the gate cap layer 120 can be further reduced, thereby further reducing the problem of short circuit or breakdown between the source-drain plug and the adjacent gate structure 110. In addition, the liner layer 170 located on the sidewall of the groove 100 can also protect the sidewall 150 on the sidewall of the groove 100.

[0044] The material of the liner layer 170 includes silicon oxide, silicon nitride or silicon oxynitride. As an example, in this embodiment, the material of the liner layer 170 is silicon oxide. Silicon oxide is a commonly used dielectric material in semiconductor processes, which is conducive to improving process compatibility.

[0045] In this embodiment, in the step of forming the liner layer 170 , the liner layer 170 is also formed on the top surfaces of the gate cap layer 120 and the bottom dielectric layer 140 .

[0046] It should be noted that in the step of forming the liner layer 170, the thickness of the liner layer 170 should not be too small or too large. If the thickness of the liner layer 170 is too small, it is easy to cause the liner layer 170 to have an unclear protective effect on the source-drain interconnection layer 160; if the thickness of the liner layer 170 is too large, it is easy to cause the remaining space of the groove 100 to be too small and the remaining opening size of the groove 100 to be too small, which is easy to increase the difficulty of the subsequent process of forming the source-drain cap layer in the groove 100 and reduce the formation quality of the source-drain cap layer in the groove 100. For this reason, in this embodiment, the thickness of the liner layer 170 is to

[0047] In this embodiment, the process of forming the liner layer 170 includes an atomic layer deposition process. The atomic layer deposition process has a high step coverage capability, thereby improving the coverage capability of the liner layer 170 at the bottom and sidewall of the groove 100, and is also beneficial to improving the thickness uniformity and density of the liner layer 170, and is also beneficial to forming a liner layer 170 with a smaller thickness, so that the thickness of the liner layer 170 meets the process requirements.

[0048] refer to Fig. 9 Through the groove 100 , ion doping 200 is performed on the sidewall of the gate capping layer 120 , which is suitable for improving the etching selectivity between the source and drain capping layer and the gate capping layer 120 .

[0049] Ion doping 200 is performed on the sidewall of the gate cap layer 120, which is suitable for improving the etching selectivity between the source-drain cap layer and the gate cap layer 120. Therefore, in the subsequent step of forming source-drain contact holes penetrating the top dielectric layer and the source-drain cap layer, since the source-drain cap layer and the gate cap layer 120 have a higher etching selectivity, it is beneficial to reduce the probability of mis-etching the gate cap layer 120. Accordingly, after the source-drain plug is formed in the source-drain contact hole, it is beneficial to reduce the probability of short circuit (Short) or breakdown between the source-drain plug and the adjacent gate structure 110, thereby improving the performance of the semiconductor structure and the production yield.

[0050] In the present embodiment, in the step of performing ion doping 200 on the sidewalls of the gate cap layer 120, ion doping 200 is also performed on the top of the gate cap layer 120, thereby helping to reduce the probability of mis-etching the top of the gate cap layer 120 in the subsequent process of forming source-drain contact holes, and helping to further reduce the probability of short circuit or breakdown between the source-drain plug and the adjacent gate structure 110.

[0051] In the present embodiment, in the step of performing ion doping 200 on the sidewalls of the gate cap layer 120, ion doping 200 is also performed on the sidewalls 150 located on the sidewalls of the gate cap layer 120, thereby correspondingly improving the etching selectivity ratio between the sidewalls 150 and the source / drain cap layer, thereby helping to reduce the probability of mis-etching the sidewalls 150 located on the sidewalls of the gate cap layer 120 during the process of forming source / drain contact holes, thereby further helping to reduce the probability of short circuit or breakdown between the source / drain plug and the adjacent gate structure 110.

[0052] In the present embodiment, during the step of ion doping 200, ions are also doped into the liner layer 170 located on the side wall of the groove 100, which can correspondingly improve the etching selectivity between the liner layer 170 and the source / drain cap layer, thereby further reducing the probability of mis-etching the liner layer 170 located on the side wall of the groove 100 during the process of forming the source / drain contact holes, thereby further reducing the probability of short circuit or breakdown between the source / drain plug and the adjacent gate structure 110.

[0053] In this embodiment, ion doping 200 is performed on the sidewalls and the top of the gate cap layer 120, which is suitable for improving the hardness of the gate cap layer 120 and correspondingly improving the etching resistance of the ion-doped gate cap layer 120, thereby facilitating improving the etching selectivity ratio between the source and drain cap layer and the gate cap layer 120.

[0054] In this embodiment, the ions ion doped 200 on the sidewall and the top of the gate cap layer 120 include silicon ions, argon ions or germanium ions. As an example, the sidewall and the top of the gate cap layer 120 are doped with silicon ions. The material of the gate cap layer 120 is silicon nitride. By doping the gate cap layer 120 with silicon ions, it is beneficial to increase the silicon content in the gate cap layer 120 material, thereby improving the density and hardness of the gate cap layer 120, and correspondingly improving the etching resistance of the gate cap layer 120.

[0055] In this embodiment, an ion implantation process is used to perform ion doping on the sidewall and top of the gate cap layer 120. The ion implantation process can implant doping ions into the sidewall and top of the gate cap layer 120 by adjusting the implantation angle and energy, and can also adjust the ion doping concentration in the gate cap layer 120 by adjusting the implantation dose.

[0056] In this embodiment, the implanted ions are silicon ions, and the process parameters of the ion implantation include: the angle between the implantation direction and the normal of the substrate surface is 5° to 30°, the implantation dose is 1E12 atoms per square centimeter to 5E15 atoms per square centimeter, and the implantation energy is 1KeV to 20KeV.

[0057] In the present embodiment, in order to ensure that ions can be implanted into the side walls of the gate cap layer 120 and to ensure that the ion dose implanted into the side walls of the gate cap layer 120 can meet the process requirements, thereby being able to achieve the effect of improving the etching resistance of the gate cap layer 120, in the present embodiment, according to the aspect ratio of the groove 100, the angle between the injection direction and the normal to the substrate surface is 5° to 30°.

[0058] In this embodiment, in order to ensure that the etching resistance of the gate cap layer 120 is improved significantly, the implantation dosage is 1E12 atoms per square centimeter to 5E15 atoms per square centimeter.

[0059] In this embodiment, in order to ensure that the ion doping depth in the gate cap layer 120 can meet the process requirements and prevent the ions from being injected into other film layer structures, the injection energy of the ion injection is 1 KeV to 20 KeV.

[0060] The direction perpendicular to the extension direction of the gate structure 110 is the lateral direction. It should be noted that, in this embodiment, the step of performing ion implantation includes: performing a first ion implantation on the gate cap layer 120 on the first side wall of the groove 100 along the lateral direction, and performing a second ion implantation on the gate cap layer 120 on the second side wall of the groove 100, so that ions can be implanted into the gate cap layer 120 on both sides of the groove 100.

[0061] refer to Figure 10 to Figure 11 After ion doping 200 , a source-drain capping layer 180 is formed in the groove 100 .

[0062] Subsequently, a gate plug in contact with the gate structure 110 is formed, and the source-drain capping layer 180 is located on the top surface of the source-drain interconnection layer 160. During the process of forming the gate plug, the source-drain capping layer 180 can protect the source-drain interconnection layer 160, which is beneficial to reduce damage to the source-drain interconnection layer 160 and reduce the probability of short circuit between the gate plug and the source-drain interconnection layer 160.

[0063] In this embodiment, the top surface of the source / drain capping layer 180 is flush with the top surface of the bottom dielectric layer 140 and the top surface of the gate capping layer 120 .

[0064] In this embodiment, the source / drain capping layer 180 is located on the liner layer 170 and fills the groove 100 .

[0065] The source-drain capping layer 180 is made of a material having a high etching selectivity with the gate capping layer 120, the bottom dielectric layer 140 and the subsequent top dielectric layer, so as to ensure that the source-drain capping layer 180 can protect the source-drain interconnection layer 160. In this embodiment, the material of the source-drain capping layer 180 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. As an example, the material of the source-drain capping layer 180 is silicon oxide. Silicon oxide is a commonly used dielectric material in semiconductor processes, has high process compatibility, and is conducive to cost savings.

[0066] In this embodiment, the steps of forming the source / drain capping layer 180 include:

[0067] like Fig.10 As shown, a source / drain cap material layer 175 is formed on the liner layer 170 to fill the groove 100 .

[0068] The process of forming the source-drain cap material layer 175 includes one or more of a plasma enhanced chemical vapor deposition process, an atomic layer deposition process, and a flow chemical vapor deposition process. The process of forming the source-drain cap material layer 175 has a high gap filling capability, thereby improving the filling capability and filling quality of the source-drain cap material layer 175 in the groove 100, and correspondingly improving the formation quality of the source-drain cap layer.

[0069] like Fig.11 As shown, the source-drain capping material layer 175 and the liner layer 170 above the top of the gate capping layer 120 are removed, and the remaining source-drain capping material layer 175 located in the groove 100 is used as the source-drain capping layer 180 .

[0070] In this embodiment, a planarization process is used to remove the source and drain cap material layer 175 and the pad layer 170 that are higher than the top of the gate cap layer 120, which is beneficial to improving the top surface flatness of the source and drain cap layer 180 and improving the top surface height consistency between the source and drain cap layer 180 and the gate cap layer 120, thereby providing a surface with consistent top surface height and high flatness for subsequent processes.

[0071] In this embodiment, the source and drain capping material layer 175 is made of the same material as the liner layer 170 , which helps to reduce the difficulty of the planarization process. Moreover, the material of the source and drain capping material layer 175 is different from that of the gate capping layer 120 , which makes it easy to stop the planarization process at the top surface of the gate capping layer 120 .

[0072] In this embodiment, the planarization process includes a chemical mechanical planarization process, which is a global planarization process and is beneficial to improving the flatness and height consistency of the top surface of the source / drain cap material layer 175 after planarization.

[0073] refer to Fig.12 , a top dielectric layer 210 covering the gate cap layer 120 and the source / drain cap layer 180 is formed on the bottom dielectric layer 140 .

[0074] Subsequently, source and drain plugs contacting the source and drain interconnection layer 160 and a gate plug contacting the gate structure 110 are formed in the top dielectric layer 210 . The top dielectric layer 210 is used to achieve electrical isolation between the source and drain plugs and the gate plug.

[0075] The material of the top dielectric layer 210 is a dielectric material. In this embodiment, the material of the top dielectric layer 210 includes a low-k dielectric material or an ultra-low-k dielectric material, which is conducive to reducing the parasitic capacitance between the source and drain plugs and the gate plug, thereby reducing the RC delay of the interconnection structure in the integrated circuit, and correspondingly improving the performance of the semiconductor structure.

[0076] refer to Fig.13, forming a source-drain contact hole 220 penetrating the top dielectric layer 210 and the source-drain cap layer 180 , exposing the source-drain interconnection layer 160 .

[0077] The source-drain contact holes 220 are used to provide space for forming source-drain plugs.

[0078] As can be seen from the foregoing, in this embodiment, ion doping 200 is performed on the sidewalls and the top of the gate cap layer 120 through the groove 100, thereby improving the etching selectivity between the source-drain cap layer 180 and the gate cap layer 120. Therefore, in the step of forming the source-drain contact hole 220, it is helpful to reduce the probability of causing mis-etching to the gate cap layer 120, thereby ensuring the protective effect of the gate cap layer 120 on the gate structure 110 and improving the profile controllability of the source-drain contact hole 220. Accordingly, after the source-drain plug is subsequently formed in the source-drain contact hole 220, it is helpful to reduce the probability of short circuit or breakdown between the source-drain plug and the adjacent gate structure 110, thereby improving the performance of the semiconductor structure and the production yield.

[0079] Moreover, in the present embodiment, in the step of ion doping 200 on the sidewall and the top of the gate cap layer 120, ion doping 200 is also performed on the sidewall 150 located on the sidewall of the gate cap layer 120 and the liner layer 170 located on the sidewall of the groove 100, thereby correspondingly improving the etching selectivity between the sidewall 150 and the source-drain cap layer 180, and the etching selectivity between the liner layer 170 and the source-drain cap layer 180, thereby facilitating reducing the process of forming the source-drain contact hole 220, causing the probability of mis-etching the sidewall 150 located on the sidewall of the gate cap layer 120, and reducing the etching rate of the liner layer 170 located on the sidewall of the groove 100, wherein the liner layer 170 and the sidewall 150 are located between the gate cap layer 120 and the source-drain cap layer 180, which can further reduce the probability of mis-etching the gate cap layer 120.

[0080] In this embodiment, in the step of forming the source-drain contact hole 220 , the source-drain contact hole 220 penetrates the liner layer 170 , the source-drain cap layer 120 and the top dielectric layer 210 on the top of the source-drain interconnection layer 160 .

[0081] In this embodiment, an etching process is used to sequentially etch the top dielectric layer 210, the source-drain cap layer 120, and the liner layer 170 located above the source-drain interconnection layer 160 to form the source-drain contact hole 220; the etching process has an etching selectivity of at least 15:1 for the source-drain cap layer 180 and the gate cap layer 120. The etching process has a high etching selectivity for the source-drain cap layer 180 and the gate cap layer 120, which is conducive to reducing the probability of causing mis-etching of the gate cap layer 120 more significantly.

[0082] Specifically, the etching process includes an anisotropic dry etching process.

[0083] refer to Fig.14 , a source-drain plug 300 contacting the source-drain interconnection layer 160 is formed in the source-drain contact hole 220 .

[0084] The source-drain plugs 300 are in contact with the source-drain interconnection layer 160 , so that the source-drain doped regions 130 are electrically connected to external circuits or other interconnection structures through the source-drain interconnection layer 160 .

[0085] As can be seen from the foregoing, in the step of forming the source-drain contact hole 220, the probability of causing mis-etching to the gate cap layer 120 is low, which correspondingly ensures the protective effect of the gate cap layer 120 on the gate structure 110, and improves the profile controllability of the source-drain contact hole 220. Therefore, after the source-drain plug 300 is formed in the source-drain contact hole 220, it is beneficial to reduce the probability of short circuit or breakdown between the source-drain plug 300 and the adjacent gate structure 110, thereby improving the performance of the semiconductor structure and the production yield.

[0086] The source-drain plug 300 is made of a conductive material. In this embodiment, the source-drain plug 300 is made of copper. In other embodiments, the source-drain plug may also be made of a conductive material such as tungsten or cobalt.

[0087] It should be noted that, in conjunction with the reference Fig.15 In this embodiment, the method for forming the semiconductor structure further includes: forming a gate plug 230 that penetrates the gate cap layer 120 and the top dielectric layer 210 on the top of the gate structure 110 and contacts the gate structure 110 .

[0088] The gate plug 230 is used to realize electrical connection between the gate structure 110 and an external circuit or other interconnection structure.

[0089] In this embodiment, the gate plug 230 is formed above the gate structure 110 in the active region. The gate plug 230 is an active gate contact plug (COAG), which is beneficial to saving chip area, thereby further reducing the chip size.

[0090] The gate plug 230 is made of a conductive material. In this embodiment, the gate plug 230 is made of copper. In other embodiments, the gate plug may also be made of a conductive material such as tungsten or cobalt.

[0091] Accordingly, the present invention also provides a semiconductor structure. Fig.15 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0092] The semiconductor structure includes: a substrate (not shown); a gate structure 110 located on the substrate; a gate cap layer 120 located on the top of the gate structure 110; source and drain doped regions 130 located in the substrate on both sides of the gate structure 110; a bottom dielectric layer 140 (such as Figure 5 As shown), it is located on the substrate at the side of the gate structure 110 and the gate cap layer 120; the source-drain interconnection layer 160 penetrates the bottom dielectric layer 140 at the top of the source-drain doped region 130 and contacts the source-drain doped region 130, and the top surface of the source-drain interconnection layer 160 is lower than the top surface of the bottom dielectric layer 140; the source-drain cap layer 180 is located on the top of the source-drain interconnection layer 160; wherein the sidewalls of the gate cap layer 120 have doped ions, and the doped ions are suitable for improving the etching selectivity between the source-drain cap layer 180 and the gate cap layer 120; the top dielectric layer 210 is located on the bottom dielectric layer 140 and covers the gate cap layer 120 and the source-drain cap layer 180; the source-drain plug 300 penetrates the source-drain cap layer 180 and the top dielectric layer 210 at the top of the source-drain interconnection layer 160, and contacts the source-drain interconnection layer 160.

[0093] The steps of forming the source-drain plug 300 include: forming a source-drain contact hole penetrating the top dielectric layer 210 and the source-drain cap layer 180; and forming the source-drain plug 300 in the source-drain contact hole.

[0094] The side walls of the gate cap layer 120 have doped ions, and the doped ions are suitable for improving the etching selectivity between the source-drain cap layer 180 and the gate cap layer 120. Therefore, in the step of forming the source-drain contact hole, since the source-drain cap layer 180 and the gate cap layer 120 have a higher etching selectivity, it is beneficial to reduce the probability of mis-etching the gate cap layer 120, so that the gate cap layer 120 can protect the gate structure 110 and improve the profile controllability of the source-drain contact hole. Accordingly, after the source-drain plug 300 is formed in the source-drain contact hole, it is beneficial to reduce the probability of short circuit (Short) or breakdown between the source-drain plug 300 and the adjacent gate structure 110, thereby improving the performance of the semiconductor structure and the production yield.

[0095] The substrate is used to provide a platform for the process. In this embodiment, the substrate is a planar substrate, and the substrate is a silicon substrate. In other embodiments, the substrate can also be a three-dimensional substrate, for example: the substrate includes a substrate and a fin protruding from the substrate.

[0096] The gate structure 110 is used as a device gate to control the opening or closing of the conductive channel when the device is working. In this embodiment, the gate structure 110 is a metal gate structure, and the gate structure 110 is formed by forming a high k last metal gate last process.

[0097] The gate cap layer 120 is used to protect the top of the gate structure 110 during the process of forming the source-drain interconnection layer 160 and the source-drain plug 300, thereby reducing the probability of damage to the gate structure 110 and short circuit problems between the gate structure 110 and the source-drain interconnection layer 160 or the source-drain plug 300.

[0098] The gate cap layer 120 is made of a material having etching selectivity with the source / drain cap layer 180, the bottom dielectric layer 140, and the top dielectric layer 210, so as to ensure that the gate cap layer 120 can protect the gate structure 110. In this embodiment, the material of the gate cap layer 120 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride, and boron carbonitride. As an example, the material of the gate cap layer 120 is silicon nitride.

[0099] The side walls of the gate cap layer 120 have doped ions, and the doped ions are suitable for improving the etching selectivity between the source-drain cap layer 180 and the gate cap layer 120, so that in the step of forming source-drain contact holes penetrating the top dielectric layer 210 and the source-drain cap layer 180, the probability of causing mis-etching of the gate cap layer 120 is reduced, and correspondingly the probability of short circuit (Short) or breakdown between the source-drain plug 300 and the adjacent gate structure 110 is reduced, thereby improving the performance of the semiconductor structure and the production yield.

[0100] In this embodiment, the top of the gate cap layer 120 also has the doped ions, which helps to reduce the probability of mis-etching the top of the gate cap layer 120 during the process of forming the source-drain contact holes, and helps to further reduce the probability of short circuit or breakdown between the source-drain plug 300 and the adjacent gate structure 110.

[0101] In this embodiment, the sidewalls and the top of the gate cap layer 120 have the doped ions, and the doped ions are suitable for increasing the hardness of the gate cap layer 120 , and correspondingly increasing the etching resistance of the gate cap layer 120 having the doped ions, which is beneficial to improving the etching selectivity ratio of the source and drain cap layer 180 to the gate cap layer 120 .

[0102] In this embodiment, the doping ions include silicon ions, argon ions or germanium ions. As an example, the doping ions are silicon ions, and the material of the gate cap layer 120 is silicon nitride. By doping the gate cap layer 120 with silicon ions, it is beneficial to increase the silicon content in the gate cap layer 120 material, thereby improving the density and hardness of the gate cap layer 120.

[0103] Along the direction perpendicular to the sidewall of the gate capping layer 120 , the doping depth of the doped ions in the sidewall of the gate capping layer 120 is 2 nm to 10 nm, thereby making the etching selectivity of the source / drain capping layer 180 and the gate capping layer 120 more significantly improved.

[0104] The source-drain doping region 130 is used to provide a carrier source when the device is working. When forming an NMOS device, the source-drain doping region 130 is doped with N-type ions; when forming a PMOS device, the source-drain doping region 130 is doped with P-type ions.

[0105] The bottom dielectric layer 140 is used to isolate adjacent devices. The material of the bottom dielectric layer 140 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon nitride oxide. In this embodiment, the material of the bottom dielectric layer 140 is silicon oxide.

[0106] In this embodiment, the semiconductor structure also includes: a sidewall 150 located on the sidewalls of the gate structure 110 and the gate cap layer 120; the bottom dielectric layer 140 covers the sidewalls of the sidewall 150, and the sidewall 150 located on the sidewall of the gate cap layer 120 has the doped ions.

[0107] The sidewall 150 is used to define the formation position of the source-drain doped region 130. The sidewall 150 is located on the sidewall of the gate structure 110 and is also used to protect the sidewall of the gate structure 110. In addition, the sidewall 150 is located between the source-drain interconnection layer 160 and the gate structure 110 and is also used to isolate the source-drain interconnection layer 160 from the gate structure 110.

[0108] In this embodiment, the material of the spacer 150 is a low-k dielectric material or an ultra-low-k dielectric material, which is beneficial to reducing the effective capacitance between the source-drain interconnection layer 160 and the gate structure 110 .

[0109] In the present embodiment, the sidewall 150 located on the sidewall of the gate cap layer 120 has the doped ions, which correspondingly improves the etching selectivity between the sidewall 150 and the source / drain cap layer 180, thereby helping to reduce the probability of mis-etching the sidewall 150 located on the sidewall of the gate cap layer 120 during the process of forming the source / drain contact holes, thereby further helping to reduce the probability of short circuit or breakdown between the source / drain plug 300 and the adjacent gate structure 110.

[0110] The source-drain interconnection layer 160 is in contact with the source-drain doped region 130 , and is used to realize electrical connection between the source-drain doped region 130 and an external circuit or other interconnection structure.

[0111] In this embodiment, the material of the source-drain interconnection layer 160 is copper. Copper has a low resistivity, which is beneficial to improving the signal delay of the back-end RC and increasing the processing speed of the chip. It is also beneficial to reduce the resistance of the source-drain interconnection layer 160, and correspondingly reduces power consumption. In other embodiments, the material of the source-drain interconnection layer can also be a conductive material such as tungsten or cobalt.

[0112] The semiconductor structure generally further includes a gate plug that penetrates the gate cap layer 120 and the top dielectric layer 210 and contacts the gate structure 110. The source-drain cap layer 180 is located on the top surface of the source-drain interconnect layer 160. During the formation of the gate plug, the source-drain cap layer 180 can protect the source-drain interconnect layer 160, thereby reducing damage to the source-drain interconnect layer 160 and reducing the probability of short circuit between the gate plug and the source-drain interconnect layer 160.

[0113] In this embodiment, the top surface of the source / drain capping layer 180 is flush with the top surface of the bottom dielectric layer 140 and the top surface of the gate capping layer 120 .

[0114] The source-drain capping layer 180 is made of a material having a high etching selectivity with the gate capping layer 120, the bottom dielectric layer 140 and the top dielectric layer 210, so as to ensure that the source-drain capping layer 180 can protect the source-drain interconnection layer 160. In this embodiment, the material of the source-drain capping layer 180 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. As an example, the material of the source-drain capping layer 180 is silicon oxide. Silicon oxide is a commonly used dielectric material in semiconductor processes, has high process compatibility, and is conducive to cost savings.

[0115] In this embodiment, the semiconductor structure further includes: a liner layer 170 located between the source-drain interconnection layer 160 and the source-drain capping layer 180 .

[0116] In the step of ion doping the sidewalls of the gate cap layer 120 , the liner layer 170 is used to protect the source-drain interconnection layer 160 , thereby preventing the ion doping from having adverse effects on the source-drain interconnection layer 160 , for example, preventing the ion doping from affecting the resistivity of the source-drain interconnection layer 160 .

[0117] In this embodiment, the liner layer 170 is also located between the sidewalls of the source / drain capping layer 180 and the gate capping layer 120 , and the liner layer 170 located on the sidewalls of the source / drain capping layer 180 contains the doping ions.

[0118] The liner layer 170 located on the sidewall of the source-drain cap layer 180 has the doped ions, which correspondingly improves the etching selectivity of the liner layer 170 to the source-drain cap layer 180, thereby reducing the etching rate of the liner layer 170 in the step of forming the source-drain contact hole penetrating the top dielectric layer 210 and the source-drain cap layer 180. The liner layer 170 is located between the gate cap layer 120 and the source-drain cap layer 180, which correspondingly can further reduce the probability of mis-etching the gate cap layer 120, thereby reducing the problem of short circuit or breakdown between the source-drain plug 300 and the adjacent gate structure 110. In addition, the liner layer 170 on the sidewall of the source-drain cap layer 180 can also protect the sidewall 150.

[0119] The material of the liner layer 170 includes silicon oxide, silicon nitride or silicon oxynitride. As an example, in this embodiment, the material of the liner layer 170 is silicon oxide. Silicon oxide is a commonly used dielectric material in semiconductor processes, which is conducive to improving process compatibility.

[0120] It should be noted that the thickness of the liner layer 170 should not be too small or too large. If the thickness of the liner layer 170 is too small, the protective effect of the liner layer 170 on the source-drain interconnection layer 160 is not obvious; if the thickness of the liner layer 170 is too large, it is easy to cause the remaining space on the top of the source-drain interconnection layer 160 for forming the source-drain cap layer 180 to be too small, which is easy to increase the difficulty of forming the source-drain cap layer 180 and reduce the formation quality of the source-drain cap layer 180. For this reason, in this embodiment, the thickness of the liner layer 170 is to

[0121] The top dielectric layer 210 is used to achieve electrical isolation between the source-drain plug 300 and the gate plug.

[0122] The material of the top dielectric layer 210 is a dielectric material. In this embodiment, the material of the top dielectric layer 210 includes a low-k dielectric material or an ultra-low-k dielectric material, which is conducive to reducing the parasitic capacitance between the source-drain plug 300 and the gate plug, thereby reducing the RC delay of the interconnection structure in the integrated circuit, and correspondingly improving the performance of the semiconductor structure.

[0123] The source-drain plugs 300 are in contact with the source-drain interconnection layer 160 , so that the source-drain doped regions 130 are electrically connected to external circuits or other interconnection structures through the source-drain interconnection layer 160 .

[0124] As can be seen from the foregoing, in the step of forming the source-drain contact holes, the probability of causing mis-etching to the gate cap layer 120 is low, which correspondingly ensures the protective effect of the gate cap layer 120 on the gate structure 110, and improves the profile controllability of the source-drain contact holes, thereby helping to reduce the probability of short circuit or breakdown between the source-drain plug 300 and the adjacent gate structure 110, and improves the profile controllability of the source-drain plug 300 and the formation quality of the source-drain plug 300, thereby improving the performance of the semiconductor structure and the production yield.

[0125] The source-drain plug 300 is made of a conductive material. In this embodiment, the source-drain plug 300 is made of copper. In other embodiments, the source-drain plug may also be made of a conductive material such as tungsten or cobalt.

[0126] In this embodiment, the source-drain plug 300 also penetrates the liner layer 170 located on the source-drain interconnection layer 160 .

[0127] In this embodiment, the semiconductor structure further includes: a gate plug 230 , which penetrates the gate cap layer 120 and the top dielectric layer 210 on the top of the gate structure 110 and contacts the gate structure 110 .

[0128] The gate plug 230 is used to realize electrical connection between the gate structure 110 and an external circuit or other interconnection structures.

[0129] In this embodiment, the gate plug 230 is formed above the gate structure 110 in the active region. The gate plug 230 is an active gate contact plug (COAG), which is beneficial to saving chip area, thereby further reducing the chip size.

[0130] The gate plug 230 is made of a conductive material. In this embodiment, the gate plug 230 is made of copper. In other embodiments, the gate plug may also be made of a conductive material such as tungsten or cobalt.

[0131] The semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0132] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein a gate structure is formed on the substrate, a gate cap layer is formed on the top of the gate structure, source and drain doped regions are formed in the substrate on both sides of the gate structure, and a bottom dielectric layer covering the source and drain doped regions is formed on the substrate at the sides of the gate structure and the gate cap layer; A source-drain interconnection layer is formed on the bottom dielectric layer that penetrates the top of the source-drain doped region and contacts the source-drain doped region. The top surface of the source-drain interconnection layer is lower than the top surface of the bottom dielectric layer. The top surface of the source-drain interconnection layer and the adjacent gate cap layer form a groove, and the groove is used to form the source-drain cap layer. Ion doping is performed on the sidewall of the gate cap layer through the groove, which is suitable for improving the etching selectivity between the source and drain cap layer and the gate cap layer; After ion doping, a source-drain capping layer is formed in the groove; Forming a top dielectric layer covering the gate cap layer and the source / drain cap layer on the bottom dielectric layer; Forming source-drain contact holes penetrating the top dielectric layer and the source-drain cap layer to expose the source-drain interconnection layer; A source-drain plug in contact with the source-drain interconnection layer is formed in the source-drain contact hole.

2. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing a substrate, sidewalls are further formed on the sidewalls of the gate structure and the gate cap layer, the source and drain doping regions are located in the substrate on both sides of the gate structure and the sidewalls, and the bottom dielectric layer covers the sidewalls of the sidewalls; In the step of forming the source-drain interconnection layer, the sidewall is located between the source-drain interconnection layer and the gate structure or the gate cap layer, and the groove is surrounded by the sidewall and the top surface of the source-drain interconnection layer; In the step of performing ion doping on the sidewall of the gate cap layer, ion doping is also performed on the sidewall located on the sidewall of the gate cap layer.

3. The method for forming a semiconductor structure according to claim 1 or 2, wherein: The method for forming a semiconductor structure further comprises: forming a liner layer at the bottom of the groove after forming the groove and before performing ion doping; In the step of forming the source-drain contact holes, the source-drain contact holes penetrate the liner layer, the source-drain cap layer and the top dielectric layer on the top of the source-drain interconnection layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: In the step of forming the liner layer, the liner layer is also formed on the sidewall of the groove; In the step of performing ion doping, ions are also doped into the liner layer located on the sidewall of the groove; In the step of forming a source / drain capping layer, the source / drain capping layer is located on the liner layer and fills the groove.

5. The method for forming a semiconductor structure according to claim 4, wherein: In the step of forming the liner layer, the thickness of the liner layer is to 6. The method for forming a semiconductor structure according to claim 3, wherein: The material of the liner layer includes silicon oxide, silicon nitride or silicon oxynitride.

7. The method for forming a semiconductor structure according to claim 3, wherein: The process of forming the liner layer includes an atomic layer deposition process.

8. The method for forming a semiconductor structure according to claim 4, wherein: In the step of forming the liner layer, the liner layer is also formed on the top surfaces of the gate cap layer and the bottom dielectric layer; The step of forming the source-drain capping layer includes: forming a source-drain capping material layer filling the groove on the liner layer; removing the source-drain capping material layer and the liner layer above the top of the gate capping layer, and the remaining source-drain capping material layer located in the groove is used as the source-drain capping layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: The process of forming the source / drain cap material layer includes one or more of a plasma enhanced chemical vapor deposition process, an atomic layer deposition process and a flow chemical vapor deposition process.

10. The method for forming a semiconductor structure according to claim 8, wherein: A planarization process is used to remove the source and drain cap material layer and the liner layer above the top of the gate cap layer; the planarization process includes a chemical mechanical planarization process.

11. The method for forming a semiconductor structure according to claim 1, wherein: In the step of performing ion doping on the sidewall of the gate cap layer, ion doping is also performed on the top of the gate cap layer.

12. The method for forming a semiconductor structure according to claim 1 or 11, characterized in that: The ions used for ion doping the sidewalls of the gate cap layer include silicon ions, argon ions or germanium ions.

13. The method for forming a semiconductor structure according to claim 1 or 11, characterized in that: An ion implantation process is used to perform ion doping on the sidewalls of the gate cap layer; the implanted ions are silicon ions, and the process parameters of the ion implantation include: an angle between the implantation direction and the normal to the substrate surface of 5° to 30°, an implantation dose of 1E12 atoms per square centimeter to 5E15 atoms per square centimeter, and an implantation energy of 1KeV to 20KeV.

14. The method for forming a semiconductor structure according to claim 1, wherein: The source-drain contact holes are formed by an etching process; the etching selection ratio of the source-drain capping layer and the gate capping layer by the etching process is at least 15:

1.

15. The method for forming a semiconductor structure according to claim 1, wherein: The material of the gate cap layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

16. A semiconductor structure, characterized in that: include: substrate; A gate structure, located on the substrate; A gate cap layer, located on top of the gate structure; Source and drain doping regions are located in the substrate on both sides of the gate structure; A bottom dielectric layer, located on the substrate at the side of the gate structure and the gate cap layer; a source-drain interconnection layer, penetrating the bottom dielectric layer on the top of the source-drain doped region and contacting the source-drain doped region, wherein the top surface of the source-drain interconnection layer is lower than the top surface of the bottom dielectric layer; A source-drain capping layer, located on top of the source-drain interconnection layer; Wherein, the sidewall of the gate cap layer has doping ions, and the doping ions are suitable for improving the etching selectivity between the source and drain cap layer and the gate cap layer; A top dielectric layer, located on the bottom dielectric layer and covering the gate cap layer and the source / drain cap layer; The source-drain plug penetrates the source-drain cap layer and the top dielectric layer on the top of the source-drain interconnection layer and contacts the source-drain interconnection layer.

17. The semiconductor structure according to claim 16, wherein: The semiconductor structure further includes: a sidewall located on the sidewalls of the gate structure and the gate cap layer; the bottom dielectric layer covers the sidewalls of the sidewalls, and the sidewalls located in the gate cap layer have the doping ions.

18. The semiconductor structure according to claim 16, wherein: The semiconductor structure further comprises: a liner layer located between the source-drain interconnection layer and the source-drain capping layer; The source-drain plug also penetrates the liner layer located on the source-drain interconnection layer.

19. The semiconductor structure according to claim 18, wherein: The liner layer is also located between the sidewall of the source / drain cap layer and the gate cap layer, and the liner layer located on the sidewall of the source / drain cap layer contains the doping ions.

20. The semiconductor structure according to claim 19, wherein: The material of the liner layer includes silicon oxide, silicon nitride or silicon oxynitride.

21. The semiconductor structure according to claim 16, wherein: The top of the gate cap layer has the doping ions therein.

22. The semiconductor structure according to claim 16 or 21, characterized in that: The doping ions include silicon ions, argon ions or germanium ions.

23. The semiconductor structure according to claim 16, wherein: Along a direction perpendicular to the sidewall of the gate capping layer, the doping depth of the doping ions in the sidewall of the gate capping layer is 2 nm to 10 nm.

24. The semiconductor structure according to claim 16, wherein: The material of the gate cap layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

25. The semiconductor structure according to claim 16, wherein: The material of the source / drain capping layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

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