Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: forming a second dielectric layer on the surface of the first dielectric layer, the gate structure and the source-drain plug; forming a connection plug in the second dielectric layer, and the connection plug is located on the top surface of the adjacent gate structure and the source-drain plug; forming a third dielectric layer on the second dielectric layer and the connection plug surface; forming a first plug in the third dielectric layer, the top surface of the first plug is higher than the top surface of the connection plug, and the first plug is electrically connected to the connection plug. The connection plug is isolated by the third dielectric layer, and the connection plug that needs to be connected externally is selected by the first plug. Since the first plug occupies a smaller area, it is beneficial to reduce the wiring difficulty of the subsequent conductive layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve integration and reduce costs, the key dimensions of components are constantly decreasing, and the circuit density inside the integrated circuit is increasing. This development makes it impossible for the wafer surface to provide enough area to make the required interconnection lines.

[0003] The connection plugs in the transistor structure include connection plugs located on the surface of the gate structure, which are used to connect the gate structure with an external circuit; and connection plugs located on the surface of the source and drain doping regions, which are used to connect the source region or drain region of the transistor with an external circuit. In order to further meet the demand for increasing integration, the connection plugs on the gate structure in the isolation region are transferred to the gate structure in the active region, which can further save area.

[0004] However, the performance of the semiconductor structure formed in the prior art still needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, a first dielectric layer and a plurality of gate structures on the substrate, source-drain doped regions in the substrate on both sides of the gate structure, source-drain doped regions having source-drain plugs on the top surfaces, the first dielectric layer being located on the surfaces of the gate structure, the source-drain doped regions and the source-drain plugs; a second dielectric layer being located on the surfaces of the first dielectric layer, the gate structure and the source-drain plugs; a connecting plug being located in the second dielectric layer, and the connecting plug being located on the top surfaces of the adjacent gate structures and the source-drain plugs; a third dielectric layer being located on the surfaces of the second dielectric layer and the connecting plugs; and a first plug being located in the third dielectric layer, the top surface of the first plug being higher than the top surface of the connecting plug, and the first plug being electrically connected to the connecting plug.

[0007] Optionally, the first plug is located on the source and drain plug.

[0008] Optionally, the first plug is located on the gate structure.

[0009] Optionally, it also includes: a second plug located in the second dielectric layer and the third dielectric layer, the second plug is located on the top surface of the source and drain plug, and the top surface of the second plug is higher than the top surface of the connecting plug; a third plug located in the second dielectric layer and the third dielectric layer, the third plug is located on the top surface of the gate structure, and the top surface of the third plug is higher than the top surface of the connecting plug.

[0010] Optionally, the method further includes: a conductive layer located on the surface of the third dielectric layer, wherein the conductive layer is electrically connected to the first plug, the second plug and the third plug.

[0011] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a first dielectric layer and a plurality of gate structures are provided on the substrate, source-drain doped regions are provided in the substrate on both sides of the gate structure, source-drain doped regions are provided on the top surfaces of the source-drain doped regions, and the first dielectric layer is located on the surfaces of the gate structure, the source-drain doped regions, and the source-drain plugs; forming a second dielectric layer on the surfaces of the first dielectric layer, the gate structure, and the source-drain plugs; forming a connecting plug in the second dielectric layer, and the connecting plug is located on the top surfaces of the adjacent gate structure and the source-drain plug; forming a third dielectric layer on the surfaces of the second dielectric layer and the connecting plug; forming a first plug in the third dielectric layer, the top surface of the first plug is higher than the top surface of the connecting plug, and the first plug is electrically connected to the connecting plug.

[0012] Optionally, it also includes: forming a second plug in the second dielectric layer and the third dielectric layer, the second plug is located on the top surface of the source and drain plug, and the top surface of the second plug is higher than the top surface of the connecting plug; forming a third plug in the second dielectric layer and the third dielectric layer, the third plug is located on the top surface of the gate structure, and the top surface of the third plug is higher than the top surface of the connecting plug.

[0013] Optionally, the first plug is located on the source and drain plug.

[0014] Optionally, the second plug and the first plug are formed in the same process.

[0015] Optionally, the method for forming the first plug and the second plug includes: forming a first patterned layer on the surface of the third dielectric layer, the first patterned layer exposing the surface of the third dielectric layer on the source and drain plugs; using the first patterned layer as a mask, etching the second dielectric layer and the third dielectric layer until the surface of the connection plug and the surface of the source and drain plugs are exposed, forming a first opening in the third dielectric layer, the first opening exposing the surface of the connection plug, forming a second opening in the second dielectric layer and the third dielectric layer, the second opening exposing the surface of the source and drain plugs; forming a first conductive material film in the first opening, in the second opening and on the surface of the third dielectric layer, the first conductive material film filling the first opening and the second opening; planarizing the first conductive material film, forming the first plug in the first opening, and forming the second plug in the second opening.

[0016] Optionally, the method for forming the third plug includes: forming a second patterned layer on the surface of the third dielectric layer, the second patterned layer exposing the surface of the third dielectric layer on the gate structure; using the second patterned layer as a mask, etching the second dielectric layer and the third dielectric layer until the top surface of the gate structure is exposed, and forming a third opening in the third dielectric layer; forming a second conductive material film in the third opening and on the surface of the third dielectric layer, the second conductive material film filling the third opening; planarizing the second conductive material film, and forming the third plug in the third opening.

[0017] Optionally, the first plug is located on the gate structure.

[0018] Optionally, the first plug and the third plug are formed in the same process.

[0019] Optionally, the method for forming the first plug and the third plug includes: forming a first patterned layer on the surface of the third dielectric layer, the first patterned layer exposing the surface of the third dielectric layer on the gate structure; using the first patterned layer as a mask, etching the third dielectric layer until the surface of the connecting plug and the surface of the gate structure are exposed, forming a first opening and a third opening in the third dielectric layer, the first opening exposing the surface of the connecting plug, and the third opening exposing the surface of the gate structure; forming a first conductive material film in the first opening, in the third opening and on the surface of the third dielectric layer, the first conductive material film filling the first opening and the third opening; planarizing the first conductive material film, forming the first plug in the first opening, and forming the third plug in the third opening.

[0020] Optionally, the method for forming the second plug includes: forming a second patterned layer on the surface of the third dielectric layer, the second patterned layer exposing the surface of the third dielectric layer on the source and drain plugs; using the second patterned layer as a mask, etching the third dielectric layer until the top surface of the source and drain plugs is exposed, and forming a second opening in the second dielectric layer and the third dielectric layer; forming a second conductive material film in the second opening and on the surface of the third dielectric layer, the second conductive material film filling the second opening; and planarizing the second conductive material film to form the second plug in the second opening.

[0021] Optionally, the method for forming a connecting plug in the second dielectric layer includes: forming a third patterned layer on the surface of the second dielectric layer, the third patterned layer exposing the surface of the second dielectric layer on the adjacent gate structure and the source and drain plug; using the third patterned layer as a mask, etching the second dielectric layer until the top surface of the gate structure and the top surface of the source and drain plug are exposed, and forming a fourth opening in the second dielectric layer; forming a third conductive material film in the fourth opening and on the surface of the second dielectric layer, the third conductive material film filling the fourth opening; and planarizing the third conductive material film until the surface of the second dielectric layer is exposed to form the connecting plug.

[0022] Optionally, the method further includes: forming a fourth dielectric layer on the surface of the third dielectric layer; and forming a conductive layer in the fourth dielectric layer, wherein the conductive layer is electrically connected to the first plug, the second plug, and the third plug.

[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0024] In the semiconductor structure provided by the technical solution of the present invention, the connection plug is electrically connected to the gate structure and the source-drain plug, the surface of the connection plug and the surface of the second dielectric layer have a third dielectric layer, and the connection plug is isolated by the third dielectric layer. The first plug is electrically connected to the connection plug, and the top surface of the first plug is higher than the top surface of the connection plug, that is, the connection plug that needs to be externally connected is selected by the first plug. Since the first plug occupies a smaller area, it is conducive to reducing the difficulty of wiring the subsequent conductive layer, thereby improving the performance of the formed semiconductor structure.

[0025] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a connection plug is first formed in the second dielectric layer, the connection plug electrically connects the gate structure and the source and drain plugs, and then a third dielectric layer is formed on the surface of the second dielectric layer, the third dielectric layer electrically isolates the connection plug. A first plug is formed in the third dielectric layer, and the top surface of the first plug is higher than the top surface of the connection plug, so that an electrical connection is formed between the first plug and the connection plug, that is, the connection plug that needs to be externally connected is selected through the first plug. Since the connection plug that needs to be externally connected has been electrically connected through the first plug, and the area occupied by the first plug is small, the wiring difficulty of the subsequent formation of the conductive layer is reduced, which is conducive to reducing the process difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1 to 5 It is a structural schematic diagram of each step of a method for forming a conventional semiconductor structure;

[0027] Figures 6 to 13 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0028] Figures 14 to 16 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0029] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0030] First, the reasons why the performance of the existing semiconductor structure is poor are described in detail with reference to the accompanying drawings. Figures 1 to 5 The present invention is a structural schematic diagram of each step of a method for forming a conventional semiconductor structure.

[0031] Please refer to Figure 1 , providing a substrate 100, the substrate 100 including a first region I and a second region II, a gate structure 110 and a first dielectric layer 120 being provided on the first region I and the second region II, source-drain doped regions 111 being provided in the substrate 100 on both sides of the gate structure 110, source-drain doped regions 111 being provided on the top surfaces of the source-drain doped regions 111, and the first dielectric layer 120 being located on the surfaces of the gate structure 110, the source-drain doped regions 111 and the source-drain plugs 130.

[0032] Please refer to Figure 2 , a second dielectric layer 140 is formed on the surface of the first dielectric layer 120 .

[0033] Please refer to Figure 3A first opening 150 is formed in the second dielectric layer 140 of the first region I, and the first opening 150 exposes the top surface of the source-drain plug 130 of the first region I. A second opening 160 is formed in the second dielectric layer 140 of the second region II, and the second opening 160 exposes the top surface of the source-drain plug 130 of the second region II.

[0034] Please refer to Figure 4 , a third opening 170 is formed in the second dielectric layer 140 of the first region I, the third opening 170 exposes the top surface of the gate structure 110 and the surface of the first dielectric layer 120 , and the third opening 170 is connected to the first opening 150 .

[0035] Please refer to Figure 5 , a first plug 180 is formed in the first opening 150 and the third opening 170 , and a second plug 190 is formed in the second opening 160 .

[0036] In the above method, after forming the first opening and the second opening, a third opening is formed, wherein the third opening not only exposes the top surface of the gate structure but is also connected to the first opening, so that the first plug formed in the first opening and the third opening can realize electrical connection between adjacent gate structures and source and drain plugs.

[0037] However, according to the requirements of a specific process, part of the first plug 180 needs to be electrically connected to the peripheral circuit, and part of the first plug 180 does not need to be electrically connected to the peripheral circuit. When the first metal layer is subsequently formed, in order to meet the process requirements, the first metal layer is electrically connected to part of the first plug 180, and the first metal layer is electrically isolated from part of the first plug 180. Since the first plug 180 is not only located on the surface of the gate structure 110, but also on the surface of the source and drain plug 130, the area occupied by the first plug 180 is relatively large, which increases the wiring difficulty of forming the first metal layer, resulting in an increase in the process difficulty of forming the first metal layer.

[0038] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, wherein a connection plug is formed in the second dielectric layer, and the connection plug is located on the top surface of the adjacent gate structure and source-drain plug; a third dielectric layer is formed on the second dielectric layer and the connection plug surface; a first plug is formed in the second dielectric layer and the third dielectric layer, the top surface of the first plug is higher than the top surface of the connection plug, and the first plug is electrically connected to the connection plug. The connection plug is isolated by the third dielectric layer, and the connection plug that needs to be connected externally is selected by the first plug. Since the first plug occupies a smaller area, it is helpful to reduce the wiring difficulty of the subsequent conductive layer.

[0039] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0040] Figures 6 to 13 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0041] Please refer to Figure 6 A substrate 200 is provided, on which a first dielectric layer 220 and a plurality of gate structures 210 are provided, source-drain doped regions 230 are provided in the substrate 200 on both sides of the gate structures 210, and source-drain doped regions 230 are provided on the top surfaces of the source-drain doped regions 230, and the first dielectric layer 220 is located on the surfaces of the gate structures 210, the source-drain doped regions 230 and the source-drain plugs 240.

[0042] In this embodiment, the substrate 200 is single crystal silicon. In other embodiments, the substrate may be made of semiconductor materials such as single crystal germanium, silicon germanium, gallium arsenide, etc., or may be a semiconductor-on-insulator structure.

[0043] The gate structure 210 includes a gate dielectric layer (not shown in the figure) and a gate layer (not shown in the figure) located on the surface of the gate dielectric layer. The material of the gate dielectric layer includes silicon oxide or high-K dielectric material. The material of the gate layer includes polysilicon or metal.

[0044] The material of the plug 240 includes cobalt, copper, tungsten, aluminum, titanium or tantalum.

[0045] The material of the first dielectric layer 220 includes silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride or silicon oxynitride. In this embodiment, the material of the first dielectric layer 220 is silicon oxide.

[0046] In this embodiment, a stop layer 221 is further provided on the surface of the first dielectric layer 220 .

[0047] The stop layer 221 serves as an indicator stop layer for subsequent etching processes.

[0048] In this embodiment, the top surface of the gate structure 210 further has a protection layer 211 .

[0049] The protection layer 211 is used to protect the top surface of the gate structure 210 , reduce the impact of subsequent processes, and is beneficial to improving the performance of the gate structure 210 .

[0050] In other embodiments, the top surface of the gate structure may not have a protection layer.

[0051] Please refer to Figure 7, a second dielectric layer 250 is formed on the surfaces of the first dielectric layer 220 , the gate structure 210 and the source / drain plugs 240 .

[0052] The second dielectric layer 250 provides support for the subsequent formation of a connecting plug, a first plug, a second plug, and a third plug.

[0053] Specifically, the second dielectric layer 250 is formed on the surface of the stop layer 221 .

[0054] The material of the second dielectric layer 250 is different from that of the stop layer 221 .

[0055] The material of the second dielectric layer 250 includes silicon oxide, silicon carbide, silicon nitride, silicon carbide nitride, silicon boronitride, silicon carbon nitride or silicon oxynitride. In this embodiment, the material of the second dielectric layer 250 and the first dielectric layer 220 is the same, that is, silicon oxide.

[0056] Next, a connection plug is formed in the second dielectric layer 250, and the connection plug is located on the top surface of the adjacent gate structure 210 and the source-drain plug 240. For the specific process of forming the connection plug in the second dielectric layer 250, please refer to Figures 8 to 9 .

[0057] Please refer to Figure 8 , a third patterned layer 251 is formed on the surface of the second dielectric layer 250, and the third patterned layer 251 exposes the surface of the second dielectric layer 250 on the adjacent gate structure 210 and the source-drain plug 240; using the third patterned layer 251 as a mask, the second dielectric layer 250 is etched until the top surface of the gate structure 210 and the top surface of the source-drain plug 240 are exposed, and a fourth opening 260 is formed in the second dielectric layer 250.

[0058] The fourth opening 260 provides a space for subsequently forming a connecting plug.

[0059] In this embodiment, specifically, the second dielectric layer 250 is etched using the third patterned layer 251 as a mask to expose the top surface of the stop layer 221 ; the stop layer 221 and the protective layer 211 are etched until the top surface of the source / drain plug 240 and the top surface of the gate structure 210 are exposed, and the fourth opening 260 is formed in the second dielectric layer 250 .

[0060] The process of etching the second dielectric layer 250 includes: one of a wet etching process and a dry etching process or a combination of the two.

[0061] In this embodiment, the process of etching the second dielectric layer 250 is a dry etching process.

[0062] In this embodiment, after forming the fourth opening 260 , the process further includes: removing the third patterned layer 251 .

[0063] Please refer to Fig. 9 , a third conductive material film (not shown in the figure) is formed in the fourth opening 260 and on the surface of the second dielectric layer 250, and the third conductive material film fills the fourth opening 260; the third conductive material film is planarized until the surface of the second dielectric layer 250 is exposed to form the connecting plug 261.

[0064] Since the fourth opening 260 exposes the top surface of the adjacent gate structure 210 and the top surface of the source-drain plug 240 , the connecting plug 261 formed in the fourth opening 260 is located on the top surface of the gate structure 210 and the top surface of the source-drain plug 240 , and the adjacent gate structure 210 and the source-drain plug 240 are electrically connected through the connecting plug 261 .

[0065] The material of the connecting plug 261 includes: cobalt, copper, tungsten, aluminum, titanium or tantalum. In this embodiment, the material of the connecting plug 261 is tungsten.

[0066] Please refer to Fig.10 After forming the connecting plug 261 , a third dielectric layer 270 is formed on the surfaces of the second dielectric layer 250 and the connecting plug 261 .

[0067] The third dielectric layer 270 provides support for the subsequent formation of a first plug, a second plug, and a third plug.

[0068] The material of the third dielectric layer 270 includes silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride or silicon oxynitride. In this embodiment, the material of the third dielectric layer 270 is silicon oxide.

[0069] The connection plug 261 is first formed in the second dielectric layer 250, and the connection plug 261 is electrically connected to the gate structure 210 and the source-drain plug 240. Then, a third dielectric layer 270 is formed on the surface of the second dielectric layer 250, and the third dielectric layer 270 electrically isolates the connection plug 261. A first plug 281 is subsequently formed in the third dielectric layer 270, and the top surface of the first plug 281 is higher than the top surface of the connection plug 261, so that the first plug 281 is electrically connected to the connection plug 261, that is, the connection plug 261 that needs to be externally connected is selected through the first plug 281. Since the connection plug 261 that needs to be externally connected has been electrically connected through the first plug 281, and the area occupied by the first plug 261 is small, the difficulty of wiring in the subsequent formation of the conductive layer is reduced, which is conducive to reducing the difficulty of the process.

[0070] After forming the third dielectric layer 270 , a first plug is formed in the second dielectric layer 250 and the third dielectric layer 270 . The top surface of the first plug is higher than the top surface of the connecting plug 261 , and the first plug is electrically connected to the connecting plug 261 .

[0071] The method for forming the semiconductor structure further includes: forming a second plug in the second dielectric layer 250 and the third dielectric layer 270, the second plug being located on the top surface of the source-drain plug 240, and the top surface of the second plug being higher than the top surface of the connecting plug 261; and forming a third plug in the second dielectric layer 250 and the third dielectric layer 270, the third plug being located on the top surface of the gate structure 210, and the top surface of the third plug being higher than the top surface of the connecting plug 240.

[0072] In this embodiment, the first plug is located on the source-drain plug 240 .

[0073] The second plug is formed in the same process as the first plug.

[0074] For details on the process of forming the first plug, the second plug and the third plug, please refer to Figures 11 to 13 .

[0075] Please refer to Fig.11 , forming a first patterned layer 252 on the surface of the third dielectric layer 270, wherein the first patterned layer 252 exposes the surface of the third dielectric layer 270 on the source-drain plug 240; using the first patterned layer 252 as a mask, etching the second dielectric layer 250 and the third dielectric layer 270 until the surface of the connecting plug 261 and the surface of the source-drain plug 240 are exposed, forming a first opening 271 in the third dielectric layer 270, wherein the first opening 271 exposes the surface of the connecting plug 261, and forming a second opening 272 in the second dielectric layer 250 and the third dielectric layer 270, wherein the second opening 272 exposes the surface of the source-drain plug 240.

[0076] The first opening 271 provides a space for subsequently forming a first plug; the second opening 272 provides a space for subsequently forming a second plug.

[0077] The process of etching the second dielectric layer 250 and the third dielectric layer 270 includes: one of a wet etching process and a dry etching process or a combination of the two.

[0078] In this embodiment, the process of etching the second dielectric layer 250 and the third dielectric layer 270 is a dry etching process.

[0079] In this embodiment, the first opening 271 and the second opening 272 are formed by etching using the same patterned layer as a mask, thereby simplifying the process steps and saving the material of the patterned layer, which is beneficial to saving process costs.

[0080] In this embodiment, after the first opening 271 and the second opening 272 are formed, the first patterned layer 252 is removed.

[0081] Please refer to Fig.12 After forming the first opening 271 and the second opening 272, a second patterned layer 253 is formed on the surface of the third dielectric layer 270, and the second patterned layer 253 exposes the surface of the third dielectric layer 270 on the gate structure 210; using the second patterned layer 253 as a mask, the second dielectric layer 250 and the third dielectric layer 270 are etched until the top surface of the gate structure 210 is exposed, and a third opening 273 is formed in the third dielectric layer 270.

[0082] The third opening 273 provides space for subsequently forming a third plug.

[0083] Specifically, the second patterned layer 253 is also filled in the first opening 271 and the second opening 272 .

[0084] In this embodiment, the process of etching the second dielectric layer 250 and the third dielectric layer 270 is a dry etching process.

[0085] In this embodiment, after the third opening 273 is formed, the second patterned layer 253 is removed.

[0086] In this embodiment, the second patterned layer 253 is filled in the first opening 271 and the second opening 272 . After the second patterned layer 253 is removed, the first opening 271 and the second opening 272 are exposed.

[0087] In other embodiments, the third opening may be formed before the first opening and the second opening are formed.

[0088] Please refer to Fig.13 A first plug 281 is formed in the third dielectric layer 270, and the first plug 281 is located on the surface of the connecting plug 261; a second plug 282 is formed in the second dielectric layer 250 and the third dielectric layer 270, and the second plug 282 is located on the top surface of the source-drain plug 240; a third plug 283 is formed in the second dielectric layer 250 and the third dielectric layer 270, and the third plug 283 is located on the top surface of the gate structure 210.

[0089] The method for forming the first plug 281 and the second plug 282 includes: forming a first conductive material film (not shown in the figure) in the first opening 271 and the second opening 272 and on the surface of the third dielectric layer 270, and the first conductive material film fills the first opening 271 and the second opening 272; planarizing the first conductive material film, forming the first plug 281 in the first opening 271, and forming the second plug 282 in the second opening 272.

[0090] The method for forming the third plug 283 includes: forming a second conductive material film (not shown) in the third opening 273 and on the surface of the third dielectric layer 270 , the second conductive material film filling the third opening 273 ; and planarizing the second conductive material film to form the third plug 283 in the third opening 273 .

[0091] In this embodiment, the first conductive material film and the second conductive material film are formed by the same deposition process, and after the planarization process, the first plug 281, the second plug 282, and the third plug 283 are formed in the same process, thereby simplifying the process steps and facilitating improving production efficiency.

[0092] In other embodiments, the third plug is formed after the first plug and the second plug are formed.

[0093] In this embodiment, the first opening 271 and the second opening 272 are formed first, and then the third opening 273 is formed.

[0094] In other embodiments, the third opening may be formed first, and then the first opening and the second opening may be formed.

[0095] In this embodiment, after forming the first plug 281 , the second plug 282 and the third plug 283 , the method further includes: forming a fourth dielectric layer on the surface of the third dielectric layer 270 ; forming a conductive layer in the fourth dielectric layer, wherein the conductive layer is electrically connected to the first plug 281 , the second plug 282 and the third plug 283 .

[0096] Accordingly, this embodiment also provides a semiconductor structure formed by the above method, please continue to refer to Fig.13, comprising: a substrate 200, a first dielectric layer 250 and a plurality of gate structures 210 on the substrate 200, source-drain doped regions 230 on both sides of the gate structure 210, source-drain doped regions 230 on the top surfaces of the source-drain doped regions 230, the first dielectric layer 220 located on the surfaces of the gate structure 210, the source-drain doped regions 230 and the source-drain plugs 240; a second dielectric layer 250 located on the surfaces of the first dielectric layer 220, the gate structure 210 and the source-drain plugs 240; layer 250; a connecting plug 261 located in the second dielectric layer 250, and the connecting plug 261 is located on the top surface of the adjacent gate structure 210 and the source-drain plug 240; a third dielectric layer 270 located on the surface of the second dielectric layer 250 and the connecting plug 261; a first plug 281 located in the third dielectric layer 270, the top surface of the first plug 281 is higher than the top surface of the connecting plug 261, and the first plug 281 is electrically connected to the connecting plug 261.

[0097] The connection plug 261 is electrically connected to the gate structure 210 and the source-drain plug 240. The surface of the connection plug 261 and the surface of the second dielectric layer 250 are provided with a third dielectric layer 270, and the connection plug 261 is isolated by the third dielectric layer 270. The first plug 281 is electrically connected to the connection plug 261, and the top surface of the first plug 281 is higher than the top surface of the connection plug 261, that is, the connection plug 261 that needs to be externally connected is selected by the first plug 281. Since the first plug 281 occupies a small area, it is beneficial to reduce the difficulty of wiring the subsequent conductive layer, thereby improving the performance of the formed semiconductor structure.

[0098] The following is a detailed description with reference to the accompanying drawings.

[0099] In this embodiment, the first plug 281 is located on the source-drain plug 240 .

[0100] In this embodiment, the semiconductor structure further includes: a second plug 282 located in the second dielectric layer 250 and the third dielectric layer 270, the second plug 282 is located on the top surface of the source-drain plug 240, and the top surface of the second plug 282 is higher than the top surface of the connecting plug 261; a third plug 283 located in the second dielectric layer 250 and the third dielectric layer 270, the third plug 283 is located on the top surface of the gate structure 210, and the top surface of the third plug 283 is higher than the top surface of the connecting plug 261.

[0101] In this embodiment, the semiconductor structure further includes: a conductive layer (not shown in the figure) located on the surface of the third dielectric layer 270 , and the conductive layer is electrically connected to the first plug 281 , the second plug 282 and the third plug 283 .

[0102] Figures 14 to 16 FIG. 1 is a cross-sectional structural diagram of another embodiment of the present invention showing the formation process of a semiconductor structure. The difference between this embodiment and the above embodiment is that the first plug is located on the gate structure. Therefore, this embodiment continues to explain the formation process of the semiconductor structure based on the above embodiment. Fig.10 Continue to refer to Fig.14 .

[0103] After forming the third dielectric layer 270 , a first plug is formed in the second dielectric layer 250 and the third dielectric layer 270 . The top surface of the first plug is higher than the top surface of the connecting plug 261 , and the first plug is electrically connected to the connecting plug 261 .

[0104] The method for forming the semiconductor structure further includes: forming a second plug in the second dielectric layer 250 and the third dielectric layer 270, the second plug being located on the top surface of the source-drain plug 240, and the top surface of the second plug being higher than the top surface of the connecting plug 261; and forming a third plug in the second dielectric layer 250 and the third dielectric layer 270, the third plug being located on the top surface of the gate structure 210, and the top surface of the third plug being higher than the top surface of the connecting plug 261.

[0105] In this embodiment, the first plug is located on the gate structure 210 .

[0106] The third plug is formed in the same process as the first plug.

[0107] For details on the process of forming the first plug, the second plug and the third plug, please refer to Figures 14 to 16 .

[0108] Please refer to Fig.14 , forming a first patterned layer 351 on the surface of the third dielectric layer 270, wherein the first patterned layer 351 exposes the surface of the third dielectric layer 270 on the gate structure 210; using the first patterned layer 351 as a mask, etching the second dielectric layer 250 and the third dielectric layer 270 until the surface of the connecting plug 261 and the surface of the gate structure 210 are exposed, forming a first opening 371 in the third dielectric layer 270, wherein the first opening 371 exposes the surface of the connecting plug 261, and forming a third opening 373 in the second dielectric layer 250 and the third dielectric layer 270, wherein the third opening 373 exposes the surface of the gate structure 210.

[0109] The first opening 371 provides a space for subsequently forming a first plug; and the third opening 373 provides a space for subsequently forming a third plug.

[0110] In this embodiment, the process of etching the second dielectric layer 250 and the third dielectric layer 270 is a dry etching process.

[0111] In this embodiment, after the first opening 371 and the third opening 373 are formed, the first patterned layer 351 is removed.

[0112] Please refer to Fig.15 After forming the first opening 371 and the third opening 373, a second patterned layer 352 is formed on the surface of the third dielectric layer 270, and the second patterned layer 352 exposes the surface of the third dielectric layer 270 on the source-drain plug 240; using the second patterned layer 352 as a mask, the second dielectric layer 250 and the third dielectric layer 270 are etched until the top surface of the source-drain plug 240 is exposed, and a second opening 372 is formed in the second dielectric layer 250 and the third dielectric layer 270.

[0113] The second opening 372 provides a space for subsequently forming a second plug.

[0114] In this embodiment, the process of etching the second dielectric layer 250 and the third dielectric layer 270 is a dry etching process.

[0115] In this embodiment, the first opening 371 and the third opening 373 are formed first, and then the second opening 372 is formed. In other embodiments, the second opening may be formed first, and then the first opening and the third opening are formed.

[0116] In this embodiment, after the second opening 272 is formed, the second patterned layer 352 is removed.

[0117] Please refer to Fig.16 A first plug 381 is formed in the third dielectric layer 270, and the first plug 381 is located on the surface of the connecting plug 261; a second plug 382 is formed in the second dielectric layer 250 and the third dielectric layer 270, and the second plug 382 is located on the top surface of the source-drain plug 240; a third plug 383 is formed in the second dielectric layer 250 and the third dielectric layer 270, and the third plug 283 is located on the top surface of the gate structure 210.

[0118] The method for forming the first plug 381 and the third plug 383 includes: forming a first conductive material film in the first opening 381, the third opening 383 and on the surface of the third dielectric layer 270, wherein the first conductive material film fills the first opening 381 and the third opening 383; planarizing the first conductive material film, forming the first plug 381 in the first opening 371, and forming the third plug 383 in the third opening 373.

[0119] The method for forming the second plug 382 includes: forming a second conductive material film (not shown) in the second opening 372 and on the surface of the third dielectric layer 270 , the second conductive material film filling the second opening 372 ; and planarizing the second conductive material film to form the second plug 382 in the second opening 372 .

[0120] In this embodiment, the first conductive material film and the second conductive material film are formed by the same deposition process, and after the planarization process, the first plug 381, the second plug 382 and the third plug 383 are formed in the same process, thereby simplifying the process steps and facilitating improving production efficiency.

[0121] In other embodiments, the second plug is formed after the first plug and the third plug are formed.

[0122] In this embodiment, after forming the first plug 381, the second plug 382 and the third plug 383, the method further includes: forming a fourth dielectric layer (not shown in the figure) on the surface of the third dielectric layer 270; forming a conductive layer (not shown in the figure) in the fourth dielectric layer, and the conductive layer is electrically connected to the first plug 381, the second plug 382 and the third plug 383.

[0123] Correspondingly, this embodiment also provides a semiconductor structure formed by the above method, please refer to Fig.16 , comprising: a substrate 200, a first dielectric layer 220 and a plurality of gate structures 210 on the substrate 200, source-drain doped regions 230 on both sides of the gate structure 210, source-drain plugs 240 on the top surfaces of the source-drain doped regions 230, the first dielectric layer 220 being located on the surfaces of the gate structure 210, the source-drain doped regions 230 and the source-drain plugs 240; a second dielectric layer 220 being located on the surfaces of the first dielectric layer 220, the gate structure 210 and the source-drain plugs 240; layer 250; a connecting plug 261 located in the second dielectric layer 250, and the connecting plug 261 is located on the top surface of the adjacent gate structure 210 and the source-drain plug 240; a third dielectric layer 270 located on the surface of the second dielectric layer 250 and the connecting plug 261; a first plug 381 located in the third dielectric layer 270, the top surface of the first plug 381 is higher than the top surface of the connecting plug 261, and the first plug 381 is electrically connected to the connecting plug 261.

[0124] In this embodiment, the first plug 381 is located on the gate structure 210 .

[0125] In this embodiment, the semiconductor structure further includes: a second plug 382 located in the second dielectric layer 250 and the third dielectric layer 270, the second plug 382 is located on the top surface of the source-drain plug 240, and the top surface of the second plug 382 is higher than the top surface of the connecting plug 261; a third plug 383 located in the second dielectric layer 250 and the third dielectric layer 270, the third plug 383 is located on the top surface of the gate structure 210, and the top surface of the third plug 383 is higher than the top surface of the connecting plug 261.

[0126] In this embodiment, the semiconductor structure further includes: a conductive layer (not shown in the figure) located on the surface of the third dielectric layer 270 , and the first plug 381 , the second plug 382 and the third plug 383 of the conductive layer are electrically connected.

[0127] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate has a first dielectric layer and a plurality of gate structures, the substrate has source-drain doped regions on both sides of the gate structures, the top surfaces of the source-drain doped regions have source-drain plugs, and the first dielectric layer is located on the surfaces of the gate structures, the source-drain doped regions, and the source-drain plugs; A second dielectric layer located on the surface of the first dielectric layer, the gate structure and the source-drain plug; A connection plug located in the second dielectric layer, and the connection plug is located on the top surface of the adjacent gate structure and source-drain plug; a third dielectric layer located on the second dielectric layer and the surface of the connecting plug; a first plug located in the third dielectric layer, wherein a top surface of the first plug is higher than a top surface of the connecting plug, and the first plug is electrically connected to the connecting plug; Wherein, the connection plug is located at the bottom of the first plug, and in the connection plug, the bottom of the surface of the source and drain plug is higher than the bottom of the surface of the gate structure; A conductive layer is located on the surface of the third dielectric layer, and the conductive layer is electrically connected to the first plug, wherein the area occupied by the first plug is smaller than the area occupied by the connecting plug.

2. The semiconductor structure according to claim 1, wherein: The first plug is located on the source-drain plug.

3. The semiconductor structure according to claim 1, wherein: The first plug is located on the gate structure.

4. The semiconductor structure according to claim 1, wherein: Also includes: A second plug located in the second dielectric layer and the third dielectric layer, the second plug being located on a top surface of the source-drain plug, and having a top surface higher than a top surface of the connection plug; A third plug is located in the second dielectric layer and the third dielectric layer, the third plug is located on the top surface of the gate structure, and the top surface of the third plug is higher than the top surface of the connecting plug.

5. The semiconductor structure according to claim 4, characterized in that Also includes: A conductive layer is located on the surface of the third dielectric layer, and the conductive layer is electrically connected to the first plug, the second plug and the third plug.

6. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a first dielectric layer and a plurality of gate structures, the substrate has source-drain doping regions on both sides of the gate structures, the top surfaces of the source-drain doping regions have source-drain plugs, and the first dielectric layer is located on the surfaces of the gate structures, the source-drain doping regions, and the source-drain plugs; forming a second dielectric layer on the surface of the first dielectric layer, the gate structure and the source-drain plugs; forming a connection plug in the second dielectric layer, wherein the connection plug is located on the top surface of the adjacent gate structure and source-drain plug; forming a third dielectric layer on the second dielectric layer and the surface of the connecting plug; forming a first plug in the third dielectric layer, wherein a top surface of the first plug is higher than a top surface of the connecting plug, and the first plug is electrically connected to the connecting plug; forming a fourth dielectric layer on the surface of the third dielectric layer; forming a conductive layer in the fourth dielectric layer, the conductive layer being electrically connected to the first plug, wherein the occupied area of ​​the first plug is smaller than the occupied area of ​​the connecting plug; The connecting plug is located at the bottom of the first plug, and in the connecting plug, the bottom of the surface of the source and drain plugs is higher than the bottom of the surface of the gate structure.

7. The method for forming a semiconductor structure according to claim 6, wherein: Also includes: forming a second plug in the second dielectric layer and the third dielectric layer, wherein the second plug is located on the top surface of the source-drain plug, and the top surface of the second plug is higher than the top surface of the connection plug; A third plug is formed in the second dielectric layer and the third dielectric layer. The third plug is located on the top surface of the gate structure, and the top surface of the third plug is higher than the top surface of the connecting plug.

8. The method for forming a semiconductor structure according to claim 7, wherein: The first plug is located on the source-drain plug.

9. The method for forming a semiconductor structure according to claim 8, wherein: The second plug is formed in the same process as the first plug.

10. The method for forming a semiconductor structure according to claim 9, wherein: The method for forming the first plug and the second plug includes: forming a first patterned layer on the surface of the third dielectric layer, the first patterned layer exposing the surface of the third dielectric layer on the source and drain plugs; using the first patterned layer as a mask, etching the second dielectric layer and the third dielectric layer until the surface of the connection plug and the surface of the source and drain plugs are exposed, forming a first opening in the third dielectric layer, the first opening exposing the surface of the connection plug, forming a second opening in the second dielectric layer and the third dielectric layer, the second opening exposing the surface of the source and drain plugs; forming a first conductive material film in the first opening, in the second opening and on the surface of the third dielectric layer, the first conductive material film filling the first opening and the second opening; planarizing the first conductive material film, forming the first plug in the first opening, and forming the second plug in the second opening.

11. The method for forming a semiconductor structure according to claim 9, wherein: The method for forming the third plug includes: forming a second patterned layer on the surface of the third dielectric layer, the second patterned layer exposing the surface of the third dielectric layer on the gate structure; using the second patterned layer as a mask, etching the second dielectric layer and the third dielectric layer until the top surface of the gate structure is exposed, and forming a third opening in the third dielectric layer; forming a second conductive material film in the third opening and on the surface of the third dielectric layer, the second conductive material film filling the third opening; planarizing the second conductive material film, and forming the third plug in the third opening.

12. The method for forming a semiconductor structure according to claim 7, wherein: The first plug is located on the gate structure.

13. The method for forming a semiconductor structure according to claim 12, wherein: The first plug and the third plug are formed in the same process.

14. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the first plug and the third plug includes: forming a first patterned layer on the surface of the third dielectric layer, the first patterned layer exposing the surface of the third dielectric layer on the gate structure; using the first patterned layer as a mask, etching the third dielectric layer until the surface of the connection plug and the surface of the gate structure are exposed, forming a first opening and a third opening in the third dielectric layer, the first opening exposing the surface of the connection plug, and the third opening exposing the surface of the gate structure; forming a first conductive material film in the first opening, in the third opening and on the surface of the third dielectric layer, the first conductive material film filling the first opening and the third opening; planarizing the first conductive material film, forming the first plug in the first opening, and forming the third plug in the third opening.

15. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the second plug includes: forming a second patterned layer on the surface of the third dielectric layer, the second patterned layer exposing the surface of the third dielectric layer on the source and drain plugs; using the second patterned layer as a mask, etching the third dielectric layer until the top surface of the source and drain plugs is exposed, and forming a second opening in the second dielectric layer and the third dielectric layer; forming a second conductive material film in the second opening and on the surface of the third dielectric layer, the second conductive material film filling the second opening; and planarizing the second conductive material film to form the second plug in the second opening.

16. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming a connection plug in the second dielectric layer includes: forming a third patterned layer on the surface of the second dielectric layer, the third patterned layer exposing the surface of the second dielectric layer on the adjacent gate structure and the source and drain plug; using the third patterned layer as a mask, etching the second dielectric layer until the top surface of the gate structure and the top surface of the source and drain plug are exposed, and forming a fourth opening in the second dielectric layer; forming a third conductive material film in the fourth opening and on the surface of the second dielectric layer, the third conductive material film filling the fourth opening; and planarizing the third conductive material film until the surface of the second dielectric layer is exposed to form the connection plug.

17. The method for forming a semiconductor structure according to claim 7, wherein: Also includes: forming a fourth dielectric layer on the surface of the third dielectric layer; A conductive layer is formed in the fourth dielectric layer, and the conductive layer is electrically connected to the first plug, the second plug, and the third plug.

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