Semiconductor memory device

Abstract

A semiconductor memory device includes: a first and a second conductive layer arranged in a first direction; a plurality of first semiconductor layers arranged in a second direction intersecting the first direction, between the first and the second conductive layers and opposite the first conductive layer; a first charge accumulation layer provided between the plurality of first semiconductor layers and the first conductive layer in the first direction, extending in the second direction across a plurality of regions between the plurality of first semiconductor layers and the first conductive layer; and a first insulating layer provided between the plurality of first semiconductor layers and the first charge accumulation layer in the first direction. The first insulating layer includes: a first region opposite a first end portion of the first semiconductor layer in the second direction in the first direction; a second region opposite a second end portion of the first semiconductor layer in the second direction in the first direction; and a third region provided between the first and the second regions in the second direction. A nitrogen concentration of the first and the second regions is lower than a nitrogen concentration of the third region.

Description

[0001] Related Application

[0002] This application claims priority to Japanese Patent Application No. 2020-149398 (Filing date: September 4, 2020) and U.S. Patent Application No. 17 / 190865 (Filing date: March 3, 2021). This application incorporates the entire contents of the base application by reference thereto. TECHNICAL FIELD

[0003] Embodiments described in the following relate to a semiconductor storage device. BACKGROUND

[0004] Known is a semiconductor storage device that has a substrate, a plurality of conductive layers stacked in a direction intersecting a surface of the substrate, a semiconductor layer extending in a stacking direction of the plurality of conductive layers and opposing the plurality of conductive layers, and a gate insulating film provided between the conductive layers and the semiconductor layer. The gate insulating film has, for example, a silicon nitride film (SiN) or a floating gate or the like that is a storage portion capable of storing data. SUMMARY

[0005] The present application has been made to solve the problem of providing a semiconductor storage device that operates appropriately.

[0006] A semiconductor storage device of an embodiment has a first conductive layer and a second conductive layer arranged in a first direction, a plurality of first semiconductor layers arranged in a second direction intersecting the first direction and opposing the first conductive layer between the first conductive layer and a second conductive layer, a first charge accumulation layer provided between the plurality of first semiconductor layers and the first conductive layer in the first direction and extending in the second direction across a plurality of regions between the plurality of first semiconductor layers and the first conductive layer, and a first insulating layer provided between the plurality of first semiconductor layers and the first charge accumulation layer in the first direction. The first insulating layer has a first region opposing one end portion of the first semiconductor layer in the second direction in the first direction, a second region opposing the other end portion of the first semiconductor layer in the second direction in the first direction, and a third region provided between the first region and the second region in the second direction. The concentration of nitrogen in the first region and the second region is lower than the concentration of nitrogen in the third region. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a schematic equivalent circuit diagram of the semiconductor storage device of the first embodiment.

[0008] Figure 2 is a schematic perspective view of the semiconductor storage device.

[0009] Figure 3 (a) of is a schematic plan view of the semiconductor storage device of the first embodiment. Figure 2a cross section of a portion indicated by a line A-A' of Figure 3 (b) is a schematic plan view corresponding to a cross section of a portion indicated by a line A-A' of Figure 3 (a) is a schematic sectional view corresponding to a cross section of a portion indicated by a line B-B' of

[0010] Figure 4 (b) is a schematic plan view corresponding to a cross section of a portion indicated by a line A-A' of Figure 3 (a) is a schematic enlarged view of a portion corresponding to a memory cell configuration MUS and its vicinity of

[0011] Figure 5 is a schematic plan view and sectional view indicating a manufacturing method of the semiconductor storage device.

[0012] Figure 6 is a schematic plan view and sectional view indicating a manufacturing method of the semiconductor storage device.

[0013] Figure 7 is a schematic plan view and sectional view indicating a manufacturing method of the semiconductor storage device.

[0014] Figure 8 is a schematic plan view and sectional view indicating a manufacturing method of the semiconductor storage device.

[0015] Figure 9 is a schematic plan view and sectional view indicating a manufacturing method of the semiconductor storage device.

[0016] Figure 10 is a schematic plan view and sectional view indicating a manufacturing method of the semiconductor storage device.

[0017] Figure 11 is a schematic plan view and sectional view indicating a manufacturing method of the semiconductor storage device.

[0018] Figure 12 is a schematic plan view and sectional view indicating a manufacturing method of the semiconductor storage device.

[0019] Figure 13 is a schematic plan view and sectional view indicating a manufacturing method of the semiconductor storage device.

[0020] Figure 14 is a schematic plan view and sectional view indicating a manufacturing method of the semiconductor storage device.

[0021] Figure 15 is a schematic plan view and sectional view indicating a manufacturing method of the semiconductor storage device.

[0022] Figure 16 is a schematic plan view and sectional view indicating a manufacturing method of the semiconductor storage device.

[0023] Figure 17 is a schematic plan view and sectional view indicating a manufacturing method of the semiconductor storage device.

[0024] Figure 18 is a schematic plan view and sectional view showing the manufacturing method.

[0025] Figure 19 is a schematic plan view and sectional view showing the manufacturing method.

[0026] Figure 20 is a schematic plan view showing a part of the structure of a semiconductor storage device of a comparative example.

[0027] Figure 21 is a schematic plan view showing a part of the structure of a semiconductor storage device of a modification example. DETAILED DESCRIPTION

[0028] Next, the semiconductor storage device of the embodiments will be described in detail with reference to the drawings. Note that these embodiments are merely examples, and are not intended to limit the present application.

[0029] Further, each drawing is schematic, and there are cases in which a part of the structure is omitted. Further, there are cases in which a part common to each embodiment is given a common reference numeral and the description is omitted.

[0030] Further, in this specification, a prescribed direction parallel to the surface of a substrate is referred to as an X direction, a direction orthogonal to the X direction and parallel to the surface of the substrate is referred to as a Y direction, and a direction orthogonal to the surface of the substrate is referred to as a Z direction.

[0031] Further, in this specification, there are cases in which a direction along a prescribed plane is referred to as a first direction, a direction along the prescribed plane and intersecting the first direction is referred to as a second direction, and a direction intersecting the prescribed plane is referred to as a third direction. These first, second, and third directions can or can not correspond to any of the X direction, the Y direction, and the Z direction.

[0032] Further, in this specification, expressions such as "above" and "below" are made with the substrate as a reference. For example, a direction away from the substrate along the above first direction is referred to as above, and a direction approaching the substrate along the first direction is referred to as below. Further, in the case where a lower surface or a lower end is referred to with respect to a certain structure, a surface or an end portion on the substrate side of the structure is meant, and in the case where an upper surface or an upper end is referred to, a surface or an end portion on the side opposite to the substrate of the structure is meant. Further, a surface intersecting the second direction or the third direction is referred to as a side surface or the like.

[0033] Further, in the present specification, regarding a structure, a component, or the like, in the case where "width" or "thickness" of a prescribed direction is mentioned, it means a width or thickness in a cross section or the like observed by SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy) or the like.

[0034] [First Embodiment]

[0035] [Configuration]

[0036] Figure 1 is a schematic equivalent circuit diagram of the semiconductor storage device of the first embodiment.

[0037] The semiconductor storage device of the present embodiment is provided with a memory cell array MCA and a peripheral circuit PC that controls the memory cell array MCA.

[0038] The memory cell array MCA is provided with a plurality of memory cells MU. The plurality of memory cells MU are each provided with two memory strings MSa, MSb that are electrically independent. One end of each of the memory strings MSa, MSb is connected to a drain side selection transistor STD and is connected to a common bit line BL via the drain side selection transistor STD. The other end of each of the memory strings MSa, MSb is connected to a common source side selection transistor STS and is connected to a common source line SL via the source side selection transistor STS.

[0039] The memory strings MSa, MSb are each provided with a plurality of memory cells MC connected in series. The memory cell MC is a field effect transistor provided with a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film is provided with a charge accumulation layer capable of storing data. The threshold voltage of the memory cell MC varies according to the amount of charge in the charge accumulation layer. The gate electrode is part of a word line WL.

[0040] The selection transistors (STD, STS) are field effect transistors provided with a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrode of the drain side selection transistor STD is part of a drain selection gate line SGD. The gate electrode of the source side selection transistor STS is part of a source side selection gate line SGS.

[0041] The peripheral circuit PC generates voltages required for, for example, a read operation, a write operation, and a delete operation, and applies the voltages to the bit line BL, the source line SL, the word line WL, and the select gate line (SGD, SGS). The peripheral circuit PC includes, for example, a row decoder, a sense amplifier module, a voltage generation circuit, a sequencer, various registers, and the like. The peripheral circuit PC is constituted of, for example, a plurality of transistors and wiring lines provided on a semiconductor substrate.

[0042] Next, a schematic configuration example of the semiconductor storage device of the present embodiment will be described with reference to Figure 2 and Figure 3 A schematic configuration example of the semiconductor storage device of the present embodiment will be described. Figure 2 is a schematic perspective view of the semiconductor storage device. Figure 3 (a) of is a schematic plan view corresponding to a cross section of a portion indicated by an A-A' line of Figure 2 Figure 3 (b) of is a schematic cross-sectional view corresponding to a cross section of a portion indicated by a B-B' line of (a) of Figure 3 Figure 2 and Figure 3 omit a part of the structure.

[0043] For example, as shown in Figure 2 , the semiconductor storage device of the present embodiment is provided with a substrate 110 and a memory cell array MCA provided above the substrate 110.

[0044] The substrate 110 is, for example, a semiconductor substrate of monocrystalline silicon (Si) or the like. The substrate 110 is provided with a double well structure having, for example, an n-type impurity layer on an upper surface of the semiconductor substrate, and further having a p-type impurity layer in the n-type impurity layer. In addition, on the surface of the substrate 110, transistors and wiring lines that constitute the peripheral circuit PC, and the like can also be provided.

[0045] The memory cell array MCA is provided with a plurality of stacked body structures LS arranged in the Y direction. The stacked body structure LS is provided with a plurality of conductive layers 120 stacked in the Z direction. Between these stacked body structures LS, a memory trench structure MT is provided. The stacked body structures LS and the memory trench structure MT are alternately arranged in the Y direction. The memory trench structure MT is provided with, for example, as shown in (a) of Figure 3 , a plurality of memory cell structures MUS and a memory cell inter-structure IMUS arranged in the X direction. The memory cell structure MUS is provided with a semiconductor layer 130, a portion of a gate insulating layer 140, and a portion of an insulating layer 150. The memory cell inter-structure IMUS is provided with a portion of the gate insulating layer 140 and a portion of the insulating layer 150. Further, for example, as shown in Figure 2 , a lower end of the semiconductor layer 130 is connected to a wiring layer 160.

[0046] ​​The conductive layer 120 is a substantially plate-shaped conductive layer extending in the X direction, such as a laminated film of titanium nitride (TiN) and tungsten (W), or a conductive layer of polysilicon (p-Si) into which an impurity is injected. These conductive layers 120 function as gate electrodes of the word lines WL and the memory cells MC (a) of the memory string MSa (b), respectively. Figure 1

[0047] Under the plurality of conductive layers 120, a conductive layer 121 (a) containing the same material as the conductive layer 120 is provided, for example. Figure 2 The conductive layer 121 functions as a gate electrode of the source side selection gate line SGS and the source side selection transistor STS (b). Figure 1

[0048] Between the plurality of conductive layers 120, between the lowermost conductive layer 120 and the conductive layer 121, and between the conductive layer 121 and the wiring layer 160, an insulating layer 122 of silicon oxide (SiO2) or the like is provided.

[0049] In the following description, one of the two laminated body configurations LS arranged in the Y direction is referred to as the laminated body configuration LSa, and the other is referred to as the laminated body configuration LSb. In addition, the conductive layer 120 included in the laminated body configuration LSa is referred to as the first conductive layer 120a, and the conductive layer 120 included in the laminated body configuration LSb is referred to as the second conductive layer 120b.

[0050] The semiconductor layer 130 is arranged in the X direction in correspondence with the plurality of memory cell configurations MUS arranged in the X direction, as shown in (a) of FIG. 13, for example. The semiconductor layer 130 is a semiconductor layer of undoped polysilicon (Si) or the like, for example. Figure 3 As shown in (b) of FIG. 13, the semiconductor layer 130 has a first semiconductor layer 130a provided between the laminated body configuration LSa and the insulating layer 150, a second semiconductor layer 130b provided between the laminated body configuration LSb and the insulating layer 150, a third semiconductor layer 130c provided at a lower end of the first semiconductor layer 130a and the second semiconductor layer 130b, and a fourth semiconductor layer 130d provided at an upper end of the first semiconductor layer 130a and the second semiconductor layer 130b. Figure 2 The first semiconductor layer 130a is arranged in the X direction in plurality, and extends in the Z direction to oppose the plurality of first conductive layers 120a, respectively. The first semiconductor layer 130a functions as a channel region of the plurality of memory cells MC included in the memory string MSa (b).

[0051] Figure 1

[0052] ​​​​Multiple second semiconductor layers 130b are arranged in the X direction, extending along the Z direction and opposite to multiple second conductive layers 120b. The second semiconductor layer 130b serves as the memory string MSb. Figure 1 The channel region of the multiple memory cells (MCs) contained in the memory cell (MC) functions.

[0053] For example, the fourth semiconductor layer 130d Figure 2 As shown, it is connected to the first semiconductor layer 130a and the second semiconductor layer 130b. The fourth semiconductor layer 130d is connected to the bit line contact BLC of tungsten (W) and the bit line BL of copper (Cu).

[0054] In addition, for example, Figure 2 As illustrated, a semiconductor layer 133 is provided below the semiconductor layer 130. The semiconductor layer 133 is connected to the third semiconductor layer 130c. The semiconductor layer 133 is disposed between two adjacent conductive layers 121 in the Y direction, and faces these two conductive layers 121. The semiconductor layer 133 is a semiconductor layer such as polycrystalline silicon (p-Si), and serves as a source-side selection transistor (STS). Figure 1 The channel region functions as a semiconductor layer. An insulating layer 135, such as silicon oxide (SiO2), is provided between the semiconductor layer 133 and the conductive layer 121.

[0055] The gate insulating layer 140 includes a first gate insulating layer 140a and a second gate insulating layer 140b.

[0056] The first gate insulating layer 140a is disposed on one side of the laminate structure LS in the Y direction between the first semiconductor layer 130a and a plurality of first conductive layers 120a arranged in the Z direction, and extends along the Z direction. Furthermore, the first gate insulating layer 140a extends along the X direction across a plurality of regions between the plurality of first semiconductor layers 130a and the first conductive layers 120a. For example, the first gate insulating layer 140a is... Figure 3 As shown in (a), it includes a first insulating layer 141a, a first charge accumulation layer 142a and a first insulating layer 143a.

[0057] The second gate insulating layer 140b is disposed on a side surface on the opposite side of the Y direction of the laminate structure LS between the second semiconductor layer 130b and a plurality of second conductive layers 120b arranged in the Z direction, and extends along the Z direction. Furthermore, the second gate insulating layer 140b extends along the X direction throughout a plurality of regions between the plurality of second semiconductor layers 130b and the second conductive layers 120b. For example, the second gate insulating layer 140b is... Figure 3 As shown in (a), it includes a second insulating layer 141b, a second charge accumulation layer 142b, and a second insulating layer 143b.

[0058] The first insulating layer 141a and the second insulating layer 141b include, for example, an insulating layer of silicon oxynitride (SiON) or the like. The first charge accumulation layer 142a and the second charge accumulation layer 142b include, for example, an insulating layer of silicon nitride (SiN) or the like. The first bulk insulating layer 143a and the second bulk insulating layer 143b include, for example, an insulating layer of silicon oxide (SiO2) or the like.

[0059] Here, the use of Figure 4 The first insulating layer 141a and the second insulating layer 141b will be described in detail. Figure 4 is Figure 3 An enlarged view of a portion corresponding to the storage unit structure MUS of (a) and its vicinity.

[0060] The first insulating layer 141a has a plurality of high-nitrogen-concentration regions provided corresponding to a plurality of storage unit structures MUS arranged in the X direction, and a plurality of low-nitrogen-concentration regions provided corresponding to a plurality of inter-storage unit structures IMUS arranged in the X direction. For example Figure 4 In the example, as two low-nitrogen-concentration regions corresponding to two inter-storage unit structures IMUS adjacent in the X direction, a first region 141a_1 and a second region 141a_2 are exemplified. Further, as a high-nitrogen-concentration region provided between these low-nitrogen-concentration regions, a third region 141a_3 is exemplified. The width X 141a _3 in the X direction of each high-nitrogen-concentration region is smaller than the width X 130a Further, the end portion in the X direction of each low-nitrogen-concentration region is opposed to the side surface in the Y direction of the two first semiconductor layers 130a adjacent in the X direction. For example, Figure 4 In the exemplified storage unit structure MUS, the end portion in the X direction of the first region 141a_1 is continuous with the side surface in the Y direction of one end portion in the X direction of the first semiconductor layer 130a. Further, the position in the X direction of the second region 141a_2 is continuous with the side surface in the Y direction of the other end portion in the X direction of the first semiconductor layer 130a. The concentration of nitrogen in the low-nitrogen-concentration region (for example, the first region 141a_1 and the second region 141a_2) is lower than the concentration of nitrogen in the high-nitrogen-concentration region (for example, the third region 141a_3).

[0061] The low-nitrogen-concentration region (for example, the first region 141a_1 and the second region 141a_2) can also include silicon oxynitride (SiON) having a lower nitrogen content than the high-nitrogen-concentration region (for example, the third region 141a_3). Further, the low-nitrogen-concentration region (for example, the first region 141a_1 and the second region 141a_2) can also include silicon oxide (SiO2).

[0062] The second insulating layer 141b has a plurality of high-nitrogen-concentration regions provided corresponding to the plurality of memory cell structures MUS arranged in the X direction, and a plurality of low-nitrogen-concentration regions provided corresponding to the plurality of inter-memory-cell structures IMUS arranged in the X direction. For example Figure 4 Among them, as the two low-nitrogen-concentration regions corresponding to the two inter-memory-cell structures IMUS adjacent in the X direction, the fourth region 141b_4 and the fifth region 141b_5 are exemplified. Further, as the high-nitrogen-concentration region provided between these low-nitrogen-concentration regions, the sixth region 141b_6 is exemplified. The width X 141b _6 in the X direction of each high-nitrogen-concentration region is smaller than the width X 130b Further, the end portion in the X direction of each low-nitrogen-concentration region opposes the side surface in the Y direction of the two second semiconductor layers 130b adjacent in the X direction. For example, Figure 4 Among the exemplified memory cell structures MUS, the end portion in the X direction of the fourth region 141b_4 is continuous with the side surface in the Y direction of one end portion in the X direction of the second semiconductor layer 130b. Further, the position in the X direction of the fifth region 141b_5 is continuous with the side surface in the Y direction of the other end portion in the X direction of the second semiconductor layer 130b. The concentration of nitrogen in the low-nitrogen-concentration region (for example, the fourth region 141b_4 and the fifth region 141b_5) is lower than the concentration of nitrogen in the high-nitrogen-concentration region (for example, the sixth region 141b_6).

[0063] The low-nitrogen-concentration region (for example, the fourth region 141b_4 and the fifth region 141b_5) can also contain silicon oxynitride (SiON) having a lower nitrogen content than the high-nitrogen-concentration region (for example, the sixth region 141b_6). Further, the low-nitrogen-concentration region (for example, the fourth region 141b_4 and the fifth region 141b_5) can also contain silicon oxide (SiO2).

[0064] In addition, the positions, ranges, and concentrations of nitrogen in the high-nitrogen-concentration regions and the low-nitrogen-concentration regions can be determined by analyzing the composition thereof using an EDS (Energy Dispersive X-ray Spectroscopy) method or the like.

[0065] The insulating layer 150 is provided at the central portion in the Y direction of the memory trench structure MT and extends in the X direction and the Z direction. For example, as shown in (b) of FIG. 14, Figure 3 The width in the Y direction of the portion included in the insulating layer 150 by the memory cell structure MUS is smaller than the width in the Y direction of the portion included in the insulating layer 150 by the inter-memory-cell structure IMUS, as shown in (b) of FIG. 14. The insulating layer 150 is, for example, an insulating layer of silicon oxide (SiO2) or the like.

[0066] Wiring layer 160 ( Figure 2 The wiring layer 160 is a plate-shaped conductive layer extending along the X and Y directions. The wiring layer 160 is, for example, a conductive layer of polysilicon (Si) implanted with impurities, serving as the source line SL. Figure 1 The source line SL can be modified to perform its function. For example, the source line SL can be part of the surface of the substrate 110. In addition, the source line SL can also contain metal layers such as titanium nitride (TiN) and tungsten (W). Furthermore, the source line SL can be connected to the lower end of the semiconductor layer 130 or to the side of the semiconductor layer 130 in the Y direction.

[0067] [Manufacturing Method]

[0068] Next, refer to Figures 5-19 The method for manufacturing the semiconductor memory device according to this embodiment will be described. Figures 5-19 (a) in the diagram is a schematic top view used to illustrate the manufacturing method. Figures 5-19 (b) in the diagram is a schematic cross-sectional view used to illustrate the manufacturing method, showing a view similar to... Figures 5-19 The cross section corresponding to line D-D′ in (a) of the diagram.

[0069] Furthermore, in the following description, the first insulating layer 141a and the second insulating layer 141b may be referred to as insulating layer 141. Additionally, the first charge accumulation layer 142a and the second charge accumulation layer 142b may be referred to as charge accumulation layer 142. Furthermore, the first block insulating layer 143a and the second insulating layer 143b may be referred to as block insulating layer 143.

[0070] like Figure 5 As shown, in this manufacturing method, a wiring layer 160 is formed above a substrate (not shown). Furthermore, multiple insulating layers 122 and sacrificial layers 120A are alternately stacked on the upper surface of the wiring layer 160. Additionally, an insulating layer 152 is formed on the upper surface of the uppermost sacrificial layer 120A. The sacrificial layer 120A is, for example, made of silicon nitride (SiN). The insulating layer 152 is, for example, made of silicon oxide (SiO2). The wiring layer 160, insulating layer 122, sacrificial layer 120A, and insulating layer 152 are formed, for example, by CVD (Chemical Vapor Deposition).

[0071] Next, as Figure 6 As shown, an opening MTa is formed in the insulating layer 122, the sacrificial layer 120A, and the insulating layer 152. The opening MTa is formed, for example, by... Figure 5The structure shown is formed by forming an insulating layer with an opening in the portion corresponding to the opening MTa on the upper surface, and then using it as a mask for RIE (Reactive Ion Etching).

[0072] The opening MTa extends along the Z direction, separating the insulating layer 122, the sacrificial layer 120A, and the insulating layer 152 in the Y direction, thus exposing the upper surface of the wiring layer 160.

[0073] Next, as Figure 7 As shown, a semiconductor layer 133 is formed on the bottom surface of the opening MTa. The semiconductor layer 133 is formed, for example, by epitaxial growth.

[0074] Next, as Figure 8 As shown, a block insulating layer 143, a charge accumulation layer 142, an insulating layer 141, and an amorphous silicon film 130A are formed on the upper surface of the insulating layer 152 and on the bottom and side surfaces of the opening MTa. This process is performed, for example, by a method such as CVD.

[0075] Next, as Figure 9 As shown, the portion of the bottom portion of the block insulating layer 143, charge accumulation layer 142, insulating layer 141, and amorphous silicon film 130A disposed at the opening MTa is removed to expose the semiconductor layer 133. This process is performed, for example, by a re-emulator (RIE).

[0076] Next, as Figure 10 As shown, an amorphous silicon film is formed on the upper surface of the semiconductor layer 133 and on the side and upper surfaces of the amorphous silicon film 130A. This process is performed, for example, by a method such as CVD. Next, heat treatment or the like is performed to improve the crystal structure of the amorphous silicon film 130A to form a semiconductor layer 130B of polycrystalline silicon (Si) or the like.

[0077] Next, as Figure 11 As shown, a carbon film 200 is formed inside the opening MTa, and then a hard mask HM, such as an oxide film, is formed on the upper surface of the carbon film 200. The opening AH is formed on the hard mask HM. The carbon film 200 is formed, for example, by spin coating of a coating-type carbon film material. The hard mask HM is formed, for example, by CVD. The opening AH is formed, for example, by photolithography and wet etching.

[0078] Next, as Figure 12 As shown, the portion of the carbon film 200 located at the position corresponding to the opening AH is removed. This process is performed, for example, by a RIE (Residual Insulation Layer). In addition, during this process, a portion of the semiconductor layer 130B, a portion of the insulating layer 141, a portion of the charge accumulation layer 142, and a portion of the bulk insulating layer 143 are also removed, exposing a portion of the insulating layer 152.

[0079] Next, as shown in Figure 13 , a portion of the semiconductor layer 130B exposed in the opening AH is removed. This process is performed, for example, by isotropic etching based on RIE or the like. By this process, the portion provided in the opening MTA in the semiconductor layer 130B is divided in the X direction, and the 1st semiconductor layer 130a and the 2nd semiconductor layer 130b arranged in the X direction are formed.

[0080] Next, as shown in Figure 14 , the exposed portion of the insulating layer 141 exposed in the opening AH and the non-exposed portion of the portion not exposed in the opening AH are oxidized. This process is performed, for example, by introducing an oxidizing agent through the opening AH and by oxidation treatment or the like. In addition, this oxidation is performed from the exposed portion of the insulating layer 141 exposed in the opening AH further to the non-exposed portion not exposed in the opening AH. The region in which oxidation is performed in this process is a low nitrogen concentration region (for example, refer to the 1st region 141a_1, the 2nd region 141a_2, the 4th region 141b_4, and the 5th region 141b_5 described in Figure 4 ). Furthermore, the region in which oxidation is not performed in this process is a high nitrogen concentration region (for example, refer to the 3rd region 141a_3 and the 6th region 141b_6 described in Figure 4 ).

[0081] Next, as shown in Figure 15 , the hard mask HM and the carbon film 200 are removed, and the insulating layer 150 is formed inside the opening MTA and buried in the opening portion. The removal of the hard mask HM is performed, for example, by wet etching or the like. The removal of the carbon film 200 is performed, for example, by ashing or the like. The formation of the insulating layer 150 is performed, for example, by CVD or the like.

[0082] Next, as shown in Figure 16 , a portion of the insulating layer 150, the 1st semiconductor layer 130a and the 2nd semiconductor layer 130b, the insulating layer 141, the charge accumulation layer 142, and the block insulating layer 143 from the upper surface of the configuration shown in Figure 15 is removed, and then the insulating layer 153 is formed on the upper surface of the configuration. This removal process is performed, for example, by RIE or the like. The formation of the insulating layer 153 is performed, for example, by CVD or the like.

[0083] Next, as shown in Figure 17 , a plurality of sacrificial layers 120A are removed via an opening not shown. This process is performed, for example, by wet etching or the like.

[0084] Next, as shown in Figure 18 , the insulating layer 135 is formed on the side surface of the semiconductor layer 133 via an opening not shown. This process is performed, for example, by oxidation treatment or the like.

[0085] Next, as shown in FIG. 1 1, the conductive layer 120 and the conductive layer 121 are formed between the insulating layers 122 arranged in the Z direction via openings not shown. This process is performed, for example, by CVD and wet etching or the like. Figure 19

[0086] Then, the upper ends of the first semiconductor layer 130a and the second semiconductor layer 130b are removed, and the fourth semiconductor layer 130d is formed in the removed portions. Then, the bit line contact BLC of tungsten (W) or the like and the bit line BL of copper (Cu) or the like are formed. Thus, a configuration as described with reference to FIG. 1 1 is formed. Figure 2

[0087] [Effects]

[0088] Figure 20 The configuration of a semiconductor storage device of a comparative example is shown in FIG. 12. The semiconductor storage device of the comparative example is provided with a memory trench configuration MT' instead of the memory trench configuration MT. The memory trench configuration MT' is provided with a plurality of memory cell configurations MUS' and a memory cell inter-configuration IMUS' arranged in the X direction. The memory cell configuration MUS' is provided with a first semiconductor layer 130a', a second semiconductor layer 130b', a gate insulating layer 140', and an insulating layer 150' instead of the first semiconductor layer 130a, the second semiconductor layer 130b, a portion of the gate insulating layer 140, and a portion of the insulating layer 150. The memory cell inter-configuration IMUS' is provided with an insulating layer 151' instead of a portion of the gate insulating layer 140 and a portion of the insulating layer 150.

[0089] The gate insulating layer 140' is provided with a first gate insulating layer 140a' and a second gate insulating layer 140b'.

[0090] Here, the first gate insulating layer 140a of the first embodiment extends in the X direction over a plurality of regions between the plurality of first semiconductor layers 130a and the first conductive layer 120a. On the other hand, the first gate insulating layer 140a' of the comparative example is provided for each of the plurality of regions between the plurality of first semiconductor layers 130a' and the first conductive layer 120a, and is separated from each other by the memory cell inter-configuration IMUS'.

[0091] Further, the second gate insulating layer 140b of the first embodiment extends in the X direction over a plurality of regions between the plurality of second semiconductor layers 130b and the second conductive layer 120b. On the other hand, the second gate insulating layer 140b' of the comparative example is provided for each of the plurality of regions between the plurality of second semiconductor layers 130b' and the second conductive layer 120b, and is separated from each other by the memory cell inter-configuration IMUS'.

[0092] ​​Further, the first gate insulating layer 140a' and the second gate insulating layer 140b' are provided instead of the first insulating layer 141a and the second insulating layer 141b, respectively. The width X 141a ' of the first insulating layer 141a' in the X direction is the same degree as the width X 130a ' of the first semiconductor layer 130a' in the X direction. The width X 141b ' of the second insulating layer 141b' in the X direction is the same degree as the width X 130b ' of the second semiconductor layer 130b' in the X direction.

[0093] The insulating layer 150' is provided to each of the plurality of memory cell structures MUS' arranged in the X direction, apart from each other by the inter-memory cell structure IMUS'.

[0094] The insulating layer 151' is provided to each of the plurality of inter-memory cell structures IMUS' arranged in the X direction, apart from each other by the memory cell structure MUS'. Further, the width Y 151 ' of the insulating layer 151' in the Y direction is larger than the width Y MUS ' of the memory cell structure MUS' in the Y direction.

[0095] In the manufacturing of the semiconductor storage device of the comparative example, for example, after the process of referring to Figure 10 , the insulating layer 150' is formed in the opening MTa. Further, on the upper surface of this structure, a hard mask HM Figure 11 in which the opening AH is formed is formed. Further, by means of RIE or the like using this hard mask HM, a through-hole is formed in the portion corresponding to the opening AH, and the semiconductor layer 130B, the insulating layer 141, the charge accumulation layer 142, the block insulating layer 143, and the insulating layer 150' in the opening MTa are divided in the X direction. Further, the insulating layer 151' is formed in the above through-hole.

[0096] According to such a structure, it is possible to form two electrically independent memory strings MS in the memory trench structure MT, and it is possible to provide a semiconductor storage device with a large storage capacity.

[0097] However, in the manufacturing of such a structure, there is a case where alignment deviation in the Y direction occurs at the patterning of the opening AH. As Figure 20 shown, in the case where alignment deviation in the Y direction occurs, for example, with respect to the width X 130a ' of the first semiconductor layer 130a' in the X direction, the width X 130bThe memory characteristics of the two memory strings MS formed on both sides of the memory trench structure MT become different, and this becomes a cause of unevenness of the memory characteristics.

[0098] Furthermore, if a margin of alignment in the Y direction of the memory trench structure MT with respect to such an opening AH is taken into consideration, it is not possible to design the separation distance of the adjacent memory trench structures MT to be short. Therefore, in a configuration like that of the comparative example, it is difficult to achieve miniaturization and high integration of the memory structure.

[0099] Therefore, in the manufacturing of the semiconductor memory device of the first embodiment, the semiconductor layer 130 is selectively divided in the process of Figure 13 In such a configuration, it is not necessary to take into consideration the margin of alignment in the Y direction of the memory trench structure MT, and therefore it is possible to design the separation distance of the adjacent memory trench structures MT in the Y direction to be small, and it is possible to achieve miniaturization of the memory cell size.

[0100] Furthermore, in the case of a configuration in which the first semiconductor layer 130a and the second semiconductor layer 130b are divided in the X direction like the present embodiment, if a gate voltage is applied to the first conductive layer 120a and the second conductive layer 120b, a high-intensity electric field is concentrated on the both end portions of the first semiconductor layer 130a and the second semiconductor layer 130b in the X direction, and there is a case in which these both end portions become so-called parasitic transistors. That is, there is a case in which the threshold voltage of the parasitic transistors corresponding to the both end portions in the X direction becomes smaller than the threshold voltage of the transistors corresponding to other portions. In such a case, the parasitic transistors corresponding to the both end portions in the X direction are turned on at a lower voltage than the transistors corresponding to other portions, and thus there is a problem in that the on characteristics corresponding to the application of the gate voltage of the memory cell MC are divided into two stages.

[0101] Therefore, in the present embodiment, as shown in Figure 4 the nitrogen concentration in the portions of the first insulating layer 141a and the second insulating layer 141b that oppose the both end portions of the first semiconductor layer 130a and the second semiconductor layer 130b in the X direction (high-nitrogen-concentration regions including the first region 141a_1, the second region 141a_2, the fourth region 141b_4, and the fifth region 141b_5) is made lower than the nitrogen concentration in the portions of the first insulating layer 141a and the second insulating layer 141b that oppose other portions of the first semiconductor layer 130a and the second semiconductor layer 130b (low-nitrogen-concentration regions including the third region 141a_3 and the sixth region 141b_6).

[0102] The electron injection efficiency of the low-nitrogen-concentration region is lower than the electron injection efficiency of the high-nitrogen-concentration region. Thus, according to the semiconductor storage device of the first embodiment, it is possible to avoid concentration of a high-intensity electric field at both end portions of the first semiconductor layer 130a and the second semiconductor layer 130b in the X direction, and to suppress the action of a parasitic transistor. Thus, it is possible to suppress 2-stage characteristics of the voltage to the memory cell MC, and to provide a semiconductor storage device that operates appropriately.

[0103] [Modified example of the first embodiment]

[0104] Figure 21 The structure of the first embodiment is modified. Figure 21 is a schematic plan view that illustrates a part of the structure of the semiconductor storage device of the present modified example.

[0105] The memory cell configuration MUS and the inter-memory-cell configuration IMUS of the present modified example are basically configured in the same manner as the first embodiment. However, the semiconductor storage device of the present modified example is provided with a first charge accumulation layer 142a" and a second charge accumulation layer 142b" instead of the first charge accumulation layer 142a and the second charge accumulation layer 142b.

[0106] The first charge accumulation layer 142a" is provided with a plurality of high-nitrogen-concentration regions that are provided in correspondence with a plurality of memory cell configurations MUS arranged in the X direction, and a plurality of low-nitrogen-concentration regions that are provided in correspondence with a plurality of inter-memory-cell configurations IMUS arranged in the X direction. For example Figure 21 In the drawing, as two low-nitrogen-concentration regions corresponding to two inter-memory-cell configurations IMUS adjacent to each other in the X direction, a seventh region 142a" 7 and an eighth region 142a" 8 are illustrated. Further, as a high-nitrogen-concentration region provided between these low-nitrogen-concentration regions, a ninth region 142a" 9 is illustrated. The width X 142a″ of each high-nitrogen-concentration region in the X direction is smaller than the width X 130a of the first semiconductor layer 130a in the X direction. Further, the end portion in the X direction of each low-nitrogen-concentration region is opposed to the side surface in the Y direction of two first semiconductor layers 130a adjacent to each other in the X direction. For example, Figure 21 In the memory cell configuration MUS illustrated in the drawing, the end portion in the X direction of the seventh region 142a" 7 is opposed to the side surface in the Y direction of one end portion in the X direction of the first semiconductor layer 130a. Further, the position in the X direction of the eighth region 142a" 8 is opposed to the side surface in the Y direction of the other end portion in the X direction of the first semiconductor layer 130a. The concentration of nitrogen in the low-nitrogen-concentration region (for example, the seventh region 142a" 7 and the eighth region 142a" 8) is lower than the concentration of nitrogen in the high-nitrogen-concentration region (for example, the ninth region 142a" 9).

[0107] The low-nitrogen-concentration regions (e.g., the 7th region 142a" 7 and the 8th region 142a" 8) can also include silicon oxynitride (SiON) having a lower nitrogen content than the high-nitrogen-concentration region (e.g., the 9th region 142a" 9). Furthermore, the low-nitrogen-concentration regions (e.g., the 7th region 142a" 7 and the 8th region 142a" 8) can also include silicon oxide (SiO2).

[0108] The 2nd charge accumulation layer 142b" has a plurality of high-nitrogen-concentration regions provided corresponding to a plurality of memory cell structures MUS arranged in the X direction, and a plurality of low-nitrogen-concentration regions provided corresponding to a plurality of inter-memory-cell structures IMUS arranged in the X direction. For example Figure 21 In the example, as two low-nitrogen-concentration regions corresponding to two inter-memory-cell structures IMUS adjacent in the X direction, the 10th region 142b" 10 and the 11th region 142b" 11 are exemplified. Furthermore, as a high-nitrogen-concentration region provided between these low-nitrogen-concentration regions, the 12th region 142b" 12 is exemplified. The width X 142b″ 12 is smaller than the width X 130b Furthermore, the end portion in the X direction of each low-nitrogen-concentration region is opposed to the side surface in the Y direction of the two 2nd semiconductor layers 130b adjacent in the X direction. For example, in the example of the memory cell structure MUS exemplified above, the end portion in the X direction of the 10th region 142b" 10 is opposed to the side surface in the Y direction of one end portion in the X direction of the 2nd semiconductor layer 130b. Furthermore, the position in the X direction of the 11th region 142b" 11 is opposed to the side surface in the Y direction of the other end portion in the X direction of the 2nd semiconductor layer 130b. Figure 21 In the memory cell structure MUS exemplified above, the end portion in the X direction of the 10th region 142b" 10 is opposed to the side surface in the Y direction of one end portion in the X direction of the 2nd semiconductor layer 130b. Furthermore, the position in the X direction of the 11th region 142b" 11 is opposed to the side surface in the Y direction of the other end portion in the X direction of the 2nd semiconductor layer 130b. The concentration of nitrogen in the low-nitrogen-concentration regions (e.g., the 10th region 142b" 10 and the 11th region 142b" 11) is lower than the concentration of nitrogen in the high-nitrogen-concentration region (e.g., the 12th region 142b" 12).

[0109] The low-nitrogen-concentration regions (e.g., the 10th region 142b" 10 and the 11th region 142b" 11) can also include silicon oxynitride (SiON) having a lower nitrogen content than the high-nitrogen-concentration region (e.g., the 12th region 142b" 12). Furthermore, the low-nitrogen-concentration regions (e.g., the 10th region 142b" 10 and the 11th region 142b" 11) can also include silicon oxide (SiO2).

[0110] [Other Embodiments]

[0111] ​The semiconductor storage device of the first embodiment has been described above. However, the above structure is merely an example, and the specific structure and the like can be appropriately adjusted.

[0112] For example, in the first embodiment and the modified example thereof, the example in which the low-nitrogen-concentration regions (the first region 141a_1, the second region 141a_2, the fourth region 141b_4, and the fifth region 141b_5) are formed by the oxidation treatment via the openings AH in the process described with reference to FIG. 7 has been described. However, the timing at which the oxidation treatment for forming the low-nitrogen-concentration regions is performed can be appropriately adjusted. For example, the process described with reference to FIG. 7 can be omitted, and the oxidation treatment for forming the low-nitrogen-concentration regions can be performed in a process later than the process described with reference to FIG. 6. Figure 4 Figure 21 For example, in the first embodiment and the modified example thereof, the example in which the low-nitrogen-concentration regions (the first region 141a_1, the second region 141a_2, the fourth region 141b_4, and the fifth region 141b_5) are formed by the oxidation treatment via the openings AH in the process described with reference to FIG. 7 has been described. However, the timing at which the oxidation treatment for forming the low-nitrogen-concentration regions is performed can be appropriately adjusted. For example, the process described with reference to FIG. 7 can be omitted, and the oxidation treatment for forming the low-nitrogen-concentration regions can be performed in a process later than the process described with reference to FIG. 6. Figure 14 For example, in the first embodiment and the modified example thereof, the example in which the low-nitrogen-concentration regions (the first region 141a_1, the second region 141a_2, the fourth region 141b_4, and the fifth region 141b_5) are formed by the oxidation treatment via the openings AH in the process described with reference to FIG. 7 has been described. However, the timing at which the oxidation treatment for forming the low-nitrogen-concentration regions is performed can be appropriately adjusted. For example, the process described with reference to FIG. 7 can be omitted, and the oxidation treatment for forming the low-nitrogen-concentration regions can be performed in a process later than the process described with reference to FIG. 6. Figure 14 For example, in the first embodiment and the modified example thereof, the example in which the low-nitrogen-concentration regions (the first region 141a_1, the second region 141a_2, the fourth region 141b_4, and the fifth region 141b_5) are formed by the oxidation treatment via the openings AH in the process described with reference to FIG. 7 has been described. However, the timing at which the oxidation treatment for forming the low-nitrogen-concentration regions is performed can be appropriately adjusted. For example, the process described with reference to FIG. 7 can be omitted, and the oxidation treatment for forming the low-nitrogen-concentration regions can be performed in a process later than the process described with reference to FIG. 6. Figure 14 For example, in the first embodiment and the modified example thereof, the example in which the low-nitrogen-concentration regions (the first region 141a_1, the second region 141a_2, the fourth region 141b_4, and the fifth region 141b_5) are formed by the oxidation treatment via the openings AH in the process described with reference to FIG. 7 has been described. However, the timing at which the oxidation treatment for forming the low-nitrogen-concentration regions is performed can be appropriately adjusted. For example, the process described with reference to FIG. 7 can be omitted, and the oxidation treatment for forming the low-nitrogen-concentration regions can be performed in a process later than the process described with reference to FIG. 6.

[0113] For example, in the first embodiment and the modified example thereof, the example in which the low-nitrogen-concentration regions (the first region 141a_1, the second region 141a_2, the fourth region 141b_4, and the fifth region 141b_5) are formed by the oxidation treatment via the openings AH in the process described with reference to FIG. 7 has been described. However, the timing at which the oxidation treatment for forming the low-nitrogen-concentration regions is performed can be appropriately adjusted. For example, the process described with reference to FIG. 7 can be omitted, and the oxidation treatment for forming the low-nitrogen-concentration regions can be performed in a process later than the process described with reference to FIG. 6. Figure 14 For example, in the first embodiment and the modified example thereof, the example in which the low-nitrogen-concentration regions (the first region 141a_1, the second region 141a_2, the fourth region 141b_4, and the fifth region 141b_5) are formed by the oxidation treatment via the openings AH in the process described with reference to FIG. 7 has been described. However, the timing at which the oxidation treatment for forming the low-nitrogen-concentration regions is performed can be appropriately adjusted. For example, the process described with reference to FIG. 7 can be omitted, and the oxidation treatment for forming the low-nitrogen-concentration regions can be performed in a process later than the process described with reference to FIG. 6. Figure 13 For example, in the first embodiment and the modified example thereof, the example in which the low-nitrogen-concentration regions (the first region 141a_1, the second region 141a_2, the fourth region 141b_4, and the fifth region 141b_5) are formed by the oxidation treatment via the openings AH in the process described with reference to FIG. 7 has been described. However, the timing at which the oxidation treatment for forming the low-nitrogen-concentration regions is performed can be appropriately adjusted. For example, the process described with reference to FIG. 7 can be omitted, and the oxidation treatment for forming the low-nitrogen-concentration regions can be performed in a process later than the process described with reference to FIG. 6.

[0114] [Others]

[0115] Several embodiments of the present application have been described above, but these embodiments are presented by way of example only, and are not intended to limit the scope of the application. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the application. These embodiments and modifications are included within the scope or spirit of the application, and are included within the scope of the application and its equivalents as recited in the claims.

[0116] Explanation of Reference Signs

[0117] ​110 …… substrate, 120 …… conductive layer, 120a …… 1st conductive layer, 120b …… 2nd conductive layer, 130 …… semiconductor layer, 130a …… 1st semiconductor layer, 130b …… 2nd semiconductor layer, 141 …… insulating layer, 141a …… 1st insulating layer, 141b …… 2nd insulating layer, 142 …… charge accumulation layer, 142a …… 1st charge accumulation layer, 142b …… 2nd charge accumulation layer, 143 …… bulk insulating layer, 150 …… insulating layer, 160 …… wiring layer.

Claims

1. A semiconductor memory device comprising: a first conductive layer and a second conductive layer arranged in a first direction; a plurality of first semiconductor layers arranged in a second direction intersecting the first direction, between the first conductive layer and the second conductive layer, opposite the first conductive layer; and a first insulating layer provided between the plurality of first semiconductor layers and the first charge accumulation layer in the first direction; the first insulating layer comprising: a first region opposite one end portion of the first semiconductor layer in the second direction in the first direction; a second region opposite the other end portion of the first semiconductor layer in the second direction in the first direction; and a third region provided between the first region and the second region in the second direction; the concentration of nitrogen in the first region and the second region being lower than the concentration of nitrogen in the third region, and an end portion of the first region in the first direction being in contact with the first semiconductor layer in the first direction.

2. The semiconductor memory device according to claim 1, comprising a substrate; the first conductive layer being arranged in a plurality of the first conductive layers in a third direction intersecting the surface of the substrate and intersecting the first direction and the second direction.

3. The semiconductor memory device according to claim 2, comprising a substrate; the first semiconductor layer extending in a third direction intersecting the surface of the substrate and intersecting the first direction and the second direction, opposite a plurality of the first conductive layers in the first direction. a first charge accumulation layer provided between the plurality of first semiconductor layers and the first conductive layer in the first direction, extending in the second direction across a plurality of regions between the plurality of first semiconductor layers and the first conductive layer; 4. The semiconductor memory device according to claim 3, the first insulating layer comprising silicon oxynitride (SiON).

5. The semiconductor memory device according to claim 4, the first charge accumulation layer comprising silicon nitride (SiN).

6. The semiconductor memory device according to any one of claims 1 to 5, comprising: a plurality of second semiconductor layers arranged in the second direction, opposite the second conductive layer between the plurality of first semiconductor layers and the second conductive layer; a second charge accumulation layer provided between the plurality of second semiconductor layers and the second conductive layer in the first direction, extending in the second direction across a plurality of regions between the plurality of second semiconductor layers and the second conductive layer; and a second insulating layer provided between the plurality of second semiconductor layers and the second charge accumulation layer in the first direction; the second insulating layer comprising: a fourth region opposite one end portion of the second semiconductor layer in the second direction in the first direction; a fifth region opposite the other end portion of the second semiconductor layer in the second direction in the first direction; and a sixth region provided between the fourth region and the fifth region in the second direction; the concentration of nitrogen in the fourth region and the fifth region being lower than the concentration of nitrogen in the sixth region.

7. The semiconductor memory device according to claim 6, comprising a substrate; ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The second conductive layers are arranged in a plurality in a third direction intersecting the surface of the substrate and intersecting the first direction and the second direction.

8. The semiconductor memory device according to claim 7, The substrate is provided. The second semiconductor layer extends in a third direction intersecting the surface of the substrate and intersecting the first direction and the second direction, and is opposed to the plurality of second conductive layers in the first direction.

9. The semiconductor memory device according to claim 8, The second insulating layer includes silicon oxynitride (SiON).

10. The semiconductor memory device according to claim 9, The second charge accumulation layer includes silicon nitride (SiN).

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