Composite memory structure

Abstract

The present invention discloses a composite memory structure, including a substrate, a flash memory, a first resistive random access memory, and a second resistive random access memory. The flash memory is located on the substrate. The flash memory includes a gate, a first doped region, and a second doped region. The gate is located on the substrate. The first doped region is located in the substrate on one side of the gate. The second doped region is located in the substrate on the other side of the gate. The first resistive random access memory is electrically connected to one of the gate, the first doped region, and the second doped region. The second resistive random access memory is electrically connected to the other of the gate, the first doped region, and the second doped region.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and more particularly to a hybrid memory structure. Background Art

[0002] Due to the problem of leakage current in a resistive random access memory (RRAM), the resistive random access memory is electrically connected to a transistor to solve the problem of leakage current. However, since the transistor occupies a large chip area, the bit density of the memory element is reduced. Summary of the Invention

[0003] The present invention provides a hybrid memory structure, which can improve the reliability and bit density of memory elements.

[0004] The present invention proposes a hybrid memory structure, including a substrate, a flash memory, a first resistive random access memory, and a second resistive random access memory. The flash memory is located on the substrate. The flash memory includes a gate, a first doped region, and a second doped region. The gate is located on the substrate. The first doped region is located in the substrate on one side of the gate. The second doped region is located in the substrate on the other side of the gate. The first resistive random access memory is electrically connected to one of the gate, the first doped region, and the second doped region. The second resistive random access memory is electrically connected to the other of the gate, the first doped region, and the second doped region.

[0005] According to an embodiment of the present invention, in the above hybrid memory structure, the flash memory may further include a charge storage layer, a first dielectric layer, and a second dielectric layer. The charge storage layer is located between the gate and the substrate. The first dielectric layer is located between the charge storage layer and the substrate. The second dielectric layer is located between the gate and the charge storage layer.

[0006] According to an embodiment of the present invention, in the above hybrid memory structure, the charge storage layer may be a floating gate or a charge trapping layer.

[0007] According to an embodiment of the present invention, in the above hybrid memory structure, the flash memory may further include a first lightly doped drain (LDD), a second lightly doped drain, and a well region. The first lightly doped drain is located in the substrate between the first doped region and the gate. The second lightly doped drain is located in the substrate between the second doped region and the gate. The well region is located in the substrate. The first doped region, the second doped region, the first lightly doped drain, and the second lightly doped drain are located in the well region.

[0008] According to an embodiment of the present invention, in the above-mentioned composite memory structure, the flash memory may further include spacer walls. The spacer walls are located on the sidewalls of the gate.

[0009] According to an embodiment of the present invention, in the above-mentioned composite memory structure, the height of the top of the first resistive random access memory may be equal to the height of the top of the second resistive random access memory.

[0010] According to an embodiment of the present invention, in the above-mentioned composite memory structure, the height of the top of the first resistive random access memory may be higher than the height of the top of the second resistive random access memory.

[0011] According to an embodiment of the present invention, in the above-mentioned composite memory structure, the height of the top of the first resistive random access memory may be lower than the height of the top of the second resistive random access memory.

[0012] According to an embodiment of the present invention, in the above-mentioned composite memory structure, the first resistive random access memory includes a first electrode, a second electrode, and a first variable resistance layer. The second electrode is located on the first electrode. The first variable resistance layer is located between the first electrode and the second electrode. The second resistive random access memory includes a third electrode, a fourth electrode, and a second variable resistance layer. The fourth electrode is located on the third electrode. The second variable resistance layer is located between the third electrode and the fourth electrode.

[0013] According to an embodiment of the present invention, in the above-mentioned composite memory structure, the first resistive random access memory may be electrically connected to the gate, and the second resistive random access memory may be electrically connected to the second doped region.

[0014] According to an embodiment of the present invention, in the above-mentioned composite memory structure, the first electrode may be electrically connected to the gate. The third electrode may be electrically connected to the second doped region.

[0015] According to an embodiment of the present invention, in the above-mentioned composite memory structure, it may further include a first wire, a second wire, a third wire, and a fourth wire. The first wire is electrically connected to the first electrode. The second wire is electrically connected to the second electrode. The third wire is electrically connected to the fourth electrode. The fourth wire is electrically connected to the first doped region.

[0016] According to an embodiment of the present invention, in the above-mentioned composite memory structure, the first resistive random access memory may be electrically connected to the gate, and the second resistive random access memory may be electrically connected to the first doped region.

[0017] According to an embodiment of the present invention, in the above-mentioned composite memory structure, the first electrode may be electrically connected to the gate. The third electrode may be electrically connected to the first doped region.

[0018] According to an embodiment of the present invention, in the above-mentioned composite memory structure, a first wire, a second wire, a third wire, and a fourth wire may further be included. The first wire is electrically connected to the first electrode. The second wire is electrically connected to the second electrode. The third wire is electrically connected to the fourth electrode. The fourth wire is electrically connected to the second doped region.

[0019] According to an embodiment of the present invention, in the above-mentioned composite memory structure, the first resistive random access memory may be electrically connected to the first doped region, and the second resistive random access memory may be electrically connected to the second doped region.

[0020] According to an embodiment of the present invention, in the above-mentioned composite memory structure, the first electrode may be electrically connected to the first doped region. The third electrode may be electrically connected to the second doped region.

[0021] According to an embodiment of the present invention, in the above-mentioned composite memory structure, a first wire, a second wire, and a third wire may further be included. The first wire is electrically connected to the second electrode. The second wire is electrically connected to the fourth electrode. The third wire is electrically connected to the gate.

[0022] According to an embodiment of the present invention, in the above-mentioned composite memory structure, the materials of the first electrode, the second electrode, the third electrode, and the fourth electrode are, for example, titanium (Ti), tantalum (Ta), platinum (Pt), iridium (Ir), ruthenium (Ru), tungsten (W), aluminum (Al), zirconium (Zr), hafnium (Hf), nickel (Ni), copper (Cu), cobalt (Co), iron (Fe), gadolinium (Gd), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), titanium tungsten (TiW) alloy, or a combination thereof.

[0023] According to an embodiment of the present invention, in the above-mentioned composite memory structure, the materials of the first variable resistance layer and the second variable resistance layer are, for example, hafnium oxide (HfO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), magnesium oxide (MgO), nickel oxide (NiO), niobium oxide (Nb2O5), aluminum oxide (Al2O3), vanadium oxide (V2O5), tungsten oxide (WO3), zinc oxide (ZnO), cobalt oxide (CoO), or a combination thereof.

[0024] Based on the above, in the composite memory structure proposed by the present invention, since the first resistive random access memory and the second resistive random access memory are respectively electrically connected to the flash memory, the problem of leakage current generated in the first resistive random access memory and the second resistive random access memory can be prevented, thereby improving the reliability of the resistive random access memory. In addition, since the flash memory is electrically connected to the first resistive random access memory and the second resistive random access memory, the flash memory can be prevented from being affected by factors such as coupling or disturbance, thereby improving the reliability of the flash memory. In addition, since a single memory cell of the composite memory structure includes a flash memory, a first resistive random access memory, and a second resistive random access memory, the bit density of the memory element can be increased, and the electrical performance of a single level cell (SLC) can be maintained. On the other hand, the manufacturing process of the composite memory structure proposed by the present invention is compatible with the manufacturing process of complementary metal-oxide-semiconductor (CMOS) elements.

[0025] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows. Brief Description of the Drawings

[0026] Figure 1 A cross-sectional view of a composite memory structure according to an embodiment of the present invention;

[0027] Figure 2 A cross-sectional view of a composite memory structure according to another embodiment of the present invention;

[0028] Figure 3 A cross-sectional view of a composite memory structure according to another embodiment of the present invention;

[0029] Figure 4 A cross-sectional view of a composite memory structure according to another embodiment of the present invention;

[0030] Figure 5 A cross-sectional view of a composite memory structure according to another embodiment of the present invention.

[0031] Symbol Description

[0032] 10, 20, 30: Composite memory structure

[0033] 100: Substrate

[0034] 102: Flash memory

[0035] 104, 106: Resistive Random Access Memory

[0036] 108: Gate

[0037] 110, 112: Doped Region

[0038] 114: Charge Storage Layer

[0039] 116, 118: Dielectric Layer

[0040] 120, 122: Lightly Doped Drain

[0041] 124: Well Region

[0042] 126a, 126b: Spacer Wall

[0043] 128, 130, 134, 136: Electrode

[0044] 132, 138: Variable Resistance Layer

[0045] 140, 144, 148, 152: Wire

[0046] 142, 146, 150: Via

[0047] 154, 156, 158: Contact Window

[0048] 160: Dielectric Structure Detailed Embodiment

[0049] Figure 1 It is a cross-sectional view of a composite memory structure according to an embodiment of the present invention. Figure 2 It is a cross-sectional view of a composite memory structure according to another embodiment of the present invention. Figure 3 It is a cross-sectional view of a composite memory structure according to another embodiment of the present invention.

[0050] Please refer to Figure 1 , the composite memory structure 10 includes a substrate 100, a flash memory 102, a resistive random access memory 104, and a resistive random access memory 106. The flash memory 102 is located on the substrate 100. The substrate 100 can be a semiconductor substrate, such as a silicon substrate. In addition, in a circuit, the flash memory 102, the resistive random access memory 104, and the resistive random access memory 106 can be three resistors connected in series. In some embodiments, the flash memory 102, the resistive random access memory 104, and the resistive random access memory 106 can have the same resistance value.

[0051] The flash memory 102 includes a gate 108, a doped region 110, and a doped region 112. The gate 108 is located on the substrate 100. The material of the gate 108 is, for example, doped polysilicon. The doped region 110 is located in the substrate 100 on one side of the gate 108. The doped region 112 is located in the substrate 100 on the other side of the gate 108. The doped region 110 and the doped region 112 can serve as a source or a drain respectively. In this embodiment, the doped region 110 is taken as an example of a source, and the doped region 112 is taken as an example of a drain, but the present invention is not limited thereto.

[0052] In addition, the flash memory 102 may further include at least one of a charge storage layer 114, a dielectric layer 116, a dielectric layer 118, a lightly doped drain 120, a lightly doped drain 122, a well region 124, a spacer 126a, and a spacer 126b. The charge storage layer 114 is located between the gate 108 and the substrate 100. The charge storage layer 114 can be a floating gate or a charge trapping layer. The material of the floating gate is, for example, doped polysilicon. The material of the charge trapping layer is, for example, silicon nitride. The dielectric layer 116 is located between the charge storage layer 114 and the substrate 100. The material of the dielectric layer 116 is, for example, silicon oxide. The dielectric layer 118 is located between the gate 108 and the charge storage layer 114. The material of the dielectric layer 118 is, for example, silicon oxide.

[0053] The lightly doped drain 120 is located in the substrate 100 between the doped region 110 and the gate 108. The lightly doped drain 122 is located in the substrate 100 between the doped region 112 and the gate 108. The well region 124 is located in the substrate 100. The doped region 110, the doped region 112, the lightly doped drain 120, and the lightly doped drain 122 are located in the well region 124. The doped region 110, the doped region 112, the lightly doped drain 120, and the lightly doped drain 122 can be of a first conductivity type, and the well region 124 can be of a second conductivity type. The first conductivity type and the second conductivity type are different conductivity types. That is, the first conductivity type and the second conductivity type can be one of the N-type conductivity type and the P-type conductivity type and the other respectively. The spacers 126a and 126b are located on the sidewalls of the gate 108. The lightly doped drain 120 and the lightly doped drain 122 can be located below the spacers 126a and 126b respectively. The spacers 126a and 126b can be a single-layer structure or a multi-layer structure. The material of the spacers 126a and 126b is, for example, silicon oxide, silicon nitride, or a combination thereof.

[0054] The resistive random access memory 104 is electrically connected to one of the gate 108, the doped region 110, and the doped region 112. In this embodiment, the resistive random access memory 104 can be electrically connected to the gate 108 of the flash memory 102, but the present invention is not limited thereto.

[0055] The resistive random access memory 104 includes an electrode 128, an electrode 130, and a variable resistance layer 132. The electrode 128 can be electrically connected to the gate 108. The electrode 130 is located on the electrode 128. The width of the electrode 128 can be greater than the width of the electrode 130 to facilitate the subsequent interconnect process, but the present invention is not limited thereto. The materials of the electrode 128 and the electrode 130 can be metals or metal nitrides, such as titanium, tantalum, platinum, iridium, ruthenium, tungsten, aluminum, zirconium, hafnium, nickel, copper, cobalt, iron, gadolinium, manganese, titanium nitride, tantalum nitride, titanium aluminum nitride, titanium tungsten alloy, or a combination thereof. The variable resistance layer 132 is located between the electrode 128 and the electrode 130. The material of the variable resistance layer 132 can be a metal oxide, such as a transition metal oxide. The material of the variable resistance layer 132 is, for example, hafnium oxide, tantalum oxide, titanium oxide, magnesium oxide, nickel oxide, niobium oxide, aluminum oxide, vanadium oxide, tungsten oxide, zinc oxide, cobalt oxide, or a combination thereof.

[0056] The resistive random access memory 106 is electrically connected to another one of the gate 108, the doped region 110, and the doped region 112. In this embodiment, the resistive random access memory 106 can be electrically connected to the doped region 112 of the flash memory 102, but the present invention is not limited thereto.

[0057] The resistive random access memory 106 includes an electrode 134, an electrode 136, and a variable resistance layer 138. The electrode 134 can be electrically connected to the doped region 112. The electrode 136 is located on the electrode 134. The materials of the electrode 134 and the electrode 136 can be metals or metal nitrides, such as titanium, tantalum, platinum, iridium, ruthenium, tungsten, aluminum, zirconium, hafnium, nickel, copper, cobalt, iron, gadolinium, manganese, titanium nitride, tantalum nitride, titanium aluminum nitride, titanium tungsten alloy, or a combination thereof. The variable resistance layer 138 is located between the electrode 134 and the electrode 136. The material of the variable resistance layer 138 can be a metal oxide, such as a transition metal oxide. The material of the variable resistance layer 138 is, for example, hafnium oxide, tantalum oxide, titanium oxide, magnesium oxide, nickel oxide, niobium oxide, aluminum oxide, vanadium oxide, tungsten oxide, zinc oxide, cobalt oxide, or a combination thereof.

[0058] In addition, the composite memory structure 10 may further include at least one of a wire 140, a via 142, a wire 144, a via 146, a wire 148, a via 150, a wire 152, a contact 154, a contact 156, and a contact 158. The wire 140 is electrically connected to the electrode 128. The via 142 is electrically connected between the wire 140 and the electrode 128, whereby the wire 140 can be electrically connected to the electrode 128. The wire 144 is electrically connected to the electrode 130. The via 146 is electrically connected between the wire 144 and the electrode 130, whereby the wire 144 can be electrically connected to the electrode 130. The wire 148 is electrically connected to the electrode 136. The via 150 is electrically connected between the wire 148 and the electrode 136, whereby the wire 148 can be electrically connected to the electrode 136. The wire 152 is electrically connected to the doped region 110. The contact 154 is electrically connected between the wire 152 and the doped region 110, whereby the wire 152 can be electrically connected to the doped region 110. The contact 156 is electrically connected between the electrode 128 and the gate 108, whereby the electrode 128 can be electrically connected to the gate 108. The contact 158 is electrically connected between the electrode 134 and the doped region 112, whereby the electrode 134 can be electrically connected to the doped region 112. The materials of the wire 140, the wire 144, the wire 148, and the wire 152 are, for example, metals such as aluminum. The materials of the via 142, the via 146, the via 150, the contact 154, the contact 156, and the contact 158 are, for example, metals such as tungsten.

[0059] However, Figure 1 the interconnection structures in (such as the via 142, the via 146, the via 150, the contact 154, the contact 156, and the contact 158) are only for illustrative purposes, but the present invention is not limited thereto. Those of ordinary skill in the art can adjust the interconnection structures according to product requirements, such as adding additional wires and vias.

[0060] In this embodiment, the resistive random access memory 104 can be operated through the wire 140 and the wire 144. For example, by setting the voltages of the wire 140 and the wire 144, a filament can be formed in the variable resistance layer 132 to change the resistance value of the variable resistance layer 132. In addition, the resistive random access memory 106 can be operated through the wire 148 and the well region 124. For example, by setting the voltages of the wire 148 and the well region 124, a filament can be formed in the variable resistance layer 138 to change the resistance value of the variable resistance layer 138.

[0061] In addition, the composite memory structure 10 may further include a dielectric structure 160. In the composite memory structure 10, the above-mentioned components located above the substrate 100 may be located in the dielectric structure 160. The dielectric structure 160 may be a multi-layer structure. The material of the dielectric structure 160 is, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0062] In this embodiment, the height of the top of the resistive random access memory 104 may be equal to the height of the top of the resistive random access memory 106. Thus, the resistive random access memory 104 and the resistive random access memory 106 may be formed simultaneously by the same manufacturing process, but the present invention is not limited thereto. In other embodiments, the height of the top of the resistive random access memory 104 may be higher than the height of the top of the resistive random access memory 106 ( Figure 2 ), or the height of the top of the resistive random access memory 104 may be lower than the height of the top of the resistive random access memory 106 ( Figure 3 ).

[0063] Based on the above embodiments, in the composite memory structure 10, since the resistive random access memory 104 and the resistive random access memory 106 are respectively electrically connected to the flash memory 102, the problem of leakage current generated by the resistive random access memory 104 and the resistive random access memory 106 can be prevented, and thus the reliability of the resistive random access memory 104 and the resistive random access memory 106 can be improved. In addition, since the flash memory 102 is electrically connected to the resistive random access memory 104 and the resistive random access memory 106, the influence of factors such as coupling or interference on the flash memory 102 can be prevented, and thus the reliability of the flash memory 102 can be improved. In addition, since a single memory cell of the composite memory structure 10 includes the flash memory 102, the resistive random access memory 104, and the resistive random access memory 106, the bit density of the memory element can be increased (at least having the bit density of a triple level cell (TLC)), and the electrical performance of a single level cell (SLC) can be maintained. On the other hand, the manufacturing process of the composite memory structure 10 can be compatible with the manufacturing process of complementary metal oxide semiconductor (CMOS) elements.

[0064] Figure 4 A cross-sectional view of a composite memory structure according to another embodiment of the present invention.

[0065] Please refer to Figure 1 and Figure 4 . Figure 4 The differences between the composite memory structure 20 and Figure 1 the composite memory structure 10 are as follows. Please refer to Figure 4, in the composite memory structure 20, the resistive random access memory 106 can be electrically connected to the doped region 110, and the wire 152 can be electrically connected to the doped region 112. For example, in the composite memory structure 20, the electrode 134 of the resistive random access memory 106 can be electrically connected to the doped region 110 through the contact window 158, and the wire 152 can be electrically connected to the doped region 112 through the contact window 154. In the composite memory structure 20, although the height of the top of the resistive random access memory 104 is taken as an example to be equal to the height of the top of the resistive random access memory 106, the present invention is not limited thereto. In other embodiments, the height of the top of the resistive random access memory 104 can also be higher or lower than the height of the top of the resistive random access memory 106. In addition, in Figure 1 the composite memory structure 10 of Figure 4 and the composite memory structure 20 of

[0066] Based on the above embodiments, it can be seen that in the composite memory structure 20, since the resistive random access memory 104 and the resistive random access memory 106 are respectively electrically connected to the flash memory 102, the reliability of the resistive random access memory 104, the resistive random access memory 106 and the flash memory 102 can be improved, the bit density of the memory elements can be increased, and the electrical performance of the single-level storage unit can be maintained. On the other hand, the manufacturing process of the composite memory structure 20 can be compatible with the manufacturing process of complementary metal oxide semiconductor elements.

[0067] Figure 5 is a cross-sectional view of a composite memory structure according to another embodiment of the present invention.

[0068] Please refer to Figure 1 and Figure 5 , Figure 5 the differences between the composite memory structure 30 of Figure 1 and the composite memory structure 10 of Figure 5 are as follows. Please refer to Figure 5 , in the composite memory structure 30, the resistive random access memory 104 can be electrically connected to the doped region 110, and the wire 152 can be electrically connected to the gate 108. For example, in the composite memory structure 30, the electrode 128 of the resistive random access memory 104 can be electrically connected to the doped region 110 through the contact window 156, and the wire 152 can be electrically connected to the gate 108 through the contact window 154. In addition, in the composite memory structure 30, since the resistive random access memory 104 can be operated through the wire 144 and the well region 124, the composite memory structure 30 may not include Figure 1The wire 140 and the via 142 in it. Additionally, in the resistive random access memory 104 of the composite memory structure 30, the width of the electrode 128 may be equal to the width of the electrode 130, but the present invention is not limited thereto. In the composite memory structure 30, although the height of the top of the resistive random access memory 104 is taken as an example to be equal to the height of the top of the resistive random access memory 106, the present invention is not limited thereto. In other embodiments, the height of the top of the resistive random access memory 104 may also be higher or lower than the height of the top of the resistive random access memory 106. On the other hand, in Figure 1 the composite memory structure 10 of Figure 5 and the composite memory structure 30, the same or similar components are denoted by the same reference numerals, and their descriptions are omitted.

[0069] Based on the above embodiments, it can be seen that in the composite memory structure 30, since the resistive random access memory 104 and the resistive random access memory 106 are respectively electrically connected to the flash memory 102, the reliability of the resistive random access memory 104, the resistive random access memory 106 and the flash memory 102 can be improved, the bit density of the memory elements can be increased, and the electrical performance of the single-level storage cells can be maintained. On the other hand, the manufacturing process of the composite memory structure 30 can be compatible with the manufacturing process of complementary metal oxide semiconductor devices.

[0070] Although the present invention is disclosed in combination with the above embodiments, it is not intended to limit the present invention. Any person having ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A composite memory structure, characterized in that, Comprising: A substrate; A flash memory, located on the substrate, and comprising: A gate, located on the substrate; A first doped region, located in the substrate on one side of the gate; and A second doped region, located in the substrate on the other side of the gate; A first resistive random access memory, electrically connected to the gate; and A second resistive random access memory, electrically connected to one of the first doped region and the second doped region.

2. The composite memory structure according to claim 1, wherein the flash memory further comprises: A charge storage layer, located between the gate and the substrate; A first dielectric layer, located between the charge storage layer and the substrate; And A second dielectric layer, located between the gate and the charge storage layer.

3. The composite memory structure according to claim 1, wherein the charge storage layer comprises a floating gate or a charge trapping layer.

4. The composite memory structure according to claim 1, wherein the flash memory further comprises: A first lightly doped drain, located in the substrate between the first doped region and the gate; A second lightly doped drain, located in the substrate between the second doped region and the gate; And A well region, located in the substrate, wherein the first doped region, the second doped region, the first lightly doped drain and the second lightly doped drain are located in the well region.

5. The composite memory structure according to claim 1, wherein the flash memory further comprises: Spacer walls, located on the sidewalls of the gate.

6. The composite memory structure according to claim 1, wherein the height of the top of the first resistive random access memory is equal to the height of the top of the second resistive random access memory.

7. The composite memory structure according to claim 1, wherein the height of the top of the first resistive random access memory is higher than the height of the top of the second resistive random access memory.

8. The composite memory structure according to claim 1, wherein the height of the top of the first resistive random access memory is lower than the height of the top of the second resistive random access memory.

9. The composite memory structure according to claim 1, wherein The first resistive random access memory comprises: A first electrode; A second electrode, located on the first electrode; and A first variable resistance layer, located between the first electrode and the second electrode, and the second resistive random access memory comprises: A third electrode; A fourth electrode, located on the third electrode; and A second variable resistance layer, located between the third electrode and the fourth electrode.

10. The composite memory structure according to claim 9, wherein the second resistive random access memory is electrically connected to the second doped region.

11. The composite memory structure according to claim 10, wherein the first electrode is electrically connected to the gate, and the third electrode is electrically connected to the second doped region.

12. The composite memory structure according to claim 11, further comprising: A first wire, electrically connected to the first electrode; A second wire, electrically connected to the second electrode; A third wire, electrically connected to the fourth electrode; and a fourth wire, electrically connected to the first doped region.

13. The composite memory structure according to claim 9, wherein the second resistive random access memory is electrically connected to the first doped region.

14. The composite memory structure according to claim 13, wherein the first electrode is electrically connected to the gate, and the third electrode is electrically connected to the first doped region.

15. The composite memory structure according to claim 14, further comprising: a first wire, electrically connected to the first electrode; a second wire, electrically connected to the second electrode; a third wire, electrically connected to the fourth electrode; and a fourth wire, electrically connected to the second doped region.

16. The composite memory structure according to claim 9, wherein the materials of the first electrode, the second electrode, the third electrode and the fourth electrode include titanium, tantalum, platinum, iridium, ruthenium, tungsten, aluminum, zirconium, hafnium, nickel, copper, cobalt, iron, gadolinium, manganese, titanium nitride, tantalum nitride, titanium aluminum nitride, titanium tungsten alloy or a combination thereof.

17. The composite memory structure according to claim 9, wherein the materials of the first variable resistance layer and the second variable resistance layer include hafnium oxide, tantalum oxide, titanium oxide, magnesium oxide, nickel oxide, niobium oxide, aluminum oxide, vanadium oxide, tungsten oxide, zinc oxide, cobalt oxide or a combination thereof.

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