Power semiconductor modules

Abstract

The present invention provides a power semiconductor module having multiple semiconductor chips arranged side by side on an insulating substrate, enabling high-density mounting of the semiconductor chips, with minimal variation in operating characteristics between the semiconductor chips and high reliability. The power semiconductor module comprises: an insulating substrate; a first conductive pattern arranged on the insulating substrate; multiple power semiconductor chips arranged on the first conductive pattern; a first bridge-shaped wiring directly connecting the gate electrodes of the multiple power semiconductor chips; and a second bridge-shaped wiring directly connecting the source electrodes of the multiple power semiconductor chips, the first wiring being arranged along the second wiring so that the angle formed with the second wiring is within 30 degrees.

Description

Technical Field

[0001] The present invention relates to the structure of a power semiconductor module, and more particularly to an effective technique applicable to a SiC power semiconductor module using a SiC substrate. Background Art

[0002] Power converters are used in power control and motor control for industrial equipment, electric railway vehicles, hybrid vehicles, electric vehicles, etc. They consist of power semiconductor modules, electrical components such as capacitors, wiring connecting them, and heat sinks that dissipate heat generated by power loss in the electrical components.

[0003] There is a continuous demand for reducing the size and weight of power converters. For example, in electric vehicles, the space gained by miniaturizing the power converter allows for the installation of new electrical components such as batteries, thereby increasing added value such as driving range, or further expanding the passenger space to enhance passenger comfort. Therefore, the power semiconductor modules that make up the power converter are required to have both a higher rated current and a smaller size. Similarly, the heat sink also needs to be smaller.

[0004] One approach to addressing the need for miniaturization of these key electrical components is the use of compound semiconductor chips made of SiC (silicon carbide) and GaN (gallium nitride) in power semiconductor modules. Compared to conventional silicon (silicon) semiconductor chips, compound semiconductor chips offer advantages such as high switching speeds and a higher upper operating temperature limit. High-speed operation reduces switching losses, and the ability to operate at high temperatures minimizes heat dissipation. Consequently, the heat sink can be designed to be smaller.

[0005] On the other hand, these compound semiconductor chips have lower chip yields compared to silicon semiconductor chips due to substrate crystal defects and manufacturing process issues. Therefore, chip dimensions are reduced to improve yield. Therefore, to construct a power semiconductor module that meets the specified rated current, multiple compound semiconductor chips must be connected in parallel and mounted on an insulating substrate within the module.

[0006] As a background technology in this technical field, there is a technology such as Patent Document 1. Patent Document 1 discloses a structure in which a plurality of transistor elements 5 and diode elements 31 are arranged in parallel on an insulating substrate 2 ( Figure 5), on the surface of the insulating substrate 2, in addition to the wiring pattern 3B connecting the collector electrodes (or drain electrodes) of multiple transistor elements 5 and the cathode electrodes of the diode elements 31, there are also provided a wiring pattern 3A connecting the emitter electrodes (or source electrodes) of each transistor element 5 and the anode electrodes of the diode elements 31 via the connection terminal 36, a wiring pattern 3C connecting the gate electrodes of each transistor element 5, and a wiring pattern 3D for source sensing wiring paired with the gate electrode wiring.

[0007] Patent Document 2 discloses that "as a wiring structure for operating a plurality of segments 1 in parallel, a bridge-shaped connection wiring 7 using a wire (made of aluminum) is used to connect the gate electrode pads of the plurality of segments 1, and a structure is formed by connecting the gate electrode pads of three segments 1 to the gate electrode terminal 43" ( Figure 1 ), by connecting the gate electrode pads of multiple segments 1 together with the gate electrode terminal 43, the area required for the gate electrode terminal 43 is reduced.

[0008] Prior art literature

[0009] Patent Literature

[0010] Patent Document 1: Japanese Patent Application Laid-Open No. 2015-142059

[0011] Patent Document 2: Japanese Patent Application Laid-Open No. 2004-289103 Summary of the Invention

[0012] Problems to be solved by the invention

[0013] Compound semiconductor chips, which are being introduced into power semiconductor modules, have become smaller in size compared to existing Si chips in order to improve the yield. Therefore, the first issue is to be able to mount more power semiconductor chips on a power semiconductor chip mounting substrate compared to the existing technology.

[0014] In order to miniaturize a power semiconductor module or increase the number of power semiconductor chips mounted inside, it is effective to connect the gate electrodes of multiple power semiconductor chips mounted on a power semiconductor chip mounting substrate with bridge-shaped wiring, as described in the above-mentioned patent document 2.

[0015] On the other hand, to maximize the performance of the power semiconductor chip, the gate drive voltage observed at the gate drive terminal of the power semiconductor module must be made to follow the gate drive voltage waveform of the power semiconductor chip mounted in the power semiconductor module without any difference.

[0016] If such tracking is possible, the noise voltage generated by switching can be suppressed within the range of the gate rated voltage of the power semiconductor chip, and the gate drive waveform can be set to a high speed or as high a voltage as possible, thereby maximizing the flexibility of the performance of the power semiconductor chip.

[0017] In the configuration of Patent Document 2, noise voltage generated during switching causes a difference between the gate drive voltage observed at the gate drive terminal of the power semiconductor module and the gate drive voltage waveform of the power semiconductor chip mounted on the substrate within the module.

[0018] Compound semiconductor chips have the advantages of lower equivalent resistance when on and lower loss during switching compared to existing Si chips. However, in order to realize this advantage in a power semiconductor module, appropriate gate drive is required. Compared with the existing technology, reducing the difference between the gate drive voltage observed at the gate drive terminal of the power semiconductor module and the gate drive voltage waveform of the power semiconductor chip mounted on the power semiconductor module becomes the second issue.

[0019] The structure of the above-mentioned patent document 1 ( Figure 5 ) is a structure in which the proportion of the area occupied by semiconductor elements such as transistor element 5 and diode element 31 on insulating substrate 2 is less than 50%, resulting in low surface mounting efficiency of the semiconductor elements. As described above, in order to form a compact power semiconductor module that meets the predetermined rated current, it is necessary to improve surface mounting efficiency. For example, it is desirable to reduce the pattern area of ​​wiring pattern 3A, wiring pattern 3C, and wiring pattern 3D.

[0020] In addition, in the above-mentioned patent document 2 ( Figure 1 ) structure, the controllability of the gate drive voltage becomes an issue. In Patent Document 2, since the source electrode terminal 41, through which a large source current flows, also serves as an input terminal for a control reference signal for a gate control signal, during switching, a noise voltage is superimposed on the gate drive voltage between the gate electrode terminal 43 and the source electrode terminal 41 due to the impedance of the path through which the main current flows. The impedance that causes the noise voltage is generated by the wiring pattern connecting the wiring (conductor) 6 and the source electrode terminal 41 in a bridge shape.

[0021] The voltage between the gate electrode terminal 43 and the source electrode terminal 41 can be measured as the terminal voltage of the power semiconductor module, but has a transient response waveform different from the gate drive voltage between the gate electrode and the source electrode of the power semiconductor chip inside the power semiconductor module.

[0022] That is, there is a difference between the gate drive voltage clearly defined at the terminal of the power semiconductor module and the gate drive voltage of the power semiconductor chip inside the power semiconductor module. Therefore, it can be said that the gate drive voltage of the power semiconductor module is poorly controllable, and it is difficult to drive the power semiconductor chip with maximum performance within the rated range of voltage and current.

[0023] Therefore, an object of the present invention is to provide a power semiconductor module having a plurality of semiconductor chips arranged in parallel on an insulating substrate, which can achieve high-density mounting of the semiconductor chips, has minimal variation in operating characteristics between the semiconductor chips, and has high reliability.

[0024] Means for solving problems

[0025] In order to solve the above-mentioned problems, the present invention is characterized in that it comprises: an insulating substrate; a first conductive pattern, which is arranged on the insulating substrate; a plurality of power semiconductor chips, which are arranged on the first conductive pattern; a first wiring in the shape of a bridge, which directly connects the gate electrodes of the plurality of power semiconductor chips to each other; a second wiring in the shape of a bridge, which directly connects the source electrodes of the plurality of power semiconductor chips to each other; a gate control terminal, which is electrically insulated from the first conductive pattern and is arranged on the shell; and a source sense control terminal, which is separated from the first conductive pattern and is arranged on the shell, and the first wiring is arranged along the second wiring so that the angle formed with the second wiring is within 30 degrees, and is not connected to the gate control terminal via other conductive patterns on the insulating substrate, and the second wiring is not connected to the source sense control terminal via other conductive patterns on the insulating substrate.

[0026] Effects of the Invention

[0027] According to the present invention, in a power semiconductor module in which a plurality of semiconductor chips are arranged in parallel on an insulating substrate, high-density mounting of the semiconductor chips is achieved, and a highly reliable power semiconductor module with minimal variation in operating characteristics between the semiconductor chips is achieved.

[0028] This makes it possible to simultaneously achieve miniaturization and improved reliability of the power converter.

[0029] Other problems, structures, and effects than those described above will become clear from the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a diagram showing the internal structure of a power semiconductor module according to the first embodiment of the present invention.

[0031] Figure 2 This is a diagram showing the internal structure of a conventional power semiconductor module.

[0032] Figure 3 yes Figure 1 The equivalent circuit diagram of the power semiconductor module is shown.

[0033] Figure 4 This is a schematic diagram of a calculation circuit used to verify the effects of the present invention.

[0034] Figure 5 This is a diagram showing an example of the effect of the present invention.

[0035] Figure 6 This is an equivalent circuit diagram of a conventional power semiconductor module.

[0036] Figure 7 This is an equivalent circuit diagram of a conventional power semiconductor module.

[0037] Figure 8 This is a diagram showing an example of the effect of the present invention.

[0038] Figure 9 It is a diagram showing the internal structure of a power semiconductor module according to a second embodiment of the present invention.

[0039] Figure 10 This is a diagram showing the internal structure of a power semiconductor module according to a third embodiment of the present invention. DETAILED DESCRIPTION

[0040] Hereinafter, embodiments of the present invention will be described using the accompanying drawings. In each of the drawings, the same components are denoted by the same reference numerals, and detailed descriptions of the duplicated components will be omitted.

[0041] Example 1

[0042] Reference Figures 1 to 8 , a power semiconductor module according to a first embodiment of the present invention is described.

[0043] In this embodiment, examples are used to illustrate that the present invention can simultaneously achieve the following functions: 1) It can improve the mounting efficiency of multiple power semiconductor chips in a power semiconductor chip mounting substrate (main substrate) built into a power semiconductor module; 2) It can improve gate controllability by reducing the noise voltage overlapping with the voltage Vgs between the gate control terminal and the source control terminal of the power semiconductor module during switching.

[0044] By making the transient response waveform of the observable voltage Vgs between the gate control terminal and the source control terminal close to the transient response waveform of the voltage Vgschip applied between the gate electrode and the source electrode of the power semiconductor chip mounted in the power semiconductor module, it is possible to grasp the voltage trend of Vgschip during switching and identify the operating margin for its rated voltage and the operating margin for malfunction.

[0045] As a result, the main voltage and the ratio of the main voltage's temporal change during switching (dv / dt and di / dt) can be set as high as possible without exceeding the rating or causing malfunction of the power semiconductor module.

[0046] For example, when a noise voltage is superimposed on Vgs, the margin to the rated voltage is predicted to be smaller than that of the actual Vgschip transient waveform, and dv / dt and di / dt must be set to smaller values, resulting in increased switching loss.

[0047] First, the configuration of multiple power semiconductor chips mounted on a power semiconductor chip mounting substrate (main substrate) is described. When configuring the power semiconductor chips on an insulating substrate (on a chip mounting substrate), it is necessary to ensure the insulation distance between the chips and form the gate control wiring of the switching element chip (here, the MOSFET chip is used as an example). Figure 5 In the embodiment, an insulating substrate (chip mounting substrate) 2 is divided into regions, and a wiring pattern 3C is provided as a gate control wiring pattern, and a wiring pattern 3D is provided as a source control wiring pattern.

[0048] Figure 1 The internal structure of the power semiconductor module of this embodiment is shown. (a) is a plan view, and (b) is a cross-sectional view taken along line AA' of (a). Figure 1 This shows the internal structure of a 2-in-1 module equipped with MOSFET-type power semiconductor chips. A power semiconductor chip mounting substrate 100 is placed on a baseplate 300 via a solder joint layer 9. Power semiconductor chip mounting substrate 100 carries both the upper and lower arm power semiconductor chips of the 2-in-1 module.

[0049] The drain 1 terminal 51, which serves as the high potential terminal (P terminal) of the 2in1 module, is connected to the drain 1 power supply point 51 of the power semiconductor chip mounting substrate 100, the drain 2 terminal 64, which serves as the intermediate potential terminal (AC terminal), is connected to the drain 2 power supply point 64 of the power semiconductor chip mounting substrate 100, and the source 2 terminal 63 (63A, 63B) which serves as the low potential terminal (N terminal) is connected to the source 2 power supply point 63 (63A, 63B) of the power semiconductor chip mounting substrate 100.

[0050] A gate 1 control terminal 91, which controls the gate of the upper arm of the power semiconductor module, is connected to the gate electrode of a power semiconductor chip 13 mounted on a power semiconductor chip mounting substrate 100 via a bonding wire 31. A source sense 1 control terminal 92 of the upper arm is connected to the source electrode of the power semiconductor chip 13 via a bonding wire 32.

[0051] Similarly, the gate 2 control terminal 93 of the lower arm is connected to the gate electrode of the power semiconductor chip 23 mounted on the power semiconductor chip mounting substrate 100 via a bonding wire 41. Furthermore, the source sense 2 control terminal 94 of the lower arm is connected to the source electrode of the power semiconductor chip 23 via a bonding wire 42.

[0052] Drain sense 1 control terminal 52 for observing the drain voltages of the upper and lower arms is connected to drain sense 1 power supply point 52, and drain sense 2 control terminal 62 is connected to drain sense 2 power supply point 62. As described above, the terminals of the power semiconductor module are electrically connected to the terminals of the power semiconductor chip mounting substrate 100.

[0053] In addition, Figure 1 Although the drain 1 terminal, drain sense 1 control terminal, drain 2 terminal, drain sense 2 control terminal, and source 2 terminal are not shown in the figure, these terminals are conductive terminals electrically connected from the power supply point of the power semiconductor chip mounting substrate 100, and of course have sufficient voltage resistance and current resistance for the voltage applied between the terminals and the current flowing.

[0054] In the power semiconductor chip mounting substrate 100, a drain 1 conductive pattern 1 (high potential P application pattern), a drain 2 conductive pattern 2 (intermediate potential AC application pattern) and a source 2 conductive pattern 3 (low potential N application pattern) are provided on one side of the insulating substrate 99, and a back conductive pattern 5 is provided on the other side.

[0055] The drain 1 conductive pattern 1 is electrically connected to drain electrodes provided on the back surfaces of a plurality of vertically structured power semiconductor chips 11 to 13 via a solder joint layer 10 and is shaped to be connectable to a drain 1 terminal 51 of a power semiconductor module and a drain 1 control terminal 52 for potential observation.

[0056] The current flowing through the upper-arm power semiconductor chips 11-13 flows from the source electrode pads 502 of the power semiconductor chips 11-13 via a plurality of bonding wires 35A, 35B, and 35C to the drain 2 conductive pattern 2 disposed on the power semiconductor chip mounting substrate 100. To allow the flow of large currents ranging from several hundred amperes to several thousand amperes, the cross-sectional areas of the drain 1 conductive pattern 1, the drain 2 conductive pattern 2, and the source 2 conductive pattern 3 are designed to be such that they will not melt due to heat generated by the current flow.

[0057] The drain 2 conductive pattern 2 has a shape capable of connecting the drain 2 terminal 64 to the drain 2 control terminal 62 for potential observation, and is electrically connected to the drain electrodes provided on the back surfaces of the lower arm power semiconductor chips 21 to 23 via the solder bonding layer 10 .

[0058] The gate electrode pads 501 of the power semiconductor chips 11 to 13 are electrically connected to the gate control terminal 91 via bonding wires 31 in which bridge-shaped wires are continuously arranged.

[0059] Furthermore, separately from the bonding wires 35A, 35B, and 35C serving as the main current path, a bonding wire 32 connecting the source electrode pads 502 of the power semiconductor chips 11 to 13 is arranged and electrically connected to the source sense control terminal 92 of the power semiconductor module.

[0060] The current flowing through the lower-arm power semiconductor chips 21 to 23 flows from the source electrode pads 502 of the power semiconductor chips 21 to 23 via a plurality of bonding wires 45A, 45B, and 45C to the source 2 conductive pattern 3 disposed on the power semiconductor chip mounting substrate 100. The source 2 conductive pattern 3 is shaped to connect the source 2 terminals 63A and 63B.

[0061] Gate electrode pads 501 of power semiconductor chips 21-23 are electrically connected to gate control terminal 93 via bonding wires 41, which are formed by continuously arranged bridge-shaped wires. Separately from bonding wires 45A, 45B, and 45C, which serve as the main current path, bonding wires 42 are arranged to connect source electrode pads 502 of power semiconductor chips 21-23, thereby electrically connecting them to source sense control terminal 94 of the power semiconductor module.

[0062] This embodiment shows a method in which the aforementioned bridge-shaped bonding wires 41 and 42 are continuously arranged to directly connect the gate electrode pads 501 and the source electrode pads 502 without a wiring pattern, thereby eliminating the need for the gate control wiring pattern and source control wiring pattern (wiring patterns 3C and 3D) described in Patent Document 1. As a result, a small-area power semiconductor chip mounting substrate can be realized while mounting a predetermined number of power semiconductor chips. Alternatively, the number of power semiconductor chips mounted on the substrate and the total chip area can be increased while maintaining the predetermined area of ​​the power semiconductor chip mounting substrate.

[0063] In this embodiment, similar to the bonding wire 31 that continuously connects the gate electrode pads 501 of the power semiconductor chips 11, 12, and 13, the bonding wire 32 that continuously connects the source electrode pads 502 is provided, and is arranged closely while ensuring electrical insulation, and its arrangement direction is roughly parallel (roughly parallel).

[0064] During switching, the gate control current and source control current of the power semiconductor chip are in opposite phases, generating an AC current loop from the bonding wire 31 through the gate electrode pad 501 and source electrode pad 502 of the power semiconductor chip to the bonding wire 32. By arranging the bonding wires 31 and 32 in parallel (or at an angle close to parallel), a negative mutual inductance is generated between the bonding wires 31 and 32, reducing the loop inductance Lgloop of the AC current loop.

[0065] Furthermore, in order to effectively reduce the loop inductance Lgloop of the AC current loop, the angle between the bonding wires 31 and 32 needs to be maintained within 30 degrees, and more preferably within 20 degrees, when routing the bonding wire 32 along the bonding wire 31 .

[0066] By reducing the loop inductance Lgloop, the gate loop inductance predicted from the gate control terminal 91 or 93 and the source sense control terminal 92 or 94 of the power semiconductor module to the inside of the module can be reduced, thereby suppressing the resonance generated between the gate drive circuit (not shown) of the power semiconductor module and suppressing the vibration noise voltage generated in the voltage Vgs between the gate control terminal 91 or 93 and the source sense control terminal 92 or 94 during switching.

[0067] Furthermore, in this embodiment, bonding wires 31 and 32 are connected to gate 1 control terminal 91 and source sense 1 control terminal 92, respectively, on the resin case 310 of the power semiconductor module, while bonding wires 41 and 42 are connected to gate 2 control terminal 93 and source sense 2 control terminal 94, respectively, on the resin case 310 of the power semiconductor module. This eliminates the need for dedicated conductive patterns on the power semiconductor chip mounting substrate 100, enabling a smaller power semiconductor chip mounting substrate 100. This further increases the number of power semiconductor chips mounted on the substrate and the total chip area, while also simultaneously suppressing the vibration noise voltage generated in Vgs.

[0068] in addition, Figure 1 The structure of this embodiment shown is characterized in that the source 2 conductive pattern 3 is arranged between the upper arm power semiconductor chips 11 to 13 and the lower arm power semiconductor chips 21 to 23. Figure 1 The area enclosed by the dotted line is configured so that the current flowing through the drain 2 conductive pattern 2 and the current flowing through the source 2 conductive pattern 3 are parallel and adjacent to each other. However, since the currents flowing through the conductive patterns 2 and 3 are in opposite directions, a negative mutual inductance is generated, which reduces the inductance generated in the area enclosed by the dotted line. This reduces the noise voltage during switching.

[0069] That is, when limited to Figure 1 When observing the area surrounded by the dotted line, a metal pattern 3 (third conductive pattern) is arranged between the metal pattern 1 (first conductive pattern) and the metal pattern 2 (second conductive pattern) and adjacent to the metal pattern 2 (second conductive pattern), and the directions of the current flowing in the respective conductive patterns of the metal pattern 2 (second conductive pattern) and the metal pattern 3 (third conductive pattern) differ by 180°.

[0070] Furthermore, the source 2 conductive pattern 3 can provide a distance between gate wirings (31-41) and source sense wirings (32-42) of the upper and lower arms of the inverter leg, thereby reducing magnetic interference.

[0071] Figure 1(b) shows a cross-sectional view taken along the dashed line segment AA' in the top view (a). While the cross-sectional view shows an example of the shape of the upwardly protruding bridge-shaped wire 31, its shape is not limited as long as it can achieve the function of connecting power semiconductor chips and ensure insulation from other wiring on the power semiconductor chip mounting substrate 100. In other words, the connection is not limited to bonding wires; the same effect can be achieved even with bonding ribbons or narrow conductors.

[0072] In the cross-sectional structure, an example is shown in which the power semiconductor chip mounting substrate 100 is connected to the base plate 300 via the solder bonding layer 9 , but the connection means is not limited thereto.

[0073] Figure 2 1 is a diagram showing the internal structure of a conventional power semiconductor module as a comparative example for easier understanding of the structure of the present invention. Figure 1 The number of the power semiconductor chip mounting substrate 100 and the number of the power semiconductor chips are equal. Figure 2 In the illustrated power semiconductor chip mounting substrate 101, for example, upper arm power semiconductor chips 11 to 13 are described. Gate conductive patterns 4 are arranged, and the gate electrode pads 501 of the power semiconductor chips 11 to 13 are connected to each other via bonding wires 31A, 31B, and 31C. Similarly, source sense conductive patterns 5 are arranged, and the source electrode pads 502 of the power semiconductor chips 11 to 13 are connected to each other via bonding wires 32A, 32B, and 32C.

[0074] These conductive patterns 4 and 5 are used to Figure 2 The conductive pattern required for gate driving of the three power semiconductor chips 11 to 13 shown as an example has a shape that conforms to the arrangement of the arranged power semiconductor chips and requires an area for connecting a plurality of bonding wires 31A to 31C and 32A to 32C.

[0075] Relative to Figure 2 The conventional power semiconductor chip mounting substrate 101 shown in FIG. Figure 1 The power semiconductor chip mounting substrate 100 of the present embodiment shown can reduce its area to 80%. In addition, although the above-mentioned reduction rate is affected by the design rules applied to the power semiconductor chip mounting substrate, it is obvious that the present embodiment ( Figure 1 ) The structure of the power semiconductor chip mounting substrate 100 shown in FIG. 1 can achieve an area reduction effect.

[0076] Figure 1The present embodiment is shown in the case where only one type of power semiconductor chip is mounted on the power semiconductor chip mounting substrate 100, for example, a plurality of MOSFET-type power semiconductor chips with built-in diodes. For example, the effects shown in this embodiment can also be achieved when the power semiconductor chips are two types: an IGBT chip and a diode chip, or two types: an IGBT chip and an SBD chip, or two types: a MOSFET and an SBD chip.

[0077] In particular, the effect of the present invention is greater when using power semiconductor chips that can perform forward and return (reverse) current flow in one chip, such as MOSFET type power semiconductor chips and IGBT type power semiconductor chips capable of reverse current flow.

[0078] Therefore, it is preferable that each of the plurality of power semiconductor chips 11 to 13 and 21 to 23 of this embodiment has a current switching function and a return function.

[0079] In addition, Figure 1 , one power supply point is shown for each of the drain 1 terminal 51 , the drain 2 terminal 64 , and the source 2 terminal 63 . However, the number of power supply points may be increased depending on the current value flowing through the terminals.

[0080] Next, the present embodiment will be used to describe how the gate controllability of the power semiconductor module during switching can be improved. Figure 3 is equivalent to Figure 1 The simplified equivalent circuit 601 of the power semiconductor module is shown. The upper arm circuit structure is described below. The gates of three MOSFET symbols M11 to M13, representing MOSFET-type power semiconductor chips, are connected via inductors Lg1 and Lg2, which are equivalent to bonding wires. Similarly, the source sense terminals are connected via inductors Lss1 and Lss2.

[0081] The gate of MOSFET M13 is connected to a node 91 corresponding to a gate 1 control terminal 91 via an inductor Lg3. The source of MOSFET M13 is connected to a node 92 corresponding to a source sense 1 control terminal 92 via an inductor Lss3. Figure 1 The bonding wires 31 and 32 are shown to be arranged in parallel or at an angle close to parallel, and mutual inductance acts between the bonding wires 31 and 32 .

[0082] exist Figure 3In the equivalent circuit, Mg1 to Mg3 represent the mutual inductance, which is set between the inductors Lg1 and Lss1, between the inductors Lg2 and Lss2, and between the inductors Lg3 and Lss3. Since the sign of the mutual inductance is negative, the loop inductance Lgloop of the gate AC current loop can be reduced. Figure 1 The drain power supply point 51 in the circuit is equivalent to the drain of MOSFET M11~M13, which is connected via inductors Ld1~Ld3. Figure 1 The impedance generated in the drain 1 conductive pattern 1 of the power semiconductor chip mounting substrate 100 .

[0083] In addition, node 64 (with Figure 1 The source power supply point 64 in the circuit is equivalent to the source of the MOSFET M11 to M13, which is connected via the inductors Ls1 to Ls3. Figure 1 The impedance generated in the source bonding wires 35A to 35C and the drain conductive pattern 2 of the power semiconductor chip mounting substrate 100 is shown in FIG. The lower arm circuit using MOSFET symbols M21 to M23 as switching elements has the same structure, and its detailed description is omitted.

[0084] In addition, Figure 1 In the region enclosed by the dashed line, the mutual inductance generated by the parallel and adjacent arrangement of drain 2 conductive pattern 2 and source 2 conductive pattern 3 is included in the equivalent circuit as M16, M25, and M34. Although the impedance of the bonding wires and conductive patterns is represented by the symbol of inductance, the influence of parasitic resistance is also taken into account in the simulation circuit described later, although not shown.

[0085] In addition, Figure 3 In the equivalent circuit, resistors Rgc11~Rgc13 and Rgc21~Rgc23 are connected in series to the gates of the MOSFET. Figure 1 Although not shown in the figure, the built-in gate resistor of the power semiconductor chip is shown, and its effect will be described later.

[0086] also, Figure 3 Arrows Is1 to Is6 indicate the direction of current flowing through the parasitic inductances Ls1 to Ls6 of the MOSFET source main current path, respectively. Furthermore, VgsChipSIM indicates the gate-source voltage of the power semiconductor chip.

[0087] Figure 4 is Figure 3 The equivalent circuit 601 of the 2-in-1 power semiconductor module and its gate drive circuit (GDC1, GDC2), inductive load L1, power supply Vcc, and power stabilization capacitor C1 are shown as a simulation circuit. Figure 3Nodes 91 to 94, node 51, node 63, and node 64 of the simplified equivalent circuit 601 are connected to the above-mentioned simulation circuit elements.

[0088] Figure 5 Figure 2 shows the switching transient waveform obtained through circuit simulation. Figure 5 The (a)-1 curve is in Figure 4 In the simulation circuit shown, transient response waveforms are obtained when the gate control terminal 91 and the source sense control terminal 92 of the upper arm circuit in the equivalent circuit 601 are driven by the gate drive circuit GDC1.

[0089] Figure 5 The solid line in (a) represents the voltage waveform of the voltage VgsSIM between the gate control terminal 91 and the source sense control terminal 92, and the dotted line represents the voltage waveform included in the equivalent circuit 601 ( Figure 3 ) between the gate and source of MOSFET M11 (refer to Figure 5 ) shows a waveform during conduction, which is a waveform in the middle of the transition from the OFF-drive voltage VGSN of GDC1 to the ON-drive voltage VGSP. Figure 5 (a)-2 is an enlarged view of the gate plateau voltage, which is the most important part during switching.

[0090] Clearly, the waveform of VgsSIM, observable as the voltage between the terminals of the power semiconductor module, accurately reproduces the gate-source voltage VgsChipSIM of the power semiconductor chip 100 incorporated into the module's chip mounting substrate. This excellent reproduction allows the power semiconductor module to be incorporated into a power converter, enabling drive control such as adjustment of dv / dt and di / dt, and loss optimization based on the transient waveform obtained at the power semiconductor module's gate drive terminals (consisting of a gate control terminal and a source sense control terminal) without requiring unnecessary margins.

[0091] Figure 6 The equivalent circuit 602 is for Figure 3 The equivalent circuit 602 is similar to the equivalent circuit 601 in that the gates of the MOSFET power semiconductor chips M11 to M13 are connected via inductors Lg1 and Lg2, and the source senses are connected via inductors Lss1 and Lss2. However, the node 92, which is the point of connection for obtaining the source sense control voltage, shares the node 64 (at the time of the main current flow) through which the main current flows. Figure 1 The lower arm circuit in the equivalent circuit 602 is also modified in the same manner as the upper arm circuit described above.

[0092] Figure 5(b)-1 and Figure 5 (b)-2 shows the switching transient waveform. Figure 5 Similarly, (a) shows the waveform at the time of conduction, which is a waveform in the middle of the change from the off-state driving voltage VGSN of GDC1 to the on-state driving voltage VGSP. Figure 5 In (b)-2, vibration occurs in the voltage (Vgs SIM) between the gate control terminal 91 (node ​​91 in the equivalent circuit) and the source sense control terminal 92 (node ​​92 in the equivalent circuit) shown by the solid line, but it can be seen that there is almost no vibration in the voltage waveform VgsChipSIM between the gate and source of M11 of the MOSFET included in the equivalent circuit 602.

[0093] That is, different from the transient waveform of the gate-source voltage of the power semiconductor chip mounted on the chip mounting substrate in the module, it indicates that a noise voltage (vibration voltage) is superimposed on the voltage between the gate control terminal and the source sense control terminal of the power semiconductor module.

[0094] Figure 7 The equivalent circuit 603 is also related to Figure 6 Similarly, this is a comparison circuit for the equivalent circuit 601. The equivalent circuit 603 connects the gates of the MOSFET power semiconductor chips M11 to M13 to the equivalent circuit 601 via the inductors Lg1 and Lg2, but excludes the source sensing path between the chips. Figure 1 The circuit and Figure 3 The equivalent circuit of FIG. 1 shows the effect of continuous wiring between source electrodes between chips.

[0095] The node 92, which is the point of obtaining the source sense control voltage, shares the node 64 through which the main current flows (in Figure 1 The same changes as those for the upper arm circuit are also applied to the lower arm circuit in the equivalent circuit 603.

[0096] Figure 5 (c)-1 and Figure 5 (c)-2 shows the switching transient waveform. Figure 5 (c)-1 and Figure 5 (c)-2, and the above Figure 5 (b) Similarly, the voltage (Vgs SIM) between the gate control terminal 91 and the source sense control terminal 92 shown by the solid line vibrates, and it can be seen that there is almost no vibration in the voltage waveform VgsChipSIM between the gate and source of the MOSFET M1 included in a substrate equivalent circuit.

[0097] exist Figure 7The equivalent circuit 603 also shows a situation in which a noise voltage (vibration voltage) is superimposed on the voltage between the gate control terminal and the source sense control terminal of the power semiconductor module, which is different from the transient waveform of the gate-source voltage of the power semiconductor chip mounted on the chip mounting substrate in the module.

[0098] That is, in Figure 5 In either waveform of (b) or 5(c), a waveform different from the transient waveform of the gate-source voltage VgsChip of the power semiconductor chip mounted on the power semiconductor chip mounting substrate in the module is shown in the transient waveform of the observable voltage Vgs between the gate control terminal and the source sense control terminal of the power semiconductor module.

[0099] Originally, it was necessary to optimize the gate drive speed within the range not exceeding the gate rated voltage based on the transient waveform appearing in VgsChip and effectively utilize the characteristics of the power semiconductor chip. However, as mentioned above, when there is a difference between the transient waveform of VgsChip and the observable Vgs, the gate drive speed is optimized based on the observable Vgs waveform.

[0100] Therefore, even though the power semiconductor chip is inherently capable of higher-speed operation, a slower gate drive is selected due to the Vgs waveform, which increases switching losses and makes it difficult to effectively utilize the characteristics of the power semiconductor chip.

[0101] On the other hand, the connection structure between chips and between gate control terminals and source sense control terminals of the power semiconductor chip mounting substrate shown in this embodiment can overcome the above problems and form a power semiconductor module that maximizes the performance of the power semiconductor chip.

[0102] As described above, according to this embodiment, the mounting efficiency of multiple power semiconductor chips built into the power semiconductor chip mounting substrate (main substrate) of the power semiconductor module can be improved, and the gate controllability of the power semiconductor module during switching can be improved.

[0103] exist Figure 3 In the equivalent circuit diagram of , resistors Rgc11 to Rgc13 are arranged in series on the gates of the MOSFET transistors M11 to M13, and the effects thereof will be described.

[0104] pass Figure 1The parallel bonding connection between the gate electrodes and source electrodes of the plurality of chips shown can improve the efficiency of chip mounting on the power semiconductor chip mounting substrate or reduce the area of ​​the power semiconductor chip mounting substrate. Furthermore, to improve the reliability of the mounted power semiconductor chips and extend the life of the power semiconductor module, it is necessary to make the thermal stress history of each power semiconductor chip and the wiring mounting materials, including the bonding wires and solder that form the wiring structure, as uniform as possible.

[0105] The gate resistor Rgc built into the power semiconductor chip is used to make the current balance of each power MOSFET chip during switching as uniform as possible, thereby equalizing the thermal history of the power semiconductor chip and the surrounding wiring and mounting materials.

[0106] Figure 8 Shows the use of Figure 4 The switching simulation circuit of FIG. 6 shows the circuit simulation results when the built-in gate resistance values ​​Rgc11 to Rgc13 of the MOSFETs M11 to M13 and the built-in gate resistance values ​​Rgc21 to Rgc23 of the MOSFETs M21 to M23 in the equivalent circuit 601 are increased or decreased.

[0107] Figure 8 This figure shows the transient waveform of the drain current of each power MOSFET chip when it is turned on. Figure 8 (a) represents the overall waveform, Figure 8 (b) shows the waveform when Rgc11 to Rgc13 and Rgc21 to Rgc23 are set to larger values, for example, 32Ω. Figure 8 (c) shows a waveform when Rgc11 to Rgc13 and Rgc21 to Rgc23 are set to small values, for example, 2Ω.

[0108] Obviously, by using parallel bonding connections between gate electrodes and source electrodes of a plurality of chips, the impedance of the gate electrodes and source electrodes of each power semiconductor chip viewed from the gate drive circuit GDC1 becomes non-uniform.

[0109] Therefore, by arranging the gate built-in resistor Rgc of an appropriate value, the impedance non-uniformity is alleviated and the timing of the power supply to each power semiconductor chip is made close.

[0110] pass Figure 8 (b) and Figure 8 As can be seen from the comparison with (c), by setting Rgc to a predetermined value or more, the current ripple of the power MOSFET chip during switching can be kept below a certain level.

[0111] As described above, the power semiconductor module of this embodiment comprises: an insulating substrate 99; a first conductive pattern (metal pattern 1) arranged on the insulating substrate 99; a plurality of power semiconductor chips 11 to 13 arranged on the first conductive pattern (metal pattern 1); a first wiring (bonding wire 31) in the shape of a bridge directly connecting the gate electrodes (gate electrode pads 501) of the plurality of power semiconductor chips 11 to 13 to each other; and a second wiring (bonding wire 32) in the shape of a bridge directly connecting the source electrodes (source electrode pads 502) of the plurality of power semiconductor chips 11 to 13 to each other, wherein the first wiring (bonding wire 31) is arranged along the second wiring (bonding wire 32) so that the angle formed with the second wiring (bonding wire 32) is within 30 degrees.

[0112] In addition, it has a gate control terminal 91 configured to be electrically insulated from the first conductive pattern (metal pattern 1) and a source sensing control terminal 92 configured to be separated from the first conductive pattern (metal pattern 1), the first wiring (bonding wire 31) is connected to the gate control terminal 91, and the second wiring (bonding wire 32) is connected to the source sensing control terminal 32.

[0113] Furthermore, the plurality of power semiconductor chips 11 to 13 arranged on the first conductive pattern (metal pattern 1 ) and the plurality of power semiconductor chips 21 to 23 arranged on the second conductive pattern (metal pattern 2 ) are arranged at point-symmetrical positions.

[0114] Furthermore, each of the power semiconductor chips 11 to 13 and 21 to 23 includes an internal resistor having a predetermined resistance value, as measured by the internal impedance of the chip as measured from the gate electrode pad 501. Furthermore, each of the power semiconductor chips 11 to 13 and 21 to 23 includes an internal resistor made of polycrystalline silicon, thereby contributing to the miniaturization of the power semiconductor module. Using polycrystalline silicon for the internal resistor facilitates formation on the semiconductor chip, minimizing its temperature dependence.

[0115] Thus, in a power semiconductor module in which a plurality of semiconductor chips are arranged in parallel on an insulating substrate, high-density mounting of the semiconductor chips is possible, and a power semiconductor module with less variation in operating characteristics between the semiconductor chips and high reliability can be realized.

[0116] Furthermore, it is possible to achieve miniaturization and improved reliability of a power converter using the power semiconductor module.

[0117] Example 2

[0118] Reference Figure 9 , the power semiconductor module of embodiment 2 of the present invention is described. Figure 1) Similarly, the internal structure of a 2in1 module equipped with a MOSFET type power semiconductor chip is shown. The cross-sectional structure is also similar to Figure 1 The diagram is omitted because it is the same as (b).

[0119] The power semiconductor chip mounting substrate 102 carries both the upper arm power semiconductor chip and the lower arm power semiconductor chip of the 2-in-1 module. The Drain 1 terminal 51, which serves as the high potential terminal (P terminal) of the 2-in-1 module, is connected to the Drain 1 power supply point 51 of the power semiconductor chip mounting substrate 102. The Drain 2 terminal 64, which serves as the intermediate potential terminal (AC terminal), is connected to the Drain 2 power supply point 64 of the power semiconductor chip mounting substrate 102. The Source 2 terminal 63, which serves as the low potential terminal (N terminal), is connected to the Source 2 power supply point 63 of the power semiconductor chip mounting substrate 102.

[0120] Drain sense 1 control terminal 52 for observing the drain voltages of the upper and lower arms is connected to drain sense 1 power supply point 52, and drain sense 2 control terminal 62 is connected to drain sense 2 power supply point 62. As described above, the terminals of the power semiconductor module are electrically connected to the power semiconductor chip mounting substrate.

[0121] In this embodiment, the case where the number of mounted power semiconductor chips is increased in order to increase the rated current of the power semiconductor module or to increase the total area of ​​the mounted power semiconductor chips within a predetermined module area is exemplified.

[0122] like Figure 9 As shown, the power semiconductor chips 11 to 16 that operate as switching elements of the upper arm circuit constitute a chip group of three chips, and the chips in the same chip group are electrically connected to each other's gate electrodes and source electrodes using bridge-shaped wiring. The power semiconductor chips 21 to 26 that operate as switching elements of the lower arm circuit are also constituted by a chip group of three chips, and the chips in the same chip group are electrically connected to each other's gate electrodes and source electrodes using bridge-shaped wiring.

[0123] The features of this embodiment will be described using the upper arm circuit as an example. The first chip group of the upper arm circuit consists of power semiconductor chips 11-13, and the second chip group consists of power semiconductor chips 14-16. The wiring between the gate electrodes and the wiring between the chips in the first and second chip groups follows the structure described in Example 1.

[0124] In this embodiment, a characteristic structure is that the wiring between the gate electrodes of the first chip group and the second chip group is electrically connected to each other using a conductor 95 disposed on or inside the resin case 310 .

[0125] Similarly, wirings between source electrodes are also electrically connected to each other via a conductor 96 disposed on or inside the resin case 310 .

[0126] Conventionally, electrical connection is performed using a conductive pattern arranged on the same chip mounting substrate. However, this conductive pattern has become a major obstacle to increasing the area of ​​the power semiconductor chip mounting substrate or the number of mounted chips.

[0127] Therefore, by adopting the structure of this embodiment, in addition to the effects of the present invention described in the first embodiment, it is possible to suppress an increase in substrate area even when a plurality of power semiconductor chips are mounted and arranged in parallel in two rows.

[0128] In the upper arm circuit, drive signals can be supplied to the gate electrodes of the power semiconductor chips 11 to 16 via a gate 1 control terminal 91 electrically connected to a conductor 95 and a source sense 1 control terminal 92 electrically connected to a conductor 96 .

[0129] The same is true for the lower arm. A drive signal can be provided to the gate electrodes of the power semiconductor chips 21 to 26 via the gate 1 control terminal 93 electrically connected to the conductor 97 and the source sense 1 control terminal 94 electrically connected to the conductor 98 .

[0130] Compared with the existing structure, the bottom area of ​​the power semiconductor module of this embodiment can be reduced to 83%.

[0131] Furthermore, although the above-mentioned reduction rate is affected by the design rules applied to the power semiconductor chip mounting substrate, it is clear that the area reduction effect can be achieved by the configuration of the power semiconductor chip mounting substrate shown in Example 2.

[0132] As described above, in the power semiconductor module of this embodiment, multiple power semiconductor chips 11 to 16 are arranged as multiple chip groups according to a certain number of chips on a first conductive pattern (metal pattern 1), and the first wiring (bonding wires 31, 33) of each chip group is connected to the common gate control terminal 91, and the second wiring (bonding wires 32, 34) of each chip group is connected to the common source sense control terminal 92.

[0133] The number of power semiconductor chips illustrated in this embodiment is set to be the same as the number of chips in the upper and lower arm circuits, and an example is shown in which a chipset is composed of 3 chips and the number of chipsets is 2 groups. Even if the number of chips in each chip group and the number of chips in the chipset are different from the illustration, the effect of the present invention can be obtained. For example, even if the number of chips in two adjacent chipsets is different, the effect of the present invention can be obtained. In addition, the same is true even if the number of chipsets in each arm circuit is 3 or more.

[0134] Example 3

[0135] Reference Figure 10 , a power semiconductor module according to a third embodiment of the present invention is described. Figure 10 The power semiconductor module shown has slit patterns 71A and 71B respectively arranged on the drain 2 conductive pattern 2 and the source 2 conductive pattern 3 formed on the power semiconductor chip mounting substrate 103. The slit patterns 71A and 71B are arranged at positions symmetrical to each other.

[0136] The slit pattern 71A reduces the inductance imbalance of the source main current path flowing from the source electrode pads of the plurality of MOSFET power semiconductor chips 11 to 13 through the plurality of bonding wires 35A, 35B, and 35C to the drain 2 feeding point 64 connected to the intermediate potential (AC) terminal.

[0137] With respect to the drain 2 power supply point 64 , the source current flowing from the power semiconductor chip 13 has the shortest path through the drain 2 conductive pattern 2 , and the path through the power semiconductor chip 11 is the longest. Figure 10 The slit pattern 71A shown in the drain 2 conductive pattern 2 is arranged in an inverted L shape to bypass the current path from the power semiconductor chip 13 closest to the drain 2 feeding point 64. The introduction of the slit 71A can reduce the inductance fluctuation of the source current path of the power semiconductor chips 11-13.

[0138] Power semiconductor chips 14-16 are similarly connected from source electrode pads via multiple bonding wires 35D, 35E, and 35F to a drain 2 power supply point 64 connected to the intermediate potential (AC) terminal. However, no slit pattern is provided in the drain 2 conductive pattern 2 for the power semiconductor chips 14-16. Since the power semiconductor chips 14-16 are electrically located farther from the power semiconductor chips 11-13, a slit pattern that would further increase inductance is not employed.

[0139] The above description is for the upper arm circuit, but the slit pattern 71B arranged in the source 2 conductive pattern 3 also has the same function, so the description thereof is omitted.

[0140] Furthermore, the shape of the slit pattern is an inverted L-shape, but the effects of this embodiment can be obtained even if the shape is L-shaped, I-shaped, or the like without departing from the above description.

[0141] As described above, in the power semiconductor module of this embodiment, the second conductive pattern (metal pattern 2) is connected to the source electrode pads 502 of the plurality of power semiconductor chips 11 to 13 on the first conductive pattern (metal pattern 1) via a plurality of bonding wires 35A, 35B, and 35C. An L-shaped or I-shaped first slit pattern 71A is provided between the connection points between the second conductive pattern (metal pattern 2) and the bonding wires 35A, 35B, and 35C and the feed point 64 of the second conductive pattern (metal pattern 2) to reduce inductance fluctuations in the source current path. Furthermore, the third conductive pattern (metal pattern 3) is connected to the source electrodes of the plurality of power semiconductor chips on the second conductive pattern (metal pattern 2) via a plurality of bonding wires 45A, 45B, and 45C. An L-shaped or I-shaped second slit pattern 71B is provided between the connection points between the third conductive pattern (metal pattern 3) and the bonding wires 45A, 45B, and 45C and the feed point 63 of the third conductive pattern (metal pattern 3) to reduce inductance fluctuations in the source current path.

[0142] The structure of the power semiconductor chip mounting substrate 103 of this embodiment using the slit patterns 71A and 71B is similar to that of the embodiment 2 ( Figure 9 ) can improve the current balance between the mounted power semiconductor chips compared to the structure of the power semiconductor module shown in FIG.

[0143] According to the various embodiments of the present invention described above, in the internal structure of the power semiconductor module, the installation efficiency of the power semiconductor chip on the power semiconductor chip mounting substrate can be improved, the area of ​​the power semiconductor chip mounting substrate can be reduced, or the number of power semiconductor chips mounted on the substrate of a predetermined area can be increased.

[0144] Furthermore, the structure of the present invention can reduce the difference between the gate drive voltage observed at the gate drive terminal of the semiconductor module and the gate drive voltage waveform of the power semiconductor chip mounted on the power semiconductor module. This effect makes it possible to achieve miniaturization of power semiconductor modules equipped with high-performance compound semiconductor chips with a small chip area, or to achieve higher current by mounting multiple chips. Furthermore, the noise voltage generated by switching can be suppressed to within the rated gate voltage range of the power semiconductor chip, and the gate drive waveform can be set to a high speed or the highest possible voltage, thereby providing a power semiconductor module that can maximize the performance of the power semiconductor chip.

[0145] Specifically, the internal structure of a power semiconductor module enables high-speed switching while connecting multiple power semiconductor chips in parallel. This allows for high performance in power semiconductor modules equipped with compound semiconductor chips made of SiC (silicon carbide) or GaN (gallium nitride), which have lower chip yields than Si semiconductor chips and result in smaller chip areas. Specifically, this allows for increased rated current and reduced switching losses.

[0146] Furthermore, the present invention is particularly effective when using compound semiconductor chips with compact chip shapes, as chip yields are low due to substrate crystal defects and manufacturing process issues. In particular, when using vertical SiC power MOSFET chips manufactured using SiC substrates, since these chips also function as freewheeling diodes, only one SiC power MOSFET chip can be mounted on the chip mounting substrate, resulting in higher chip mounting efficiency.

[0147] Furthermore, the present invention is not limited to the above-described embodiments and encompasses various variations. For example, the above-described embodiments are described in detail to facilitate understanding of the present invention and are not necessarily limited to all of the described structures. Furthermore, a portion of the structure of one embodiment can be replaced with a structure of another embodiment, and a structure of another embodiment can be added to a structure of one embodiment. Furthermore, other structures can be added, deleted, or substituted for a portion of the structure of each embodiment.

[0148] For example, for the MOSFET type (MOS field effect transistor) used in this embodiment, the switching element is replaced by any one of the unipolar devices such as the J-FET type (junction field effect transistor) and the bipolar device such as the IGBT type (insulated gate bipolar transistor), and within the function of the terminal, for example, even if the drain is replaced by the collector, the source is replaced by the emitter, and the gate is replaced by the base, the effect of the present invention will not change. In addition, with respect to the diode element, similarly, the effect of the present invention will not change even if any one of the PN junction diode and the SB (Schottky junction) diode is used.

[0149] Explanation of symbols

[0150] 1-7 Metal (conductive) patterns on insulating substrates

[0151] 9, 10 Solder bonding layer

[0152] 11~16, 21~26 power semiconductor chips

[0153] 31~34, 35A~35C, 41~44, 45A~45C bonding wires

[0154] 36, 46 gate wiring wires

[0155] 37, 47 source wiring wire

[0156] Terminals 51, 63A, 63B, and 64 (terminal power supply points on the substrate)

[0157] Terminals 52 and 62 (power supply points for potential monitoring on the substrate)

[0158] 71A, 71B slit patterns

[0159] 91, 93 gate control terminals

[0160] 92, 94 source sensing control terminals

[0161] 95, 97 (for gate connection between chips) conductors

[0162] 96, 98 (inter-chip source sensing connection) conductors

[0163] 99 Insulation Substrate

[0164] 100~103 power semiconductor chip mounting substrate

[0165] 300 baseboard

[0166] 310 resin shell

[0167] 501 Gate electrode pad (of a power semiconductor chip)

[0168] 502 Source electrode pad (of power semiconductor chip)

[0169] 601, 602, 603 (Simplified) Equivalent Circuit

[0170] Mg1~Mg6、M16、M25、M34 mutual inductance

[0171] Ld1~Ld6 Parasitic inductance of MOSFET drain path

[0172] Ls1~Ls6 Parasitic inductance of the main current path of the MOSFET source

[0173] Lg1~Lg6 Parasitic inductance of MOSFET gate path

[0174] Lss1~Lss6 MOSFET source control path parasitic inductance

[0175] Rgc11~Rgc13, Rgc21~Rgc23 are the resistance values ​​of the gate path inside the MOSFET chip.

Claims

1. A power semiconductor module, characterized in that: have: insulating substrate; a first conductive pattern, which is arranged on the insulating substrate; a plurality of power semiconductor chips, which are arranged on the first conductive pattern; a first wiring in a bridge shape directly connecting the gate electrodes of the plurality of power semiconductor chips to each other; a second wiring in a bridge shape, which directly connects the source electrodes of the plurality of power semiconductor chips to each other; a gate control terminal, which is electrically insulated from the first conductive pattern and is configured on the housing; as well as a source sensing control terminal, which is configured on the housing separately from the first conductive pattern; The first wiring is arranged along the second wiring so that the angle formed with the second wiring is within 30 degrees and is connected to the gate control terminal without passing through other conductive patterns on the insulating substrate. The second wiring is connected to the source sense control terminal without passing through other conductive patterns on the insulating substrate.

2. The power semiconductor module according to claim 1, wherein: On the first conductive pattern, the plurality of power semiconductor chips are configured into a plurality of chip groups according to a certain number of chips. The first wiring of each chip group is connected to a common gate control terminal. The second wiring of each chip group is connected to a common source sense control terminal.

3. The power semiconductor module according to claim 1, wherein: The power semiconductor module comprises: a second conductive pattern, which is disposed on the insulating substrate; a plurality of power semiconductor chips, which are arranged on the second conductive pattern; a third wiring in a bridge shape, which directly connects the gate electrodes of the plurality of power semiconductor chips on the second conductive pattern; as well as a fourth wiring in a bridge shape, which directly connects the source electrodes of the plurality of power semiconductor chips on the second conductive pattern to each other; The third wiring is arranged along the fourth wiring so that the angle formed with the fourth wiring is within 30 degrees.

4. The power semiconductor module according to claim 3, characterized in that A third conductive pattern is disposed between the first conductive pattern and the second conductive pattern and adjacent to the second conductive pattern. There is a portion where the directions of currents flowing through the second conductive pattern and the third conductive pattern differ by 180°.

5. The power semiconductor module according to claim 4, characterized in that The second conductive pattern is connected to the source electrodes of the plurality of power semiconductor chips on the first conductive pattern via a plurality of bonding wires, and a first slit pattern in an L-shape or an I-shape is provided between the connection point between the second conductive pattern and the bonding wires and the power supply point of the second conductive pattern to reduce inductance fluctuations in the source current path. The third conductive pattern is connected to the source electrodes of multiple power semiconductor chips on the second conductive pattern through multiple bonding wires, and has an L-shaped or I-shaped second slit pattern between the connection point between the third conductive pattern and the bonding wire and the power supply point of the third conductive pattern to reduce the inductance fluctuation of the source current path.

6. The power semiconductor module according to claim 5, characterized in that The first slit pattern and the second slit pattern are arranged at point-symmetrical positions.

7. The power semiconductor module according to claim 1, wherein: The plurality of power semiconductor chips each have a current switching function and a return function.

8. The power semiconductor module according to claim 1, wherein: Each of the plurality of power semiconductor chips includes a built-in resistor having a predetermined resistance value when the impedance inside the chip is estimated from the gate electrode pad.

9. The power semiconductor module according to claim 8, characterized in that Each of the plurality of power semiconductor chips includes a built-in resistor made of polycrystalline silicon.

10. The power semiconductor module according to any one of claims 1 to 9, characterized in that The plurality of power semiconductor chips are SiC power semiconductor chips.

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