Verification method, verification device, electronic device, and computer-readable storage medium

Abstract

A verification method for a processor circuit, a verification device for verifying a processor circuit, an electronic device, and a computer-readable storage medium. The processor circuit includes at least a first processor core and a second processor core. The verification method includes: configuring a connector according to configuration information, such that the connector selects a target connection mode from a plurality of optional connection modes to couple the first processor core and the second processor core; generating test data for excitation, using the test data to excite the processor circuit, such that the first processor core and the second processor core communicate through the connector in the target connection mode, and outputting a response result of the test data; and comparing the response result with a reference result for verification. The verification method can flexibly configure the connection mode of the first processor core and the second processor core according to the configuration information, can be applied to a variety of test scenarios, and reduces the verification difficulty.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a verification method, a verification device, an electronic device, and a computer-readable storage medium. Background Art

[0002] With the rapid development of the integrated circuit industry, the complexity of chips has increased significantly. The requirements for CPU chip function verification are getting higher and higher, and the requirements for the iteration cycle are getting shorter and shorter.

[0003] Currently, the Universal Verification Methodology (UVM), which is a verification platform development framework mainly based on the SystemVerilog library, is widely used in the verification of CPU chips. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a verification method for a processor circuit. The processor circuit includes at least a first processor core and a second processor core. The method includes: configuring a connector according to configuration information, so that the connector selects a target connection method from a variety of optional connection methods to couple the first processor core and the second processor core; generating test data for excitation, using the test data to excite the processor circuit, so that the first processor core and the second processor core communicate through the connector in the target connection method, and outputting a response result of the test data; and comparing the response result with a reference result for verification.

[0005] For example, in the verification method provided by an embodiment of the present disclosure, the variety of connection methods include single connection and multi-connection. The single connection is to couple the first processor core and the second processor core through a single bus, and the multi-connection is to couple the first processor core and the second processor core through multiple buses.

[0006] For example, in the verification method provided by an embodiment of the present disclosure, the method further includes: generating configuration information and providing the configuration information to the connector.

[0007] For example, in the verification method provided by an embodiment of the present disclosure, before comparing the response result with the reference result, the method further includes: obtaining a reference result according to the test data.

[0008] For example, in the verification method provided by an embodiment of the present disclosure, obtaining a reference result according to the test data includes: calculating the test data using a reference model to obtain a reference result.

[0009] For example, in the verification method provided by an embodiment of the present disclosure, the method further includes: obtaining a configuration result of the connector configured according to the configuration information; and determining whether the connector is configured as the target connection method according to the configuration result.

[0010] For example, in the verification method provided by an embodiment of the present disclosure, in the case where the target connection mode is multi-connection, the method further includes: predicting a target bus for transmitting the response result of the test data among multiple buses according to the allocation protocol of the multiple buses; and determining whether the response result of the test data comes from the target bus for verification.

[0011] For example, in the verification method provided by an embodiment of the present disclosure, the test data includes a read instruction or a write instruction between a first processor core and a second processor core, such that the first processor core and the second processor core communicate through a connector in a target connection mode, and output the response result of the test data, including: causing the first processor core and the second processor core to execute a read instruction or a write instruction through the connector in the target connection mode, generating a response result, and then outputting the response result of the test data.

[0012] At least one embodiment of the present disclosure provides a verification device for verifying a processor circuit. The processor circuit includes at least a first processor core and a second processor core. The verification device includes: a connector configured to provide optional multiple connection modes, and configured to be coupled to the first processor core and the second processor core, and select a target connection mode for coupling the first processor core and the second processor core from the multiple connection modes according to configuration information; an excitation generation unit configured to generate test data and use the test data to excite the processor circuit, such that the first processor core and the second processor core communicate through the connector in the target connection mode and output the response result of the test data; and a comparison unit configured to compare the response result with a reference result for verification.

[0013] For example, in the verification device provided by an embodiment of the present disclosure, the excitation generation unit is further configured to generate configuration information and provide the configuration information to the connector.

[0014] For example, in the verification device provided by an embodiment of the present disclosure, the verification device further includes: a monitoring unit configured to monitor the test data generated by the excitation generation unit and provide the test data to the comparison unit, and monitor the response result generated by the processor circuit and provide the response result to the comparison unit.

[0015] For example, in the verification device provided by an embodiment of the present disclosure, the comparison unit receives the test data and the response result from the monitoring unit, obtains a reference result according to the test data, and compares the response result with the reference result.

[0016] For example, in the verification device provided by an embodiment of the present disclosure, the comparison unit includes a reference model.

[0017] Obtaining a reference result according to the test data includes: calculating the reference result by using the reference model for the test data.

[0018] For example, in the verification device provided in an embodiment of the present disclosure, the monitoring unit is further configured to monitor the configuration information and provide the configuration information to the comparison unit.

[0019] For example, in the verification device provided in an embodiment of the present disclosure, the monitoring unit is further configured to monitor the configuration result of the connector configured according to the configuration information, and provide the configuration result to the comparison unit, so that the comparison unit determines whether the connector is configured as the target connection mode according to the configuration result.

[0020] For example, in the verification device provided in an embodiment of the present disclosure, the multiple connection modes include single connection and multi-connection. The single connection is to couple the first processor core and the second processor core through one bus, and the multi-connection is to couple the first processor core and the second processor core through multiple buses.

[0021] For example, in the verification device provided in an embodiment of the present disclosure, in the case where the target connection mode is multi-connection, the comparison unit is further configured to: predict the target bus for transmitting the response result of the test data among the multiple buses according to the allocation protocol of the multiple buses; and determine whether the response result of the test data comes from the target bus for verification.

[0022] For example, in the verification device provided in an embodiment of the present disclosure, the test data is a read instruction or a write instruction between the first processor core and the second processor core. The excitation generation unit includes: a read-write sub-unit configured to use the read instruction or the write instruction to excite the processor circuit, so that the first processor core and the second processor core execute the read instruction or the write instruction through the connector in the target connection mode to generate a response result, and output the response result of the test data.

[0023] At least one embodiment of the present disclosure provides an electronic device, including: a processor; a memory including one or more computer program instructions; wherein, the one or more computer program instructions are stored in the memory and, when executed by the processor, implement the instructions of the verification method provided in at least one embodiment of the present disclosure.

[0024] At least one embodiment of the present disclosure provides a computer-readable storage medium, which non-temporarily stores computer-readable instructions, and when the computer-readable instructions are executed by a processor, implements the verification method provided in at least one embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0026] Figure 1AShows a flowchart of a verification method for a processor circuit provided by at least one embodiment of the present disclosure;

[0027] Figure 1B , Figure 1C and Figure 1D Shows examples of various connection methods provided by at least one embodiment of the present disclosure;

[0028] Figure 2 Shows a flowchart of another verification method provided by at least one embodiment of the present disclosure;

[0029] Figure 3 Shows a flowchart of another verification method provided by at least one embodiment of the present disclosure;

[0030] Figure 4 Shows a verification device for verifying a processor circuit provided by at least one embodiment of the present disclosure;

[0031] Figure 5 Shows a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure; and

[0032] Figure 6 Shows a schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure;

[0033] Figure 7 Is a schematic diagram of a storage medium provided by some embodiments of the present disclosure. Detailed implementation manners

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0035] Unless otherwise defined, the technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "an" or "the" do not denote a limitation of quantity, but mean that there is at least one. The terms such as "comprising" or "including" mean that the elements or items appearing before this term cover the elements or items listed after this term and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0036] The integration level of modern CPU chips is getting higher and higher. A CPU chip usually consists of many processor cores (i.e., DIEs), and there are also many ways to connect DIEs to each other. Usually, multiple core circuits form a DIE, and multiple DIEs form a CPU chip. The RTL circuits inside each DIE are usually the same, but the connection ways between DIEs can be different.

[0037] In the related art, usually a verification platform is established separately for each connection way to verify each connection way independently. The simulation time consumed by this method increases exponentially with the number of connection ways, and there are certain limitations in verifying multiple scenarios. Once the connection way changes, the verification platform can only be rebuilt.

[0038] At least one embodiment of this disclosure provides a verification method for a processor circuit, where the processor circuit includes at least a first processor core and a second processor core. The verification method includes: configuring a connector according to configuration information, so that the connector selects a target connection way from a variety of optional connection ways to couple the first processor core and the second processor core; generating test data for excitation, using the test data to excite the processor circuit, so that the first processor core and the second processor core communicate through the connector in the target connection way, and outputting the response result of the test data; and comparing the response result with a reference result for verification. This verification method can flexibly configure the connection way between the first processor core and the second processor core according to the configuration information, can be applied to multiple test scenarios, and reduces the verification difficulty.

[0039] Figure 1AThe flowchart of a verification method for a processor circuit provided by at least one embodiment of the present disclosure is shown. In this embodiment, the processor circuit includes a first processor core and a second processor core.

[0040] As Figure 1A shown, the verification method may include steps S10 to S30.

[0041] Step S10: Configure the connector according to the configuration information, so that the connector selects a target connection method from a variety of optional connection methods to couple the first processor core and the second processor core.

[0042] Step S20: Generate test data for excitation, use the test data to excite the processor, so that the first processor core and the second processor core communicate through the connector in the target connection method, and output the response result of the test data.

[0043] Step S30: Compare the response result with the reference result for verification.

[0044] For step S10, the configuration information is used to indicate the connection method for coupling the first processor core and the second processor core by the connector.

[0045] In some embodiments of the present disclosure, the configuration information may be obtained from an external device communicatively connected to a verification device for verifying the processor circuit, or may also be generated by a verification device for verifying the processor circuit.

[0046] As Figure 1A shown, on the basis of including steps S10 to S30, the verification method may further include step S40. Step S40 may be executed, for example, before step S10.

[0047] Step S40: Generate configuration information and provide the configuration information to the connector.

[0048] For step S40, in some embodiments of the present disclosure, for example, the configuration information may be randomly generated. Randomly generating the configuration information can flexibly verify the processor circuit.

[0049] In another embodiment of the present disclosure, for example, the configuration information may be generated according to the user's input. This embodiment can verify the processor circuit according to the user's needs.

[0050] In some embodiments of the present disclosure, for example, a variety of connection methods may be preset in the connector, so that the connector selects a target connection method from multiple connection methods according to the configuration information.

[0051] The multiple connection methods include single connection and multiple connections. Single connection means coupling the first processor core and the second processor core through a single bus, and multiple connections mean coupling the first processor core and the second processor core through multiple buses.

[0052] In an embodiment of the present disclosure, the first processor core and the second processor core perform data interaction through a bus.

[0053] Figure 1B 、 Figure 1C and Figure 1D show examples of multiple connection methods provided by at least one embodiment of the present disclosure.

[0054] For example, in Figure 1B , the processor core DIE0 and the processor core DIE1 are connected through a single bus, that is, the processor core DIE0 and the processor core DIE1 are in a single connection.

[0055] For example, in Figure 1C , the processor core DIE0 and the processor core DIE1 are connected through two buses, that is, the processor core DIE0 and the processor core DIE1 are in multiple connections.

[0056] For example, in Figure 1D , the processor core DIE0 and the processor core DIE1 are connected through three buses, that is, the processor core DIE0 and the processor core DIE1 are in multiple connections.

[0057] It should be understood that Figure 1B 、 Figure 1C and Figure 1D The three connection methods shown are only examples to illustrate single connection and multiple connections, Figure 1B 、 Figure 1C and Figure 1D The connection methods shown do not limit the present disclosure. For example, multiple connections can also be through 4 buses, 5 buses, etc.

[0058] Connecting the first processor core and the second processor core through multiple buses enables the CPU chip to process multiple test data simultaneously, thereby improving the data interaction efficiency between the first processor core and the second processor.

[0059] In some embodiments of the present disclosure, the configuration information can be, for example, an information sequence, and this information sequence includes write instructions, register addresses, and operands written to the registers corresponding to the register addresses, etc.

[0060] The connector reads the operand from the register and configures the connection method according to the operand. Different operands correspond to different connection methods.

[0061] For example, the operand in the register is 1, and 1 indicates a single - bus connection. Then the single - connection is the target connection mode, and the connector selects to couple the first processor core and the second processor through the single connection.

[0062] For another example, the operand in the register is 2, and 2 indicates a two - bus connection. Then the two - bus connection is the target connection mode, and the connector selects to couple the first processor core and the second processor through the two buses.

[0063] Regarding step S20, in the embodiments of the present disclosure, the test data includes a read instruction or a write instruction between the first processor core and the second processor core.

[0064] Enable the first processor core and the second processor core to communicate in the target connection mode through the connector, and generate a response result of the test data, including: enabling the first processor core and the second processor core to execute a read instruction or a write instruction in the target connection mode through the connector, and generating a response result.

[0065] For example, the test data is that the first processor core reads the first operand at the first address of the second processor core. In response to receiving the test data, the first processor core accesses the first address in the second processor core in the target connection mode to read the first operand. In this embodiment, the operand read by the first processor core from the first address is the response result of the test data.

[0066] If the target connection mode is a single - bus connection, the first processor core accesses the first address in the second processor core through the single bus.

[0067] If the target connection mode is a multi - bus connection, the first processor core can select a bus that matches the test data from multiple buses according to the bus allocation protocol to access the first address in the second processor core.

[0068] For another example, the test data is that the second processor core writes the second operand to the second address in the first processor core. In response to receiving the test data, the second processor core accesses the second address in the first processor core in the target connection mode to write the second operand to the second address. In this embodiment, the operand written to the second address is the response result of the test data.

[0069] Regarding step S30, for example, if the response result is consistent with the reference result, it indicates that the response result of the hardware circuit to be tested is correct; if the response result is inconsistent with the reference result, it indicates that the response result of the hardware circuit to be tested is incorrect.

[0070] The hardware circuit to be tested may, for example, refer to the hardware circuit of the first processor core, the hardware circuit of the second processor core, and the connection circuit between the first processor core and the second processor core.

[0071] In some embodiments of the present disclosure, the hardware circuit to be tested may be a real hardware circuit built by physical devices, that is, the first processor core and the second processor core are hardware circuits built by physical devices. In some other embodiments of the present disclosure, the hardware circuit to be tested may be a hardware circuit written in a hardware language such as Verilog, imitating the behavior of the hardware.

[0072] The reference result is obtained, for example, by imitating the hardware circuit to be tested, performing the same functions as the hardware circuit to be tested, and processing the test data.

[0073] As Figure 1A shown, in some embodiments of the present disclosure, step S50 may further be included before step S30.

[0074] Step S50: Obtain a reference result according to the test data.

[0075] In some embodiments of the present disclosure, for example, a reference result is obtained by calculating the test data using a reference model.

[0076] The reference model is used to perform the same functions as the DUT. For example, the reference model can directly use the features of systemverilog to perform the same functions as the DUT, or can call other languages through interfaces such as the SystemVerilog Direct Programming Interface (DPI) to perform the same functions as the DUT.

[0077] Figure 2 The flowchart of another verification method provided by at least one embodiment of the present disclosure is shown.

[0078] As Figure 2 shown, based on the foregoing embodiments, this verification method may further include steps S60 and S70. For example, steps S60 and S70 may be executed before step S20, but are not limited thereto.

[0079] Step S60: Obtain the configuration result of the connector configured according to the configuration information.

[0080] Step S70: Determine whether the connector is configured as the target connection method according to the configuration result.

[0081] This method can verify the configuration result of the connector to ensure that when the connector is configured as the target connection method, the processor circuit is verified, thereby ensuring the accuracy of the verification result.

[0082] For step S60, for example, the configuration of the connector is monitored by a listener, so that the listener obtains the configuration result of the connector. Alternatively, the connector can output the configuration result.

[0083] For step S70, for example, it is determined whether the configuration result corresponds to the operand in the above register. If the configuration result corresponds to the operand in the register, the connector is configured as the target connection mode. If the configuration result does not correspond to the operand in the register, the connector is not configured as the target connection mode.

[0084] For example, the operand in the register is 1, and 1 indicates connection through a single bus. If the listener monitors that the configuration result is a single connection, the connector is configured as the target connection mode.

[0085] In some embodiments of the present disclosure, in response to the target connection mode being a multi-connection, before comparing the response result of the test data with the reference result, it further includes: obtaining the response result of the test data from multiple response results.

[0086] For example, a listener monitors multiple buses to obtain the response result on each bus

[0087] In the case where the target connection mode is a multi-connection, multiple buses can be respectively used to transmit different test data and the response results of the multiple test data. Therefore, before comparing the response result of the test data with the reference result, it is necessary to determine the response result corresponding to each test data from multiple response results.

[0088] In some embodiments of the present disclosure, for example, the response result of the test data can be determined by information such as the data source and destination in the test data and the response result.

[0089] Figure 3 The flowchart of another verification method provided by at least one embodiment of the present disclosure is shown.

[0090] As Figure 3 shown, based on the foregoing embodiments, this verification method may further include steps S80 and S90. For example, steps S80 and S90 can be executed after or before step S30, but are not limited thereto.

[0091] Step S80: Predict the target bus for transmitting the response result of the test data among multiple buses according to the allocation protocol of the multiple buses.

[0092] Step S90: Determine whether the response result of the test data comes from the target bus for verification.

[0093] For step S80, the allocation protocol can be predefined by those skilled in the art. The allocation protocol can, for example, define the bus used for different test data communications between DIEs.

[0094] For step S80, for example, DIE0 includes kernel circuit 01, kernel circuit 02, IO interface 01, IO interface 02, etc., and DIE1 includes kernel circuit 11, kernel circuit 12, IO interface 11, and IO interface 12, etc. The connection between DIE0 and DIE1 is through two buses (bus 0 and bus 1). In this embodiment, the allocation protocol is, for example, that kernel circuit 01 communicates with kernel circuit 11 through bus 0, kernel circuit 02 communicates with kernel circuit 12 through bus 1, IO interface 01 communicates with IO interface 11 through bus 0, and IO interface 02 communicates with IO interface 12 through bus 1.

[0095] Also, for example, the allocation protocol can include that the bus for transmitting the response result is the same as the bus for transmitting the access request. For example, if the access request from DIE0 to DIE1 is transmitted through bus 0, then the response result generated by DIE1 is also provided to DIE0 through bus 0.

[0096] In some embodiments of the present disclosure, the target bus for transmitting the response result of the test data can be predicted according to the allocation protocol of multiple buses.

[0097] For step S90, for example, if the response result of the test data comes from the target bus, the processor circuit passes the verification. If the response result of the test data does not come from the target bus, there is a problem with the processor circuit.

[0098] For example, the listener not only provides the response result for verification, but also provides the source of the response result, that is, from which bus the response result is actually obtained, and then determines whether the actual bus and the target bus are the same bus.

[0099] This embodiment can verify the bus for transmitting the response result, thereby enriching the perspective of verification and making the verification more sufficient and comprehensive.

[0100] Figure 4 Fig. shows a verification device 400 provided by at least one embodiment of the present disclosure for verifying a processor circuit.

[0101] As Figure 4 shown, the verification device 400 can include a connector 401, an excitation generation unit 402, and a comparison unit 403.

[0102] In this embodiment, the processor circuit includes a processor core 410 and a processor core 420. The processor core 410 and the processor core 420 are examples of a first processor core and a second processor core, respectively.

[0103] Connector 401 is configured to provide multiple optional connection modes, and is configured to couple with processor core 410 and processor core 420, and select a target connection mode for coupling processor core 410 and processor core 420 from the multiple connection modes according to configuration information.

[0104] The stimulus generating unit 402 is configured to generate test data and stimulate the processor using the test data, so that the processor core 410 and the processor core 420 communicate in a target connection manner through the connector and output a response result of the test data.

[0105] The comparison unit 403 is configured to compare the response result with the reference result for verification.

[0106] The verification device 400 can flexibly configure the connection mode between the first processor core and the second processor core according to the configuration information, and can be applied to a variety of test scenarios, thereby reducing the difficulty of verification.

[0107] In some embodiments of the present disclosure, for example, those skilled in the art may pre-write a variety of connection modes into the connector 401. The connector 401 may be, for example, a circuit written in a hardware language such as Verilog.

[0108] In some embodiments of the present disclosure, the multiple connection modes include single connection and multiple connection. Single connection is to couple the processor core 410 and the second processor core 420 through one bus, and multiple connection is to couple the processor core 410 and the second processor core 420 through multiple buses.

[0109] For more information about the various connection methods, please refer to the above Figure 1B , Figure 1C and Figure 1D Related description.

[0110] In some embodiments of the present disclosure, for example, in an initialization phase, the connector 401 selects a target connection method for coupling the processor core 410 and the processor core 420 from a plurality of connection methods according to configuration information.

[0111] The stimulus generation unit 402, for example, randomly generates a large amount of test data as test cases. For a description of the stimulus generation unit 402, please refer to the above Figure 1A See the relevant description of step S20 in .

[0112] In some embodiments of the present disclosure, the test data may be a read instruction or a write instruction. The excitation generation unit 402 includes: a read / write sub-unit configured to use the read instruction or the write instruction to excite the processor circuit, so that the processor core 410 and the processor core 420 execute the read instruction or the write instruction through the connector 401 in a target connection manner to generate a response result, and output the response result of the test data.

[0113] Hereinafter, the read instruction or the write instruction will be referred to as a read / write request, and some embodiments of the present disclosure will be described by taking the test data as the read / write request.

[0114] In some embodiments of the present disclosure, as Figure 4 shown, the verification device 400 includes an emulation unit 430, and the emulation unit 430 includes the above-mentioned excitation generation unit 402. In addition to generating a large amount of test data through the excitation generation unit 402, the emulation unit 430 also completes the read / write tasks for the hardware circuit to be tested.

[0115] The excitation generation unit 402 is further configured to generate configuration information and provide the configuration information to the connector. For example, the excitation generation unit 402 may be a sequence generator. For example, in the initialization stage, the sequence generator generates an excitation of the configuration information, and the excitation of the configuration information is sent by the emulation unit 430 to the connector 401. After the initialization is completed, the sequence generator block randomly generates excitations of various read / write requests for normal data interaction. For the configuration information, please refer to the relevant description above.

[0116] For example, in the initialization stage, the emulation unit 430 provides a sequence of configuration information generated by the excitation generation unit 402 to tell the connector 401 the current connection state expected by the user. After receiving the excitation generation unit 402, the connector 401 creates a corresponding connection (i.e., creates a target connection manner). After the initialization is completed, the emulation unit 430 generates excitations of read / write requests between the processor core 410 and the processor core 420, and these excitations of read / write requests are sent to the interface of the top-level connection, and then driven into the hardware circuit to be tested, completing the read / write access from the master device on one processor core to the slave device on another processor core.

[0117] The comparison unit 403, for example, receives the excitation of the read / write request to calculate a reference result, and on the other hand, receives the true value (i.e., the response result) generated by the hardware circuit to be tested. The comparison unit 403 compares the reference result with the true value generated by the hardware circuit to be tested to generate a comparison result, so as to verify the correctness of the hardware circuit to be tested.

[0118] As Figure 4As shown, the verification device 400 may further include a monitoring unit 404. The monitoring unit 404 is configured to monitor the test data generated by the excitation generation unit 402, and provide the test data to the comparison unit 403, and monitor the response result generated by the processor circuit, and provide the response result to the comparison unit 403.

[0119] In some embodiments of the present disclosure, the monitoring unit 404 is further configured to monitor the configuration information, and provide the configuration information to the comparison unit 403.

[0120] In some embodiments of the present disclosure, the monitoring unit 404 is further configured to monitor the configuration result of the configuration of the connector 401 according to the configuration information, and provide the configuration result to the comparison unit 403, so that the comparison unit 403 determines whether the connector 404 is configured as the target connection mode according to the configuration result.

[0121] For example, in the initialization stage, the monitoring unit 404 will monitor the excitation of the configuration information sent by the simulation unit 430 to the connector 401, and then send the monitored configuration information to the comparison unit 403. After the initialization is completed, the monitoring unit 404 will also monitor the excitation of the read / write request sent by the simulation unit 430 to the hardware circuit to be tested, and send the read / write request to the comparison unit 403 as well. At the same time, the monitoring unit 404 will also monitor the response result generated by the hardware circuit to be tested, and send the response result to the comparison unit 403 as well.

[0122] In some embodiments of the present disclosure, the monitoring unit 404 may monitor the response result generated by the hardware circuit to be tested from the bus.

[0123] In some embodiments of the present disclosure, the comparison unit is further configured to receive the test data and the response result from the monitoring unit, and obtain a reference result according to the test data, and compare the response result with the reference result.

[0124] For example, the comparison unit includes a reference model, and the comparison unit uses the reference model to calculate the test data to obtain a reference result. For the description of calculating the test data using the reference model to obtain a reference result, please refer to the relevant description above.

[0125] In some embodiments of the present disclosure, in the case where the target connection mode is multi-connection, the comparison unit 403 is further configured to: predict the target bus for transmitting the response result of the test data among multiple buses according to the allocation protocol of the multiple buses; and determine whether the response result of the test data comes from the target bus for verification.

[0126] For example, the comparison unit 403 executes step S80 and step S90 referred to above Figure 3 in the above.

[0127] At least one embodiment of the present disclosure further provides an electronic device, which includes a processor; a memory including one or more computer program instructions; when the one or more computer program instructions are stored in the memory and executed by the processor, the instructions for implementing the verification method provided by at least one embodiment of the present disclosure are realized. The electronic device can flexibly configure the connection mode of the first processor core and the second processor core according to the configuration information, can be applied to a variety of test scenarios, and reduces the verification difficulty.

[0128] Figure 5 It is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure. As Figure 5 shown, the electronic device 500 includes a processor 510 and a memory 520. The memory 520 is used to store non-transitory computer-readable instructions (such as one or more computer program modules). The processor 510 is used to run the non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are run by the processor 510, one or more steps of the verification method described above can be executed. The memory 520 and the processor 510 can be interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0129] For example, the processor 510 can be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units with data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) can be of X86 or ARM architecture, etc. The processor 510 can be a general-purpose processor or a dedicated processor, and can control other components in the electronic device 500 to perform desired functions.

[0130] For example, the memory 520 can include any combination of one or more computer program products. The computer program products can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory can include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory can include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules can be stored on the computer-readable storage media. The processor 510 can run one or more computer program modules to implement various functions of the electronic device 500. Various application programs and various data, as well as various data used and / or generated by the application programs, can also be stored in the computer-readable storage media.

[0131] It should be noted that in the embodiments of the present disclosure, the specific functions and technical effects of the electronic device 500 can refer to the description of the verification method above, and will not be elaborated here.

[0132] Figure 6 A schematic block diagram of another electronic device provided for some embodiments of the present disclosure. The electronic device 600 is, for example, suitable for implementing the authentication method provided by the embodiments of the present disclosure. The electronic device 600 may be a terminal device or the like. It should be noted that, Figure 6 The illustrated electronic device 600 is merely an example and will not impose any limitations on the functions and usage scope of the embodiments of the present disclosure.

[0133] As Figure 6 shown, the electronic device 600 may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 610, which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 620 or a program loaded from a storage device 680 into a random access memory (RAM) 630. In the RAM 630, various programs and data required for the operation of the electronic device 600 are also stored. The processing device 610, the ROM 620, and the RAM 630 are connected to each other through a bus 640. An input / output (I / O) interface 650 is also connected to the bus 640.

[0134] Generally, the following devices may be connected to the I / O interface 650: an input device 660 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 670 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 680 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 690. The communication device 690 may allow the electronic device 600 to communicate with other electronic devices wirelessly or wiredly to exchange data. Although Figure 6 the illustrated electronic device 600 shows various devices, it should be understood that it is not required to implement or have all the shown devices, and the electronic device 600 may alternatively implement or have more or fewer devices.

[0135] For example, according to the embodiments of the present disclosure, the above authentication method may be implemented as a computer software program. For example, the embodiments of the present disclosure include a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes program codes for executing the above authentication method. In such an embodiment, the computer program may be downloaded and installed from a network through the communication device 690, or installed from the storage device 680, or installed from the ROM 620. When the computer program is executed by the processing device 610, the functions defined in the authentication method provided by the embodiments of the present disclosure may be implemented.

[0136] At least one embodiment of the present disclosure also provides a computer-readable storage medium for storing non-transitory computer-readable instructions, which can implement the above verification method when executed by a computer. By using this computer-readable storage medium, the connection mode of the first processor core and the second processor core can be flexibly configured according to the configuration information, which can be applied to various test scenarios and reduces the verification difficulty.

[0137] Figure 7 FIG. is a schematic diagram of a storage medium provided by some embodiments of the present disclosure. As Figure 7 shown, the storage medium 700 is used to store non-transitory computer-readable instructions 710. For example, when the non-transitory computer-readable instructions 710 are executed by a computer, one or more steps in the verification method described above can be executed.

[0138] For example, the storage medium 700 can be applied to the above electronic device 500. For example, the storage medium 700 can be Figure 5 the memory 520 in the shown electronic device 500. For example, the relevant description of the storage medium 700 can refer to Figure 5 the corresponding description of the memory 520 in the shown electronic device 500, which will not be elaborated here.

[0139] The following points need to be noted:

[0140] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0141] (2) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0142] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A verification method for a processor circuit, wherein, The processor circuit includes at least a first processor core and a second processor core, and the method includes: Configuring a connector according to configuration information such that the connector selects a target connection mode from a plurality of optional connection modes to couple the first processor core and the second processor core; Generating test data for excitation, using the test data to excite the processor circuit such that the first processor core and the second processor core communicate through the connector in the target connection mode, and outputting a response result of the test data; and Comparing the response result with a reference result for verification; wherein the plurality of connection modes includes single connection and multi-connection, wherein the single connection couples the first processor core and the second processor core through a single bus, and the multi-connection couples the first processor core and the second processor core through a plurality of buses.

2. The method according to claim 1, further comprising: Generating the configuration information and providing the configuration information to the connector.

3. The method according to claim 1, wherein, Before comparing the response result with the reference result, the method further includes: Obtaining the reference result according to the test data.

4. The method according to claim 3, wherein, Obtaining the reference result according to the test data includes: Calculating the reference result by using a reference model for the test data.

5. The method according to claim 1, further comprising: Obtaining a configuration result of the connector configured according to the configuration information; and Determining whether the connector is configured as the target connection mode according to the configuration result.

6. The method according to claim 1, wherein, In a case where the target connection mode is the multi-connection, the method further includes: Predicting a target bus for transmitting the response result of the test data among the plurality of buses according to an allocation protocol of the plurality of buses; Determining whether the response result of the test data comes from the target bus for verification.

7. The method according to claim 1, wherein, The test data includes a read instruction or a write instruction between the first processor core and the second processor core, such that the first processor core and the second processor core communicate through the connector in the target connection mode, and outputting the response result of the test data, includes: Causing the first processor core and the second processor core to execute the read instruction or the write instruction through the connector in the target connection mode, generating the response result, and then outputting the response result of the test data.

8. A verification device for verifying a processor circuit, wherein, The processor circuit includes at least a first processor core and a second processor core, and the verification device includes: A connector configured to provide a plurality of optional connection modes, and configured to couple with the first processor core and the second processor core, and select a target connection mode for coupling the first processor core and the second processor core from the plurality of connection modes; wherein the plurality of connection modes includes single connection and multi-connection, wherein the single connection couples the first processor core and the second processor core through a single bus, and the multi-connection couples the first processor core and the second processor core through a plurality of buses; An excitation generation unit, configured to generate test data and use the test data to excite the processor circuit, so that the first processor core and the second processor core communicate through the connector in the target connection manner, and output a response result of the test data; and A comparison unit, configured to compare the response result with a reference result for verification.

9. The device according to claim 8, wherein, The excitation generation unit is further configured to generate the configuration information and provide the configuration information to the connector.

10. The device according to claim 8, wherein, The verification device further includes: A monitoring unit, configured to monitor the test data generated by the excitation generation unit and provide the test data to the comparison unit, and monitor the response result generated by the processor circuit and provide the response result to the comparison unit.

11. The device according to claim 10, wherein, The comparison unit is further configured to receive the test data and the response result from the monitoring unit, obtain a reference result according to the test data, and compare the response result with the reference result.

12. The device according to claim 11, wherein, The comparison unit includes a reference model, and the comparison unit uses the reference model to calculate the reference result from the test data.

13. The device according to claim 10, wherein, The monitoring unit is further configured to monitor the configuration information and provide the configuration information to the comparison unit.

14. The device according to claim 13, wherein, The monitoring unit is further configured to monitor a configuration result of the connector configured according to the configuration information, and provide the configuration result to the comparison unit, so that the comparison unit determines whether the connector is configured in the target connection manner according to the configuration result.

15. The device according to claim 8, wherein, In the case where the target connection manner is the multi-connection, the comparison unit is further configured to: Predict a target bus for transmitting the response result of the test data among the multiple buses according to the allocation protocol of the multiple buses; And Determine whether the response result of the test data comes from the target bus for verification.

16. The device according to claim 8, wherein, The test data is a read instruction or a write instruction between the first processor core and the second processor core, The excitation generation unit includes: A read / write sub-unit, configured to use the read instruction or the write instruction to excite the processor circuit, so that the first processor core and the second processor core execute the read instruction or the write instruction through the connector in the target connection manner to generate the response result, and output the response result of the test data.

17. An electronic device, comprising: A processor; A memory, including one or more computer program instructions; Wherein, the one or more computer program instructions are stored in the memory and, when executed by the processor, implement the instructions of the verification method according to any one of claims 1-7.

18. A computer-readable storage medium, non-transitorily storing computer-readable instructions, which can implement the verification method according to any one of claims 1-7 when the computer-readable instructions are executed by a processor.

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