Method for manufacturing semiconductor device and semiconductor manufacturing apparatus

Abstract

Embodiments of the present invention relate to a method for manufacturing a semiconductor device and a semiconductor manufacturing apparatus. According to one embodiment, a method for manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes: etching the first film using a first gas containing carbon and fluorine, thereby forming a recess in the first film and forming a second film in the recess. The method further includes treating the second film by using a second gas or a second liquid, and the treatment of the second film is performed without using plasma.

Description

[0001] [Cross - Reference to Related Applications]

[0002] This application claims priority based on Japanese Patent Application No. 2020-150725 (filing date: September 8, 2020). This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0003] Embodiments of the present invention relate to a method of manufacturing a semiconductor device and a semiconductor manufacturing apparatus. Background Art

[0004] When forming a recess in a film on a substrate, in order to suppress the shape of the recess from becoming bowing, a sidewall film is sometimes formed on the side surface of the recess. However, depending on the method of forming the sidewall film, the sidewall film sometimes cannot sufficiently protect the side surface of the recess. Summary of the Invention

[0005] The present invention provides a method of manufacturing a semiconductor device and a semiconductor manufacturing apparatus capable of appropriately forming a recess in a film on a substrate.

[0006] According to one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes etching the first film using a first gas containing carbon and fluorine, thereby forming a recess in the first film and forming a second film in the recess. The method further includes treating the second film by using a second gas or a second liquid, and the treatment of the second film is performed without using plasma. Brief Description of the Drawings

[0007] Figures 1A - 1C and Figures 2A - 2C is a cross-sectional view showing a method of manufacturing a semiconductor device according to a first embodiment.

[0008] Figure 3 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment.

[0009] Figure 4A , 4B is a top view showing an example of the structure of a semiconductor manufacturing apparatus according to a second embodiment.

[0010] Figure 5A , 5B is a cross-sectional view showing the structure of a semiconductor manufacturing apparatus according to a second embodiment and the structure of a semiconductor manufacturing apparatus according to a comparative example of the second embodiment.

[0011] Figure 6 is a cross-sectional view showing the structure of a semiconductor manufacturing apparatus according to a first modification of the second embodiment.

[0012] Figure 7A 、 7B is a cross-sectional view showing the structure of a semiconductor manufacturing apparatus according to the second and third modified examples of the second embodiment. Detailed Embodiment

[0013] Hereinafter, embodiments will be described with reference to the drawings. In Figures 1A through 7B the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0014] (First Embodiment)

[0015] Figures 1A - 1C and Figures 2A - 2C are cross-sectional views showing a method of manufacturing a semiconductor device according to the first embodiment. The semiconductor device of this embodiment is, for example, a three-dimensional memory.

[0016] First, a lower layer 2 is formed on a substrate 1, and a stacked film ([[]] Figure 1A ) alternately including a plurality of insulating layers 3 and a plurality of insulating layers 4 is formed on the lower layer 2. The insulating layer 3 is an example of a first insulating layer, and the insulating layer 4 is an example of a second insulating layer. Next, an upper layer 5 is formed on the stacked film, and a hard mask layer 6 ([[]] Figure 1A ) is formed on the upper layer 5. The lower layer 2, the insulating layer 3, the insulating layer 4, the upper layer 5, and the hard mask layer 6 are films to be processed on the substrate 1 of this embodiment. The film to be processed is an example of a first film.

[0017] The substrate 1 is, for example, a semiconductor substrate such as a silicon (Si) substrate. Figure 1A The X direction and the Y direction, which are parallel to and perpendicular to each other on the surface of the substrate 1, and the Z direction, which is perpendicular to the surface of the substrate 1, are shown. In this specification, the +Z direction is regarded as the upward direction, and the -Z direction is regarded as the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0018] The lower layer 2 includes, for example, insulating films such as a silicon oxide film (SiO2) and a silicon nitride film (SiN), and a conductive layer formed between the insulating films. The insulating layer 3 is, for example, a silicon nitride film. The insulating layer 4 is, for example, a silicon oxide film. The upper layer 5 includes, for example, insulating films such as a silicon oxide film and a silicon nitride film, and a conductive layer formed between the insulating films. The hard mask layer 6 is, for example, an organic film.

[0019] Next, an etching process for etching the film to be processed on the substrate 1 is performed ( Figure 1A)。Specifically, an opening for forming the memory hole M is formed in the hard mask layer 6 by photolithography and etching. Further, the insulating layer 3, the insulating layer 4, and the upper layer 5 are etched using the hard mask layer 6 as a mask. As a result, the memory hole M is formed halfway in the insulating layer 3, the insulating layer 4, and the upper layer 5. The memory hole M and the opening are examples of recesses. The etching process is an example of the first process.

[0020] The etching process is performed, for example, using a gas G1 containing a carbon element and a fluorine element. The gas G1 contains, for example, C x H y F z gas. Here, C represents carbon, H represents hydrogen, F represents fluorine, x represents an integer of 1 or more, y represents an integer of 0 or more, and z represents an integer of 1 or more (x ≧ 1, y ≧ 0, z ≧ 1). When y = 0, C x H y F z is fluorocarbon, and when y ≠ 0, C x H y F z is hydrofluorocarbon. C x H y F z gas is, for example, C4F6 gas, C4F8 gas, CH2F2 gas, etc. The gas G1 is an example of the first gas for treating the first film.

[0021] In the etching process, etching is performed by C x H y F z gas-generated C x H y F z plasma, and sidewall films 11 ( Figure 1A ) are formed on the surfaces of the insulating layer 3, the insulating layer 4, the upper layer 5, and the hard mask layer 6 exposed in the memory hole M and the opening. The sidewall film 11 is, for example, a fluorocarbon film containing a carbon element and a fluorine element. The sidewall film 11 is an example of the second film.

[0022] Next, a modification process ( Figure 1B ) for modifying the sidewall film 11 is performed. In the present embodiment, the sidewall film 11 is modified, for example, by reducing the sidewall film 11. Figure 1B The modified sidewall film 12 obtained by modifying the sidewall film 11 is shown. The modification process is an example of the second process.

[0023] The modification treatment is performed, for example, using a gas G2 containing hydrogen element. The gas G2 contains, for example, HCOOH (formic acid) gas. Here, O represents oxygen. Formic acid is a liquid under normal temperature and pressure. In the present embodiment, HCOOH gas is generated from HCOOH liquid, and the sidewall film 11 is modified using the HCOOH gas. In the modification treatment, the sidewall film 11 is modified by exposing the sidewall film 11 to the HCOOH gas. In the present embodiment, the etching treatment is performed using plasma. In contrast, the modification treatment is performed without using plasma. The gas G2 is an example of the second gas for treating the second film.

[0024] Hereinafter, the modification treatment of the sidewall film 11 will be described in detail.

[0025] As described above, the sidewall film 11 is, for example, a fluorocarbon film containing carbon element and fluorine element. The sidewall film 11 functions as a protective film for the film to be processed during etching. However, when high-energy ions are incident on the sidewall film 11, the sidewall film 11 may sometimes assist in etching. That is, the sidewall film 11 may promote the etching of the film to be processed in the memory hole M. The reason is that the sidewall film 11 helps as a supply source of CF a in the following formula (1).

[0026] SiO2 + CF a → SiF b ↑ + CO c ↑ (1)

[0027] Here, a, b, and c represent the composition ratios. As described above, the insulating layer 4 is, for example, a silicon oxide film (SiO2 film). In addition, the lower layer 2 and the upper layer 5 may contain a silicon oxide film. These silicon oxide films may be etched by the reaction of formula (1).

[0028] According to formula (1), when the amount of fluorine atoms in the sidewall film 11 is reduced, the supply amount of CF a can be reduced, and the etching of the film to be processed in the memory hole M can be suppressed. Therefore, in the modification treatment, the sidewall film 11 is modified. Specifically, the fluorine atoms in the sidewall film 11 react with the hydrogen atoms in the gas G2 (reduction reaction) and are removed as hydrogen fluoride. Thus, a modified sidewall film 12 richer in carbon than the sidewall film 11 can be obtained, and the fluorine concentration in the modified sidewall film 12 can be made lower than the fluorine concentration in the sidewall film 11. That is, by treating with the gas G2, the ratio of the carbon amount to the fluorine amount in the modified sidewall film 12 becomes larger than the ratio of the carbon amount to the fluorine amount in the sidewall film 11. Thus, even when high-energy ions are incident on the modified sidewall film 12, the reaction of formula (1) hardly occurs, and the etching of the film to be processed in the memory hole M is suppressed.

[0029] Thus, according to the present embodiment, it is possible to suppress the assistance of the sidewall film 11 to etching, and the modified sidewall film 12 can function as a protective film. Thus, it is possible to suppress the shape of the memory hole M from becoming arcuate.

[0030] Next, the annealing in the modification treatment of the sidewall film 11 will be described in detail.

[0031] It is considered that the modification treatment and the etching treatment are also performed using the plasma generated by the gas G2. By using this plasma, the modification treatment can be promoted. However, this plasma may not reach a deeper location inside the memory hole M. In this case, at a deeper location inside the memory hole M, the sidewall film 11 is not sufficiently modified, and it may not be possible to sufficiently suppress the etching of the film to be processed inside the memory hole M. It is considered that this problem becomes more obvious when, for example, the capacity of the three-dimensional memory becomes larger and the aspect ratio of the memory hole M becomes higher.

[0032] Therefore, in the modification treatment of the present embodiment, the sidewall film 11 is modified by exposing the sidewall film 11 to the gas G2. Thus, it is possible to modify the sidewall film 11 without using plasma. Through this modification treatment, the sidewall film 11 can be sufficiently modified up to a deeper location inside the memory hole M, and a modified sidewall film 12 that is more conformal than the case of using plasma can be formed. In addition, exposing the sidewall film 11 to the gas G2 includes, for example, annealing the sidewall film 11 in an environment of the gas G2, or exposing the sidewall film 11 to the gas G2 at a specified temperature.

[0033] Examples of the gas contained in the gas G2 are H2 (hydrogen) gas and the HCOOH (formic acid) gas. In the case of performing the modification treatment using H2 gas, in order to sufficiently reduce the fluorocarbon film (sidewall film 11), it is desirable to perform annealing in an environment of H2 gas, and it is desirable that the annealing be performed at 300°C or higher. On the other hand, generally, the upper limit of the process temperature in a dry etching chamber is 100 - 150°C, and it is difficult to reduce the fluorocarbon film (sidewall film 11) with H2 gas below this upper limit temperature. Therefore, when performing the etching treatment in this chamber, it is difficult to continue the modification treatment using H2 gas in this chamber. Therefore, in the case of performing the modification treatment using H2 gas, it is desirable that this modification treatment and the etching treatment be performed in different chambers.

[0034] On the other hand, the reducing ability of HCOOH gas is higher than that of H2 gas, and its boiling point is low, at 100 °C. Therefore, in the case of using HCOOH gas for the modification treatment, annealing is performed at 100 to 150 °C in an HCOOH gas environment. By performing this annealing at 100 to 150 °C, the fluorocarbon film (sidewall film 11) can be sufficiently reduced. Thus, in the case of using HCOOH gas for the modification treatment, the modification treatment and the etching treatment can be performed in the same chamber, that is, the modification treatment and the etching treatment can be performed in-situ.

[0035] The modification treatment can also be performed by supplying HCOOH gas to an etching chamber at a specified temperature. For example, HCOOH gas can be supplied after the temperature of the etching chamber is set to a temperature below the upper limit of the process temperature in the etching chamber. For example, HCOOH gas can be supplied to an etching chamber at 150 °C. In addition, usually, the temperature of the etching chamber during the etching treatment is from room temperature to 60 °C. When the modification treatment of the sidewall film is sufficiently performed, HCOOH gas can be supplied to an etching chamber at a temperature similar to that of the etching treatment. In addition, the temperature of the etching chamber is, for example, the temperature of the stage in the etching chamber. By using HCOOH gas, the manufacturing steps of the semiconductor device of the present embodiment can be simplified, and the productivity of the semiconductor device can be improved.

[0036] Formic acid (HCOOH) is a liquid substance under normal temperature and pressure. Thus, in the modification treatment of the present embodiment, HCOOH gas is generated from HCOOH liquid, and the sidewall film 11 is modified using this HCOOH gas. Since the boiling point of HCOOH gas is relatively low at 100 °C, it can be vaporized by a vaporizer and introduced into the chamber. In addition, gas G2 can contain gases other than HCOOH gas. For example, it can contain other gases obtained from substances that are liquid under normal temperature and pressure. Furthermore, in the modification treatment, the sidewall film 11 can also be modified by annealing the sidewall film 11 in an environment of a liquid rather than gas G2. This liquid is an example of the second liquid. An example of this liquid is HCOOH liquid. Moreover, in the modification treatment, the sidewall film 11 can also be modified by exposing the sidewall film 11 to a liquid rather than gas G2 at a specified temperature.

[0037] The gas contained in gas G2 can be an organic gas such as HCOOH gas, or an inorganic gas. Examples of organic gases are HCHO (formaldehyde) gas and CH3OH (methanol) gas. Examples of inorganic gases are gases of substances having a silyl group (Si-R3), such as SiH4 gas, Si2H6 gas, SiH2[NH(C4H9)]2 gas, etc. Herein, Si represents silicon and N represents nitrogen. Other examples of inorganic gases are AsH3 (arsine) gas, B2H6 (diborane) gas, H2Se (hydrogen selenide) gas, PH3 (phosphine) gas, GeH4 (germane), etc. In addition, an organic liquid or an inorganic liquid can also be used in the modification treatment instead of gas G2. Further, when using SiH4 gas for the modification treatment, a substitution reaction in which F atoms are substituted by H atoms as shown in the following formula (2) is expected to occur.

[0038] (-CF2-) n +SiH4→(-CH2-) n +SiF4↑ (2)

[0039] Herein, n represents an integer of 1 or more.

[0040] In addition, gas G2 can also contain other elements on the basis of containing hydrogen element, or contain other elements without containing hydrogen element. An example of this element is sulfur element. For example, gas G2 can contain H2S (hydrogen sulfide) gas, SF6 (sulfur hexafluoride) gas or COS (carbonyl sulfide) gas on the basis of containing HCOOH gas, or contain H2S (hydrogen sulfide) gas, SF6 (sulfur hexafluoride) gas or COS (carbonyl sulfide) gas without containing HCOOH gas. For example, when gas G2 contains H2S gas, the sidewall film 11 is modified by annealing the sidewall film 11 in an environment of H2S gas. A liquid containing sulfur element can also be used for the modification treatment instead of gas G2 containing sulfur element.

[0041] Furthermore, gas G2 can also contain He (helium) gas, Ar (argon) gas, Kr (krypton) gas or Xe (xenon) gas on the basis of containing a gas containing hydrogen element and / or sulfur element.

[0042] Thereafter, in the present embodiment, the memory hole M is completed by alternately repeating the etching treatment and the modification treatment. In other words, the memory hole M of the present embodiment is formed by alternately repeating the supply of gas G1 and gas G2. In the modification treatment, gas G2 is supplied and the annealing is performed. Hereinafter, these treatments will be described in detail.

[0043] In Figure 1BAfter the step of Figure 1C ), an etching process for etching the insulating layer 3 and the insulating layer 4 is performed again using the gas G1 ( x H y F z ). As a result, a process of forming the memory hole M is performed, and the bottom surface of the memory hole M descends. In this etching process, etching is performed by C

[0044] Next, a modification process for modifying the sidewall film 13 is performed again using the gas G2 ( Figure 2A ). Figure 2A The modified sidewall film 14 obtained by the modification of the sidewall film 13 is shown. In this modification process, the sidewall film 13 is modified by annealing the sidewall film 13 in an HCOOH gas environment. The modified sidewall film 14 has the same properties as the modified sidewall film 12.

[0045] Next, an etching process for etching the insulating layer 3 and the insulating layer 4 is performed again using the gas G1 ( Figure 2B ). As a result, a process of forming the memory hole M is performed, and the bottom surface of the memory hole M further descends. In Figure 2B , the memory hole M penetrates the lower layer 2 and reaches the substrate 1, and the memory hole M is completed. In this etching process, etching is performed by C x H y F z ). The sidewall film 15 is formed on the surfaces of the lower layer 2, the insulating layer 3, and the insulating layer 4 exposed in the memory hole M. The sidewall film 15 has the same properties as the sidewall films 11 and 13 and is formed below the modified sidewall film 14. In addition, when the memory hole M is not completed in the step of Figure 2B , the modification process and the etching process are alternately repeated until the memory hole M is completed.

[0046] Next, after removing the modified sidewall films 12 and 14, the sidewall film 15, and the hard mask layer 6, a memory insulating film 7 and a channel semiconductor layer 8 are sequentially formed in the memory hole M ( Figure 2C ). The memory insulating film 7 is formed by sequentially forming a barrier insulating film, a charge storage layer, and a tunnel insulating film in the memory hole M as described below. In addition, in the step of Figure 2C , a memory insulating film 7, a channel semiconductor layer 8, and a core insulating film may also be sequentially formed in the memory hole M.

[0047] Thereafter, various interlayer insulating films, plug layers, wiring layers, etc. are formed on the substrate 1. The semiconductor device of the present embodiment is manufactured in this way.

[0048] In addition, Figures 1A through 2C The method shown in can also be applied to the film to be processed other than the lower layer 2, the insulating layer 3, the insulating layer 4, the upper layer 5, and the hard mask layer 6, and the recesses other than the memory hole M. This method can also be applied to, for example, the case of forming contact holes and trenches in the interlayer insulating film, and the case of forming memory holes in a stacked film alternately including multiple electrode layers (e.g., polysilicon layers) and multiple insulating layers (e.g., silicon oxide films).

[0049] The multi-layer insulating layer 3 of the present embodiment is replaced with a multi-layer electrode layer by a replacement step performed after the steps shown in Figures 1A through 2C . In the replacement step, by removing these insulating layers 3, a plurality of cavities are formed between the insulating layers 4, and the multi-layer electrode layer is embedded in these cavities. By Figure 3 , an example of such an electrode layer is described.

[0050] Figure 3 is a cross-sectional view showing the structure of the semiconductor device of the first embodiment. Figure 3 An example of a semiconductor device manufactured by the method of the present embodiment is shown.

[0051] Figure 3 The storage unit portion and the stepped contact portion of the three-dimensional memory are shown. In Figure 3 , the lower layer 2 includes an insulating film 2a, a source-side conductive layer 2b, and an insulating film 2c, and the upper layer 5 includes a covering insulating film 5a, a drain-side conductive layer 5b, an interlayer insulating film 5c, and an interlayer insulating film 5d. In addition, the multi-layer insulating layer 3 is replaced with a multi-layer electrode layer 3' including a tungsten (W) layer or the like.

[0052] Figure 3 The barrier insulating film 7a, the charge storage layer 7b, and the tunnel insulating film 7c included in the memory insulating film 7 are also shown. The memory insulating film 7 and the channel semiconductor layer 8 are formed, for example, by sequentially forming the barrier insulating film 7a, the charge storage layer 7b, and the tunnel insulating film 7c on the surface of the memory hole M, removing the barrier insulating film 7a, the charge storage layer 7b, and the tunnel insulating film 7c from the bottom of the memory hole M, and then embedding the channel semiconductor layer 8 in the memory hole M. At this time, the channel semiconductor layer 8 and the core insulating film may also be sequentially embedded in the memory hole M. The channel semiconductor layer 8 is electrically connected to the diffusion layer L in the substrate 1.

[0053] Figure 3Also shown are a plurality of contact holes H formed in the upper layer 5 and a plurality of contact plugs 9 formed in these contact holes H. Each contact plug 9 is formed so as to be electrically connected to the corresponding electrode layer 3'.

[0054] As described above, the memory hole M of the present embodiment is formed by performing an etching process using the gas G1 and a modification process using the gas G2. In the etching process, the memory hole M is etched, and sidewall films (such as sidewall film 11) are formed in the memory hole M. In the modification process, the sidewall films are modified by exposing the sidewall films to the gas G2.

[0055] Thus, according to the present embodiment, it is possible to suppress the shape of the memory hole M from becoming bow-shaped by the sidewall films, and a memory hole M with a high aspect ratio can be appropriately realized. Furthermore, according to the present embodiment, the sidewall films can be sufficiently modified by heat up to a deep location in the memory hole M, and the memory hole M can be appropriately protected by the modified sidewall films (such as modified sidewall film 12). In this way, according to the present embodiment, by modifying the sidewall films without using plasma, the memory hole M can be appropriately formed in the film to be processed on the substrate 1.

[0056] In addition, the sidewall films of the present embodiment are modified, for example, using HCOOH gas as the gas G2. Thus, the sidewall films can be reduced (modified) by the gas G2 having a high reduction ability. As a result, the annealing temperature can be lowered, and the etching process and the modification process can be performed in the same chamber. In this way, according to the present embodiment, by modifying the sidewall films using HCOOH gas, the memory hole M can be appropriately formed in the film to be processed on the substrate 1. In this case, the sidewall films of the present embodiment are modified by HCOOH gas and the heat, but if the heat is not required, the sidewall films can also be modified using HCOOH gas without annealing. In addition, the sidewall films can also be modified using a gas other than HCOOH gas.

[0057] (Second Embodiment)

[0058] Figure 4A 、 4B is a top view showing an example of the structure of the semiconductor manufacturing apparatus of the second embodiment.

[0059] Figure 4A Shows a first example of the structure of the semiconductor manufacturing apparatus of the present embodiment. The semiconductor manufacturing apparatus of the first example includes a plurality of FOUP (Front-Opening Unified Pod) stations 21, a load lock vacuum chamber 22, a transfer chamber 23, a plurality of processing chambers 24, and a control unit 25.

[0060] Each FOUP stage 21 is used to place a FOUP (not shown) for accommodating the substrate 1. When the substrate 1 is carried into the semiconductor manufacturing apparatus, the FOUP is placed on any one of the FOUP stages 21, and the substrate 1 in the FOUP is carried into the load lock vacuum chamber 22. On the other hand, when the substrate 1 is carried out of the semiconductor manufacturing apparatus, the substrate 1 in the load lock vacuum chamber 22 is carried out into the FOUP on any one of the FOUP stages 21. The substrate 1 carried into the semiconductor manufacturing apparatus of the first example is carried into any one of the processing chambers 24 via the load lock vacuum chamber 22 and the transfer chamber 23.

[0061] Each processing chamber 24 has a function of performing the etching process and a function of performing the modification process (reduction process). In the first example, the substrate 1 is carried into any one of the processing chambers 24, and the etching process and the modification process are alternately repeated on the substrate 1 in the processing chamber 24. In the etching process, the memory hole M in the processed film is etched by treating the processed film on the substrate 1 with the gas G1, and a sidewall film (sidewall film 11, etc.) is formed in the memory hole M. In the modification process, the sidewall film is modified into a modified sidewall film (modified sidewall film 12, etc.) by treating the sidewall film with the gas G2. In this modification process, instead of annealing the sidewall film in the environment of the gas G2, the sidewall film can be modified by exposing the sidewall film to the gas G2 in the processing chamber 24 at a specified temperature.

[0062] The semiconductor manufacturing apparatus of the first example is used, for example, in the case of using HCOOH gas as the gas G2. Each processing chamber 24 can be used for dry etching, and the upper limit of the process temperature in the chamber of each processing chamber 24 is generally 100 to 150 °C. In this case, annealing cannot be performed at a temperature higher than 150 °C in each processing chamber 24. However, in the case of using HCOOH gas as the gas G2, the sidewall film can be sufficiently modified by annealing at 100 to 150 °C. According to the first example, the etching process and the modification process can be performed in situ in the same processing chamber 24.

[0063] The control unit 25 controls various operations of the semiconductor manufacturing apparatus. The control unit 25 controls, for example, the transfer of the substrate 1 and the etching process and the modification process in each processing chamber 24. Examples of the control unit 25 are a processor, a circuit, a computer, etc.

[0064] Figure 4B A second example showing the structure of the semiconductor manufacturing apparatus of the present embodiment. The semiconductor manufacturing apparatus of the second example includes an etching chamber 26 and a reduction chamber 27 instead of the plurality of processing chambers 24.

[0065] The etching chamber 26 has the function of performing the etching process. The reduction chamber 27 has the function of performing the modification process (reduction process). In the second example, the substrate 1 is alternately and repeatedly carried into the etching chamber 26 and the reduction chamber 27. The etching process is performed on the substrate 1 in the etching chamber 26, and the modification process is performed on the substrate 1 in the reduction chamber 27. In the etching process, the memory hole M in the processed film is etched by treating the processed film on the substrate 1 with the gas G1, and sidewall films (such as sidewall film 11) are formed in the memory hole M. In the modification process, the sidewall film is modified into a modified sidewall film (such as modified sidewall film 12) by treating the sidewall film with the gas G2. In this modification process, instead of annealing the sidewall film in the environment of the gas G2, the sidewall film can be modified by exposing the sidewall film to the gas G2 in the reduction chamber 27 at a specified temperature.

[0066] The semiconductor manufacturing apparatus of the second example is used, for example, in a case where H2 gas is used as the gas G2. The etching chamber 26 can be used for dry etching, and the upper limit of the process temperature in the chamber of the etching chamber 26 is generally 100 to 150 °C. In this case, annealing cannot be performed at a temperature higher than 150 °C in the etching chamber 26. On the other hand, when H2 gas is used as the gas G2, it is desired to modify the sidewall film by annealing at a temperature of 300 °C or higher. Therefore, the modification process in the second example is performed in the reduction chamber 27 provided separately from the etching chamber 26. In addition, the reduction chamber 27 can also perform the modification process using a liquid such as HCOOH liquid instead of the gas G2. In this case, the reduction chamber 27 can also be used as a liquid treatment chamber such as a wet treatment chamber.

[0067] The control unit 25 controls various operations of the semiconductor manufacturing apparatus in the same manner as in the first example. The control unit 25 controls, for example, the transfer of the substrate 1, the etching process in the etching chamber 26, and the modification process in the reduction chamber 27.

[0068] Figure 5A 、 5B is a cross-sectional view showing the structure of the semiconductor manufacturing apparatus of the second embodiment and the structure of the semiconductor manufacturing apparatus of the comparative example of the second embodiment.

[0069] Figure 5A Shows the structure of the semiconductor manufacturing apparatus of the present embodiment. Specifically, it shows Figure 4A the structure of the processing chamber 24. In Figure 5AIn this case, the processing chamber 24 includes a dry etching chamber 31, a stage 32, a gas supply unit 33, an MFC (Mass Flow Controller) 34, a showerhead 35, an annealing unit 36, pipes 41, 42, and heaters 43, 44, 45. The dry etching chamber 31 is an example of a housing unit, the gas supply unit 33 is an example of a first supply unit, and the MFC 34 is an example of a first machine. The pipe 41 is an example of a second flow path, and the pipe 42 is an example of a first flow path. The heater 43 is an example of a second heating unit, the heater 44 is an example of a first heating unit, and the heater 45 is an example of a third heating unit.

[0070] The dry etching chamber 31 can accommodate the substrate 1 to be dry-etched. In the present embodiment, the etching process and the modification process for the substrate 1 are performed in the dry etching chamber 31.

[0071] The stage 32 is used to support the substrate 1 in the dry etching chamber 31.

[0072] The gas supply unit 33 supplies a gas capable of processing the film on the substrate 1 to the dry etching chamber 31. For example, the gas supply unit 33 supplies a gas G1 for etching the film to be processed and forming a sidewall film (such as the sidewall film 11), and a gas G2 for modifying the sidewall film into a modified sidewall film (such as the modified sidewall film 12). The gases G1 and G2 are sequentially supplied to the dry etching chamber 31 via the pipe 41, the MFC 34, and the pipe 42, and are supplied to the showerhead 35 in the dry etching chamber 31.

[0073] The MFC 34 has a function of measuring the mass flow rate of the gas and a function of controlling the mass flow rate of the gas. The MFC 34 of the present embodiment is disposed between the pipe 41 and the pipe 42, and can measure and control the flow rate of the gas supplied from the gas supply unit 33 to the dry etching chamber 31. For example, the control unit 25 ( Figure 4A ) can receive the flow rate of the gas measured by the MFC 34 and control the flow rate of the gas via the MFC 34.

[0074] The showerhead 35 injects the gas supplied by the gas supply unit 33 into the dry etching chamber 31. The showerhead 35 of the present embodiment is disposed near the top of the dry etching chamber 31 and injects the gas downward in the dry etching chamber 31. Thereby, the film on the substrate 1 placed on the stage 32 can be processed using this gas.

[0075] The annealing unit 36 anneals the substrate 1 on the stage 32. Thereby, the sidewall film on the substrate 1 can be annealed during the modification process. The annealing unit 36 of the present embodiment is provided inside the stage 32.

[0076] The heater 43 is disposed around the pipe 41 to heat the gas passing through the pipe 41. Thus, the heater 43 can heat the gas from the gas supply unit 33 toward the MFC 34. The heater 43 of the present embodiment has, for example, a cylindrical shape surrounding the pipe 41.

[0077] The heater 44 is disposed around the pipe 42 to heat the gas passing through the pipe 42. Thus, the heater 44 can heat the gas from the MFC 34 toward the dry etching chamber 31. The heater 44 of the present embodiment has, for example, a cylindrical shape surrounding the pipe 42.

[0078] The heater 45 is used to heat the showerhead 35 and the space between the top in the dry etching chamber 31 and the showerhead 35. Thus, the heater 45 can heat the gas in the showerhead 35 and the gas toward the showerhead 35 in the dry etching chamber 31.

[0079] In Figure 5A the processing chamber 24, for example, CH x H y F z gas is used as the gas G1, and HCOOH gas is used as the gas G2. Further, in the reforming process, the sidewall film on the substrate 1 is annealed at an annealing temperature of 100 to 150°C. In this case, when the temperature of the HCOOH gas is lower than the annealing temperature, the temperature of the sidewall film decreases during the annealing process, which may cause insufficient reforming of the sidewall film.

[0080] In the present embodiment, in order to suppress the occurrence of this phenomenon, when the gas G2 is supplied from the gas supply unit 33 for the reforming process, the gas G2 is heated by the heaters 43, 44, and 45. Thus, during the period when the gas G2 reaches the sidewall film from the gas supply unit 33, a significant decrease in the temperature of the gas G2 can be suppressed.

[0081] In order to effectively suppress the temperature decrease of the gas G2, it is desirable to heat the gas G2 as close as possible to the sidewall film. Thus, when the gas G2 is heated by the heater 44 and the heater 45, compared with the case where the gas G2 is heated by the heater 43, the temperature decrease of the gas G2 can be effectively suppressed.

[0082] In addition, the heater 43 can be used, for example, to suppress the HCOOH gas from returning to the HCOOH liquid due to cooling. Further, the heaters 44 and 45 can be used, for example, to suppress the HCOOH gas from returning to the HCOOH liquid and to supply the high-temperature HCOOH gas to the sidewall film.

[0083] The heater 44 of the present embodiment extends from the outlet of the MFC 34 to the inlet of the dry etching chamber 31. That is, one end of the heater 44 extends to the outlet of the MFC 34, and the other end of the heater 44 extends to the inlet of the dry etching chamber 31. Thus, it is possible to suppress the cooling of the gas G2 between one end of the heater 44 and the outlet of the MFC 34, and to suppress the cooling of the gas G2 between the other end of the heater 44 and the inlet of the dry etching chamber 31. Similarly, the heater 43 of the present embodiment also extends to the inlet of the MFC 34.

[0084] Figure 5A The operation of the processing chamber 24 is controlled by the control unit 25( Figure 4A ). The control unit 25 controls, for example, the on and off of the annealing unit 36, the annealing time, the annealing temperature, the on and off of the heaters 43, 44, 45, the heating time, the heating temperature, and the operations of the chamber 31, the stage 32, the gas supply unit 33, the MFC 34, the shower head 35, etc.

[0085] Figure 5B Shows the structure of a semiconductor manufacturing apparatus according to a comparative example of the present embodiment. Specifically, and Figure 5A similarly shows the structure of the processing chamber 24. However, the processing chamber 24 of this comparative example does not include the heaters 44 and 45. Therefore, in this comparative example, during the period when the gas G2 reaches the sidewall film from the gas supply unit 33, it is possible to cause a significant decrease in the temperature of the gas G2. In addition, it should be noted that the heater 43 of this comparative example does not extend to the inlet of the MFC 34. This may also prevent the suppression of the temperature decrease of the gas G2.

[0086] Figure 6 Is a cross-sectional view showing the structure of a semiconductor manufacturing apparatus according to a first modification of the second embodiment.

[0087] Figure 6 Shows the structure of the processing chamber 24 of this modification. The structure of the processing chamber 24 of this modification is the same as that of the processing chamber 24 shown in Figure 5A except for the following aspects. That is, in this modification, the gas supply unit 33, the MFC 34, the pipes 41, 42, and the heater 43 are replaced with two sets of gas supply units 33a, 33b, MFCs 34a, 34b, pipes 41a, 41b, pipes 42a, 42b, and heaters 43a, 43b.

[0088] The structures and functions of the gas supply unit 33a, MFC 34a, pipes 41a and 42a, and heater 43a are the same as those of the gas supply unit 33, MFC 34, pipes 41 and 42, and heater 43. Furthermore, the structures and functions of the gas supply unit 33b, MFC 34b, pipes 41b and 42b, and heater 43b are the same as those of the gas supply unit 33, MFC 34, pipes 41 and 42, and heater 43. Among them, in this variation, the gas supply unit 33a supplies the gas G1, and the gas supply unit 33b supplies the gas G2. The dry etching chamber 31 is an example of a housing unit, the gas supply unit 33b is an example of a first supply unit, the MFC 34b is an example of a first machine, the gas supply unit 33a is an example of a second supply unit, and the MFC 34a is an example of a second machine. The pipe 41b is an example of a second flow path, the pipe 42b is an example of a first flow path, and the pipe 41a is an example of a third flow path. The heater 43b is an example of a second heating unit, the heater 44 is an example of a first heating unit, the heater 45 is an example of a third heating unit, and the heater 43a is an example of a fourth heating unit.

[0089] The processing chamber 24 of this variation only has the heater 44 around the pipe 42b among the pipes 42a and 42b. Thus, by heating the gas G2 using the heaters 43b, 44, etc., it is possible to suppress a significant decrease in the temperature of the gas G2 during the period when the gas G2 reaches the sidewall film from the gas supply unit 33b. Furthermore, it is possible to suppress a significant change in the temperature of the gas G2 upstream and downstream of the MFC 34b, and it is possible to appropriately control the flow rate of the gas G2.

[0090] Figure 7A 、 7B It is a cross-sectional view showing the structure of a semiconductor manufacturing apparatus according to the second and third variations of the second embodiment.

[0091] Figure 7A It shows the structure of the processing chamber 24 of the second variation. The structure of the processing chamber 24 of this variation is the same as that of the processing chamber 24 of the first variation except for the following aspects. That is, in this variation, the gas supply unit 33a, MFC 34a, pipe 41a, and heater 43a of the first variation are replaced with N sets (N is an integer of 2 or more) of the gas supply unit 33a, MFC 34a, pipe 41a, and heater 43a.

[0092] The semiconductor manufacturing apparatus of this variation is used, for example, in a case where N types of gases are supplied as the gas G1 by N gas supply units 33a. In addition, the pipe 42a of this variation has N branches, and these branches are connected to N MFCs 34a.

[0093] Figure 7BThe structure of the processing chamber 24 showing the second modification example. The structure of the processing chamber 24 in this modification example is the same as that of the processing chamber 24 in the second modification example except for the following aspects. That is, the pipes 42a and 42b in this modification example merge. Thereby, the total length of the pipes 42a and 42b can be shortened.

[0094] As described above, the semiconductor manufacturing apparatus of the present embodiment includes the processing chamber 24 capable of performing both the etching process and the modification process, and the heaters 43(43b), 44, and 45 for suppressing the temperature drop of the gas G2. Thereby, according to the present embodiment, the manufacturing method of the semiconductor device of the first embodiment can be implemented in a suitable form by this semiconductor manufacturing apparatus.

[0095] In addition, in Figure 5A the processing chamber 24, instead of annealing the sidewall film in the environment of the gas G2 to modify the sidewall film, the sidewall film can be modified by exposing the sidewall film to the gas G2 in the processing chamber 24 at a specified temperature. In this case, the temperature of the processing chamber 24 can be adjusted to the specified temperature by the heater 45, can be adjusted to the specified temperature by the annealing unit 36, or can be adjusted to the specified temperature by other mechanisms. In addition, in the case of modifying the sidewall film by exposing the sidewall film to the gas G2, the annealing unit 36 may not be provided in Figure 5A the processing chamber 24. This also applies to Figure 6 , Figure 7A and Figure 7B the processing chamber 24.

[0096] In addition, Figure 5A the structure of the processing chamber 24 can also be applied to the reduction chamber 27( Figure 4B ). In this case, the gas supply unit 33 is used to supply only the gas G2 among the gases G1 and G2. This also applies to Figure 6 , Figure 7A and Figure 7B the processing chamber 24.

[0097] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their variations are included in the scope and gist of the invention, and are also included in the invention described in the claims and its equivalent scope.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a first film on a substrate; etching the first film using a first gas containing carbon and fluorine, thereby forming a recess in the first film and forming a second film in the recess, the second film being a fluorocarbon film containing carbon and fluorine elements; and treating the second film by using a second gas or a second liquid; the second gas or the second liquid lowers the fluorine concentration in the second film and contains at least any one of hydrogen sulfide, sulfur fluoride, and carbonyl sulfide; the treatment of the second film is performed without using plasma.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the treatment of the second film is performed by at least any one of the following: annealing the second film in an environment of the second gas or the second liquid; and exposing the second film to the second gas or the second liquid at a specified temperature.

3. The manufacturing method of the semiconductor device according to claim 1, wherein the first gas contains C x H y F z gas, C represents carbon, H represents hydrogen, F represents fluorine, x represents an integer of 1 or more, y represents an integer of 0 or more, and z represents an integer of 1 or more.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the second gas or the second liquid contains hydrogen.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the second gas or the second liquid contains at least any one of hydrogen, formic acid, formaldehyde, methanol, arsine, borane, hydrogen selenide, phosphine, germane, and a substance having a silyl group.

6. The method for manufacturing a semiconductor device according to claim 1, wherein the second gas contains helium, argon, krypton, or xenon.

7. The method for manufacturing a semiconductor device according to claim 1, wherein the second gas contains a gas derived from a substance that is liquid at normal temperature and pressure.

8. The method for manufacturing a semiconductor device according to claim 1, wherein the ratio of the amount of carbon to the amount of fluorine in the second film increases by treatment with the second gas or the second liquid.

9. The method for manufacturing a semiconductor device according to claim 1, wherein the first film is formed by alternately laminating a plurality of first insulating layers and a plurality of second insulating layers, or is formed by alternately laminating a plurality of electrode layers and a plurality of insulating layers.

10. The method for manufacturing a semiconductor device according to claim 1, wherein a first treatment of etching the first film using the first gas and a second treatment of treating the second film using the second gas or the second liquid are performed in the same chamber.

11. The method for manufacturing a semiconductor device according to claim 1, wherein a first treatment of etching the first film using the first gas and a second treatment of treating the second film using the second gas or the second liquid are performed alternately.

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