Semiconductor devices

Abstract

A semiconductor device according to an embodiment comprises: a base having a base surface; a semiconductor chip having a bottom surface larger than the base surface and arranged in a manner that the center of the bottom surface is arranged on the base surface; a bonding material arranged between the base surface and the bottom surface; a plate-shaped first wiring having a first surface and arranged in a manner that the first surface is opposite to a first end of the bottom surface; a plate-shaped second wiring having a second surface and arranged in a manner that the second surface is opposite to a second end of the bottom surface; and a third insulating film having a first insulating film and a second insulating film, the first insulating film having a third surface and a fourth surface arranged on the opposite side of the third surface, the third surface being connected to the first end, and the fourth surface being connected to the first surface, the second insulating film having a fifth surface and a sixth surface arranged on the opposite side of the fifth surface, the fifth surface being connected to the second end, and the sixth surface being connected to the second surface, and the third insulating film being arranged in a manner that surrounds the semiconductor chip when viewed from above the semiconductor chip.

Description

[0001] Related Applications

[0002] This application claims the priority of Japanese Patent Application No. 2020-150570 (filing date: September 8, 2020) as a basic application, and the present application incorporates all the contents of the basic application by reference. Technical Field

[0003] The embodiments mainly relate to semiconductor devices. Background Art

[0004] We are developing power semiconductor chips designed for power control, such as MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) and IGBT (Insulated Gate Bipolar Transistor), for a wide range of fields, including power generation and transmission, rotating machines such as pumps and blowers, power supply devices for communication systems and factories, railways based on AC motors, electric vehicles, and home appliances.

[0005] In addition, development of semiconductor devices as power modules using the power semiconductor chips is in progress. Such semiconductor devices are required to have specifications such as high current density, low loss, and high heat dissipation. Summary of the invention

[0006] An embodiment of the present invention provides a miniaturized semiconductor device.

[0007] The semiconductor device of this embodiment comprises: a base having a base surface; a semiconductor chip having a bottom surface larger than the base surface and arranged in a manner that the center of the bottom surface is arranged on the base surface; a bonding material arranged between the base surface and the bottom surface; a plate-shaped first wiring having a first surface and arranged in a manner that the first surface and the first end of the bottom surface are opposite to each other; a plate-shaped second wiring having a second surface and arranged in a manner that the second surface and the second end of the bottom surface are opposite to each other; and a third insulating film having a first insulating film and a second insulating film, the first insulating film having a third surface and a fourth surface arranged on the opposite side of the third surface, the third surface is connected to the first end, and the fourth surface is connected to the first surface, the second insulating film having a fifth surface and a sixth surface arranged on the opposite side of the fifth surface, the fifth surface is connected to the second end, and the sixth surface is connected to the second surface, and when observed from above the semiconductor chip, the third insulating film is arranged in a manner that surrounds the semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A as well as Figure 1B It is a schematic diagram of the semiconductor device according to the first embodiment.

[0009] Figure 2 This is a schematic cross-sectional view of a semiconductor device according to a first comparative embodiment of the first embodiment.

[0010] Figure 3 This is a schematic cross-sectional view of a semiconductor device according to a second comparative embodiment of the first embodiment.

[0011] Figure 4A as well as Figure 4B It is a schematic diagram of a semiconductor device according to a second embodiment.

[0012] Figure 5 It is a schematic cross-sectional view of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION

[0013] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In addition, in the following description, the same reference numerals are sometimes used to mark the same or similar components. In addition, the description of components that have been described once is sometimes appropriately omitted.

[0014] In this specification, in order to show the positional relationship of components, the upper direction of the drawings is described as "up", and the lower direction of the drawings is described as "down". In this specification, the concepts of "up" and "down" are not necessarily terms that indicate the relationship with the direction of gravity.

[0015] (First Embodiment)

[0016] Figure 1A as well as Figure 1B It is a schematic diagram of a semiconductor device 100 according to this embodiment. Figure 1A 1 is a schematic plan view of the semiconductor device 100 according to the present embodiment. Figure 1B yes Figure 1A Schematic cross-sectional view of the semiconductor device 100 according to the present embodiment, taken along the line AA′.

[0017] The semiconductor device 100 includes a base 2 , a semiconductor chip 10 , a bonding material 20 , a wiring 30 , and an insulating film 40 .

[0018] The base 2 is formed of a metal material or alloy such as Cu (copper). The base 2 has a base surface 4 on the upper surface. On the surface of the base surface 4, a thin film containing Au (gold), Pt (platinum), Pd (palladium), Ag (silver), Cu (copper), Sn (tin) or Ni (nickel) may be provided.

[0019] Here, an X direction, a Y direction perpendicular to the X direction, and a Z direction perpendicular to the X direction and the Y direction are defined. A base surface 4 of a base 2 described later is arranged parallel to the XY plane.

[0020] The semiconductor chip 10 is, for example, a vertical Si-IGBT using Si (silicon). In addition, the semiconductor chip 10 may also be a Si-MOSFET, a Si-FRD (Fast Recovery Diode), a SiC-IGBT, a SiC-MOSFET or a SiC-SBD (Schottky Barrier Diode) using SiC (silicon carbide), or a GaN-MOSFET using a nitride semiconductor whose V element in the III-V group semiconductor is nitrogen. In addition, the semiconductor chip 10 may not be a so-called power semiconductor chip.

[0021] The semiconductor chip 10 has a bottom surface 12 that is larger than the seating surface 4 in at least one direction. The semiconductor chip 10 is provided so that the center 12a of the bottom surface is disposed on the seating surface 4. The bottom surface 12 is, for example, a chip surface of the semiconductor chip 10.

[0022] The bonding material 20 is provided between the seating surface 4 and the bottom surface 12 of the semiconductor chip. The bonding material 20 bonds the seating surface 4 and the bottom surface 12 of the semiconductor chip.

[0023] The bonding material 20 bonds the base surface 4 to the semiconductor chip 10. The bonding material 20 includes, for example, a die attach (DA) paste. The die attach paste includes, for example, a sintering material containing a specified metal material and a specified resin. The bonding material 20 is formed by heat-treating a paste containing metal particles containing the above-mentioned specified metal material, the above-mentioned specified resin, and a specified solvent such as a polar solvent, evaporating the specified solvent, and sintering the above-mentioned metal particles. The bonding material 20 is conductive and electrically connects the bottom surface 12 of the semiconductor chip to an external electrical circuit (not shown) of the semiconductor device 100 via the base 2 and the bonding material 20.

[0024] The prescribed metal material is not particularly limited, and for example, Au, Pt, Pd, Ru (ruthenium), Rh (rhodium), Ir (iridium), Ag (silver), Cu (copper), Ni (nickel), Zn (zinc), Bi (bismuth), Fe (iron), Mo (molybdenum), Al (aluminum), Cr (chromium) or V (vanadium) are preferably used. As the prescribed metal material, Ag, Cu or Au is particularly preferably used because of its high thermal conductivity and electrical conductivity.

[0025] The prescribed resin is not particularly limited, and for example, polyethylene resin, polypropylene resin, vinyl chloride resin, polystyrene resin, acrylonitrile-styrene resin, ABS resin, polyethylene terephthalate resin, methacrylic resin, polyvinyl alcohol resin, vinylidene chloride resin, polycarbonate resin, polyamide resin, acetal resin, polybutylene terephthalate resin, fluororesin, phenolic resin, melamine resin, urea resin, polyurethane resin, epoxy resin, or unsaturated polyester resin are preferably used. As the prescribed resin, epoxy resin is particularly preferably used.

[0026] The sintering paste is an example of a die attach paste and is preferably used in the semiconductor device 100 of the present embodiment. The silver paste is a die attach paste using Ag as a predetermined metal material and is preferably used in the semiconductor device of the present embodiment.

[0027] like Figure 1A As shown, when viewed from above the semiconductor chip 10, a plurality of wirings 30 are provided around the semiconductor chip 10. The plurality of wirings 30 are formed of, for example, a metal or alloy such as Cu (copper). The plurality of wirings 30 are electrically connected to an electrode (not shown) provided on the upper surface of the semiconductor chip 10 using, for example, a wire (not shown).

[0028] exist Figure 1A , wirings 30a, 30b, 30c, 30d, 30e, 30f, 30g, 30h, 30i, 30j, 30k, 30l, 30m, 30n, 30o, and 30p are shown as a plurality of wirings 30. Each wiring 30 has a plate-like shape. Moreover, each wiring 30 has a surface that is disposed so as to face the end of the bottom surface 12 of the semiconductor chip. In other words, a portion of the wiring 30 is disposed below the bottom surface 12 of the semiconductor chip. Figure 1B The wiring 30a and the wiring 30j are used as examples for explanation. The wiring 30a (an example of a first wiring) has an upper surface 30a1 (an example of a first surface). The upper surface 30a1 is arranged to be opposite to the end 12b (an example of a first end) of the bottom surface 12 of the semiconductor chip. The wiring 30j (an example of a second wiring) has an upper surface 30j1 (an example of a second surface). The upper surface 30j1 is arranged to be opposite to the end 12c (an example of a second end) of the bottom surface 12 of the semiconductor chip. In addition, the number of the plurality of wirings 30 is not limited to Figure 1A The number shown.

[0029] like Figure 1AAs shown in FIG. 1 , when viewed from above the semiconductor chip 10, the insulating film 40 (an example of the third insulating film) is provided so as to surround the semiconductor chip 10 and is provided between the semiconductor chip 10 and the plurality of wirings 30. The shape of the insulating film 40 when viewed from above the semiconductor chip 10 is not limited to Figure 1A Shape shown.

[0030] The insulating film 40 preferably includes polyimide. For example, the insulating film 40 has a withstand voltage of 400 kV·mm －1 The thickness of the insulating film 40 is preferably, for example, 25 μm or more.

[0031] like Figure 1B As shown, the upper surface 40a1 (an example of the third surface) of the insulating film 40a (an example of the first insulating film) as a part of the insulating film 40 is in contact with the end 12b of the bottom surface 12, and the lower surface 40a2 (an example of the fourth surface) is in contact with the upper surface 30a1. In addition, the insulating film 40a is bonded to the end 12b and the upper surface 30a1.

[0032] In addition, if Figure 1B As shown, the upper surface 40j1 (an example of the fifth surface) of the insulating film 40j (an example of the second insulating film) as a part of the insulating film 40 is in contact with the end 12c of the bottom surface 12, and the lower surface 40j2 (an example of the sixth surface) is in contact with the upper surface 30j1. In addition, the insulating film 40j is bonded to the end 12c and the upper surface 30j1.

[0033] For example, a sealing resin (not shown) is provided around the base 2 , the semiconductor chip 10 , and the bonding material 20 .

[0034] The height of the base surface 4 in the Z direction, the height of the upper surface 30a1 of the wiring 30a, and the height of the upper surface 30j1 of the wiring 30j are preferably equal. Furthermore, the height of the base surface 4 in the Z direction, the height of the upper surface of the wiring 30b, the height of the upper surface of the wiring 30c, the height of the upper surface of the wiring 30d, the height of the upper surface of the wiring 30e, the height of the upper surface of the wiring 30f, the height of the upper surface of the wiring 30g, the height of the upper surface of the wiring 30h, the height of the upper surface of the wiring 30i, the height of the upper surface of the wiring 30k, the height of the upper surface of the wiring 30l, the height of the upper surface of the wiring 30m, the height of the upper surface of the wiring 30n, the height of the upper surface of the wiring 30o, and the height of the upper surface of the wiring 30p are preferably equal.

[0035] Next, the operation and effects of the semiconductor device 100 according to the present embodiment are described.

[0036] In order to miniaturize the semiconductor device 100, it is preferable to shorten the distance between the semiconductor chip 10 and the wiring 30 in a plane parallel to the XY plane. For example, if the base surface 4 can be reduced and the semiconductor chip 10 is mounted on the wiring 30, the area occupied by the semiconductor chip 10 in the semiconductor device 100 becomes higher, and miniaturization can be achieved.

[0037] Figure 2 1 is a schematic cross-sectional view of a semiconductor device 800 serving as a first comparative embodiment of the present embodiment. In the semiconductor device 800, the wiring 30a and the wiring 30j are different from the semiconductor device 100, and are not provided under the semiconductor chip 10 because the base surface 4 is large. Therefore, in a structure such as the semiconductor device 800, it is difficult to achieve miniaturization.

[0038] Figure 3 1 is a schematic cross-sectional view of a semiconductor device 900 which is a second comparative embodiment of the present embodiment. In the semiconductor device 900, an insulating film 60 is bonded to the bottom surface 12 of the semiconductor chip 10. The insulating film 60 is, for example, a die attach film (DAF). Moreover, the wiring 30a and the wiring 30j are respectively arranged below the end 12b and the end 12c of the bottom surface 12 of the semiconductor chip via the insulating film 60. In addition, the semiconductor chip 10 is arranged on the base 2 via the insulating film 60. According to this structure, the semiconductor device can be miniaturized. However, in the case where the semiconductor chip 10 is a power semiconductor chip, since a large voltage is applied to the semiconductor device 900, there is a problem that the insulating film 60 cannot ensure the insulation between the wiring 30 and the semiconductor chip 10. In addition, the die attach film used as the insulating film 60 has a problem that it cannot ensure high reliability.

[0039] Therefore, in the semiconductor device 100 of the present embodiment, the upper surface 30a1 of the wiring 30a is arranged in a manner opposite to the end 12b of the bottom surface 12 of the semiconductor chip. The upper surface 30j1 of the wiring 30j is arranged in a manner opposite to the end 12c of the bottom surface 12 of the semiconductor chip. Moreover, the upper surface 40a1 of the insulating film 40a is in contact with the end 12b of the bottom surface 12, and the lower surface 40a2 is in contact with the upper surface 30a1. In addition, the upper surface 40j1 of the insulating film 40j is in contact with the end 12c of the bottom surface 12, and the lower surface 40j2 is in contact with the upper surface 30j1. In addition, a bonding material 20 is provided between the base surface 4 and the bottom surface 12 of the semiconductor chip.

[0040] A bonding material 20 is provided between the bottom surface 12 of the semiconductor chip and the base 2. The bonding material 20 generally has higher reliability than a die attach film. Furthermore, a portion of the wiring 30 is provided under the bottom surface 12 of the semiconductor chip using the insulating film 40. Thus, a miniaturized semiconductor device 100 can be provided.

[0041] In addition, the height of the base surface 4, the height of the upper surface 30a1 of the wiring 30a, and the height of the upper surface 30j1 of the wiring 30j are preferably equal. This is because the semiconductor chip 10 is stably arranged on the base 2 through the insulating film 40, so the film thickness of the bonding material 20 can be ensured stably, and high reliability can be maintained more stably.

[0042] The bonding material 20 preferably includes a die attach paste. In addition, the bonding material 20 preferably includes a silver paste or a sintering paste because they have stable reliability.

[0043] The insulating film 40 preferably includes polyimide. This is because it has high insulation properties. In addition, the film thickness of the insulating film 40 is preferably 25 μm or more. The thicker the film thickness of the insulating film 40, the higher the withstand voltage can be ensured. This is because, for example, when the withstand voltage of 400 kV·mm is used as the insulating film 40, －1 In the case of Kapton (registered trademark), if the film thickness is 25 μm or more, a withstand voltage of 10 kV can be ensured.

[0044] Furthermore, when the insulating film 40 and the semiconductor chip 10 are misaligned, the misalignment can be easily recognized when the semiconductor device 100 is viewed from above, so defective products can be easily identified.

[0045] According to the semiconductor device 100 of the present embodiment, a miniaturized semiconductor device can be provided.

[0046] (Second Embodiment)

[0047] The semiconductor device of this embodiment is different from the semiconductor device of the first embodiment in that the first insulating film and the second insulating film include a solder resist. Here, descriptions overlapping with those of the semiconductor device of the first embodiment are omitted.

[0048] Figure 4A as well as Figure 4B It is a schematic diagram of a semiconductor device 110 according to this embodiment. Figure 4A 1 is a schematic plan view of a semiconductor device 110 according to the present embodiment. Figure 4B yes Figure 4A Schematic cross-sectional view of the semiconductor device 110 according to the present embodiment, taken along the line AA′.

[0049] A solder resist is used as the insulating film 40. The solder resist is applied to each wiring 30 and dried to form the insulating film 40. Specifically, the insulating film 40a is provided on the wiring 30a, the insulating film 40b is provided on the wiring 30b, the insulating film 40c is provided on the wiring 30c, the insulating film 40d is provided on the wiring 30d, the insulating film 40e is provided on the wiring 30e, the insulating film 40f is provided on the wiring 30f, the insulating film 40g is provided on the wiring 30g, the insulating film 40h is provided on the wiring 30h, the insulating film 40i is provided on the wiring 30i, the insulating film 40j is provided on the wiring 30j, the insulating film 40k is provided on the wiring 30k, the insulating film 40l is provided on the wiring 30l, the insulating film 40m is provided on the wiring 30m, the insulating film 40n is provided on the wiring 30n, and the insulating film 40o is provided on the wiring 30o. For example, it is preferable to use a solder resist having a film thickness of 20 μm and capable of ensuring a withstand voltage of 1.2 kV as the insulating film 40 .

[0050] The semiconductor device 110 of this embodiment can also provide a miniaturized semiconductor device.

[0051] (Third Embodiment)

[0052] The semiconductor device of this embodiment is different from the semiconductor devices of the first and second embodiments in that an insulating film 50 is provided between the seating surface 4 and the bottom surface 12. Here, description of the differences from the semiconductor devices of the first and second embodiments is omitted.

[0053] Figure 5 1 is a schematic cross-sectional view of the semiconductor device 120 of this embodiment. As the insulating film 50, for example, polyimide used in the semiconductor device 100 of the first embodiment or solder resist used in the semiconductor device 110 of the second embodiment is preferably used. Of course, the type of the insulating film 50 is not limited thereto.

[0054] According to the semiconductor device 120 of this embodiment, a miniaturized semiconductor device can also be provided.

[0055] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device comprising: a base having a base surface; a semiconductor chip having a bottom surface larger than the base surface and arranged in such a manner that the center of the bottom surface is arranged above the base surface; A bonding material is disposed between the base surface and the bottom surface; A plate-shaped first wiring has a first surface, and is arranged in such a manner that the first surface is opposed to a first end of the bottom surface; A second plate-shaped wiring has a second surface, and is disposed in such a manner that the second surface is opposed to a second end portion of the bottom surface; as well as A third insulating film having a first insulating film and a second insulating film, wherein the first insulating film has a third surface and a fourth surface arranged on the opposite side of the third surface, the third surface is connected to the first end, and the fourth surface is connected to the first surface, the second insulating film has a fifth surface and a sixth surface arranged on the opposite side of the fifth surface, the fifth surface is connected to the second end, and the sixth surface is connected to the second surface, and the third insulating film is arranged in a manner to surround the semiconductor chip when observed from above the semiconductor chip.

2. The semiconductor device according to claim 1, wherein: The height of the seating surface, the height of the upper surface of the first wiring, and the height of the upper surface of the second wiring are respectively equal.

3. The semiconductor device according to claim 1, wherein: The bonding material has electrical conductivity.

4. The semiconductor device according to claim 1, wherein: The bonding material includes a die attach paste.

5. The semiconductor device according to claim 4, wherein: The die attach paste includes silver paste or sintering paste.

6. The semiconductor device according to claim 4, wherein: The die attach paste includes a sintering material containing a predetermined metal material and a predetermined resin.

7. The semiconductor device according to claim 1, wherein: The first insulating film and the second insulating film include polyimide.

8. The semiconductor device according to claim 7, wherein: The thickness of the first insulating film and the thickness of the second insulating film are greater than or equal to 25 μm.

9. The semiconductor device according to claim 1, wherein: The first insulating film and the second insulating film include a solder resist.

10. The semiconductor device according to claim 9, wherein: The first insulating film is provided separately from the second insulating film.

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