Power semiconductor device

Abstract

The present invention discloses a power semiconductor device, comprising: a substrate, a first well region, a second well region, a drain, a source, a first gate structure, a second gate structure, and a doped region. The first well region has a first electrical property and extends from the surface of the substrate into the substrate. The second well region has a second electrical property and extends from the surface of the substrate into the substrate. The drain has the first electrical property and is located in the first well region. The source has the first electrical property and is located in the second well region. The first gate structure is located on the surface of the substrate and at least partially overlaps with the first well region and the second well region. The second gate structure is located on the surface of the substrate, overlaps with the second well region, and is isolated from the first gate structure. The doped region has the first electrical property, is located in the second well region, and connects the first gate structure and the second gate structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a power semiconductor device (powersemiconductor device). Background Art

[0002] Power semiconductor devices, such as Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), are power control components for electronic information products, featuring large on-state current, low on-state resistance, high switching speed, and high breakdown voltage resistance. They are mainly applied to switched-mode power control systems of computers, mobile phones, and portable products.

[0003] In order to achieve higher voltage operation, the existing approach is to extend the gate length (Lg) of the Metal-Oxide-Semiconductor Field-Effect Transistor to prevent punchthrough leakage caused by hot carriers injection (HCI). However, considering the limitations of device dimensions (design rule) and manufacturing process technology (e.g., the flatness of Chemical-Mechanical Planarization (CMP)), the gate length cannot be extended excessively. Therefore, how to increase the operating voltage and device reliability of the Metal-Oxide-Semiconductor Field-Effect Transistor without excessively extending the gate length has become one of the important issues in this technical field.

[0004] Therefore, there is a need to provide an advanced power semiconductor device to solve the problems faced by the prior art. Summary of the Invention

[0005] An embodiment of the present invention discloses a power semiconductor device, characterized in that the power semiconductor device includes: a substrate, a first well region, a second well region, a drain, a source, a first gate structure, a second gate structure, and a doped region. The first well region has a first electrical property and extends from the surface of the substrate into the substrate. The second well region has a second electrical property and extends from the surface of the substrate into the substrate. The drain has the first electrical property and is located in the first well region. The source has the first electrical property and is located in the second well region. The first gate structure is located on the surface of the substrate and at least partially overlaps with the first well region and the second well region. The second gate structure is located on the surface of the substrate, overlaps with the second well region, and is isolated from the first gate structure. The doped region has the first electrical property, is located in the second well region, and connects the first gate structure and the second gate structure.

[0006] According to the above embodiments, the present invention provides a power semiconductor device including at least two metal-oxide-semiconductor field-effect transistor elements, in which a first gate structure and a second gate structure are at least formed to be separated from each other between the source and the drain, and then the two gate structures are electrically connected together by a doped region. Among them, the electrical property of this doped region is the same as that of the source and the drain, and is used to form a first transistor unit by combining the first gate structure with the source and the drain; and a second transistor unit is formed by combining the second gate structure with the doped region and the drain, and is connected in series with the first transistor unit. Through this design, the operating voltage and reliability of the power semiconductor device can be improved without excessively extending the gate length. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to have a better understanding of the above and other aspects of the present invention, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings as follows:

[0008] Figures 1A to 1E A series of process structure cross-sectional schematic diagrams for manufacturing a power semiconductor device shown in an embodiment of the present invention;

[0009] Figure 2 A cross-sectional schematic diagram of the structure of a power semiconductor device shown in another embodiment of the present invention;

[0010] Figure 3A For Figure 2 A graph showing the relationship between the gate-source / drain overlap length and the drive current (Ion) of the provided power semiconductor device and the power semiconductor device of the comparative example;

[0011] Figure 3B For Figure 2 A graph showing the relationship between the gate-source / drain overlap length and the cut-off current (Ioff) of the provided power semiconductor device and the power semiconductor device of the comparative example;

[0012] Figure 3C For Figure 2 A graph showing the relationship between the gate-source / drain overlap length and the maximum substrate current (Isubmax) of the provided power semiconductor device and the power semiconductor device of the comparative example;

[0013] Figure 4 A cross-sectional schematic diagram of the structure of a power semiconductor device shown in yet another embodiment of the present invention;

[0014] Figure 5A For Figure 4 A graph showing the relationship between the gate-source / drain overlap length and the drive current (Ion) of the provided power semiconductor device and the power semiconductor device of the comparative example;

[0015] Figure 5B For Figure 4 Graphs showing the relationship between the gate-source / drain overlap length and the cut-off current (Ioff) of the provided power semiconductor device and the power semiconductor device of the comparative example; and

[0016] Figure 5C For Figure 4 Graphs showing the relationship between the gate-source / drain overlap length and the maximum substrate current (Isubmax) of the provided power semiconductor device and the power semiconductor device of the comparative example.

[0017] Symbol Explanation

[0018] 100, 200, 400: Power semiconductor devices

[0019] 101, 401: Substrates

[0020] 101a, 401a: Substrate surfaces

[0021] 102, 403: p-type well regions

[0022] 103, 402: n-type well regions

[0023] 104: Gate dielectric layer

[0024] 105: Conductor layer

[0025] 106, 107, 407: Gate structures

[0026] 108, 408: Virtual gate structures

[0027] 109, 409: Sources

[0028] 110, 410: Drains

[0029] 111, 411: Doped regions

[0030] 112: Metal interconnection structure

[0031] 113: Common voltage source

[0032] 120, 130: Metal oxide semiconductor field effect transistor units

[0033] 240: Shallow trench isolation structure

[0034] 301, 302, 303, 311, 312, 313, 501, 502, 503, 511, 512, 513: Curves showing the relationship between the gate-source / drain overlap length and the drive current

[0035] P: Distance between the p-type well region and the n-type well region

[0036] Lov2, Lov4: Gate-source / drain overlap length

[0037] H: Distance between the p-type well region and the n-type well region Detailed implementation manner

[0038] The present invention provides a power semiconductor device that can increase the operating voltage and device reliability of a metal oxide semiconductor field effect transistor without overly extending the gate length. In order to make the above embodiments and other purposes, features, and advantages of the present invention more obvious and understandable, multiple embodiments are specifically given below and are described in detail in conjunction with the accompanying drawings.

[0039] However, it must be noted that these specific implementation cases and methods are not used to limit the present invention. The present invention can still be implemented using other features, elements, methods, and parameters. The proposed preferred embodiments are only used to illustrate the technical features of the present invention and are not used to limit the claims of the present invention. Those with ordinary knowledge in the technical field can make equivalent modifications and changes without departing from the spirit of the present invention according to the following description. In different embodiments and drawings, the same elements will be represented by the same element symbols.

[0040] Please refer to Figures 1A to 1E , Figures 1A to 1E is a series of cross-sectional schematic diagrams of the manufacturing process structure for manufacturing the power semiconductor device 100 according to an embodiment of the present invention. The manufacturing method of the power semiconductor device 100 includes the following steps: First, a substrate 101 is provided. In some embodiments of the present invention, the substrate 101 may be made of a semiconductor material, such as silicon (Si), germanium (Ge), or a compound semiconductor material, such as gallium arsenide (GaAs). However, in other embodiments, the substrate 101. It can also be a silicon-on-insulator (SOI) substrate. In this embodiment, the substrate 101 is preferably a silicon substrate, such as a silicon wafer (as shown in Figure 1A ).

[0041] Next, at least one ion implantation process is used to form at least one p-type well region 102 and at least one n-type well region 103 on the surface 101a of the device substrate 101. In some embodiments of the present invention, both the p-type well region 102 (denoted as PW) and the n-type well region 103 (denoted as NW) extend from the surface 101a of the substrate 101 into the substrate 101. Among them, the n-type well region 103 is adjacent to the p-type well region 102 but isolated from each other. In this embodiment, the substrate 101 has a p-type electrical property; the p-type well region 102 and the n-type well region 103 have a doping concentration higher than that of the substrate 101, and the two are isolated from each other by a part of the substrate 101. The distance H between the p-type well region 102 and the n-type well region 103 (as Figure 1B shown).

[0042] However, the configuration of the n-type well region 103 and the p-type well region 102 is not limited thereto. For example, in another embodiment of the present invention, the n-type well region 103 and the p-type well region 102 are not isolated from each other.

[0043] Next, a gate dielectric layer 104 and a conductor layer 105 are sequentially stacked on the surface 101a of the substrate 101. In some embodiments of the present invention, the material constituting the dielectric layer 104 can be silicon dioxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiNO), high-k dielectric material (for example, hafnium oxide (HfO 2 ), aluminum oxide (AlO x )) or a combination of the above dielectric materials. The conductor layer 105 can be polysilicon, metal (for example, gold, silver, copper, aluminum or tungsten), metal compound (for example, titanium nitride or tantalum nitride) or a combination of the above.

[0044] After that, a photoresist etching process is used to pattern the gate dielectric layer 104 and the conductor layer 105 to form a plurality of gate structures 106 and 107 including a part of the dielectric layer 104 and a part of the conductor layer 105 on the surface 101a of the substrate 101. Among them, the gate structure 106 overlaps with the p-type well region 102; the gate structure 107 at least partially overlaps with the p-type well region 102 and the n-type well region 103 respectively. In other words, the gate structure 107 straddles the p-type well region 102 and the n-type well region 103 and overlaps with a part of the substrate 101 used to isolate the p-type well region 102 and the n-type well region 103 (as Figure 1C shown).

[0045] In some embodiments of the present invention, in the steps of patterning the dielectric layer 104 and the conductor layer 105, at least one virtual gate structure 108 including a part of the dielectric layer 104 and a part of the conductor layer 105 may also be formed on the surface 101a of the substrate 101. For example, in this embodiment, the steps of patterning the dielectric layer 104 and the conductor layer 105 further include forming a virtual gate structure 108 overlapping with the n-type well region 103 and isolated from the gate structures 106 and 107. The gate structure 107 is located between the gate structure 106 and the virtual gate structure 108.

[0046] Subsequently, through at least one ion doping or epitaxial fabrication process, a source 109, a drain 110, and a doped region 111 having an n-type electrical property are formed in the surface 101a of the device substrate 101; the source 109 is located in the p-type well region 102 and adjacent to the gate structure 106; the drain 110 is located in the n-type well region 103 and adjacent to the virtual gate structure 108, and the virtual gate structure 108 is located between the gate structure 107 and the drain 110; the doped region 111 is located in the p-type well region 102 and connects the gate structure 106 and the gate structure 107 (as Figure 1D shown). In some embodiments of the present invention, the doping concentrations of the source 109, the drain 110, and the doped region 111 are all greater than the doping concentrations of the p-type well region 102 and the n-type well region 103. Therefore, the source 109, the drain 110, and the doped region 111 are denoted as N+.

[0047] Among them, the gate structure 106, the source 109, the drain 110, the p-type well region 102, the n-type well region 103, and the substrate 101 constitute a metal-oxide-semiconductor field-effect transistor unit 120. The gate structure 107, the doped region 111, the drain 110, the p-type well region 102, the n-type well region 103, and the substrate 101 constitute another metal-oxide-semiconductor field-effect transistor unit 130, and the two metal-oxide-semiconductor field-effect transistor units 120 and 130 are connected in series with each other through the doped region 111.

[0048] Subsequently, a back-end fabrication process, such as a metal damascene process, is performed to form a metal interconnection structure 112 on the surface 101a of the substrate 101, floating the virtual gate structure 108, and connecting the gate structures 106 and 107 to a common voltage source 113, thereby forming the power semiconductor device 100 as Figure 1E shown.

[0049] The fabricated power semiconductor device 100 includes: a substrate 101, a p-well region 102, an n-well region 103, a drain 110, a source 109, a gate structure 106, a gate structure 107, a dummy gate structure 108, and a doped region 111. The p-well region 102 and the n-well region 103 extend from the surface 101a of the substrate 101 into the substrate 101 and may (but are not limited to) be isolated from each other. The source 109, the drain 110, and the doped region 111 all have an n-type electrical property. Among them, the drain 110 is located in the n-well region 103; the source 109 is located in the p-well region 102. The gate structure 107 is located on the surface 101a of the substrate 101 and at least partially overlaps with the p-well region 102 and the n-well region 103. The gate structure 106 is located on the surface 101a of the substrate 101, overlaps with the p-well region 102, and is isolated from the gate structure 107. The doped region 111 is located in the p-well region 102 and connects the gate structure 106 and the gate structure 107. The dummy gate structure 108 is located on the surface 101a of the substrate 101, overlaps with the n-well region 103, and is located between the gate structure 107 and the drain 110.

[0050] However, it should be noted that the structure of the power semiconductor device 100 is not limited thereto. For example, in some other embodiments of the present invention, the power semiconductor device 100 may include more dummy gate structures (not shown), having the same structure as the dummy gate structure 108 and located between the gate structure 107 and the dummy gate structure 108. In some other embodiments of the present invention, the power semiconductor device 100 may include more gate structures identical to the gate structure 106, configured between the gate structure 107 and the gate structure 106.

[0051] In addition, please refer to Figure 2 , Figure 2 FIG. is a schematic cross-sectional view of the structure of a power semiconductor device 200 illustrated according to another embodiment of the present invention. In this embodiment, the structure of the power semiconductor device 200 is generally similar to that of the power semiconductor device 100, except that the power semiconductor device 200 further includes an isolation structure, such as a shallow trench insulator (STI) 240, located in the n-well region 103 and between the gate structure 107 and the dummy gate structure 108 (or between the gate structure 107 and the drain 111).

[0052] Next, according to the present invention Figure 2Regarding the structure of the power semiconductor device 200, a plurality of power semiconductor devices 200 with different gate-to-S / D overlap lengths (LOV) Lov2 are fabricated, and the variations in the drive current (Ion), cut-off current (Ioff), and maximum substrate current (Isubmax) of these power semiconductor devices 200 are recorded and analyzed. Moreover, a comparison is made with a comparative example of a conventional power semiconductor device having a single n-type metal oxide semiconductor field effect transistor unit.

[0053] Please refer to Figures 3A to 3C , Figure 3A which shows Figure 2 a graph of the gate-to-S / D overlap length - drive current (Ion) relationship for the provided power semiconductor device 200 and the power semiconductor device of the comparative example. Figure 3B which shows Figure 2 a graph of the gate-to-S / D overlap length - cut-off current (Ioff) relationship for the provided power semiconductor device 200 and the power semiconductor device of the comparative example. Figure 3C which shows Figure 2 a graph of the gate-to-S / D overlap length - maximum substrate current (Isubmax) relationship for the provided power semiconductor device 200 and the power semiconductor device of the comparative example.

[0054] Among them, the horizontal axis represents the normalized gate-to-S / D overlap length (in units of a.u.), and the horizontal axis represents the normalized drive current (Ion), cut-off current (Ioff), and maximum substrate current (Isubmax) (in units of a.u.), respectively. Curves 301, 302, and 303 represent the gate-to-S / D overlap length - drive current (Ion) relationship curve, the gate-to-S / D overlap length - cut-off current (Ioff) relationship curve, and the gate-to-S / D overlap length - maximum substrate current (Isubmax) relationship curve of the power semiconductor device 200, respectively. Curves 311, 312, and 313 represent the gate-to-S / D overlap length - drive current (Ion) relationship curve, the gate-to-S / D overlap length - cut-off current (Ioff) relationship curve, and the gate-to-S / D overlap length - maximum substrate current (Isubmax) relationship curve of the power semiconductor device provided in the comparative example, respectively.

[0055] From Figures 3A to 3CIt can be seen that at the same gate-source / drain overlap length Lov2, the drive current (Ion), cut-off current (Ioff), and maximum substrate current (Isubmax) of the power semiconductor device 200 are all smaller than those of the power semiconductor device provided in the comparative example. It can be seen that compared with the power semiconductor device provided in the comparative example, when having the same drive current (Ion), cut-off current (Ioff), and maximum substrate current (Isubmax), the power semiconductor device 200 can have a longer gate-source / drain overlap length Lov2, and is less likely to generate hot carrier injection (the breakdown leakage phenomenon caused thereby), and thus has a higher operating voltage.

[0056] In addition, the drive current (Ion), cut-off current (Ioff), and maximum substrate current (Isubmax) of the power semiconductor device 200 do not show obvious fluctuations as the gate-source / drain overlap length increases. On the contrary, the drive current (Ion), cut-off current (Ioff), and maximum substrate current (Isubmax) of the power semiconductor device provided in the comparative example increase significantly as the gate-source / drain overlap length increases. It shows that the power semiconductor device 200 has higher design flexibility and operating reliability compared with the power semiconductor device provided in the comparative example.

[0057] In addition, although the laterally diffused metal oxide semiconductor field effect transistor elements 120 and transistor elements 130 included in the power semiconductor devices 100 and 200 described in the above embodiments are both n-type electric field effect transistors. However, the power semiconductor devices described in the present invention are not limited thereto. For example, please refer to Figure 4 , Figure 4 FIG. 400 is a schematic cross-sectional view of the structure of a power semiconductor device 400 according to another embodiment of the present invention. In some embodiments of the power semiconductor device 400, the structure of the power semiconductor device 400 is generally similar to that of the power semiconductor device 200, except that the power semiconductor device 400 includes a p-type electric field effect transistor.

[0058] In this embodiment, the power semiconductor device 400 includes: a substrate 401, an n-type well region 402, a p-type well region 403, a drain 410, a source 409, a gate structure 406, a gate structure 407, a dummy gate structure 408, and a doping region 411. Among them, the substrate 401 has an n-type electric property.

[0059] The n-type well region 402 and the p-type well region 403 extend from the surface 401a of the substrate 401 into the substrate 401 and are isolated from each other. The source electrode 409, the drain electrode 410, and the doped region 411 all have p-type electrical properties. Among them, the drain electrode 410 is located in the p-type well region 403; the source electrode 409 is located in the n-type well region 402. The gate structure 407 is located on the surface 401a of the substrate 401 and at least partially overlaps with the n-type well region 402 and the p-type well region 403. The gate structure 406 is located on the surface 401a of the substrate 401, overlaps with the n-type well region 402, and is isolated from the gate structure 407. The doped region 411 is located in the n-type well region 402 and connects the gate structure 406 and the gate structure 407. The dummy gate structure 408 is located on the surface 401a of the substrate 401, overlaps with the p-type well region 403, and is located between the gate structure 407 and the drain electrode 410. The shallow trench isolation structure 440 is located in the p-type well region 403 and is located between the gate structure 407 and the dummy gate structure 408 (or between the gate structure 407 and the drain electrode 411).

[0060] Similarly, according to the present invention Figure 4 the structure of the power semiconductor device 400 as described, a plurality of power semiconductor devices 400 with different gate-source / drain overlap lengths Lov4 are fabricated, and the variations of the drive current (Ion), the cut-off current (Ioff), and the maximum substrate current (Isubmax) of these power semiconductor devices 400 are recorded and analyzed. And a comparison is made with a comparative example of a power semiconductor device having a single p-type metal oxide semiconductor field effect transistor unit in the prior art.

[0061] Please refer to Figures 5A to 5C , Figure 5A which shows Figure 4 the graph of the gate-source / drain overlap length - drive current (Ion) relationship of the provided power semiconductor device 400 and the power semiconductor device of the comparative example. Figure 5B which shows Figure 4 the graph of the gate-source / drain overlap length - cut-off current (Ioff) relationship of the provided power semiconductor device 400 and the power semiconductor device of the comparative example. Figure 5C which shows Figure 4 the graph of the gate-source / drain overlap length - maximum substrate current (Isubmax) relationship of the provided power semiconductor device 400 and the power semiconductor device of the comparative example.

[0062] Among them, the horizontal axis represents the normalized gate-source / drain overlap length (in a.u.), and the horizontal axis represents the normalized drive current (Ion), cut-off current (Ioff), and maximum substrate current (Isubmax) (in a.u. respectively). Curves 501, 502, and 503 represent the gate-source / drain overlap length-drive current (Ion) relationship curve, gate-source / drain overlap length-cut-off current (Ioff) relationship curve, and gate-source / drain overlap length-maximum substrate current (Isubmax) relationship curve of the power semiconductor device 400 respectively. Curves 511, 512, and 513 represent the gate-source / drain overlap length-drive current (Ion) relationship curve, gate-source / drain overlap length-cut-off current (Ioff) relationship curve, and gate-source / drain overlap length-maximum substrate current (Isubmax) relationship curve of the power semiconductor device provided by the comparative example respectively.

[0063] It can be seen that Figures 5A to 5C at the same gate-source / drain overlap length, the drive current (Ion), cut-off current (Ioff), and maximum substrate current (Isubmax) of the power semiconductor device 400 are all smaller than those of the power semiconductor device provided by the comparative example. It can be seen that compared with the power semiconductor device provided by the comparative example, when having the same drive current (Ion), cut-off current (Ioff), and maximum substrate current (Isubmax), the power semiconductor device 400 can have a longer gate-source / drain overlap length, and is less likely to generate hot carrier injection (the breakdown leakage phenomenon caused thereby), so it has a higher operating voltage.

[0064] In addition, the drive current (Ion), cut-off current (Ioff), and maximum substrate current (Isubmax) of the power semiconductor device 400 do not show obvious fluctuations as the gate-source / drain overlap length increases. On the contrary, the drive current (Ion), cut-off current (Ioff), and maximum substrate current (Isubmax) of the power semiconductor device provided by the comparative example increase significantly as the gate-source / drain overlap length increases. It shows that the power semiconductor device 400 has higher design flexibility and operation reliability compared with the power semiconductor device provided by the comparative example.

[0065] According to the above embodiments, the present invention provides a power semiconductor device including at least two metal oxide semiconductor field effect transistor elements, in which a first gate structure and a second gate structure are at least formed separately from each other between a source and a drain, and then the two gate structures are electrically connected together by a doped region. Among them, the electrical property of this doped region is the same as that of the source and the drain, and is used to form a first transistor unit by combining the first gate structure with the source and the drain; the second gate structure is combined with the doped region and the drain to form a second transistor unit, and is connected in series with the first transistor unit. Through this design, the operating voltage and reliability of the power semiconductor device can be improved without excessively extending the gate length.

[0066] Although the present invention is disclosed in combination with the above preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A power semiconductor device, characterized in that, the power semiconductor device comprises: a substrate having a surface; a first well region having a first electrical property, extending from the surface into the substrate; a second well region having a second electrical property, extending from the surface into the substrate and isolated from the first well region; a drain having the first electrical property and located in the first well region; a source having the first electrical property and located in the second well region; a first gate structure located on the surface and at least partially overlapping with the first well region and the second well region; a second gate structure located on the surface and overlapping with the second well region; and a doped region having the first electrical property, located in the second well region and connecting the first gate structure and the second gate structure.

2. The power semiconductor device according to claim 1, characterized in that, it further comprises an isolation structure located in the first well region and between the first gate structure and the drain.

3. The power semiconductor device according to claim 2, characterized in that, the isolation structure is a shallow trench insulator (STI).

4. The power semiconductor device according to claim 1, characterized in that, it further comprises a dummy gate structure located on the surface and between the first gate structure and the drain.

5. The power semiconductor device according to claim 4, characterized in that, the dummy gate structure is adjacent to the drain and isolated from the first gate structure.

6. The power semiconductor device according to claim 1, characterized in that, the first electrical property is an n-type electrical property; and the second electrical property is a p-type electrical property.

7. The power semiconductor device according to claim 1, characterized in that, the first electrical property is a p-type electrical property; and the second electrical property is an n-type electrical property.

8. The power semiconductor device according to claim 1, characterized in that, the first gate structure and the second gate structure are connected to a common voltage source.

9. The power semiconductor device according to claim 1, characterized in that, the second gate structure is isolated from the first gate structure.

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