Drive backplane and display panel

Abstract

The present disclosure relates to a driving backplane and a display panel, and pertains to the field of display technologies. The driving backplane includes: a substrate and a driving layer, the driving layer includes a shielding layer and a circuit layer, and a plurality of pixel circuits are formed in the circuit layer; the pixel circuit includes a driving transistor and a first switching transistor; the shielding layer includes a first shielding sheet, there is an overlapping region between the driving transistor and the first shielding sheet in the direction perpendicular to the substrate, and the first shielding sheet is electrically connected to the first pole of the driving transistor. In the embodiments of the present disclosure, the driving transistor is shielded by the first shielding sheet, so as to avoid being affected by external light, thereby avoiding an increase in photo-generated carriers, and further avoiding fluctuations in the threshold voltage of the driving transistor; secondly, through the electrical connection between the first shielding sheet and the first pole of the driving transistor, the accumulation of charges on the first shielding sheet is avoided, and the service life of the first shielding sheet is extended.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a driving backplane and a display panel. Background Art

[0002] Display panels have been widely used in electronic devices such as mobile phones, computers, and televisions. Among them, the display area of the display panel has pixel circuits, and the display brightness of the display panel is mainly related to the pixel circuits. Usually, the pixel circuits are adjusted to avoid the problem of uneven display (Mura) on the display panel. For example, a compensation circuit is arranged. However, after the pixel circuits are compensated by technicians, it is found that there is still a problem of uneven display in some electronic devices.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] The purpose of the present disclosure is to provide a driving backplane and a display panel, which can reduce the uniformity problem of the display panel and improve the display effect.

[0005] According to one aspect of the present disclosure, a driving backplane is provided, including:

[0006] A substrate;

[0007] A driving layer, located on one side of the substrate, the driving layer includes a shielding layer and a circuit layer distributed in a direction away from the substrate, and a plurality of pixel circuits are formed in the circuit layer;

[0008] The pixel circuit includes a driving transistor and a first switching transistor. The first pole of the driving transistor is electrically connected to the first pole of the first switching transistor. The first pole of the driving transistor is used to input a first power signal. The second pole of the driving transistor is used to be electrically connected to a light-emitting device. The second pole of the first switching transistor is used to input a data signal;

[0009] The shielding layer includes a first shielding sheet. There is an overlapping area between the driving transistor and the first shielding sheet in a direction perpendicular to the substrate. The first shielding sheet is electrically connected to the first pole of the driving transistor.

[0010] According to the driving backplane BP described in any one of the present disclosures, the circuit layer PC includes:

[0011] An active layer, located on a side of the shielding layer away from the substrate, and includes a first active portion. The first active portion includes a first channel region and a first connection portion and a second connection portion located on both sides of the first channel region;

[0012] The first gate insulating layer is located on a side of the active layer facing away from the substrate, and at least covers the first active portion;

[0013] The first gate metal layer is located on a side of the first gate insulating layer facing away from the substrate, and includes a first conductive portion. There is an overlapping region between the first conductive portion and the first channel region in a direction perpendicular to the substrate;

[0014] The second gate insulating layer is located on a side of the first gate metal layer facing away from the substrate, and at least covers the first conductive portion;

[0015] The first source-drain metal layer is located on a side of the second gate insulating layer facing away from the substrate, and includes a first connection line. A first end of the first connection line is electrically connected to the first connection portion, and a second end of the first connection line is electrically connected to the first shielding sheet;

[0016] The first connection portion and the second connection portion respectively form the first pole and the second pole of the driving transistor, and a region of the first conductive portion overlapping with the first channel region forms the control pole of the driving transistor.

[0017] According to the driving backplane of any one of the present disclosures, the first shielding sheet includes a body portion and a protruding portion;

[0018] A projection of the first conductive portion on a plane where the body portion is located is within a region where the body portion is located, and the protruding portion is electrically connected to the body portion and the second end of the first connection line respectively.

[0019] According to the driving backplane of any one of the present disclosures, the body portion and the protruding portion are distributed along the row direction, and the first connection line extends along the column direction.

[0020] According to the driving backplane of any one of the present disclosures, the first source-drain metal layer includes a data line and a first power supply signal line;

[0021] The data line and the first power supply signal line are distributed along the row direction and extend along the column direction, and the first power supply signal line is electrically connected to the first connection portion;

[0022] The first power supply signal line has a bent portion facing away from the data line. There is an overlapping region between the bent portion and the first conductive portion in a direction perpendicular to the substrate, and the first connection line is located within a region surrounded by the data line and the bent portion.

[0023] According to the driving backplane of any one of the present disclosures, the control pole of the first switching transistor is used to input a scan signal;

[0024] The light-shielding layer includes a second light-shielding sheet. There is an overlapping area between the first switching transistor and the second light-shielding sheet in a direction perpendicular to the substrate. The second light-shielding sheet is electrically connected to the control electrode of the first switching transistor.

[0025] According to the driving backplane described in any one of the present disclosures, the active layer includes a second active portion. The second active portion includes a second channel region and third and fourth connection portions located on both sides of the second channel region. The first gate insulating layer covers the second active portion;

[0026] The first gate metal layer includes a scanning signal line. There is an overlapping area between the scanning signal line and the second channel region in a direction perpendicular to the substrate. The second gate insulating layer covers the scanning signal line;

[0027] The first source-drain metal layer includes a second connection line. The first end of the second connection line is electrically connected to the scanning signal line, and the second end of the second connection line is electrically connected to the second light-shielding sheet;

[0028] The third connection portion and the fourth connection portion correspondingly form the first and second poles of the first switching transistor. The overlapping area between the scanning signal line and the second channel region forms the control electrode of the first switching transistor.

[0029] According to the driving backplane described in any one of the present disclosures, the driving layer has a display area and a non-display area located outside the display area;

[0030] The second connection line is located in the non-display area. The scanning signal line and the second light-shielding sheet both extend from the display area to the non-display area. The portions of the scanning signal line and the second light-shielding sheet located in the non-display area are both electrically connected to the second connection line.

[0031] According to the driving backplane described in any one of the present disclosures, within the display area, the scanning signal line is directly above the second light-shielding sheet;

[0032] The width of the overlapping area between the scanning signal line and the second channel region is smaller than the width of the overlapping area between the second light-shielding sheet and the second channel region.

[0033] According to the driving backplane described in any one of the present disclosures, the pixel circuit includes a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, and a capacitor;

[0034] The first pole of the second switching transistor is electrically connected to the first pole of the third switching transistor, the control pole of the driving transistor, and the first electrode plate of the capacitor respectively. The second pole of the second switching transistor is used to input a first initial voltage signal, and the control pole of the second switching transistor is used to input a reset signal;

[0035] The second pole of the third switching transistor is electrically connected to the second pole of the driving transistor and the first pole of the fourth switching transistor respectively. The control pole of the third switching transistor is used to input a scanning signal;

[0036] The second pole of the fourth switching transistor is electrically connected to the first pole of the fifth switching transistor and is used to be electrically connected to the light-emitting device. The control pole of the fourth switching transistor is used to input a light-emitting control signal;

[0037] The second pole of the fifth switching transistor is used to input a second initial voltage signal, and the control pole of the fifth switching transistor is used to input the reset signal;

[0038] The first pole of the sixth switching transistor is electrically connected to the first pole of the driving transistor. The second pole of the sixth switching transistor is electrically connected to the second electrode plate of the capacitor and is used to input the power supply signal. The control pole of the sixth switching transistor is used to input the light-emitting control signal;

[0039] There is an overlapping area between the third switching transistor and the second light-shielding sheet in the direction perpendicular to the substrate. The control pole of the third switching transistor is electrically connected to the second light-shielding sheet;

[0040] The light-shielding layer further includes a third light-shielding sheet and a fourth light-shielding sheet. There are overlapping areas between the fourth switching transistor, the sixth switching transistor and the third light-shielding sheet in the direction perpendicular to the substrate. The control poles of the fourth switching transistor and the sixth switching transistor are both electrically connected to the third light-shielding sheet;

[0041] In the same column of pixel circuits, there are overlapping areas between the fifth switching transistor of the nth pixel circuit, the second switching transistor of the (n + 1)th pixel circuit and the fourth light-shielding sheet in the direction perpendicular to the substrate. The control poles of the fifth switching transistor of the nth pixel circuit and the second switching transistor of the (n + 1)th pixel circuit are both electrically connected to the fourth light-shielding sheet.

[0042] According to a second aspect of the present disclosure, there is provided a display panel, including:

[0043] The driving backplane described in the above first aspect;

[0044] The light-emitting device is located on a side of the driving layer facing away from the substrate, and is electrically connected to a second pole of the driving transistor.

[0045] In the embodiment of the present disclosure, there is an overlapping area between the driving transistor and the first light-shielding sheet in the direction perpendicular to the substrate, so as to shield the driving transistor through the first light-shielding sheet, avoid being affected by external light, thereby avoiding the increase of photo-generated carriers, and further avoiding the fluctuation of the threshold voltage of the driving transistor. Secondly, by electrically connecting the first light-shielding sheet to the first pole of the driving transistor, the accumulation of charges on the first light-shielding sheet is avoided, the service life of the first light-shielding sheet is extended, and it is ensured that the first light-shielding sheet always maintains the voltage of the first pole of the driving transistor, that is, it is ensured that the threshold voltage of the driving transistor always maintains the same state, thereby further avoiding the fluctuation of the threshold voltage of the driving transistor and ensuring that the driving transistor always operates in a normal state.

[0046] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0048] Figure 1 It is an Id-Vg curve of a driving transistor provided by an embodiment of the present disclosure.

[0049] Figure 2 It is another Id-Vg curve of a driving transistor provided by an embodiment of the present disclosure.

[0050] Figure 3 It is yet another Id-Vg curve of a driving transistor provided by an embodiment of the present disclosure.

[0051] Figure 4 It is an Id-Vg curve of a driving transistor under external light provided by an embodiment of the present disclosure.

[0052] Figure 5 It is another Id-Vg curve of a driving transistor under external light provided by an embodiment of the present disclosure.

[0053] Figure 6 It is yet another Id-Vg curve of a driving transistor under external light provided by an embodiment of the present disclosure.

[0054] Figure 7 Schematic diagram of a driving backplane provided by an embodiment of the present disclosure.

[0055] Figure 8 Schematic diagram of a pixel circuit provided by an embodiment of the present disclosure.

[0056] Figure 9 Structural layout of an active layer provided by an embodiment of the present disclosure.

[0057] Figure 10 Structural layout of a first gate metal layer provided by an embodiment of the present disclosure.

[0058] Figure 11 Structural layout of the stacked active layer and the first gate metal layer provided by an embodiment of the present disclosure.

[0059] Figure 12 Structural layout of a second gate metal layer provided by an embodiment of the present disclosure.

[0060] Figure 13 Structural layout of the stacked first gate metal layer and the second gate metal layer provided by an embodiment of the present disclosure.

[0061] Figure 14 Structural layout of a first source-drain metal layer provided by an embodiment of the present disclosure.

[0062] Figure 15 Structural layout of a pixel circuit provided by an embodiment of the present disclosure.

[0063] Figure 16 Another schematic diagram of a driving backplane provided by an embodiment of the present disclosure.

[0064] Figure 17 Structural layout of a second source-drain metal layer provided by an embodiment of the present disclosure.

[0065] Figure 18 Structural layout of the stacked first source-drain metal layer and the second source-drain metal layer provided by an embodiment of the present disclosure.

[0066] Figure 19 Yet another schematic diagram of a driving backplane provided by an embodiment of the present disclosure.

[0067] Figure 20 Structural layout of the stacked second source-drain metal layer, the first electrode layer, and the pixel definition layer provided by an embodiment of the present disclosure.

[0068] Figure 21 Structural layout of a shielding layer provided by an embodiment of the present disclosure.

[0069] Figure 22Another structural layout of a pixel circuit provided by an embodiment of the present disclosure.

[0070] Figure 23 Another structural layout of a pixel circuit provided by an embodiment of the present disclosure. Detailed implementation manners

[0071] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0072] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component described as "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0073] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", "third", etc. are used only as labels and are not a limitation on the quantity of their objects.

[0074] In addition, in the drawings, the thicknesses and areas of the respective layers are exaggerated for clarity. It should be understood that when referring to a layer, region, or component being "on" another part, it means that it is directly on the other part, or there may also be other components in between.

[0075] In the embodiments of the present disclosure, the transistors involved can all be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Taking a transistor as an example, a transistor refers to an element including at least three terminals: a control electrode, a first electrode, and a second electrode. There is a channel region between the first electrode and the second electrode of the transistor, and current can flow through the first electrode, the channel region, and the second electrode. The channel region refers to the region where the current mainly flows. Among them, the first electrode is the source electrode, the second electrode is the drain electrode, or the first electrode is the drain electrode, and the second electrode is the source electrode. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, etc., the functions of the "first electrode" and the "second electrode" are sometimes swapped with each other.

[0076] With the continuous development of display technology, the market share of display panels (such as AMOLED (Active-matrix organic light emitting diode)) is increasing year by year, and the terminal market has higher and higher requirements for the quality of display panels. This has prompted the need for continuous improvement in the design of display panels to meet the market demand. The display uniformity problem is a widespread problem in current display panels. With the requirements of product updates and iterations and the continuous improvement of customers' quality requirements, the detection limit for uniformity is also becoming increasingly stringent.

[0077] The display panel includes a driving backplane BP and light-emitting devices. A plurality of pixel circuits are formed in the driving backplane BP, and the plurality of pixel circuits are respectively electrically connected to the corresponding light-emitting devices. Each pixel circuit drives the light-emitting device to emit light through three stages: resetting, charging, and emitting light. In order to ensure the uniformity of the light emission of the plurality of light-emitting devices and avoid the problem of image sticking, the operating states of the transistors included in the pixel circuit need to be precisely and strictly controlled. For example, adjusting the data voltage of the pixel circuit, the size parameters of the transistors in the pixel circuit, adjusting the process of the driving layer CL, etc. However, the inventor found that the improvement of these solutions is limited, and after careful research, it was found that the characteristics of the transistors in the pixel circuit are also easily affected by external environmental factors, resulting in at least some transistors not operating in a normal state.

[0078] For example, during the charging stage, when the driving transistor DT of the pixel circuit is affected by external light, the photo-generated carriers in the channel of the driving transistor DT increase, causing the current to increase and the threshold voltage of the driving transistor DT to fluctuate, resulting in the charging not reaching the saturation state. Furthermore, when the light-emitting device emits light during the light-emitting stage, the brightness is insufficient, causing a display uniformity problem in the display panel. In addition, if the switching transistors in the pixel circuit fail to open or close in a timely manner at the moment of turning on and off, it will also cause a display uniformity problem in the display panel.

[0079] Based on the problem that the threshold voltage of a transistor is affected by external light, after careful research and experimental verification by the inventor, it is creatively proposed to set an opaque film under the transistor and electrically connect the opaque film to the transistor to ensure that the threshold voltage of the transistor is in a stable state.

[0080] Taking the driving transistor DT as an example, three cases are set: without an opaque film, with an opaque film and the relative voltage of the opaque film being 0V, and with an opaque film and the relative voltage of the opaque film being 4.6V. Experiments are carried out on these three cases respectively, and the Id (drain-source current)-Vg (gate-source voltage) curves shown in Figure 1 、 Figure 2 and Figure 3 are obtained.

[0081] Among them, the relative voltage of the opaque film refers to the difference between the voltage of the opaque film after being electrically connected to the driving transistor DT and the voltage of one pole of the driving transistor DT used to be electrically connected to the first power signal. The other pole of the driving transistor DT is used to be electrically connected to the light-emitting device. Figure 1 、 Figure 2 and Figure 3 The abscissas in

[0082] are all gate-source voltages, and the ordinates are all drain-source currents. Curve 1 represents the Id-Vg curve of the driving transistor DT before leaving the factory, and curve 2 represents the Id-Vg curve of the driving transistor DT after leaving the factory. Figure 1 、 Figure 2 and Figure 3 Combined with

[0083] It can be seen that the gentler the slope of the end of curve 2 where Vg is greater than 0, the more stable the Id of the driving transistor DT. At this time, the threshold voltage of the driving transistor DT is also more stable and not prone to fluctuations.

[0084]

[0085] It can be seen from the above table that the threshold voltage of the driving transistor DT is closer to the reference threshold voltage of -2.8V when there is an opaque film and the relative voltage is 0V; the drain current of the driving transistor DT is the smallest when there is an opaque film and the relative voltage is 4.6V; the subthreshold swing of the driving transistor DT is 0.65 when there is an opaque film and the relative voltage is 0V, which is closest to the reference value of 0.69.

[0086] Although the leakage current of the driving transistor DT is minimized when there is an occlusion sheet and the relative voltage is 4.6V, since the threshold voltage at this time is -3.4V, with a large deviation, it makes the correction difficult. Therefore, the situation with the smallest deviation of the threshold voltage and a relatively small leakage current is selected, that is, the situation with an occlusion sheet and a relative voltage of 0V, to improve the threshold voltage of the driving transistor DT.

[0087] In addition, for the above three cases, tests are all carried out under normal external light illumination, and the Id-Vg curves as shown in Figure 4 , Figure 5 and Figure 6 are obtained. The abscissas in Figure 4 , , Figure 5 , and Figure 6 are all gate-source voltages, and the ordinates are all drain-source currents. Through analysis, it can be known that Figure 5 the curve of the driving transistor DT when there is an occlusion sheet and the relative voltage is 0V in is more concentrated, that is, the Id fluctuation of the driving transistor DT is smaller, and thus the threshold voltage of the driving transistor DT is more stable.

[0088] Combining the above discussion, an embodiment of the present disclosure provides a driving backplane BP, as shown in Figure 7 . The driving backplane BP includes a substrate SU and a driving layer CL. The driving layer CL is located on one side of the substrate SU. The driving layer CL includes an occlusion layer BSM and a circuit layer PC distributed in a direction away from the substrate SU. The circuit layer PC forms a plurality of pixel circuits. Among them, the pixel circuit includes a driving transistor DT and a first switching transistor ST1. The first pole DT-a1 of the driving transistor DT is electrically connected to the first pole of the first switching transistor ST1. The first pole DT-a1 of the driving transistor is used to input a first power signal. The second pole of the driving transistor DT is used to be electrically connected to a light-emitting device. The second pole of the first switching transistor ST1 is used to input a data signal. The occlusion layer BSM includes a first occlusion sheet SM1. There is an overlapping area between the driving transistor DT and the first occlusion sheet SM1 in the direction perpendicular to the substrate SU. The first occlusion sheet SM1 is electrically connected to the first pole DT-a1 of the driving transistor.

[0089] ​​In the embodiments of the present disclosure, there is an overlapping region between the driving transistor DT and the first light shielding sheet SM1 in the direction perpendicular to the substrate SU, so as to shield the driving transistor DT through the first light shielding sheet SM1, avoid the influence of external light, thus avoid the increase of photo-generated carriers, and further avoid the fluctuation of the threshold voltage of the driving transistor DT; secondly, through the electrical connection between the first light shielding sheet SM1 and the first pole DT-a1 of the driving transistor, the accumulation of charges on the first light shielding sheet SM1 is avoided, the service life of the first light shielding sheet SM1 is extended, and it is also ensured that the first light shielding sheet SM1 always maintains the voltage of the first pole DT-a1 of the driving transistor, that is, it is ensured that the threshold voltage of the driving transistor DT always maintains the same state, thereby further avoiding the fluctuation of the threshold voltage of the driving transistor DT and ensuring that the driving transistor DT always works in a normal state.

[0090] Next, the pixel circuit formed by the circuit layer PC in the embodiments of the present disclosure will be explained in detail:

[0091] In the embodiments of the present disclosure, the driving layer CL can be at least divided into a display area AA and a non-display area WA located outside the display area AA, that is, the driving layer CL has a display area AA and a non-display area WA, and a plurality of pixel circuits formed by the circuit layer PC are located in the display area AA. The number of pixel circuits is the same as the number of light-emitting devices, and they are connected to each light-emitting device one by one to control the light emission of each light-emitting device respectively. Of course, it is also possible that the same pixel circuit drives multiple light-emitting devices to emit light, and the embodiments of the present disclosure do not limit this.

[0092] Among them, the plurality of pixel circuits can be arranged in a matrix. The pixel circuit can be a 6T1C, 7T1C, etc. circuit, as long as it can drive the light-emitting device to emit light, and the embodiments of the present disclosure do not make special limitations on this. nTmC means that a pixel circuit includes n transistors (represented by the letter "T") and a capacitor Cst (represented by the letter "C").

[0093] In some embodiments of the present disclosure, as Figure 8 shown, the pixel circuit includes a driving transistor DT and a first switching transistor ST1. The first pole DT-a1 of the driving transistor is used to input a first power signal. The second pole of the driving transistor DT is electrically connected to the light-emitting device. The first pole of the first switching transistor ST1 is electrically connected to the first pole DT-a1 of the driving transistor. The second pole of the first switching transistor ST1 is used to input a data signal. The control pole ST1-g of the first switching transistor is used to input a scan signal. Among them, one end of the light-emitting device connected to the driving transistor DT is used to input a second power signal.

[0094] It should be noted that, in addition to the driving transistor DT and the first switching transistor ST1, the pixel circuit may further include other transistors and a capacitor Cst. By way of example, taking a 7T1C circuit as an example, as Figure 8 shown, the pixel circuit includes a driving transistor DT, a first switching transistor ST1, a second switching transistor ST2, a third switching transistor ST3, a fourth switching transistor ST4, a fifth switching transistor ST5, a sixth switching transistor ST6, and a capacitor Cst.

[0095] The first pole DT-a1 of the driving transistor is electrically connected to the first pole of the first switching transistor ST1 and the first pole of the sixth switching transistor ST6 respectively. The second pole of the driving transistor DT is electrically connected to the second pole of the third switching transistor ST3 and the first pole of the fourth switching transistor ST4 respectively. The control pole DT-g of the driving transistor is electrically connected to the first pole of the second switching transistor ST2, the first pole of the third switching transistor ST3, and the first electrode plate of the capacitor Cst.

[0096] The second pole of the first switching transistor ST1 is used to input a data signal, and the control pole ST1-g of the first switching transistor is used to input a scanning signal; the second pole of the second switching transistor ST2 is used to input a first initial voltage signal, and the control pole ST2-g of the second switching transistor is used to input a reset signal; the control pole ST3-g of the third switching transistor is used to input a scanning signal; the second pole of the fourth switching transistor ST4 is electrically connected to the first pole of the fifth switching transistor ST5 and is used to be electrically connected to a light-emitting device. The control pole ST4-g of the fourth switching transistor is used to input a light-emitting control signal; the second pole of the fifth switching transistor ST5 is used to input a second initial voltage signal, and the control pole ST5-g of the fifth switching transistor is used to input a reset signal; the second pole of the sixth switching transistor ST6 is electrically connected to the second electrode plate of the capacitor Cst and is used to input a power supply signal, and the control pole ST6-g of the sixth switching transistor is used to input a light-emitting control signal.

[0097] Next, the structure of the circuit layer PC involved in the embodiments of the present disclosure will be explained in detail:

[0098] In some embodiments of the present disclosure, as Figure 7 shown, the circuit layer PC includes, distributed in a direction away from the substrate SU: a buffer layer BUF, an active layer POLY, a first gate insulating layer GI1, a first gate metal layer Ga1, a second gate insulating layer GI2, and a first source-drain metal layer SD1. The active layer POLY may be a polysilicon layer, an oxide thin film layer, or other structural layers, as long as it can form the channel region of the transistor and the two connecting portions (having electrical conductivity) on both sides of the channel region. The embodiments of the present disclosure do not limit this.

[0099] Of course, the circuit layer PC may further include other structural layers. By way of example, as Figure 7 shown, in addition to the above-mentioned structural layers, the circuit layer PC may further include a third gate insulating layer GI3 and a second gate metal layer Ga2 that are located between the first gate metal layer Ga1 and the second gate insulating layer GI2 and are distributed in a direction away from the substrate SU.

[0100] Combined with the above pixel circuit, when the pixel circuit formed by the circuit layer PC includes a driving transistor DT, as Figure 9 、 Figure 10 and Figure 11 shown, the active layer POLY includes a first active portion P1, and the first active portion P1 includes a first channel region and first connection portions P11 and second connection portions P12 located on both sides of the first channel region; the first gate insulating layer GI1 covers at least the first active portion P1; the first gate metal layer Ga1 includes a first conductive portion 10, and the first conductive portion 10 has an overlapping region with the first channel region in a direction perpendicular to the substrate SU; the second gate insulating layer GI2 covers at least the first conductive portion 10. Thus, the first pole DT-a1 and the second pole of the driving transistor are correspondingly formed by the first connection portion P11 and the second connection portion P12, and the control pole DT-g of the driving transistor is formed by the region of the first conductive portion 10 that overlaps with the first channel region, so as to form the driving transistor DT of the pixel circuit.

[0101] When the pixel circuit formed by the circuit layer PC includes a first switching transistor ST1, as Figure 9 、 Figure 10 and Figure 11 shown, the active layer POLY includes a second active portion P2, and the second active portion P2 includes a second channel region and third connection portions P21 and fourth connection portions P22 located on both sides of the second channel region. The first gate insulating layer GI1 covers the second active portion P2; the first gate metal layer Ga1 includes a scan signal line Gate, and the scan signal line Gate has an overlapping region with the second channel region in a direction perpendicular to the substrate SU. The second gate insulating layer GI2 covers the scan signal line Gate. Thus, the first pole and the second pole of the first switching transistor ST1 are correspondingly constituted by the third connection portion P21 and the fourth connection portion P22, and the control pole ST1-g of the first switching transistor is constituted by the region of the scan signal line Gate that overlaps with the second channel region, so as to form the first switching transistor ST1 of the pixel circuit.

[0102] When the pixel circuit formed by the circuit layer PC includes a second switching transistor ST2, as Figure 9 、 Figure 10 and Figure 11As shown, the active layer POLY includes a third active portion P3. The third active portion P3 includes a third channel region and fifth and sixth connection portions P31 and P32 located on both sides of the third channel region. The first gate insulating layer GI1 covers the third active portion P3. The first gate metal layer Ga1 includes a reset signal line Reset. The reset signal line Reset has an overlapping region with the third channel region in the direction perpendicular to the substrate SU. The second gate insulating layer GI2 covers the reset signal line Reset. Thus, the fifth and sixth connection portions P31 and P32 respectively form the first and second poles of the second switching transistor ST2, and the region of the reset signal line Reset that overlaps with the third channel region forms the control pole ST2-g of the second switching transistor, so as to form the second switching transistor ST2 of the pixel circuit.

[0103] When the pixel circuit formed by the circuit layer PC includes a third switching transistor ST3, as Figure 9 、 Figure 10 and Figure 11 shown, the active layer POLY includes a fourth active portion P4. The fourth active portion P4 includes a fourth channel region and seventh and eighth connection portions P41 and P42 located on both sides of the fourth channel region. The first gate insulating layer GI1 covers the fourth active portion P4. The scan signal line Gate included in the first gate metal layer Ga1 has an overlapping region with the fourth channel region in the direction perpendicular to the substrate SU. Thus, the seventh and eighth connection portions P41 and P42 respectively form the first and second poles of the third switching transistor ST3, and the region of the scan signal line Gate that overlaps with the fourth channel region forms the control pole ST3-g of the third switching transistor, so as to form the third switching transistor ST3 of the pixel circuit.

[0104] When the pixel circuit formed by the circuit layer PC includes a fourth switching transistor ST4, as Figure 9 、 Figure 10 and Figure 11 shown, the active layer POLY includes a fifth active portion P5. The fifth active portion P5 includes a fifth channel region and ninth and tenth connection portions P51 and P52 located on both sides of the fifth channel region. The first gate insulating layer GI1 covers the fifth active portion P5. The light emission control signal line EM included in the first gate metal layer Ga1 has an overlapping region with the fifth channel region in the direction perpendicular to the substrate SU. Thus, the ninth and tenth connection portions P51 and P52 respectively form the first and second poles of the fourth switching transistor ST4, and the region of the light emission control signal line that overlaps with the fifth channel region forms the control pole ST4-g of the fourth switching transistor, so as to form the fourth switching transistor ST4 of the pixel circuit.

[0105] When the pixel circuit formed by the circuit layer PC includes a fifth switching transistor ST5, asFigure 9 , Figure 10 and Figure 11 As shown in Figure 9 , Figure 10 , and Figure 11 , the active layer POLY includes a sixth active portion P6. The sixth active portion P6 includes a sixth channel region and eleventh and twelfth connection portions P61 and P62 located on both sides of the sixth channel region. The first gate insulating layer GI1 covers the sixth active portion P6. The reset signal line Reset included in the first gate metal layer Ga1 has an overlapping region with the sixth channel region in the direction perpendicular to the substrate SU. Thus, the eleventh and twelfth connection portions P61 and P62 respectively constitute the first and second poles of the fifth switching transistor ST5, and the overlapping region of the reset signal line Reset with the sixth channel region constitutes the control pole ST5-g of the fifth switching transistor, so as to form the fifth switching transistor ST5 of the pixel circuit.

[0106] When the pixel circuit formed by the circuit layer PC includes a sixth switching transistor ST6, as Figure 9 , Figure 10 and Figure 11 As shown in Figure 9 , Figure 10 , and Figure 11 , the active layer POLY includes a seventh active portion P7. The seventh active portion P7 includes a seventh channel region and thirteenth and fourteenth connection portions P71 and P72 located on both sides of the seventh channel region. The first gate insulating layer GI1 covers the seventh active portion P7. The emission control signal line EM included in the first gate metal layer Ga1 has an overlapping region with the seventh channel region in the direction perpendicular to the substrate SU. Thus, the thirteenth and fourteenth connection portions P71 and P72 respectively constitute the first and second poles of the sixth switching transistor ST6, and the overlapping region of the emission control signal line EM with the seventh channel region constitutes the control pole ST6-g of the sixth switching transistor, so as to form the sixth switching transistor ST6 of the pixel circuit.

[0107] When the pixel circuit formed by the circuit layer PC includes a capacitor Cst, as Figure 10 , Figure 12 and Figure 13 As shown in Figure 10 , Figure 12 , and Figure 13 , the second gate metal layer Ga2 includes a second conductive portion 20. The second conductive portion 20 has an overlapping region with the first conductive portion 10 in the direction perpendicular to the substrate SU. Thus, the first conductive portion 10 and the second conductive portion 20 respectively constitute the two electrodes of the capacitor Cst.

[0108] Among them, as Figure 10As shown, the first gate metal layer Ga1 includes a first conductive portion 10, a reset signal line Reset, a scan signal line Gate, and a light emission control signal line EM. The reset signal line Reset, the scan signal line Gate, and the light emission control signal line EM extend along the row direction X. A plurality of first conductive portions 10 are sequentially distributed along the row direction X, and the reset signal line Reset, the scan signal line Gate, the first conductive portion 10, and the light emission control signal line EM are sequentially distributed along the column direction Y perpendicular to the row direction X. As Figure 12 As shown, the second gate metal layer Ga2 includes a first initial voltage signal line Vinit1, a second initial voltage signal line Vinit2, a shielding layer 30, and a second conductive portion 20. The first initial voltage signal line Vinit1 and the second initial voltage signal line Vinit2 extend along the row direction X. A plurality of shielding layers 30 and a plurality of second conductive portions 20 are both distributed along the row direction X, and the first initial voltage signal line Vinit1, the second initial voltage signal line Vinit2, the shielding layer 30, and the second conductive portion 20 are distributed along the column direction Y perpendicular to the row direction X. The second conductive portion 20 faces the corresponding first conductive portion 10.

[0109] Combined with the 7T1C circuit in the above example, as Figure 8 As shown, the first active layer POLY includes a first active portion P1, a second active portion P2, a third active portion P3, a fourth active portion P4, a fifth active portion P5, a sixth active portion P6, and a seventh active portion P7 which are of an integral structure to realize the electrical connection of the first connection portion P11, the third connection portion P21, and the thirteenth connection portion P71, the electrical connection of the second connection portion P12, the eighth connection portion P42, and the ninth connection portion P51, the electrical connection of the fifth connection portion P31 and the seventh connection portion P41, and the electrical connection of the tenth connection portion P52 and the eleventh connection portion P61.

[0110] As Figure 14 As shown, the first source-drain metal layer SD1 includes a data line Data, a first power supply signal line VDD1, a third connection line C, a fourth connection line D, a fifth connection line E, and a sixth connection line F. The data line Data and the first power supply signal line VDD1 extend along the column direction and are distributed along the row direction.

[0111] At this time, as Figure 15As shown, the first conductive part 10 is electrically connected to the fifth connection part P31 through via 1, the third connection line CC, and via 2; the first initial voltage signal line Vinit1 is electrically connected to the sixth connection part P32 through via 3, the fourth connection line DD, and via 4, the second initial voltage signal line Vinit2 is electrically connected to the twelfth connection part P62 through via 5, the fifth connection line EE, and via 6, the second conductive part 20 is electrically connected to the first power supply signal line VDD1 through via 7, and the shielding layer 30 is electrically connected to the first power supply signal line VDD1 through via 8; the first power supply signal line VDD1 is electrically connected to the fourteenth connection part P72 through via 9, the data line Data is electrically connected to the fourth connection part P22 through via 10, the tenth connection part P52 is electrically connected to one end of the sixth connection line F through via 11, and the other end of the sixth connection line F is used for electrical connection to a light-emitting device.

[0112] In some other embodiments of the present disclosure, in addition to including the above-mentioned buffer layer BUF, active layer POLY, first gate insulating layer GI1, first gate metal layer Ga1, third gate insulating layer GI3, second gate metal layer Ga2, second gate insulating layer GI2, and first source-drain metal layer SD1, as Figure 16 shown, the circuit layer PC further includes a passivation layer PVX, a first protective layer PLN1, and a second source-drain metal layer SD2 located on the side of the first source-drain metal layer SD1 away from the substrate SU and distributed in a direction away from the substrate SU.

[0113] Among them, as Figure 17 shown, the second source-drain metal layer SD2 includes a second power supply signal line VDD2 and a seventh connection line G. As Figure 18 shown, the second power supply signal line VDD2 is electrically connected to the first power supply signal line VDD1 through via 11, one end of the seventh connection line G is electrically connected to the sixth connection line F through via 12, and the other end of the seventh connection line G is used for electrical connection to a light-emitting device. The electrical connection between the second power supply signal line VDD2 and the first power supply signal line VDD1 increases the current-carrying area of the first power supply signal, thereby reducing the resistance of the first power supply signal transmission.

[0114] In still some other embodiments of the present disclosure, in addition to including the above-mentioned buffer layer BUF, active layer POLY, first gate insulating layer GI1, first gate metal layer Ga1, third gate insulating layer GI3, second gate metal layer Ga2, second gate insulating layer GI2, first source-drain metal layer SD1, passivation layer PVX, first protective layer PLN1, and second source-drain metal layer SD2, for the convenience of fabricating light-emitting devices on the subsequent driving backplane BP, as Figure 19As shown, the circuit layer PC further includes a second protective layer PLN2, a first electrode layer ANO, and a pixel definition layer PDL, which are located on the side of the second source-drain metal layer SD2 away from the substrate SU and are distributed in a direction away from the substrate SU.

[0115] Among them, the first electrode layer ANO includes electrode pieces. As shown in Figure 20 The electrode pieces are electrically connected to the seventh connection line G of the second source-drain metal layer SD2 through vias 13 to realize the electrical connection between the seventh connection line G and the light-emitting device.

[0116] Next, the light-shielding layer BSM in the embodiments of the present disclosure will be explained in detail:

[0117] In the embodiments of the present disclosure, as shown in Figure 21 and Figure 22 The light-shielding layer BSM includes a first light-shielding piece SM1. There is an overlapping area between the driving transistor DT and the first light-shielding piece SM1 in the direction perpendicular to the substrate SU. The first light-shielding piece SM1 is electrically connected to the first pole DT-a1 of the driving transistor. In this way, the driving transistor DT is shielded by the first light-shielding piece SM1 to avoid being affected by external light. Secondly, through the electrical connection between the first light-shielding piece SM1 and the first pole DT-a1 of the driving transistor, the accumulation of charges on the first light-shielding piece SM1 is avoided, and the voltage of the first pole DT-a1 of the driving transistor is always maintained on the first light-shielding piece SM1.

[0118] Among them, since external light mainly affects the control pole DT-g of the driving transistor, that is, it mainly affects the area of the first conductive portion 10 overlapping with the first channel region. Therefore, the first light-shielding piece SM1 can be used to shield the first conductive portion 10 to avoid the influence of the threshold voltage of the driving transistor DT caused by external light. For example, the area of the first conductive portion 10 overlapping with the first channel region can be shielded by the first light-shielding piece SM1, that is, the projection of the area of the first conductive portion 10 overlapping with the first channel region on the first light-shielding piece SM1 is located within the area of the first light-shielding piece SM1. Of course, the first conductive portion 10 is an overall conductive structure. At this time, in order to ensure the shielding effect of the first light-shielding piece SM1 on the driving transistor DT, the first conductive portion 10 can also be shielded by the first light-shielding piece SM1 as a whole, that is, the projection of the first conductive portion 10 on the plane where the first light-shielding piece SM1 is located is located within the first light-shielding piece SM1. In this way, the first light-shielding piece SM1 is used to shield external light, avoiding the influence of external light on the first conductive portion 10, and further avoiding the increase in photo-generated carriers in the first channel region.

[0119] Among them, the first light-shielding sheet SM1 is directly electrically connected to the first pole DT-a1 of the driving transistor, or the first light-shielding sheet SM1 is indirectly electrically connected to the first pole DT-a1 of the driving transistor through a connection line. Exemplarily, as Figure 22 shown, the first source-drain metal layer SD1 further includes a first connection line A. The first end of the first connection line A is electrically connected to the first pole DT-a1 of the driving transistor, and the second end of the first connection line A is electrically connected to the first light-shielding sheet SM1. Combining with the driving transistor DT constituted by the circuit layer PC layer structure described above, the first light-shielding sheet SM1 is directly electrically connected to the first connection portion P11, or the first light-shielding sheet SM1 is indirectly electrically connected to the first connection portion P11 through a connection line. Exemplarily, the first source-drain metal layer SD1 further includes a first connection line A. The first end of the first connection line A is electrically connected to the first connection portion P11 through a via 14, and the second end of the first connection line A is electrically connected to the first light-shielding sheet SM1 through a via 15.

[0120] In some embodiments of the present disclosure, as Figure 21 shown, the first light-shielding sheet SM1 includes a main body portion SM11 and a protruding portion SM12. The projection of the first conductive portion 10 on the plane where the main body portion SM11 is located is located within the area where the main body portion SM11 is located. The protruding portion SM12 is electrically connected to the main body portion SM11 and the second end of the first connection line A respectively. Thus, the control pole DT-g of the driving transistor is formed by the area overlapping with the channel region on the main body portion SM11, and through the setting of the protruding portion SM12, interference caused by the first conductive portion 10 can be avoided when the main body portion SM11 is electrically connected to the first connection portion P11.

[0121] Among them, the main body portion SM11 and the protruding portion SM12 can be an integral structure to simplify the formation process of the first light-shielding sheet SM1. As Figure 21 described, the main body portion SM11 and the protruding portion SM12 are distributed along the row direction. Exemplarily, the protruding portion SM12 is located on the left side of the main body portion SM11. Of course, the main body portion SM11 and the protruding portion can also be distributed along the column direction, and the embodiments of the present disclosure do not limit this.

[0122] When the main body portion SM11 and the protruding portion SM12 are distributed along the row direction, in order to facilitate the electrical connection between the first connection line A and the protruding portion SM12 and the first connection portion P11, and at the same time save the space occupied by the first connection line A, the length direction of the first connection line A is the same as the extension direction of the data line Data. Exemplarily, as Figure 22 shown, the first connection line A extends along the column direction, that is, the first end and the second end of the first connection line A are respectively two ends in the column direction.

[0123] In some embodiments of the present disclosure, in order to simplify the process and at the same time ensure the stability of the electrical connection between the first connection line A and the first connection portion P11 and the protruding portion SM12 respectively, there is an overlapping area between the first end of the first connection line A and the first connection portion P11 in the direction perpendicular to the substrate SU, and there is an overlapping area between the second end of the first connection line A and the protruding portion SM12 in the direction perpendicular to the substrate SU. In this way, the first end of the first connection line A and the first connection portion P11 can be directly electrically connected through a via hole, and the second end of the first connection line A and the protruding portion SM12 can also be directly electrically connected through a via hole.

[0124] In some embodiments of the present disclosure, the first source-drain metal layer SD1 includes a data line Data and a first power supply signal line VDD1. The data line Data and the first power supply signal line VDD1 are distributed along the row direction and extend along the column direction. The first power supply signal line VDD1 is electrically connected to the first connection portion P11.

[0125] When setting the first connection line A on the first source-drain metal layer SD1 at this time, in order to avoid positional interference with the data line Data and the first power supply signal line VDD1, as Figure 14 shown, the first power supply signal line VDD1 has a bent portion VDD1-o facing away from the data line Data. There is an overlapping area between the bent portion VDD1-o and the first conductive portion 10 in the direction perpendicular to the substrate SU. The first connection line A is located in the area surrounded by the data line Data and the bent portion VDD1-o.

[0126] Among them, through the design of the bent portion VDD1-o, it is not only convenient for the electrical connection between the bent portion VDD1-o and the first conductive portion 10, but also can achieve avoidance, which is convenient for arranging vias electrically connected to the first connection portion P11 and the protruding portion SM12 directly below the first connection line A.

[0127] In some embodiments of the present disclosure, as Figure 21 and Figure 22 shown, the shielding layer BSM includes a second shielding sheet SM2. There is an overlapping area between the first switching transistor ST1 and the second shielding sheet SM2 in the direction perpendicular to the substrate SU. The second shielding sheet SM2 is electrically connected to the control electrode ST1-g of the first switching transistor.

[0128] In this way, the first shielding sheet SM1 shields the first switching transistor ST1 to avoid the influence of external light, thereby preventing the increase of photo-generated carriers, and further avoiding the fluctuation of the threshold voltage of the first switching transistor ST1. Secondly, by electrically connecting the second shielding sheet SM2 to the control electrode ST1-g of the first switching transistor, the accumulation of charges on the second shielding sheet SM2 is avoided, the service life of the second shielding sheet SM2 is extended, and it is ensured that the second shielding sheet SM2 always maintains the voltage of the control electrode ST1-g of the first switching transistor, that is, it is ensured that the threshold voltage of the first switching transistor ST1 always maintains the same state, thereby further avoiding the fluctuation of the threshold voltage of the first switching transistor ST1 and ensuring that the first switching transistor ST1 always operates in a normal state.

[0129] For multiple pixel circuits in the same row direction, there are overlapping regions between the first switching transistors ST1 and the second shielding sheets SM2 of the multiple pixel circuits in the direction perpendicular to the substrate SU. That is, by providing a single-piece second shielding sheet SM2, the influence of external light on the first switching transistors ST1 of the multiple pixel circuits can be blocked simultaneously. Multiple pixel circuits in the same row direction receive the same scanning signal.

[0130] Among them, the second shielding sheet SM2 is directly electrically connected to the control electrode ST1-g of the first switching transistor, or the second shielding sheet SM2 is indirectly electrically connected to the control electrode ST1-g of the first switching transistor through a connecting wire. Exemplarily, the second source-drain metal layer SD2 further includes a second connecting wire B. The first end of the second connecting wire B is electrically connected to the control electrode ST1-g of the first switching transistor, and the second end of the first connecting wire A is electrically connected to the second shielding sheet SM2. Combining the first switching transistor ST1 formed by the circuit layer PC described above, the second shielding sheet SM2 is directly electrically connected to the scanning signal line Gate, or the second shielding sheet SM2 is indirectly electrically connected to the scanning signal line Gate through a connecting wire. Exemplarily, as Figure 23 shown, the second source-drain metal layer SD2 further includes a second connecting wire B. The first end of the second connecting wire B is electrically connected to the scanning signal line Gate through a via 16, and the second end of the first connecting wire A is electrically connected to the second shielding sheet SM2 through a via 17.

[0131] Among them, for the first switching transistors ST1 of multiple pixel circuits in the same row direction, the control electrodes ST1-g of the multiple first switching transistors ST1 are all electrically connected to the scanning signal line Gate. Furthermore, the control electrodes ST1-g of the multiple first switching transistors ST1 are simultaneously electrically connected to the second shielding sheet SM2 through the second connecting wire B, reducing the setting of electrical connection points between the first switching transistor ST1 and the second shielding sheet SM2, simplifying the structure diagram, and thus simplifying the manufacturing process of the electrical connection between the first switching transistor ST1 and the second shielding sheet SM2.

[0132] In some embodiments of the present disclosure, in combination with the display area AA and the non-display area WA of the driving layer CL described above, the second connection line B is located in the display area AA, and the part of the scanning signal line Gate located in the display area AA and the part of the second light-shielding sheet SM2 located in the display area AA are both electrically connected to the second connection line B. In this way, the electrical connection between the scanning signal line Gate and the second light-shielding sheet SM2 can be achieved in the display area AA.

[0133] Of course, in order to simplify the complexity of the pixel circuit layout in the display area AA, the electrical connection between the scanning signal line Gate and the second light-shielding sheet SM2 can also be achieved in the non-display area WA. As Figure 23 described, the second connection line B is located in the non-display area WA, and both the scanning signal line Gate and the second light-shielding sheet SM2 extend from the display area AA to the non-display area WA. The part of the scanning signal line Gate located in the non-display area WA and the part of the second light-shielding sheet SM2 located in the non-display area WA are both electrically connected to the second connection line B.

[0134] It should be noted that since the external light mainly affects the control electrode ST1-g of the first switching transistor, that is, it mainly affects the area of the scanning signal line Gate overlapping with the second channel region. Therefore, the scanning signal line Gate can be shielded from light by the second light-shielding sheet SM2 to avoid the influence of the external light on the threshold voltage of the first switching transistor ST1. Exemplarily, the area of the scanning signal line Gate overlapping with the first channel region can be shielded by the second light-shielding sheet SM2, that is, the projection of the area of the scanning signal line Gate overlapping with the first channel region on the second light-shielding sheet SM2 is located within the area where the second light-shielding sheet SM2 is located. Of course, the scanning signal line Gate is an overall conductive structure. At this time, in order to ensure the shielding effect of the second light-shielding sheet SM2 on the first switching transistor ST1, the scanning signal line Gate can also be shielded as a whole by the second light-shielding sheet SM2, that is, within the display area AA, the scanning signal line Gate is directly above the second light-shielding sheet SM2. Exemplarily, the projection of the scanning signal line Gate on the plane where the second light-shielding sheet SM2 is located within the display area AA is located within the second light-shielding sheet SM2. In this way, the shielding of the external light is achieved through the second light-shielding sheet SM2, avoiding the influence of the external light on the scanning signal line Gate, and further avoiding the increase in photo-generated carriers in the second channel region.

[0135] Furthermore, as Figure 21As shown, the width of the overlapping region between the scanning signal line Gate and the second channel region is smaller than the width of the overlapping region between the second light-shielding sheet SM2 and the second channel region. In this way, it is possible to avoid the irradiation of non-normal incident light beams in external light on the first switching transistor ST1, so as to prevent the threshold voltage of the first switching transistor ST1 from fluctuating, and further ensure that the first switching transistor ST1 operates in a normal state.

[0136] In some embodiments of the present disclosure, the light-shielding layer BSM further includes a light-shielding sheet for shielding the third switching transistor ST3, and the light-shielding sheet for shielding the third switching transistor ST3 is electrically connected to the control electrode ST3-g of the third switching transistor.

[0137] Combined with the description of the above pixel circuit, the third switching transistor ST3 is also used to receive a scanning signal. And combined with the description of the above circuit layer PC layer structure, the region overlapping with the fourth channel region on the same scanning signal line Gate constitutes the control electrode ST3-g of the third switching transistor. Therefore, as Figure 22 shown, when the scanning signal line Gate is shielded by the second light-shielding sheet SM2, it is possible to simultaneously shield the first switching transistor ST1 and the third switching transistor ST3. That is, there is an overlapping region between the third switching transistor ST3 and the second light-shielding sheet SM2 in the direction perpendicular to the substrate SU, and the control electrode ST3-g of the third switching transistor is electrically connected to the second light-shielding sheet SM2. In this way, not only can the influence of external light on the first switching transistor ST1 and the third switching transistor ST3 be avoided, but also the regularity of the structural layer can be ensured, the aesthetics can be improved, and the manufacturing process can be simplified.

[0138] Among them, the electrical connection between the control electrode ST3-g of the third switching transistor and the second light-shielding sheet SM2 is actually the electrical connection between the scanning signal line Gate and the second light-shielding sheet SM2. For this, reference can be made to the above-described embodiments, and the embodiments of the present disclosure will not be elaborated herein.

[0139] In some embodiments of the present disclosure, combined with the description of the above pixel circuit, the fourth switching transistor ST4 and the sixth switching transistor ST6 are used to receive the same light-emitting control signal. And combined with the description of the above circuit layer PC layer structure, the region overlapping with the fifth channel region on the same light-emitting control signal line EM constitutes the control electrode ST4-g of the fourth switching transistor, and the region overlapping with the seventh channel region constitutes the control electrode ST6-g of the sixth switching transistor. In this way, when shielding the fourth switching transistor ST4 and / or the sixth switching transistor ST6, the same light-shielding sheet can be used for shielding.

[0140] As Figure 21 and Figure 22As shown, the light-shielding layer BSM further includes a third light-shielding sheet SM3. The fourth switching transistor ST4, the sixth switching transistor ST6, and the third light-shielding sheet SM3 all have overlapping regions in the direction perpendicular to the substrate SU. The control electrode ST4-g of the fourth switching transistor and the control electrode ST6-g of the sixth switching transistor are both electrically connected to the third light-shielding sheet SM3. In this way, not only can the influence of external light on the fourth switching transistor ST4 and the sixth switching transistor ST6 be avoided, but also the regularity of the structural layer can be ensured, the aesthetics can be improved, and the manufacturing process can be simplified.

[0141] In addition, through the electrical connection between the third light-shielding sheet SM3 and the control electrode ST4-g of the fourth switching transistor and the control electrode ST6-g of the sixth switching transistor, the accumulation of charges on the third light-shielding sheet SM3 is avoided, the service life of the third light-shielding sheet SM3 is extended, and the voltage of the control electrode ST4-g of the fourth switching transistor is always maintained by the third light-shielding sheet SM3.

[0142] For multiple pixel circuits in the same row direction, the fourth switching transistors ST4, the sixth switching transistors ST6 of the multiple pixel circuits, and the third light-shielding sheet SM3 all have overlapping regions in the direction perpendicular to the substrate SU. That is, by providing a single third light-shielding sheet SM3, the influence of external light on the fourth switching transistors ST4 and the sixth switching transistors ST6 of the multiple pixel circuits can be blocked simultaneously. At this time, the control electrodes ST4-g of the multiple fourth switching transistors and the control electrodes ST6-g of the multiple sixth switching transistors are both electrically connected to the third light-shielding sheet SM3. Among them, the multiple pixel circuits are used to receive the same light-emitting control signal.

[0143] Among them, in combination with the layer structure of the circuit layer PC described above, the third light-shielding sheet SM3 is directly electrically connected to the light-emitting control signal line EM, or the third light-shielding sheet SM3 is indirectly electrically connected to the light-emitting signal line through a connection line. Exemplarily, the second source-drain metal layer SD2 further includes an eighth connection line. The first end of the eighth connection line is electrically connected to the light-emitting control signal line EM, and the second end of the eighth connection line is electrically connected to the third light-shielding sheet SM3. For the specific description of electrically connecting the scanning signal line Gate and the second light-shielding sheet SM2 through the second connection line B, which can be referred to the above-described embodiments, the embodiments of the present disclosure will not be elaborated herein.

[0144] Exemplarily, the eighth connection line is located in the non-display area WA. The light-emitting control signal line EM and the third light-shielding sheet SM3 both extend from the display area AA to the non-display area WA. The part of the light-emitting control signal line EM located in the non-display area WA and the part of the third light-shielding sheet SM3 located in the non-display area WA are both electrically connected to the eighth connection line through vias.

[0145] It should be noted that the structure of the third light-shielding sheet SM3 can refer to the structure of the second light-shielding sheet SM2 described in the above embodiments, and the embodiments of the present disclosure will not elaborate on this again.

[0146] In some embodiments of the present disclosure, in combination with the description of the above pixel circuit, the second switching transistor ST2 and the fifth switching transistor ST5 are used to receive the same reset signal. And in combination with the description of the structure of the above circuit layer PC layer, as Figure 15 shown, in the same column of pixel circuits, the region overlapping with the channel region of the fifth switching transistor ST5 of the nth pixel circuit on the same reset signal line Reset forms the control electrode ST5-g of the fifth switching transistor of the nth pixel circuit, and the region overlapping with the channel region of the second switching transistor ST2 of the (n + 1)th pixel circuit forms the control electrode ST2-g of the second switching transistor of the (n + 1)th pixel circuit. In this way, when shielding the fifth switching transistor ST5 of the nth pixel circuit and / or the second switching transistor ST2 of the (n + 1)th pixel circuit, the same light-shielding sheet can be used for shielding.

[0147] Wherein, n is an integer greater than or equal to 1, and both the nth pixel circuit and the (n + 1)th pixel circuit refer to the pixel circuits obtained by counting from the top to the bottom of the display panel in the same column direction.

[0148] As Figure 21 and Figure 22 shown, the light-shielding layer BSM further includes a fourth light-shielding sheet SM4. In the same column of pixel circuits, there are overlapping regions between the fifth switching transistor ST5 of the nth pixel circuit, the second switching transistor ST2 of the (n + 1)th pixel circuit and the fourth light-shielding sheet SM4 in the direction perpendicular to the substrate SU. The control electrode ST5-g of the fifth switching transistor of the nth pixel circuit and the control electrode ST2-g of the second switching transistor of the (n + 1)th pixel circuit are both electrically connected to the fourth light-shielding sheet SM4. In this way, not only can the influence of external light on the fifth switching transistor ST5 of the nth pixel circuit and the second switching transistor ST2 of the (n + 1)th pixel circuit be avoided, but also the regularity of the structure layer can be ensured, the aesthetics can be improved, and the manufacturing process can be simplified.

[0149] In addition, through the electrical connection between the fourth light-shielding sheet SM4 and the control electrode ST5-g of the fifth switching transistor of the nth pixel circuit and the control electrode ST2-g of the second switching transistor of the (n + 1)th pixel circuit, the accumulation of charges on the fourth light-shielding sheet SM4 is avoided, the service life of the fourth light-shielding sheet SM4 is extended, and the voltage of the control electrode ST5-g of the fifth switching transistor of the nth pixel circuit is always maintained by the fourth light-shielding sheet SM4.

[0150] For the fifth switching transistor ST5 of the nth pixel circuit in each column direction, the second switching transistor ST2 of the (n + 1)th pixel circuit in each column direction, and the fourth light-shielding sheet SM4, there are overlapping regions in the direction perpendicular to the substrate SU. That is, by providing a single fourth light-shielding sheet SM4, the influence of external light on the fifth switching transistor ST5 of the nth pixel circuit in each column direction and the second switching transistor ST2 of the (n + 1)th pixel circuit in each column direction can be blocked simultaneously. At this time, the control electrodes ST5-g of the fifth switching transistors of the nth pixel circuit in each column direction and the control electrodes ST2-g of the second switching transistors of the (n + 1)th pixel circuit in each column direction are both electrically connected to the fourth light-shielding sheet SM4. Among them, the fifth switching transistor ST5 of the nth pixel circuit in each column direction and the second switching transistor ST2 of the (n + 1)th pixel circuit in each column direction are both used to receive the same reset signal.

[0151] Combined with the actual working principle of the pixel circuit, the scanning signal of the mth row pixel circuit can be used as the reset signal of the (m + 1)th row pixel circuit. Thus, the scanning signal line Gate corresponding to the mth row pixel circuit and the reset signal line Reset corresponding to the (m + 1)th row pixel circuit are an integral signal line. At this time, for the electrical connection between the reset signal line Reset and the fourth light-shielding sheet SM4, the second light-shielding sheet SM2 and the fourth light-shielding sheet SM4 can be integrally designed. For example, as Figure 23 shown, the scanning signal line Gate corresponding to the mth row pixel circuit and the reset signal line Reset corresponding to the (m + 1)th row pixel circuit are combined into an integral structure in the non-display area WA, and the second light-shielding sheet SM2 corresponding to the mth row pixel circuit and the fourth light-shielding sheet SM4 corresponding to the (m + 1)th row pixel circuit are combined into an integral structure in the non-display area WA. At this time, while the scanning signal line Gate is electrically connected to the second light-shielding sheet SM2, the electrical connection between the reset signal line Reset and the fourth light-shielding sheet SM4 is realized.

[0152] It should be noted that the structure of the fourth light-shielding sheet SM4 can refer to the structure of the second light-shielding sheet SM2 described in the above embodiments, and the embodiments of the present disclosure will not be elaborated herein.

[0153] The embodiments of the present disclosure also provide a manufacturing method of a driving backplane BP. The manufacturing method may include step S110 and step S120, where:

[0154] Step S110: Form a light-shielding layer on one side of the substrate.

[0155] Step S120: Form a circuit layer on a side of the shielding layer facing away from the substrate. The circuit layer includes an active layer, the active layer includes a first active portion, the first active portion includes a first channel region and first and second connection portions located on two sides of the first channel region, and the first connection portion is electrically connected to the shielding layer.

[0156] In some embodiments of the present disclosure, the shielding layer BSM includes a first shielding sheet SM1 and at least one of a second shielding sheet SM2, a third shielding sheet SM3, and a fourth shielding sheet SM4. When forming the shielding layer BSM, each shielding sheet can be formed simultaneously. For example: First, deposit a light-shielding material layer on the substrate SU, and then pattern the light-shielding material layer through exposure, development, and etching to obtain the shielding layer BSM including each shielding sheet.

[0157] The driving backplane BP manufactured by the manufacturing method of the embodiments of the present disclosure can be the driving backplane BP of any of the above embodiments. Its specific structure and beneficial effects have been described in detail above. Specifically, reference can be made to the embodiments of the driving backplane BP, and details will not be described herein again.

[0158] The embodiments of the present disclosure further provide a display panel, which includes a driving backplane BP and a light-emitting device, wherein:

[0159] The driving backplane BP can be the driving backplane BP of any of the above embodiments. Its structure can refer to the embodiments of the driving backplane BP above, and details will not be described herein again.

[0160] The light-emitting device is disposed on a side of the driving layer CL facing away from the substrate SU and is electrically connected to the second pole of the driving transistor DT.

[0161] The light-emitting device will be described in detail below:

[0162] In some embodiments of the present disclosure, the light-emitting device is an organic light-emitting diode (OLED), which may include a first electrode layer ANO, a light-emitting functional layer, and a second electrode layer stacked in sequence in a direction away from the driving backplane BP, wherein:

[0163] The first electrode layer ANO can be disposed on a side of the second protective layer PLN2 facing away from the substrate SU and is electrically connected to the connection line of the second source-drain metal layer SD2 through a via hole penetrating the second protective layer PLN2, so as to realize connection to the drain or source of a thin-film transistor of the pixel circuit. The light-emitting functional layer may include a hole injection layer, a hole transport layer, a composite light-emitting layer, an electron transport layer, and an electron injection layer stacked in sequence in a direction away from the driving backplane BP. In addition, an electron blocking layer may be provided between the hole transport layer and the composite light-emitting layer. The second electrode layer covers the light-emitting functional layer and can extend to the peripheral area and is connected to the peripheral circuit, and can be used to input a second power signal. The specific principle of the organic light-emitting diode emitting light will not be described in detail herein.

[0164] The number of light-emitting devices is multiple, and they are arrayed on the driving backplane BP. Each light-emitting device can be connected to a pixel circuit. Each light-emitting device can be divided into multiple light-emitting units, and the light-emitting units are arrayed. Each light-emitting unit includes multiple light-emitting devices with different emission colors. For example, the same light-emitting unit can include a light-emitting device that emits red light, a light-emitting device that emits green light, and a light-emitting device that emits blue light.

[0165] In the embodiments of the present disclosure, the display panel further includes a pixel definition layer PDL. The pixel definition layer PDL can be made of a light-shielding material. For example, the material of the pixel definition layer PDL can be a black photoresist.

[0166] In some embodiments of the present disclosure, the display panel may further include a plurality of support pillars, which can be disposed on the surface of the pixel definition layer PDL facing away from the substrate SU. When forming the light-emitting functional layer through an evaporation process, the support pillars can be used to support the mask. The specific height of the support pillars is not specifically limited herein. At the same time, in order to further block stray light, the support pillars can also be made of a light-shielding material, and its material can be the same as that of the pixel definition layer PDL. Thus, the pixel definition layer PDL and the support pillars can be formed simultaneously through a gray-scale mask process. Of course, they can also be formed independently. For example, the material of the support pillars can be a black photoresist.

[0167] Since the support pillars are formed on the pixel definition layer PDL, the second electrode layer of the light-emitting device can cover the support pillars and bulge at the support pillars, but does not break.

[0168] In the embodiments of the present disclosure, the display panel further includes a packaging layer, which can cover the surface of the light-emitting layer facing away from the driving backplane BP and cover all the light-emitting devices, thereby protecting the light-emitting layer and preventing water and oxygen in the outside world from eroding the light-emitting devices. At the same time, the boundary of the packaging layer extends into the peripheral area but does not exceed the peripheral area, and can also protect the peripheral circuits in the peripheral area.

[0169] In some embodiments of the present disclosure, encapsulation can be achieved by means of thin-film encapsulation (TFE). The packaging layer can include a first inorganic layer, an organic layer, and a second inorganic layer. The first inorganic layer covers the surface of the light-emitting layer facing away from the driving backplane BP. The organic layer can be disposed on the surface of the first inorganic layer facing away from the driving backplane BP, and the boundary of the organic layer is defined inside the boundary of the first inorganic layer. The second inorganic layer covers the organic layer and the first inorganic layer not covered by the organic layer, and can block the intrusion of water and oxygen through the second inorganic layer and achieve planarization through the flexible organic layer.

[0170] Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A driving backplane, characterized in that, it includes: a substrate; a driving layer located on one side of the substrate, the driving layer includes a shielding layer and a circuit layer distributed in a direction away from the substrate, and a plurality of pixel circuits are formed in the circuit layer; the pixel circuit includes a driving transistor and a first switching transistor, a first pole of the driving transistor is electrically connected to a first pole of the first switching transistor, the first pole of the driving transistor is used for inputting a first power signal, a second pole of the driving transistor is used for electrically connecting to a light-emitting device, and a second pole of the first switching transistor is used for inputting a data signal; the shielding layer includes a first shielding sheet, and there is an overlapping area between the driving transistor and the first shielding sheet in a direction perpendicular to the substrate, and the first shielding sheet is electrically connected to the first pole of the driving transistor; the circuit layer includes: an active layer located on a side of the shielding layer away from the substrate and including a first active portion, the first active portion includes a first channel region and first and second connection portions located on both sides of the first channel region; a first gate insulating layer located on a side of the active layer away from the substrate and at least covering the first active portion; a first gate metal layer located on a side of the first gate insulating layer away from the substrate and including a first conductive portion, and there is an overlapping area between the first conductive portion and the first channel region in a direction perpendicular to the substrate; a second gate insulating layer located on a side of the first gate metal layer away from the substrate and at least covering the first conductive portion; a first source-drain metal layer located on a side of the second gate insulating layer away from the substrate and including a first connection line, a first end of the first connection line is electrically connected to the first connection portion, and a second end of the first connection line is electrically connected to the first shielding sheet; the first connection portion and the second connection portion respectively form the first and second poles of the driving transistor, and an area of the first conductive portion overlapping with the first channel region forms the control pole of the driving transistor; the first shielding sheet includes a body portion and a protruding portion; a projection of the first conductive portion on a plane where the body portion is located is located in an area where the body portion is located, and the protruding portion is electrically connected to the body portion and the second end of the first connection line respectively; the first source-drain metal layer includes a data line and a first power signal line; the data line and the first power signal line are distributed along a row direction and extend along a column direction, and the first power signal line is electrically connected to the first connection portion; the first power signal line has a bent portion facing away from the data line, and there is an overlapping area between the bent portion and the first conductive portion in a direction perpendicular to the substrate, and the first connection line is located in an area surrounded by the data line and the bent portion; The control electrode of the first switching transistor is used to input a scanning signal; the shielding layer includes a second shielding sheet, and there is an overlapping area between the first switching transistor and the second shielding sheet in the direction perpendicular to the substrate; the second shielding sheet is electrically connected to the control electrode of the first switching transistor; there are overlapping areas between the first switching transistors and the second shielding sheets included in multiple pixel circuits in the same row direction in the direction perpendicular to the substrate.

2. The driving backplane according to claim 1, characterized in that the body part and the protruding part are distributed in the row direction, and the first connection line extends in the column direction.

3. The driving backplane according to claim 1, characterized in that the active layer includes a second active part, the second active part includes a second channel region and a third connection part and a fourth connection part located on both sides of the second channel region, and the first gate insulating layer covers the second active part; the first gate metal layer includes a scanning signal line, there is an overlapping area between the scanning signal line and the second channel region in the direction perpendicular to the substrate, and the second gate insulating layer covers the scanning signal line; the first source-drain metal layer includes a second connection line, the first end of the second connection line is electrically connected to the scanning signal line, and the second end of the second connection line is electrically connected to the second shielding sheet; the third connection part and the fourth connection part correspondingly form the first pole and the second pole of the first switching transistor, and the area on the scanning signal line overlapping with the second channel region forms the control electrode of the first switching transistor.

4. The driving backplane according to claim 3, characterized in that the driving layer has a display area and a non-display area located outside the display area; the second connection line is located in the non-display area, the scanning signal line and the second shielding sheet both extend from the display area to the non-display area, and the part of the scanning signal line located in the non-display area and the part of the second shielding sheet located in the non-display area are both electrically connected to the second connection line.

5. The driving backplane according to claim 4, characterized in that in the display area, the scanning signal line is directly above the second shielding sheet; the width of the area on the scanning signal line overlapping with the second channel region is smaller than the width of the area on the second shielding sheet overlapping with the second channel region.

6. The driving backplane according to claim 1, characterized in that the pixel circuit includes a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor and a capacitor; the first pole of the second switching transistor is electrically connected to the first pole of the third switching transistor, the control electrode of the driving transistor, and the first electrode plate of the capacitor respectively, the second pole of the second switching transistor is used to input a first initial voltage signal, and the control electrode of the second switching transistor is used to input a reset signal; the second pole of the third switching transistor is electrically connected to the second pole of the driving transistor and the first pole of the fourth switching transistor respectively, and the control electrode of the third switching transistor is used to input a scanning signal; The second electrode of the fourth switch transistor is electrically connected to the first electrode of the fifth switch transistor and is used to be electrically connected to the light emitting device, and the control electrode of the fourth switch transistor is used to input a light emitting control signal; The second electrode of the fifth switch transistor is used to input the second initial voltage signal, and the control electrode of the fifth switch transistor is used to input the reset signal; The first electrode of the sixth switch transistor is electrically connected to the first electrode of the driving transistor, the second electrode of the sixth switch transistor is electrically connected to the second electrode plate of the capacitor and is used to input the power supply signal, and the control electrode of the sixth switch transistor is used to input the light emission control signal; The third switch transistor and the second shielding sheet have an overlapping area in a direction perpendicular to the base substrate, and the control electrode of the third switch transistor is electrically connected to the second shielding sheet; The shielding layer further includes a third shielding sheet and a fourth shielding sheet, the fourth switch transistor, the sixth switch transistor and the third shielding sheet all have overlapping areas in a direction perpendicular to the base substrate, and the control electrode of the fourth switch transistor and the control electrode of the sixth switch transistor are both electrically connected to the third shielding sheet; In the same column of pixel circuits, the fifth switching transistor of the nth pixel circuit, the second switching transistor of the n+1th pixel circuit and the fourth shielding film all have overlapping areas in a direction perpendicular to the base substrate, and the control electrode of the fifth switching transistor of the nth pixel circuit and the control electrode of the second switching transistor of the n+1th pixel circuit are both electrically connected to the fourth shielding film.

7. A display panel, It is characterized in that include: The driving backplane according to any one of claims 1 to 6; The light emitting device is located on a side of the driving layer away from the base substrate and is electrically connected to the second electrode of the driving transistor.

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