Phase-locked loop parameter correction method, phase-locked loop, data processing device and storage medium

Abstract

A phase-locked loop (PLL) circuit parameter correction method, a phase-locked loop (PLL) circuit, a data processing device, an electronic device, and a non-transitory readable storage medium. The phase-locked loop circuit parameter correction method includes: setting multiple target parameters for the PLL circuit; obtaining multiple filter coefficients of a digital loop filter based on the multiple target parameters; and providing the multiple filter coefficients to the digital loop filter so that multiple operating parameters of the PLL circuit are correspondingly consistent with the multiple target parameters. The method automatically adjusts the multiple filter coefficients of the digital loop filter based on the set multiple target parameters so that the multiple operating parameters of the PLL circuit are correspondingly consistent with the multiple target parameters, thereby maintaining the overall operating characteristics (e.g., frequency characteristics) of the PLL circuit and improving the stability of the PLL circuit.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a parameter correction method for a phase-locked loop circuit, a phase-locked loop circuit, a data processing device, an electronic device, and a non-transitory readable storage medium. Background Art

[0002] A phase-locked loop (PLL) circuit is a circuit module based on negative feedback that generates a stable local oscillator or clock signal. It is an indispensable component in many radio frequency, communication, and digital systems. With the advancement of integrated circuit technology, analog PLLs face a series of challenges, including performance degradation and increased design difficulty caused by reduced power supply voltages and increased gate leakage of metal-oxide semiconductor field-effect transistors (MOSFETs). Furthermore, the loop filter capacitors of analog PLLs occupy a large chip area, especially in narrowband applications. These factors restrict the application of analog PLLs in advanced processes. To address these issues, fully digital PLLs are gaining increasing popularity. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a parameter correction method for a phase-locked loop circuit, which includes a digital loop filter. The method includes: setting multiple target parameters of the phase-locked loop circuit; based on the multiple target parameters, obtaining multiple filter coefficients of the digital loop filter, and providing the multiple filter coefficients to the digital loop filter, so that the multiple operating parameters of the phase-locked loop circuit are correspondingly consistent with the multiple target parameters.

[0004] For example, in at least one embodiment of the present disclosure, the phase-locked loop circuit further includes a time-to-digital converter and a digitally controlled oscillator. The time-to-digital converter is communicatively coupled to a digital loop filter, and the digital loop filter is communicatively coupled to the digitally controlled oscillator. Acquiring multiple filter coefficients for the digital loop filter based on multiple target parameters includes: acquiring the multiple filter coefficients based on the multiple target parameters, a first measurement result associated with the digitally controlled oscillator, and a second measurement result associated with the time-to-digital converter.

[0005] For example, the method provided by at least one embodiment of the present disclosure further includes: setting a first initial value for at least one target parameter among a plurality of target parameters; setting a second initial value corresponding to the first measurement result; and setting a third initial value for at least one filter coefficient among a plurality of filter coefficients based on the first initial value and the second initial value. The first initial value, the second initial value, and the third initial value are used as reference parameters for obtaining the plurality of filter coefficients.

[0006] For example, in at least one embodiment of the present disclosure, a plurality of filter coefficients are obtained based on a plurality of target parameters and a first measurement result associated with a digitally controlled oscillator and a second measurement result associated with a time-to-digital converter, including: obtaining a first filter coefficient and a second filter coefficient based on the plurality of target parameters and the first measurement result, and by means of the first filter coefficient and the second filter coefficient, making a plurality of operating parameters of the phase-locked loop circuit correspondingly consistent with the plurality of target parameters in a first locking phase.

[0007] For example, in at least one embodiment of the present disclosure, a plurality of filter coefficients are obtained based on a plurality of target parameters and a first measurement result associated with a digitally controlled oscillator and a second measurement result associated with a time-to-digital converter, and the method further includes: obtaining a third filter coefficient and a fourth filter coefficient based on the first filter coefficient, the second filter coefficient and the second measurement result, and using the third filter coefficient and the fourth filter coefficient, a plurality of operating parameters of the phase-locked loop circuit are correspondingly kept consistent with the plurality of target parameters in the second locking phase.

[0008] For example, in at least one embodiment of the present disclosure, the first measurement result is based on a first oscillation signal output by the digitally controlled oscillator when the input is a first frequency control word, and based on a second oscillation signal output by the digitally controlled oscillator when the input is a second frequency control word.

[0009] For example, in at least one embodiment of the present disclosure, the first frequency control word is different from the second frequency control word.

[0010] For example, in at least one embodiment of the present disclosure, the first measurement result includes a gain value of the digitally controlled oscillator.

[0011] For example, in at least one embodiment of the present disclosure, the second measurement result is based on a digital signal output by the time-to-digital converter when the inputs are a first clock signal and a second clock signal, and there is a preset phase difference between the first clock signal and the second clock signal.

[0012] For example, in at least one embodiment of the present disclosure, the preset phase difference corresponds to a clock period of the digitally controlled oscillator.

[0013] For example, in at least one embodiment of the present disclosure, the second measurement result includes a ratio between a first quantization accuracy and a second quantization accuracy of the time-to-digital converter; the first quantization accuracy corresponds to a first locking stage, and the second quantization accuracy corresponds to a second locking stage.

[0014] For example, in at least one embodiment of the present disclosure, the first quantization accuracy is based on a clock period of the digitally controlled oscillator, and the second quantization accuracy is based on a delay time of an inverter in the time-to-digital converter.

[0015] For example, in at least one embodiment of the present disclosure, the plurality of target parameters include at least the bandwidth and phase margin of the phase-locked loop circuit.

[0016] For example, in at least one embodiment of the present disclosure, the phase-locked loop circuit includes a fully digital phase-locked loop circuit.

[0017] For example, at least one embodiment of the present disclosure further provides a phase-locked loop circuit, comprising a digital loop filter and a data processing device. The digital loop filter and the data processing device are communicatively connected, and the data processing device comprises: a setting unit configured to set multiple target parameters of the phase-locked loop circuit; and an acquisition unit configured to acquire multiple filter coefficients of the digital loop filter based on the multiple target parameters, and provide the multiple filter coefficients to the digital loop filter, so that multiple operating parameters of the phase-locked loop circuit are correspondingly consistent with the multiple target parameters.

[0018] For example, at least one embodiment of the present disclosure provides a phase-locked loop circuit further comprising a time-to-digital converter and a digitally controlled oscillator. The time-to-digital converter is communicatively coupled to the digital loop filter, the digital loop filter is communicatively coupled to the digitally controlled oscillator, and the data processing device is communicatively coupled to the time-to-digital converter and the digitally controlled oscillator. The acquisition unit comprises a calculation unit configured to acquire the plurality of filter coefficients based on the plurality of target parameters, a first measurement result associated with the digitally controlled oscillator, and a second measurement result associated with the time-to-digital converter.

[0019] For example, at least one embodiment of the present disclosure provides a phase-locked loop circuit further comprising a frequency divider. The frequency divider is communicatively coupled to the time-to-digital converter and the digitally controlled oscillator. The frequency divider is configured to perform frequency division processing on the digital loop filter output signal and provide the divided signal to the time-to-digital converter.

[0020] For example, at least one embodiment of the present disclosure further provides a data processing device comprising a processor and a memory, wherein the memory comprises one or more computer program modules. The one or more computer program modules are stored in the memory and configured to be executed by the processor to execute instructions of the method for calibrating parameters of a phase-locked loop circuit as provided in any of the above embodiments.

[0021] For example, at least one embodiment of the present disclosure further provides an electronic device, including a data processing device as provided in any of the above embodiments and a phase-locked loop circuit, wherein the phase-locked loop circuit is connected to the data processing device.

[0022] For example, at least one embodiment of the present disclosure further provides a non-transitory readable storage medium having computer instructions stored thereon, wherein when the computer instructions are executed by a processor, the method for calibrating parameters of a phase-locked loop circuit provided in any of the above embodiments is executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0024] Figure 1 A schematic structural diagram of a fully digital phase-locked loop circuit provided by at least one embodiment of the present disclosure;

[0025] Figure 2 A flow chart of a method for calibrating parameters of a phase-locked loop circuit provided by at least one embodiment of the present disclosure;

[0026] Figure 3 A schematic diagram of a frequency characteristic model of a phase-locked loop circuit provided by at least one embodiment of the present disclosure;

[0027] Figure 4 An operational diagram of a method for calibrating parameters of a phase-locked loop circuit provided by at least one embodiment of the present disclosure;

[0028] Figure 5 Another operational diagram of a method for calibrating parameters of a phase-locked loop circuit provided by at least one embodiment of the present disclosure;

[0029] Figure 6A A schematic diagram of detecting a second measurement result provided by at least one embodiment of the present disclosure;

[0030] Figure 6B A comparison diagram of multiple signals used in a process of detecting a second measurement result provided by at least one embodiment of the present disclosure;

[0031] Figure 7 A schematic diagram of a method for calibrating parameters of a phase-locked loop circuit provided by at least one embodiment of the present disclosure;

[0032] Figure 8 A schematic diagram of a method for calculating a fourth filter coefficient according to at least one embodiment of the present disclosure;

[0033] Figure 9AA schematic structural diagram of a phase-locked loop circuit provided by at least one embodiment of the present disclosure;

[0034] Figure 9B A schematic structural diagram of another phase-locked loop circuit provided by at least one embodiment of the present disclosure;

[0035] Figure 10 A schematic block diagram of a data processing device provided for at least one embodiment of the present disclosure;

[0036] Figure 11 A schematic block diagram of another data processing device provided for at least one embodiment of the present disclosure;

[0037] Figure 12 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure; and

[0038] Figure 13 A schematic diagram of a non-transitory readable storage medium provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0040] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0041] Figure 1 A schematic structural diagram of a fully digital phase-locked loop circuit provided in at least one embodiment of the present disclosure.

[0042] like Figure 1 As shown, at least one embodiment of the present disclosure provides a fully digital phase-locked loop circuit 10. The fully digital phase-locked loop circuit 10 includes a time to digital converter (TDC) 11, a digital loop filter (DLF) 12, a digitally controlled oscillator (DCO) 13, a feedback divider (FD) 14, and an integral differential modulator (Sigma-Delta Modulator, SDM) 15.

[0043] For example, Figure 1 As shown, the TDC 11 can be used to detect the reference clock signal F ref and the clock signal F after FD 14 division v The time difference between the two clock signals (i.e., F ref and F v ) is proportional to the time difference between the two. The digital signal generated by TDC 11 is sent to DLF 12. DLF 12 is a digital filter, for example, Figure 1 The DLF 12 in FIG is a first-order digital filter. The DLF 12 includes an integral path and a proportional path. The integral path performs a moving cumulative average process on the input signal of the DLF 12, and the proportional path performs a linear scaling process on the input signal of the DLF 12. The two paths are respectively determined by the coefficient K i and coefficient K p By controlling its frequency response characteristics, the frequency response characteristics of the DLF 12 will directly affect the frequency characteristics of the entire fully digital phase-locked loop circuit 10. i and K p It can be controlled externally, and usually the frequency characteristics of the fully digital phase-locked loop circuit 10 can be manually corrected and adjusted through these two sets of parameters. It should be noted that the embodiments of the present disclosure do not limit the DLF 12 to a first-order digital filter, but can also be a multi-order digital filter, which can be set according to actual needs.

[0044] The signal output from the TDC 11 is filtered by the DLF 12 to generate a set of digital frequency control words (FCW) to control the DCO 13. The DCO 13 can be used to generate a stable oscillating clock signal, i.e. Figure 1 The output clock signal F shown in out The output clock signal F of DCO 13out The output clock signal F is controlled by the above frequency control word and out The frequency of DCO 13 is proportional to the value of the frequency control word. out The frequency division process is carried out by FD 14, and the frequency division ratio is set by the external frequency division control word N. The clock signal F output by FD 14 v The frequency of the clock signal F output by DCO 13 out The SDM 15 enables the FD 14 to implement the functions of fractional frequency division and spread spectrum clocking (SSC). The clock signal F after the FD 14 frequency division v Transmitted to TDC 11, TDC 11 converts the clock signal F v With the reference clock signal F ref Due to the control of the loop negative feedback, when the phase-locked loop circuit 10 enters the locked state, the clock signal F output by FD 14 v With the reference clock signal F ref In this case, the output clock signal F of the full digital phase-locked loop circuit 10 is the same as the frequency and phase. ou The frequency of the reference clock signal F ref N times the frequency.

[0045] It should be noted that Figure 1 The fully digital phase-locked loop circuit 10 shown is merely exemplary, and the fully digital phase-locked loop circuit 10 may also include more or fewer components, such as Figure 1 The fully digital phase-locked loop circuit 10 shown may not include the SDM 15 , and the embodiments of the present disclosure do not limit the specific structure of the fully digital phase-locked loop circuit.

[0046] As a closed-loop feedback system, the frequency transfer characteristics of a phase-locked loop (PLL) circuit are crucial to the entire loop system. These characteristics not only determine the dynamic characteristics of the entire loop system but also significantly impact the PLL circuit's noise characteristics. However, in current CMOS processes, variations in process parameters during chip manufacturing and temperature and voltage fluctuations during chip operation (hereinafter referred to as PVT (Process, Voltage, Temperature) variations) can cause variations in the PLL circuit's frequency transfer characteristics, leading to deviations in the loop's characteristics and noise performance from the intended design. To ensure that the PLL circuit meets the desired performance requirements under varying PVT environments, sufficient margin must be reserved during circuit design, or circuit parameters must be manually adjusted based on actual test results in subsequent applications. This increases circuit area and power consumption, making circuit design more difficult.

[0047] To address the aforementioned issues faced by phase-locked loop circuits, at least one embodiment of the present disclosure provides a parameter calibration method for a phase-locked loop circuit. The phase-locked loop circuit includes a digital loop filter. The method includes setting multiple target parameters for the phase-locked loop circuit, obtaining multiple filter coefficients for the digital loop filter based on the multiple target parameters, and providing the multiple filter coefficients to the digital loop filter, so that multiple operating parameters of the phase-locked loop circuit are correspondingly consistent with the multiple target parameters.

[0048] Accordingly, at least one embodiment of the present disclosure further provides a phase-locked loop circuit, a data processing device, an electronic device, and a non-transitory readable storage medium corresponding to the parameter correction method of the phase-locked loop circuit.

[0049] At least one embodiment of the present disclosure provides a parameter correction method for a phase-locked loop circuit. By setting multiple target parameters, multiple filter coefficients of a digital loop filter can be automatically adjusted so that multiple operating parameters of the phase-locked loop circuit are correspondingly consistent with the multiple target parameters, thereby keeping the overall operating characteristics (for example, frequency characteristics) of the phase-locked loop circuit unchanged and improving the stability of the phase-locked loop circuit.

[0050] It should be noted that the parameter correction method of the phase-locked loop circuit provided by at least one embodiment of the present disclosure is not limited to application in Figure 1 The fully digital phase-locked loop circuit shown can also be applied to phase-locked loop circuits of other types or structures.

[0051] The following non-restrictive description of the parameter correction method of the phase-locked loop circuit provided according to at least one embodiment of the present disclosure is given through several examples or embodiments. As described below, different features in these specific examples or embodiments can be combined with each other without conflicting with each other to obtain new examples or embodiments, and these new examples or embodiments also fall within the scope of protection of the present disclosure.

[0052] Figure 2 A flowchart of a method for calibrating parameters of a phase-locked loop circuit provided by at least one embodiment of the present disclosure.

[0053] For example, at least one embodiment of the present disclosure provides a parameter calibration method 20 for a phase-locked loop circuit, such as Figure 2 For example, the parameter correction method 20 of the phase-locked loop circuit can be applied to various types of phase-locked loop circuits, and the phase-locked loop circuit includes a digital loop filter. For example, in one example, the parameter correction method 20 of the phase-locked loop circuit can be applied to Figure 1The fully digital phase-locked loop circuit 10 shown includes a digital loop filter 12. For example, the parameter calibration method 20 of the phase-locked loop circuit includes the following operations S201-S202:

[0054] Step S201: setting multiple target parameters of the phase-locked loop circuit.

[0055] Step S202: Based on the multiple target parameters, multiple filter coefficients of the digital loop filter are obtained, and the multiple filter coefficients are provided to the digital loop filter, so that the multiple operating parameters of the phase-locked loop circuit are correspondingly consistent with the multiple target parameters.

[0056] At least one embodiment of the present disclosure provides a phase-locked loop circuit parameter calibration method 20 that automatically adjusts multiple filter coefficients of a digital loop filter by setting multiple target parameters, so that multiple operating parameters of the phase-locked loop circuit are correspondingly consistent with the multiple target parameters. As a result, the overall operating characteristics (e.g., frequency characteristics) of the phase-locked loop circuit remain unchanged, improving the stability of the phase-locked loop circuit.

[0057] It should be noted that in at least one embodiment of the present disclosure, steps S201-S202 can be executed sequentially, in parallel, or in other adjusted orders. The embodiments of the present disclosure do not limit the execution order of the steps and can be adjusted according to actual conditions.

[0058] It should also be noted that, in at least one embodiment of the present disclosure, the parameter correction method 20 for the phase-locked loop circuit may selectively execute some of the steps in step S201-step S202, or may execute some additional steps in addition to step S201-step S202, and the embodiments of the present disclosure do not limit this.

[0059] For example, in at least one embodiment of the present disclosure, the multiple target parameters of a phase-locked loop circuit may include the bandwidth of the phase-locked loop circuit and the phase margin of the phase-locked loop circuit. Correspondingly, the multiple operating parameters of the phase-locked loop circuit are the bandwidth and phase margin of the phase-locked loop circuit during operation. The bandwidth and phase margin of the phase-locked loop circuit are both related to the frequency characteristics of the phase-locked loop circuit. It should be noted that the multiple target parameters of the phase-locked loop circuit may also include other parameters, and the embodiments of the present disclosure are not limited in this regard.

[0060] Figure 3 A schematic diagram of a frequency characteristic model of a phase-locked loop circuit provided in at least one embodiment of the present disclosure.

[0061] For example, at least one embodiment of the present disclosure provides a frequency characteristic model of a fully digital phase-locked loop circuit, such as Figure 3 shown. Figure 3The all-digital phase-locked loop circuit shown in the figure includes a time-to-digital converter (TDC), a digital loop filter (DLF), a digitally controlled oscillator (DCO) and a feedback divider (FD). The boxes corresponding to each component are the transfer functions corresponding to the component.

[0062] For example, in one example, combining Figure 3 , the transfer function H of the fully digital phase-locked loop circuit open (s) is as shown in expression (1):

[0063]

[0064] Among them, T ref is the reference clock signal F ref The clock period, T tdc K is the quantization accuracy of the time-to-digital converter (TDC), that is, the change in the input signal time difference corresponding to a change of one least significant bit (LSB) of the TDC output digital signal. p and K i They are the gain coefficients of the proportional path and the integral path in the digital loop filter (DLF), usually K p >>K i , K dco is the gain value of the digitally controlled oscillator (DCO), that is, the magnitude of the output frequency change caused by a change of one least significant bit (LSB) of the DCO input frequency control word, and N is the division ratio of the feedback divider (FD). In expression (1), The term is also called the gain value of TDC, expressed as K tdc .

[0065] For example, in one exemplary aspect, according to the above expression (1), the expression (2) regarding the bandwidth BW can be derived:

[0066]

[0067] According to expression (2), the parameters that affect the bandwidth BW in the phase-locked loop circuit include: T ref , K dco , K p 、T tdc and N. Among these parameters, K dco and T tdc Determined by the characteristics of the actual DCO module and TDC module, K dco and T tdc The size of K is affected by PVT variations. For example, in one example, when PVT variations slow down the components on the chip, K dco It will become smaller, T tdcFor example, in one example, when PVT changes cause components on the chip to run faster, K dco It will get bigger, T tdc will become smaller. dco and T tdc The direction of change with PVT is opposite, and in the expression of bandwidth BW (i.e., in expression (2)) K dco and T tdc In the denominator and numerator respectively, the change of the two will cause the change of bandwidth BW to be more significant. In order to avoid the impact of bandwidth BW change on the performance of the phase-locked loop circuit, the conventional approach is to increase the design margin or manually adjust the DLF coefficient K according to the process change. p .

[0068] For example, in another exemplary aspect, from the perspective of the stability of the phase-locked loop circuit, the phase-locked loop circuit has two poles and one zero located at the origin, and the frequency f of the zero position is z It is expressed by expression (3):

[0069]

[0070] Taking into account the effects of these poles and zeros, at the bandwidth frequency BW, the phase margin PM is:

[0071]

[0072] According to expression (4), the size of the phase margin PM depends on According to expression (3), f z By K i and K p The ratio of T ref Determine, these three parameters (K i , K p and T ref ) itself is not affected by PVT changes. Therefore, when these three parameters are fixed, the BW change caused by PVT changes will directly cause the phase margin PM to change. In order to avoid the stability problem of the phase-locked loop circuit caused by the change of phase margin PM, the conventional approach is to increase the design margin or manually adjust the DLF coefficient K according to the process changes. p and K i .

[0073] The parameter correction method 20 of the phase-locked loop circuit provided by at least one embodiment of the present disclosure introduces a loop parameter automatic correction mechanism, which can automatically adjust the filter coefficient K of the loop filter. p and K i , so that the overall frequency characteristics of the loop remain unchanged.

[0074] For example, in at least one embodiment of the present disclosure, in step S201, multiple target parameters of the phase-locked loop circuit, such as bandwidth and phase margin, may be pre-set. For example, in one example, the multiple target parameters may be set via external registers. For example, in another example, the multiple target parameters may be set via a preset table. The embodiments of the present disclosure do not limit the specific manner in which the target parameters are set.

[0075] For example, in at least one embodiment of the present disclosure, the bandwidth is set by an external bandwidth setting register. set For example, in at least one embodiment of the present disclosure, the phase margin is set by an external phase margin setting register, and the PM set express.

[0076] For example, in at least one embodiment of the present disclosure, for step S202, based on the preset bandwidth BW set and phase margin PM set , you can get the filter coefficient K of the digital loop filter p and K i , multiple filter coefficients K p and K i Provided to the digital loop filter, so that the bandwidth and phase margin of the phase-locked loop circuit in actual operation are always equal to the preset BW set and PM set , thereby ensuring that the overall frequency characteristics of the phase-locked loop circuit remain unchanged and improving the stability of the phase-locked loop circuit.

[0077] For example, in at least one embodiment of the present disclosure, a locking process of a fully digital phase-locked loop circuit can be divided into three stages: a fast frequency locking stage, a coarse locking stage, and a fine locking stage.

[0078] It should be noted that, in at least one embodiment of the present disclosure, the coarse lock stage may be a specific implementation of the first lock stage mentioned in the embodiments of the present disclosure, and the fine lock stage may be a specific implementation of the second lock stage mentioned in the embodiments of the present disclosure. For example, in one example, the phase error of the phase-locked loop circuit in the coarse lock stage is greater than the phase error of the phase-locked loop circuit in the fine lock stage. For example, in one example, the phase error of the phase-locked loop circuit in the coarse lock stage is within a first predetermined range, and the phase error of the phase-locked loop circuit in the fine lock stage is within a second predetermined range, and the first predetermined range is different from the second predetermined range. For example, the first predetermined range and the second predetermined range can be set according to actual needs. It should be noted that the division of the locking stages of the phase-locked loop circuit in the embodiments of the present disclosure is merely exemplary and can be set according to actual needs.

[0079] For example, in the frequency fast locking stage, the full digital phase-locked loop circuit works in the form of a frequency locked loop. A counter can be used inside the phase-locked loop circuit to count the period of the DCO output clock signal and calculate the period of the reference clock signal F. ref The count value within one cycle is compared with N. When the count value is close to N, it is generally considered that the DCO frequency is close to the locked state. For example, in this case, the DCO frequency is at f ref *N nearby, where f ref Represents the frequency value of the reference clock signal Fref, that is

[0080] For example, in the coarse lock stage, the DCO outputs the clock signal F out The frequency of the DCO is close to the locked state, however, the output clock signal F out The clock signal F after the feedback divider FD is divided v With the reference clock signal F ref In this case, a larger TDC quantization accuracy can be used to quantize the phase error.

[0081] For example, in at least one embodiment of the present disclosure, in the coarse lock stage, the quantization accuracy of the TDC is based on the DCO output clock signal F out The clock period T dco It should be noted that, in at least one embodiment of the present disclosure, the quantization accuracy of the TDC in the coarse lock stage may be a specific implementation of the first quantization accuracy mentioned in the embodiment of the present disclosure.

[0082] For example, in one example, the quantization accuracy of the TDC can be expressed as the DCO output clock signal F out The period T dco For example, using T dco The multiple of TDC is used as the quantization accuracy, that is, T tdc =α*T dco , where α can be 0.5, 1, 2, etc. The embodiment of the present disclosure does not limit the value of α and can be set according to actual conditions. In this case, the gain value of TDC

[0083] For example, in one example, assuming that α takes a value of 1, the quantization accuracy of the TDC is the DCO output clock signal F out The period T dco , that is, T tdc =T dco , the phase error quantization result is Δφ*T ref / (2*π*T dco). In the coarse lock stage, since the TDC quantization accuracy is relatively coarse, that is, T tdc The larger the TDC gain value is, the Usually, in order to maintain the constant characteristics of the phase-locked loop circuit, in the coarse lock stage, the filter coefficient K of the digital loop filter DLF is p and K i Will be set to a larger value.

[0084] For example, during the fine lock phase, the phase error of the fully digital phase-locked loop circuit is reduced to a relatively small value. To ensure a small static phase error, a higher TDC quantization accuracy is required. For example, in at least one embodiment of the present disclosure, during the fine lock phase, the TDC quantization accuracy is based on the delay time of the TDC inverter. It should be noted that, in at least one embodiment of the present disclosure, the TDC quantization accuracy during the fine lock phase can be a specific implementation of the second quantization accuracy mentioned in the embodiments of the present disclosure.

[0085] For example, in at least one embodiment of the present disclosure, the TDC is in the form of an inverter chain, and the quantization accuracy of the TDC can be set to the delay time of the first-stage inverter, which is expressed as T res , that is, T tdc =T res , the phase error quantization result is △φ*T ref / (2*π*T res ). In this case, the TDC gain value Generally, in order to maintain the constant characteristics of the phase-locked loop circuit, in the fine lock stage, the filter coefficient K of the digital loop filter DLF is p and K i Will be set to a smaller value.

[0086] For example, in at least one embodiment of the present disclosure, during the rapid frequency lock phase, the digitally controlled oscillator (DCO) is typically controlled directly based on the counter output, without passing through the digital loop filter (DLF). Therefore, during the rapid frequency lock phase, the phase-locked loop (PLL) circuit's stability issues are avoided, and there's no need to calibrate the PLL circuit's parameters.

[0087] For example, in at least one embodiment of the present disclosure, during the coarse lock phase (also referred to as the first lock phase), the phase-locked loop circuit has switched to a state where the digital control oscillator DCO is controlled via the digital loop filter DLF. Therefore, during the coarse lock phase, it is necessary to consider the dynamic characteristics of the phase-locked loop circuit and adjust the filter coefficient (K) of the digital loop filter DLF under different PVT conditions. p and K i ) for correction.

[0088] For example, in at least one embodiment of the present disclosure, in the coarse lock stage, the quantization accuracy of the time-to-digital converter TDC is set to α*T dco , then the time-to-digital converter TDC gain value is According to the working principle of the above phase-locked loop circuit, it can be known that T ref =N*T dco , combined with the above expression (2), we can deduce the bandwidth BW in the coarse lock stage c The expression (5) is as follows:

[0089]

[0090] Among them, K pc Indicates the filter coefficient K in the coarse lock stage p Since the TDC gain value is small in the coarse lock stage, the filter coefficient K of the loop filter is p and K i For example, in the embodiment of the present disclosure, K pc and K ic It should be noted that, in the embodiment of the present disclosure, the filter coefficients K of the loop filter corresponding to the coarse locking stage are pc and K ic These are respectively specific implementations of the first filter coefficient and the second filter coefficient mentioned in the embodiments of the present disclosure.

[0091] According to the above expression (5), in the coarse lock stage, the bandwidth BW is affected c The only parameter is K dco and K pc Since the frequency of the output clock signal of the digitally controlled oscillator DCO is basically stable in the coarse lock stage, the quantization accuracy of the time-to-digital converter TDC is T tdc =α*T dco It can be regarded as a constant value and will not be affected by PVT changes. Therefore, in the coarse lock stage, in order to ensure the bandwidth BW c Constant, only needs to be adjusted according to the digitally controlled oscillator (DCO) gain value K dco Adjust the first filter coefficient K by changing pc .

[0092] For example, in at least one embodiment of the present disclosure, combined with the above expression (3), it can be seen that for the zero point position frequency f in the coarse lock stage, zc The expression (6) is as follows:

[0093]

[0094] According to expression (6), in the coarse locking stage, in order to ensure fzc Constant, only needs to be based on the first filter coefficient K pc Determine the second filter coefficient K ic According to expression (4), the size of the phase margin PM depends on Therefore, in the coarse lock stage, as long as BW c and f zc remains unchanged, the phase margin PM c Also remains unchanged.

[0095] For example, in at least one embodiment of the present disclosure, during the fine lock phase, the quantization accuracy of the time-to-digital converter (TDC) is switched to a higher quantization accuracy. For example, taking a time-to-digital converter (TDC) in the form of an inverter chain as an example, its quantization accuracy is set to the delay of the first inverter, i.e., T tdc =T res , then the time-to-digital converter TDC gain value is Combined with the above expression (2), the bandwidth BW in the fine lock phase can be derived f The expression (7) is as follows:

[0096]

[0097] Among them, K pf Indicates the filter coefficient K in the fine lock stage p Since the TDC gain is large in the fine lock phase, the filter coefficient K of the loop filter is p and K i For example, in at least one embodiment of the present disclosure, K pf and K if Respectively represent the filter coefficients of the digital loop filter corresponding to the fine lock stage. It should be noted that, in the embodiment of the present disclosure, the filter coefficients K of the loop filter corresponding to the fine lock stage are pf and K if These are the specific implementations of the third filter coefficient and the fourth filter coefficient mentioned in this disclosure.

[0098] According to the above expression (7), in the fine lock phase, the bandwidth BW is affected f The parameters are K dco 、T res and K pf Therefore, in the fine lock phase, in order to ensure the bandwidth BW f Constant, needs to be based on the gain value K dco and T res Adjust the third filter coefficient K pf .

[0099] For example, in at least one embodiment of the present disclosure, combined with the above expression (3), it can be seen that for the zero point position frequency f in the fine lock stage, zf The expression (8) is as follows:

[0100]

[0101] According to expression (8), in the fine lock stage, in order to ensure f zf Constant, only needs to be calculated based on the third filter coefficient K pf Determine the fourth filter coefficient K if According to expression (4), the size of the phase margin PM depends on Therefore, in the fine lock stage, as long as BW f and f zf remains unchanged, the phase margin PM f Also remains unchanged.

[0102] For example, at least one embodiment of the present disclosure provides a parameter calibration method for a phase-locked loop circuit, which can ensure that the frequency characteristics of the phase-locked loop circuit remain constant in both the coarse lock stage and the fine lock stage, and are not affected by PVT changes. Therefore, the bandwidth (BW) of the coarse lock stage is c ) and phase margin (PM c ) and the bandwidth of the fine lock phase (BW f ) and phase margin (PM f ) are equal to the preset bandwidth (BW set ) and phase margin (PM set ) size, namely BW c =BW f =BW set , PM c =PM f =PM set .

[0103] According to expressions (5) and (7), BW c =BW f , we can get:

[0104]

[0105] Right now

[0106]

[0107] Assumptions

[0108]

[0109] Therefore, in order to ensure BW c =BW f ,

[0110] K pc =β tdc ·K pf (9)

[0111] Among them, β tdc It represents the ratio between the TDC quantization accuracy in the coarse lock stage and the TDC quantization accuracy in the fine lock stage, that is, the ratio between the first quantization accuracy and the second quantization accuracy.

[0112] According to expressions (6) and (8), f zc =f zf , we can get:

[0113]

[0114] but

[0115]

[0116] Based on expressions (9) and (10), the filter coefficient (K) of the loop filter corresponding to the coarse lock stage is pc and K ic ) and the filter coefficient of the loop filter corresponding to the fine lock stage (K pf and K if ), that is, there is a proportional relationship between tdc .

[0117] In combination with the above description and derived expressions, the specific implementation of step S202 (ie, obtaining multiple filter coefficients of the digital loop filter based on multiple target parameters) in the parameter correction method 20 of the phase-locked loop circuit is described in detail below.

[0118] Figure 4 This is a schematic diagram of an operation of a method for calibrating parameters of a phase-locked loop circuit according to at least one embodiment of the present disclosure. Figure 5 Another operational diagram of a method for calibrating parameters of a phase-locked loop circuit provided by at least one embodiment of the present disclosure is provided.

[0119] For example, in at least one embodiment of the present disclosure, the phase-locked loop circuit includes, in addition to the digital loop filter, a time-to-digital converter and a digitally controlled oscillator, the time-to-digital converter and the digital loop filter are communicatively connected, and the digital loop filter and the digitally controlled oscillator are communicatively connected. Figure 1The fully digital phase-locked loop circuit 10 shown is an example. The phase-locked loop circuit 10 includes a TDC 11, a DLF 12, and a DCO 13. The time-to-digital converter TDC 11 is communicatively connected to the digital loop filter DLF 12, and the digital loop filter DLF 12 is communicatively connected to the digitally controlled oscillator DCO 13. For step S202, based on multiple target parameters, multiple filter coefficients of the digital loop filter are obtained, including the following steps S401: Figure 4 shown.

[0120] Step S401 : Acquire a plurality of filter coefficients based on a plurality of target parameters and a first measurement result associated with a digitally controlled oscillator and a second measurement result associated with a time-to-digital converter.

[0121] For example, in at least one embodiment of the present disclosure, the first measurement result associated with the digitally controlled oscillator includes a gain value K of the digitally controlled oscillator. dco .

[0122] For example, in at least one embodiment of the present disclosure, the second measurement result associated with the time-to-digital converter includes a ratio between the first quantization accuracy and the second quantization accuracy of the time-to-digital converter. In combination with the above, the second measurement result includes β tdc , that is, the ratio between the quantization accuracy of the time digital converter TDC in the coarse lock stage and the quantization accuracy of the time digital converter TDC in the fine lock stage.

[0123] It should be noted that the first measurement result and the second measurement result may further include other parameters, which are not limited in the embodiments of the present disclosure and can be set according to actual needs.

[0124] For example, in one example, based on the preset bandwidth BW set and phase margin PM set , and the measured digitally controlled oscillator DCO gain value K dco and β associated with the time-to-digital converter TDC tdc , the first filter coefficient K of the digital loop filter can be calculated pc , the second filter coefficient K ic , the third filter coefficient K pf and the fourth filter coefficient K if .

[0125] For example, in at least one embodiment of the present disclosure, for step S401, obtaining a plurality of filter coefficients based on a plurality of target parameters and a first measurement result associated with a digitally controlled oscillator and a second measurement result associated with a time-to-digital converter may include the following steps S501 and S502: Figure 5 shown.

[0126] Step S501: Based on multiple target parameters and the first measurement result, obtain a first filter coefficient and a second filter coefficient, and through the first filter coefficient and the second filter coefficient, make multiple operating parameters of the phase-locked loop circuit consistent with the multiple target parameters in the first locking stage.

[0127] For example, in at least one embodiment of the present disclosure, according to the above expression (5), And BW set =BW c , where α is a pre-set fixed value. Therefore, based on the set bandwidth BW set And the first measurement result K dco , we can get the first filter coefficient K pc For example, according to the above expressions (4) and (6), where T ref is the reference clock signal F ref The period is also a fixed value that can be set in advance. Therefore, based on the set phase margin PM set And the first filter coefficient K obtained above pc , we can get the second filter coefficient K ic For example, in one example, the first filter coefficient K is obtained pc and the second filter coefficient K ic By setting it on the all-digital loop filter, the bandwidth and phase margin of the phase-locked loop circuit in the coarse lock stage (also called the first lock stage) can be kept consistent with the set bandwidth and phase margin.

[0128] Step S502: Based on the first filter coefficient, the second filter coefficient and the second measurement result, obtain the third filter coefficient and the fourth filter coefficient, and through the third filter coefficient and the fourth filter coefficient, make the multiple operating parameters of the phase-locked loop circuit consistent with the multiple target parameters in the second locking stage.

[0129] For example, in one example, according to expression (9), K pc =β tdc ·K pf , and expression (10), namely K ic =β tdc ·K if It can be seen that based on the first filter coefficient K pc , the second filter coefficient K ic and the second measurement result β tdc , the third filter coefficient K can be calculated pf and the fourth filter coefficient K if For example, in one example, the third filter coefficient K is obtained pf and the fourth filter coefficient Kif By setting it on the all-digital loop filter, the bandwidth and phase margin of the phase-locked loop circuit in the fine lock stage (also called the second lock stage) can be kept consistent with the set bandwidth and phase margin.

[0130] Therefore, the parameter correction method of the phase-locked loop circuit provided by at least one embodiment of the present disclosure can automatically adjust multiple filter coefficients of the digital loop filter DLF based on the set target parameters, so that the frequency characteristics of the phase-locked loop circuit remain unchanged, thereby improving the stability of the phase-locked loop circuit.

[0131] For example, in at least one embodiment of the present disclosure, the first measurement result is based on a first oscillation signal output by the digitally controlled oscillator when the input is a first frequency control word, and based on a second oscillation signal output by the digitally controlled oscillator when the input is a second frequency control word.

[0132] For example, in at least one embodiment of the present disclosure, due to the gain value K of the digitally controlled oscillator DCO dco Under different DCO oscillation frequencies, in order to reduce the measurement error, K dco The measurement of K should be performed after the frequency fast lock phase ends, for example, at the beginning of the coarse lock phase. This is because during the coarse lock phase, the DCO oscillation frequency has stabilized and is close to the final locked frequency of the phase-locked loop circuit. For example, in at least one embodiment of the present disclosure, K can be measured by adjusting the DCO frequency control word and detecting the change in the DCO output frequency. dco .

[0133] Since the frequency detection requires a reference frequency, in one example, the reference clock signal F ref The frequency value f ref As a detection reference. For example, in one example, the reference clock signal F ref The DCO outputs the clock signal F within M cycles. out The number of cycles is counted, and the count value is divided by M to obtain the current oscillation frequency of the DCO. It should be noted that M is an integer greater than 0.

[0134] For example, in at least one embodiment of the present disclosure, the gain value K of the digital controlled oscillator DCO can be measured in the following manner: dco First, two frequency control words (fcw0 and fcw1) are selected as the input of DCO. It should be noted that these two frequency control words (fcw0 and fcw1) should be selected as close to the frequency control word of DCO after the frequency fast locking phase is completed, so as to avoid too large deviation between the measured frequency point and the locked frequency. For example, with the reference clock signal F ref The M cycles of the measurement duration (M*T ref), the number of cycles of the clock signal output by the DCO measured under the frequency control word fcw0 is Ndco0, and the number of cycles of the clock signal output by the DCO measured under the frequency control word fcw1 is Ndco1. The oscillation frequencies of the DCO under fcw0 and fcw1 are:

[0135]

[0136]

[0137] From this we can get the gain value K of DCO dco The expression (11):

[0138]

[0139] Therefore, according to expression (11), the gain value K of the digital controlled oscillator DCO can be measured: dco .

[0140] It should be noted that, in the embodiments of the present disclosure, the above-mentioned frequency control word fcw0 is a specific implementation of the first frequency control word mentioned in the embodiments of the present disclosure, and the above-mentioned frequency control word fcw1 is a specific implementation of the second frequency control word mentioned in the embodiments of the present disclosure. The clock signal output by the DCO under the control of fcw0 is a specific implementation of the first oscillation signal mentioned in the embodiments of the present disclosure, and the frequency of the first oscillation signal is freq0. The clock signal output by the DCO under the control of fcw1 is a specific implementation of the second oscillation signal mentioned in the embodiments of the present disclosure, and the frequency of the second oscillation signal is freq1.

[0141] For example, in at least one embodiment of the present disclosure, the first frequency control word is different from the second frequency control word. For example, the first frequency control word and the second frequency control word can be set so that the difference between the first frequency control word and the second frequency control word and the DCO lock frequency is less than a certain threshold. The embodiments of the present disclosure do not limit the specific values ​​of the first frequency control word and the second frequency control word, and they can be set according to actual circumstances.

[0142] For example, in at least one embodiment of the present disclosure, the second measurement result is based on a digital signal output by the time-to-digital converter when the first clock signal and the second clock signal are input, and there is a preset phase difference between the first clock signal and the second clock signal. For example, in at least one embodiment of the present disclosure, the preset phase difference between the first clock signal and the second clock signal corresponds to a clock period of a digitally controlled oscillator.

[0143] For example, in at least one embodiment of the present disclosure, the second measurement result includes β tdc, that is, the ratio between the quantization accuracy of the time digital converter TDC in the coarse lock phase and the quantization accuracy of the time digital converter TDC in the fine lock phase. For example, as mentioned above, the TDC quantization accuracy in the coarse lock phase is set to the DCO output clock signal F out The period T dco α times, that is, T tdc =α*T dco , where the value of α can be set according to the actual situation. For example, as mentioned above, the TDC quantization accuracy in the fine lock stage is set to the delay time of the first-stage inverter, that is, T tdc =T res .

[0144] For example, in at least one embodiment of the present disclosure, the second measurement result β can be measured in the following manner: tdc For example, in one example, α*T dco The TDC quantization accuracy T of the fine lock stage is detected as the benchmark res , directly get β tdc =α*T dco / T res For example, in another example, you can first use T dco The TDC quantization accuracy T of the fine lock stage is detected as the benchmark res , and then the ratio T dco / T res Multiply by α to get β tdc =α*T dco / T res =α*β, where β represents the ratio T dco / T res , α is a preset fixed value, such as 0.5, 1, 2, etc.

[0145] Figure 6A A schematic diagram of detecting a second measurement result provided by at least one embodiment of the present disclosure, Figure 6B A comparison diagram of multiple signals used in the process of detecting a second measurement result provided by at least one embodiment of the present disclosure.

[0146] like Figure 6A and Figure 6B As shown, T dco As a benchmark, the detection method is to input two phase difference intervals T at the fine lock TDC input end. dco For example, in at least one embodiment of the present disclosure, the first clock signal clk_cal1 and the second clock signal clk_cal2 are used as inputs of a time-to-digital converter TDC, and the quantized output of the TDC is the ratio T dco / T res =β. Then, β is multiplied by the set fixed value α to obtain the second measurement result β tdc.

[0147] For example, in one example, the first clock signal clk_cal1 and the second clock signal clk_cal2 have a phase difference T dco The phase difference T dco The DCO output clock signal F dco After a D-type flip-flop (DFF), it is delayed by one clock cycle. Figure 6B As shown, the phase difference between the first clock signal clk_cal1 and the second clock signal clk_cal2 is the output clock signal F of the DCO. dco One cycle T dco It should be noted that, in the embodiment of the present disclosure, the output clock signal F dco Not necessarily equal to the output clock signal F of the phase-locked loop circuit out , because the DCO output clock signal F dco It may also need to be divided through a frequency divider.

[0148] Figure 7 A schematic diagram of a parameter correction method for a phase-locked loop circuit provided in at least one embodiment of the present disclosure.

[0149] For example, at least one embodiment of the present disclosure further provides a parameter calibration method 70 for a phase-locked loop circuit, such as Figure 7 shown.

[0150] For example, in at least one embodiment of the present disclosure, a parameter calibration method 70 for a phase-locked loop circuit includes setting a first initial value for at least one target parameter among a plurality of target parameters, setting a second initial value corresponding to a first measurement result, and setting a third initial value for at least one filter coefficient among a plurality of filter coefficients based on the first initial value and the second initial value. The first initial value, the second initial value, and the third initial value are used as reference parameters for obtaining the plurality of filter coefficients.

[0151] For example, in an embodiment of the present disclosure, by setting the first initial value, the second initial value and the third initial value as reference parameters for obtaining multiple filter coefficients, all operations in the parameter correction method 70 of the phase-locked loop circuit are division operations, so as to be multiplexed on the hardware and save hardware logic resources.

[0152] For example, Figure 7 As shown, the parameter calibration method 70 for a phase-locked loop circuit includes the following steps S701-S708.

[0153] For step S701, set a set of initial values ​​(BW_0, K dco_0 , K pc_0For example, a bandwidth BW_0 is selected as a default value, ie, a first initial value, within the preset bandwidth range of the phase-locked loop circuit. According to the characteristics of the digitally controlled oscillator DCO, a K dco The initial value K dco_0 , i.e. the second initial value. It should be noted that the second initial value does not need to be very accurate, and it only needs to ensure that the subsequent ratio calculation does not cause bit width overflow. Using the first initial value (bandwidth BW_0) and the second initial value (K dco_0 ), based on the following expression, we can get K pc The initial value K pc_0 , which is the third initial value.

[0154]

[0155] This set of initial values ​​(BW_0, K dco_0 , K pc_0 ) are stored in the circuit as reference parameters for subsequent acquisition of multiple filter coefficients. For example, in one example, the filter coefficients of the phase-locked loop circuit in the coarse lock phase and the filter coefficients of the phase-locked loop circuit in the fine lock phase can both be derived from the set of initial values.

[0156] For step S702, calculate the first initial value BW_0 and set bandwidth BW set For example, in one example, the bandwidth BW is set by an external bandwidth setting register. set , according to the bandwidth BW of the coarse lock stage c The expression of, that is, the above expression (5), bandwidth BW c With K dco *K pc Therefore, based on the reference parameters, according to the set bandwidth BW set The ratio B between the first initial value BW_0 and the K is increased proportionally dco *K pc You can get the set bandwidth BW set size.

[0157] In step S703, based on the reference parameters, the internal parameter K is adjusted according to the ratio B calculated in step S702. dco_1 , K pc_1 For example, through the following expression,

[0158] K dco_1 =K dco_0

[0159]

[0160] Available

[0161]

[0162] That is, the internal parameter K after adjustment dco_1 , K pc_1 The bandwidth BW c_1 Equal to the bandwidth BW set by the external register set .

[0163] In step S704, the reference clock signal F ref As a benchmark, the K in the detection circuit dco The size of K is calculated dco With the internal parameter K dco_1 The ratio RK dco ,Right now It should be noted that the previous embodiment has already introduced how to detect the gain value K of the DCO. dco The method will not be described here.

[0164] In step S705, according to the K measured in step S704, dco With the internal parameter K dco_1 The ratio RK dco Correction K pc :

[0165]

[0166] Available

[0167]

[0168] It can be seen that in the coarse lock stage, when K dco When the PVT conditions change, the first filter coefficient K can be automatically adjusted pc Maintain and set bandwidth during operation set consistent.

[0169] In step S706, the phase margin PM is set by the external phase margin setting register. set Or pmset, the pmset is obtained by the expression PM set =arctan(pmset)*180° / π, that is, pmset=BW set / f z According to expressions (5) and (6), we have

[0170]

[0171] Where K dco ·T ref K has been measured in step S704 dcoWhen (Expression 11) is obtained, it is expressed here as MNdco:

[0172]

[0173] You can get:

[0174]

[0175] Based on the above expression, we can get K ic Therefore, in the coarse lock stage, when K dco When the PVT conditions change, the second filter coefficient K can be automatically adjusted ic Make the phase margin during operation equal to the set phase margin PM set Or keep pmset consistent. Figure 8 The second filter coefficient K provided by at least one embodiment of the present disclosure ic For example, in one example, by Figure 8 The calculation method shown is to calculate K ic In this calculation method, all operations are division operations so that they can be reused on the hardware, thereby saving hardware logic resources.

[0176] It should be noted that the embodiment of the present disclosure sets the second filter coefficient K ic There is no restriction on the calculation method, and other calculation methods can also be used as long as K can be calculated. ic The value of .

[0177] In step S707, the second measurement result β is detected. tdc It should be noted that the above embodiments have already described how to detect the second measurement result β tdc The method will not be described here.

[0178] For step S708, the first filter coefficient K pc and the second filter coefficient K ic According to the β detected in step S707 tdc Scaling to get the third filter coefficient K pf and the fourth filter coefficient K if .

[0179]

[0180]

[0181] We can get:

[0182]

[0183]

[0184] Therefore, in the fine lock stage, when K dco and T res When the PVT conditions change, the third filter coefficient K can be automatically adjusted pf and the fourth filter coefficient K if Make the bandwidth during work and set bandwidth BW set Maintain consistency, the phase margin during operation and the set phase margin PM set Or keep pmset consistent.

[0185] It should be noted that in the embodiments of the present disclosure, the reference parameters may not be set, and multiple filter coefficients may be calculated based on the expressions provided in the embodiments of the present disclosure (for example, the above expressions (5)-(11), etc.), which can be set according to actual needs.

[0186] For example, in at least one embodiment of the present disclosure, it is assumed that the reference clock signal F ref The frequency value f ref =50MHz=50E6,N=40,f dco =f ref *N=2GHz=2E9,T dco =1 / f dco =500ps=5E-10, T res =10ps=1E-11, externally set bandwidth BW set =1MHZ=1E6, externally set pmset=BW set / f z =10, select the TDC quantization accuracy of the coarse lock stage as one DCO cycle, that is, α=1, select K dco Measurement benchmark F ref The number of cycles M=8.

[0187] For example, in step S701, the first initial value bandwidth BW_0 is set to 5 MHz = 5E6, and the second initial value K dco_0 =10MHz / LSB=10E6, the third initial value K pc_0 =3.14. It can be seen that this set of initial values ​​satisfies the expression

[0188] For example, in step S702, the bandwidth BW is set set =1MHz=1E6, based on the expression, Calculation shows B=5.

[0189] For example, in step S703, the parameters are adjusted according to the ratio B as follows:

[0190] K dco_1 =K dco_0 =10MHz / LSB=10E6;

[0191] K pc_1 =K pc_0 / B=3.14 / 5=0.628;

[0192]

[0193] For example, in step S704, the actual gain value K of the DCO is detected. dco For example, with the reference clock signal F ref As a benchmark, in M ​​(8) cycles T ref The number of DCO output clock cycles is counted. When the first frequency control word fcw0 of the DCO is set to 600, the count value Ndco0 is 320; when the second frequency control word fcw1 of the DCO is set to 602, the count value Ndco1 is 324. Based on expression (11), we can get:

[0194] MN dco =(Ndco1-Ndco0) / [(fcw1-fcw0)*M]=0.25

[0195] K dco =MN dco *T ref =12.5MHz / LSB=12.5E6

[0196] RK dco =K dco / K dco_1 =1.25

[0197] For example, in step S705, according to the K measured in step S704 dco With the internal parameter K dco_1 The ratio RK dco Corrected K pc .K pc =K pc_1 / RK dco =0.5025. At this time, the actual bandwidth BW c =(K dco *K pc ) / (2·π·α)=1MHz=1E6=BW set .

[0198] For example, in step S706, according to Figure 8 The calculation method of , we can get:

[0199] a=1 / K pc =1.99

[0200] b=K pc / a=0.2525(=K pc 2 )

[0201] c=α / MN dco =4

[0202] d = b / c = 0.063125;

[0203] Since the externally set phase margin value pmset = 10, we can get K ic =d / pmset=0.0063125. At this time, Thus, the first filter coefficient K is calculated pc and the second filter coefficient K ic The first filter coefficient K pc and the second filter coefficient K ic The operating bandwidth and phase margin of the phase-locked loop circuit in the coarse lock stage are made equal to the set bandwidth and phase margin.

[0204] For example, in step S707, by Figure 6A The method shown in the figure is used to measure β = T dco / T res =50, then β tdc =α*β=50.

[0205] For example, in step S708, based on K pc and K ic , and β tdc Get K pf and K if .

[0206] K pf =K pc / β tdc =1.005E-2

[0207] K if =K ic / β tdc =1.2625E-4

[0208] At this time, the working bandwidth

[0209] It can be seen that the third filter coefficient K is calculated pf and the fourth filter coefficient K if The third filter coefficient K pf and the fourth filter coefficient K ifThe working bandwidth and phase margin of the phase-locked loop circuit in the fine lock stage are made equal to the set bandwidth and phase margin.

[0210] Therefore, at least one embodiment of the present disclosure provides a method for parameter correction of a phase-locked loop circuit. This method can automatically adjust multiple filter coefficients of a digital loop filter (DLF) based on set target parameters, maintaining the frequency characteristics of the phase-locked loop circuit and improving its stability. Furthermore, by converting all operations during the adjustment process into division operations, hardware multiplexing allows for these operations, thus conserving hardware logic resources.

[0211] Figure 9A A schematic diagram of a phase-locked loop circuit according to at least one embodiment of the present disclosure is provided. Figure 9B A schematic structural diagram of another phase-locked loop circuit provided in at least one embodiment of the present disclosure.

[0212] For example, at least one embodiment of the present disclosure provides a phase-locked loop circuit 90, such as Figure 9A As shown. The phase-locked loop circuit 90 includes a digital loop filter 91 and a data processing device 92, and the digital loop filter 91 and the data processing device 92 are communicatively connected. For example, Figure 9A As shown, the data processing device 92 includes a setting unit 920 and an acquisition unit 921 .

[0213] For example, the setting unit 920 is configured to set multiple target parameters of the phase-locked loop circuit. For example, the setting unit 920 can implement step S201. The specific implementation method can refer to the relevant description of step S201 and will not be repeated here.

[0214] For example, the acquisition unit 921 is configured to acquire multiple filter coefficients of the digital loop filter based on the multiple target parameters, and provide the multiple filter coefficients to the digital loop filter, so that the multiple operating parameters of the phase-locked loop circuit are correspondingly consistent with the multiple target parameters. For example, the acquisition unit 921 can implement step S202. The specific implementation method can be referred to the relevant description of step S202, and will not be repeated here.

[0215] For example, the specific operations that the setting unit 920 and the acquiring unit 921 are configured to perform can be referred to the relevant description of the parameter correction method 20 / 70 of the phase-locked loop circuit provided in at least one embodiment of the present disclosure above, and will not be repeated here.

[0216] It should be noted that the setting unit 920 and the acquisition unit 921 can be implemented by software, hardware, firmware or any combination thereof. For example, the setting unit 920 and the acquisition unit 921 can be implemented as a setting circuit 920 and an acquisition circuit 921, respectively. The embodiments of the present disclosure do not limit their specific implementation methods.

[0217] For example, in at least one embodiment of the present disclosure, Figure 9B As shown, the phase-locked loop circuit 900 includes a time-to-digital converter (TDC) 910, a digital loop filter (DLF) 920, a digitally controlled oscillator (DCO) 930, and a data processing device 940. The time-to-digital converter (TDC) 910 and the digital loop filter (DLF) 920 are in communication with each other, the digital loop filter (DLF) 920 and the digitally controlled oscillator (DCO) 930 are in communication with each other, and the data processing device 940 is in communication with both the time-to-digital converter (TDC) 910 and the digitally controlled oscillator (DCO) 930. For example, the acquisition unit in the data processing device 940 includes a calculation unit configured to acquire a plurality of filter coefficients based on a plurality of target parameters, a first measurement result associated with the digitally controlled oscillator, and a second measurement result associated with the time-to-digital converter (TDC). For example, the calculation unit can implement step S401. The specific implementation method can refer to the description of step S401 and will not be repeated here.

[0218] For example, in at least one embodiment of the present disclosure, Figure 9B As shown, in addition to the time-to-digital converter TDC 910, the digital loop filter DLF 920, the digitally controlled oscillator DCO 930, and the data processing device 940, the phase-locked loop circuit 900 may further include a feedback frequency divider FD 950. The feedback frequency divider FD 950 is communicatively connected to the time-to-digital converter TDC 910 and the digitally controlled oscillator DCO 930. The feedback frequency divider FD 950 is configured to perform frequency division processing on the output signal of the digitally controlled oscillator DCO 930 and provide the frequency-divided signal to the time-to-digital converter TDC 910.

[0219] For example, in at least one embodiment of the present disclosure, the phase-locked loop circuit 900 further includes an integral differential modulator SDM950. It should be noted that, Figure 9A and Figure 9B The phase-locked loop circuit 90 / 900 shown is merely exemplary, and the phase-locked loop circuit may further include more or fewer components, which is not limited in the embodiments of the present disclosure.

[0220] For example, in at least one embodiment of the present disclosure, the data processing device 940 may include a target parameter setting unit, a measurement result setting unit, and a filter coefficient setting unit. For example, the target parameter setting unit is configured to set a first initial value of at least one target parameter among a plurality of target parameters. For example, the measurement result setting unit is configured to set a second initial value corresponding to the first measurement result. For example, the filter coefficient setting unit is configured to set a third initial value of at least one filter coefficient among a plurality of filter coefficients based on the first initial value and the second initial value. The first initial value, the second initial value, and the third initial value are used as reference parameters for obtaining a plurality of filter coefficients. For example, the operations that can be implemented by the target parameter setting unit, the measurement result setting unit, and the filter coefficient setting unit can refer to the relevant description of the parameter correction method 20 / 70 of the aforementioned phase-locked loop circuit, and will not be repeated here.

[0221] For example, in at least one embodiment of the present disclosure, the calculation unit may include a coarse lock maintaining unit and a fine lock maintaining unit. For example, the coarse lock maintaining unit is configured to obtain a first filter coefficient and a second filter coefficient based on multiple target parameters and the first measurement result, and to ensure that multiple operating parameters of the phase-locked loop circuit are consistent with the multiple target parameters in the first lock phase through the first filter coefficient and the second filter coefficient. For example, the coarse lock maintaining unit can implement step S501. The specific implementation method thereof can refer to the relevant description of step S501 and is not repeated here.

[0222] For example, the fine lock maintaining unit is configured to obtain a third filter coefficient and a fourth filter coefficient based on the first filter coefficient, the second filter coefficient, and the second measurement result. Using the third filter coefficient and the fourth filter coefficient, the plurality of operating parameters of the phase-locked loop circuit are kept consistent with the plurality of target parameters in the second locking phase. For example, the fine lock maintaining unit may implement step S502. The specific implementation method thereof may be referred to the description of step S502 and will not be further elaborated here.

[0223] For example, in an embodiment of the present disclosure, the specific operations that the above-mentioned calculation unit, target parameter setting unit, measurement result setting unit, filter coefficient setting unit, coarse lock holding unit and fine lock holding unit are configured to perform can all be referred to the relevant description of the parameter correction method 20 / 70 of the phase-locked loop circuit provided in at least one embodiment of the present disclosure above, and will not be repeated here.

[0224] It should be noted that the above-mentioned calculation unit, target parameter setting unit, measurement result setting unit, filter coefficient setting unit, coarse lock holding unit and fine lock holding unit can be implemented by software, hardware, firmware or any combination thereof. For example, the above-mentioned calculation unit, target parameter setting unit, measurement result setting unit, filter coefficient setting unit, coarse lock holding unit and fine lock holding unit can be respectively implemented as a calculation circuit, a target parameter setting circuit, a measurement result setting circuit, a filter coefficient setting circuit, a coarse lock holding circuit and a fine lock holding circuit. The embodiments of the present disclosure do not limit their specific implementation methods.

[0225] For example, in at least one embodiment of the present disclosure, the first measurement result may be based on a first oscillation signal output by the digitally controlled oscillator when the input is a first frequency control word, and based on a second oscillation signal output by the digitally controlled oscillator when the input is a second frequency control word. For example, in at least one embodiment of the present disclosure, the first frequency control word is different from the second frequency control word. For example, in at least one embodiment of the present disclosure, the first measurement result includes a gain value of the digitally controlled oscillator.

[0226] For example, in at least one embodiment of the present disclosure, the second measurement result is based on a digital signal output by the time-to-digital converter when the input is a first clock signal and a second clock signal, and there is a preset phase difference between the first clock signal and the second clock signal. For example, in at least one embodiment of the present disclosure, the preset phase difference corresponds to a clock period of a digitally controlled oscillator. For example, in at least one embodiment of the present disclosure, the second measurement result includes a ratio between a first quantization accuracy and a second quantization accuracy of the time-to-digital converter, the first quantization accuracy corresponds to a first locking stage, and the second quantization accuracy corresponds to a second locking stage. For example, in at least one embodiment of the present disclosure, the first quantization accuracy is based on a clock period of the digitally controlled oscillator, and the second quantization accuracy is based on a delay time of an inverter in the time-to-digital converter.

[0227] For example, in at least one embodiment of the present disclosure, the plurality of target parameters include at least a bandwidth and a phase margin of a phase-locked loop circuit. For example, in at least one embodiment of the present disclosure, the phase-locked loop circuit includes a fully digital phase-locked loop circuit.

[0228] It should be understood that the phase-locked loop circuit 90 / 900 provided in at least one embodiment of the present disclosure can implement the parameter correction method 20 / 70 of the aforementioned phase-locked loop circuit, and can also achieve technical effects similar to the parameter correction method 20 / 70 of the aforementioned phase-locked loop circuit, which will not be elaborated here.

[0229] It should be noted that in the embodiments of the present disclosure, the phase-locked loop circuit 90 / 900 may include more or fewer circuits or units, and the connection relationship between the various circuits or units is not limited and can be determined according to actual needs. The specific configuration of each circuit is not limited and can be composed of analog devices, digital chips, or other applicable methods based on circuit principles.

[0230] Figure 10 This is a schematic block diagram of a data processing device provided by at least one embodiment of the present disclosure.

[0231] For example, in at least one embodiment of the present disclosure, Figure 10 As shown, the data processing device 1001 includes a processor 110 and a memory 120. The memory 120 includes one or more computer program modules 1201. The one or more computer program modules 1201 are stored in the memory 120 and are configured to be executed by the processor 110. The one or more computer program modules 1201 include instructions for executing the parameter calibration method 20 / 70 for the phase-locked loop circuit provided by at least one embodiment of the present disclosure. When executed by the processor 110, the one or more steps in the parameter calibration method 20 / 70 for the phase-locked loop circuit provided by at least one embodiment of the present disclosure can be performed. The memory 120 and the processor 110 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0232] For example, the processor 110 may be a central processing unit (CPU), a digital signal processor (DSP), or other processing units with data processing capabilities and / or program execution capabilities, such as a field programmable gate array (FPGA). For example, the central processing unit (CPU) may be an X86 or ARM architecture. The processor 110 may be a general-purpose processor or a dedicated processor, and may control other components in the data processing device 1001 to perform desired functions.

[0233] For example, the memory 120 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer program modules 1201 may be stored on the computer-readable storage medium, and the processor 110 may execute one or more computer program modules 1201 to implement the various functions of the data processing device 1001. The computer-readable storage medium may also store various applications and various data, as well as various data used and / or generated by the applications. The data processing device 1001 may be, for example, a system on a chip (SOC) or a computer, television, monitor, etc. that includes the SOC. The specific functions and technical effects of the data processing device 1001 can be referred to the description of the parameter correction method 20 / 70 of the phase-locked loop circuit above, which will not be repeated here.

[0234] Figure 11 A schematic block diagram of another data processing device 300 provided for at least one embodiment of the present disclosure. The terminal devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 11 The data processing device 300 shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0235] For example, Figure 11 As shown, in some examples, the data processing device 300 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 301, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 302 or a program loaded from a storage device 308 into a random access memory (RAM) 303. Various programs and data required for the operation of the computer system are also stored in the RAM 303. The processing device 301, the ROM 302, and the RAM 303 are connected to each other via a bus 304. An input / output (I / O) interface 305 is also connected to the bus 304.

[0236] For example, the following components can be connected to the I / O interface 305: an input device 306 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 307 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 308 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 309 including, for example, a network interface card such as a LAN card, a modem, etc. The communication device 309 can allow the data processing device 300 to communicate with other devices wirelessly or by wire to exchange data, performing communication processing via a network such as the Internet. A drive 310 is also connected to the I / O interface 305 as needed. Removable media 311, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 310 as needed, so that the computer program read therefrom can be installed into the storage device 308 as needed. Although Figure 11 The data processing device 300 is shown as including various devices, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0237] For example, the data processing device 300 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 309 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communications may use any of a variety of communication standards, protocols, and technologies, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0238] For example, the data processing device 400 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, etc., or it can be any combination of data processing devices and hardware. The embodiments of the present disclosure are not limited to this.

[0239] For example, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network via the communication device 309, or installed from the storage device 308, or installed from the ROM 302. When the computer program is executed by the processing device 301, the parameter correction method 20 / 70 of the phase-locked loop circuit disclosed in the embodiment of the present disclosure is executed.

[0240] It should be noted that the computer-readable medium mentioned above in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In embodiments of the present disclosure, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device, or device. In embodiments of the present disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wires, optical cables, RF (radio frequency), etc., or any suitable combination thereof.

[0241] In some embodiments, the client and server can communicate using any currently known or future developed network protocol, such as HTTP (HyperText Transfer Protocol), and can be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), an internet (e.g., the Internet), and a peer-to-peer network (e.g., an ad hoc peer-to-peer network), as well as any currently known or future developed network.

[0242] The computer-readable medium may be included in the data processing device 300 , or may exist independently without being incorporated into the data processing device 300 .

[0243] At least one embodiment of the present disclosure further provides an electronic device. Figure 12 FIG is a schematic block diagram of an electronic device 1200 according to at least one embodiment of the present disclosure. Figure 12 As shown, the electronic device 1200 may include Figure 10 or Figure 11 Any data processing device 1001 / 300 shown in FIG; and a phase-locked loop circuit, for example, the phase-locked loop circuit can be provided in an embodiment of the present disclosure. Figure 1 The fully digital phase-locked loop circuit 10 shown may also be a phase-locked loop circuit of other similar or similar structures, and the embodiments of the present disclosure are not limited thereto. The phase-locked loop circuit is connected to the aforementioned data processing device 1001 / 300. It should be understood that the electronic device 1200 provided in the embodiments of the present disclosure can implement the aforementioned phase-locked loop circuit parameter calibration method 20 / 70 and can also achieve technical effects similar to the aforementioned phase-locked loop circuit parameter calibration method 20 / 70, and will not be described in detail here.

[0244] At least one embodiment of the present disclosure also provides a non-transitory readable storage medium. Figure 13 This is a schematic block diagram of a non-transient readable storage medium provided by at least one embodiment of the present disclosure. Figure 13 As shown, the non-transitory readable storage medium 130 stores computer instructions 111 , which, when executed by a processor, perform one or more steps of the parameter calibration method 20 / 70 for a phase-locked loop circuit as described above.

[0245] For example, the non-transitory readable storage medium 130 can be any combination of one or more computer-readable storage media. For example, one computer-readable storage medium contains computer-readable program code for setting multiple target parameters of a phase-locked loop circuit, and another computer-readable storage medium contains computer-readable program code for obtaining multiple filter coefficients of a digital loop filter based on the multiple target parameters, providing the multiple filter coefficients to the digital loop filter, so that the multiple operating parameters of the phase-locked loop circuit are correspondingly consistent with the multiple target parameters. Of course, the above-mentioned program codes can also be stored in the same computer-readable medium, and the embodiments of the present disclosure are not limited to this.

[0246] For example, when the program code is read by a computer, the computer can execute the program code stored in the computer storage medium and perform, for example, the parameter correction method 20 / 70 for the phase-locked loop circuit provided by any embodiment of the present disclosure.

[0247] For example, the storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a flash memory, or any combination of the above storage media, or other suitable storage media. For example, the readable storage medium may also be Figure 10 For the memory 120 in the embodiment, the related description can be referred to the aforementioned content and will not be repeated here.

[0248] In the present disclosure, the term "plurality" refers to two or more than two, unless clearly defined otherwise.

[0249] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the disclosure herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0250] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A method for calibrating parameters of a phase-locked loop circuit, wherein the phase-locked loop circuit includes a digital loop filter, the method comprising: Setting a plurality of target parameters of the phase-locked loop circuit; Based on the multiple target parameters, obtain multiple target filter coefficients for the digital loop filter, and provide the multiple target filter coefficients to the digital loop filter to correspondingly update the multiple filter coefficients of the digital loop filter, so that multiple operating parameters of the phase-locked loop circuit are correspondingly consistent with the multiple target parameters; The phase-locked loop circuit further includes a time-to-digital converter and a digitally controlled oscillator, wherein the time-to-digital converter is communicatively connected to the digital loop filter, and the digital loop filter is communicatively connected to the digitally controlled oscillator. Obtaining a plurality of target filter coefficients of the digital loop filter based on the plurality of target parameters, comprising: obtaining the plurality of target filter coefficients based on the plurality of target parameters and a first measurement result associated with the digitally controlled oscillator and a second measurement result associated with the time-to-digital converter; The multiple target parameters include at least the bandwidth and phase margin of the phase-locked loop circuit, the first measurement result includes the gain value of the digitally controlled oscillator, and the second measurement result includes the ratio between the first quantization accuracy and the second quantization accuracy of the time-to-digital converter, the first quantization accuracy corresponds to the first locking stage, and the second quantization accuracy corresponds to the second locking stage.

2. The method according to claim 1, further comprising: setting a first initial value of at least one target parameter among the plurality of target parameters; setting a second initial value corresponding to the first measurement result; Based on the first initial value and the second initial value, a third initial value of at least one target filter coefficient among the multiple target filter coefficients is set, wherein the first initial value, the second initial value and the third initial value are used as benchmark parameters for obtaining the multiple target filter coefficients.

3. The method according to claim 1, wherein Obtaining the plurality of target filter coefficients based on the plurality of target parameters and a first measurement result associated with the digitally controlled oscillator and a second measurement result associated with the time-to-digital converter comprises: Based on the multiple target parameters and the first measurement result, a first filter coefficient and a second filter coefficient are obtained, and through the first filter coefficient and the second filter coefficient, multiple operating parameters of the phase-locked loop circuit are kept consistent with the multiple target parameters in the first locking phase.

4. The method according to claim 3, wherein: Obtaining the plurality of target filter coefficients based on the plurality of target parameters and a first measurement result associated with the digitally controlled oscillator and a second measurement result associated with the time-to-digital converter further includes: Based on the first filter coefficient, the second filter coefficient and the second measurement result, a third filter coefficient and a fourth filter coefficient are obtained, and through the third filter coefficient and the fourth filter coefficient, multiple operating parameters of the phase-locked loop circuit are kept consistent with the multiple target parameters in the second locking phase.

5. The method according to claim 1, wherein The first measurement result is based on a first oscillation signal output by the digitally controlled oscillator when the input is a first frequency control word, and based on a second oscillation signal output by the digitally controlled oscillator when the input is a second frequency control word.

6. The method according to claim 5, wherein: The first frequency control word is different from the second frequency control word.

7. The method according to claim 1, wherein The second measurement result is based on a digital signal output by the time-to-digital converter when the first clock signal and the second clock signal are input, There is a preset phase difference between the first clock signal and the second clock signal.

8. The method according to claim 7, wherein: The preset phase difference corresponds to a clock period of the digitally controlled oscillator.

9. The method according to claim 1, wherein The first quantization accuracy is based on a clock period of the digitally controlled oscillator, The second quantization accuracy is based on a delay time of an inverter in the time-to-digital converter.

10. The method according to any one of claims 1 to 9, wherein The phase-locked loop circuit includes a fully digital phase-locked loop circuit.

11. A phase-locked loop circuit comprising a digital loop filter and a data processing device, wherein: The digital loop filter is communicatively connected to the data processing device, and the data processing device includes: a setting unit configured to set a plurality of target parameters of the phase-locked loop circuit; an acquiring unit configured to acquire a plurality of target filter coefficients for the digital loop filter based on the plurality of target parameters, and provide the plurality of target filter coefficients to the digital loop filter to correspondingly update the plurality of filter coefficients of the digital loop filter, so that the plurality of operating parameters of the phase-locked loop circuit are correspondingly consistent with the plurality of target parameters; The phase-locked loop circuit further includes a time-to-digital converter and a digitally controlled oscillator, the time-to-digital converter is communicatively connected to the digital loop filter, the digital loop filter is communicatively connected to the digitally controlled oscillator, and the data processing device is communicatively connected to the time-to-digital converter and the digitally controlled oscillator. The acquisition unit includes a calculation unit configured to: acquire the plurality of target filter coefficients based on the plurality of target parameters and based on a first measurement result associated with the digitally controlled oscillator and a second measurement result associated with the time-to-digital converter; The multiple target parameters include at least the bandwidth and phase margin of the phase-locked loop circuit, the first measurement result includes the gain value of the digitally controlled oscillator, and the second measurement result includes the ratio between the first quantization accuracy and the second quantization accuracy of the time-to-digital converter, the first quantization accuracy corresponds to the first locking stage, and the second quantization accuracy corresponds to the second locking stage.

12. The phase-locked loop circuit according to claim 11, further comprising a frequency divider, wherein: The frequency divider is in communication with the time-to-digital converter and the digitally controlled oscillator, The frequency divider is configured to perform frequency division processing on the digitally controlled oscillator output signal and provide the frequency-divided signal to the time-to-digital converter.

13. A data processing device comprising processor; a memory comprising one or more computer program modules; in, The one or more computer program modules are stored in the memory and configured to be executed by the processor to execute instructions of the parameter correction method for a phase-locked loop circuit according to any one of claims 1 to 10.

14. An electronic device comprising The data processing apparatus according to claim 13; and A phase-locked loop circuit is connected to the data processing device.

15. A non-transitory readable storage medium having computer instructions stored thereon, wherein: When the computer instructions are executed by a processor, a parameter correction method for a phase-locked loop circuit according to any one of claims 1 to 10 is performed.

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