Array substrate and display panel

Abstract

The embodiment of the present disclosure belongs to the technical field of display panels, and particularly relates to an array substrate and a display panel. The embodiment of the present disclosure aims to solve the problem of occupying wiring space and affecting the performance of the display panel caused by setting a reference voltage auxiliary line in the related art. The array substrate of the embodiment of the present disclosure comprises a transparent region and a non-transparent region, and further comprises a substrate, the substrate being provided with an array layer and an electrode layer in a stacked manner, the array layer comprising a plurality of pixel driving units located in the non-transparent region, the electrode layer comprising a plurality of electrode blocks provided at intervals, each pixel driving unit being connected with a corresponding electrode block; the array layer further comprises a first conductive layer, the first conductive layer comprising a plurality of reference voltage lines provided at intervals, and the substrate is further provided with a transparent conductive layer, the transparent conductive layer located in the non-transparent region being connected with at least two reference voltage lines to balance the voltage of the reference voltage lines; compared with setting a reference voltage auxiliary line, the array substrate can avoid occupying wiring space and improve the performance of the display panel.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of display panel, and particularly to an array substrate and a display panel. BACKGROUND

[0002] An organic light-emitting diode display panel (OLED) has advantages of low power consumption, high saturation, fast response time, wide viewing angle, and the like, and is applied in more and more fields.

[0003] In the related art, a display panel includes an array substrate and a light-emitting layer which are stacked, the array substrate includes a substrate, a first conductive layer, a second conductive layer, and an insulating layer which are stacked on the substrate, the insulating layer is located between the first conductive layer and the second conductive layer, the first conductive layer includes a plurality of reference voltage lines which are parallel and spaced, the second conductive layer includes a plurality of data lines which are parallel and spaced, a plurality of power lines which are parallel and spaced, and a plurality of reference voltage auxiliary lines, each reference voltage auxiliary line is spaced from the power lines and the data lines, and each reference voltage auxiliary line is connected with two different reference voltage lines to balance the voltage of each reference voltage line.

[0004] However, the space of the second conductive layer is limited, and the setting of the reference voltage auxiliary line causes the cross-sectional area of the power line or the data line to decrease, so that the resistance of the power line or the data line increases, and the performance of the display panel is affected. SUMMARY

[0005] Embodiments of the present disclosure provide an array substrate and a display panel to solve the problem that the increase of the reference voltage auxiliary line occupies the wiring space of the second conductive layer, causes the cross-sectional area of the power line or the data line to decrease, so that the resistance of the power line or the data line increases, and the display performance of the display panel is affected.

[0006] In one aspect, an array substrate is provided, including a transparent region and a non-transparent region adjacent to the transparent region, and further including: a substrate; an array layer and an electrode layer which are stacked on the substrate, the array layer is located between the electrode layer and the substrate, the array layer includes a plurality of pixel driving units located in the non-transparent region, the electrode layer includes a plurality of electrode blocks which are spaced, each of the pixel driving units is connected with a corresponding electrode block; the array layer further includes a first conductive layer, the first conductive layer includes a plurality of reference voltage lines which are spaced; a transparent conductive layer is provided on the substrate, the first transparent conductive layer located in the non-transparent region is connected with at least two reference voltage lines.

[0007] By the above setting, the transparent conductive layer is connected with the reference voltage lines in the first conductive layer, a mesh connection structure of the reference voltage lines is realized, and the display performance of the display panel is improved.

[0008] In some embodiments which can comprise the above-mentioned embodiments, the transparent conductive layer comprises a first transparent conductive layer, the first transparent conductive layer in the transparent region comprises a plurality of first transparent conductive lines, each of the first transparent conductive lines is connected with the electrode block and a corresponding pixel driving unit in the transparent region.

[0009] In some embodiments which can comprise the above-mentioned embodiments, the first transparent conductive layer is disposed between the array layer and the electrode layer.

[0010] In some embodiments which can comprise the above-mentioned embodiments, the array layer further comprises a second conductive layer, the second conductive layer is disposed on a side of the first conductive layer away from the substrate; the second conductive layer comprises a plurality of data lines, the plurality of data lines are disposed in parallel and at intervals; the first transparent conductive layer in the non-transparent region is provided with a avoiding port, a projection of the data line on the substrate is located within a projection of the avoiding port on the substrate.

[0011] In some embodiments which can comprise the above-mentioned embodiments, a conductive plug is disposed between the transparent conductive layer and the first conductive layer, the transparent conductive layer is connected with at least two reference voltage lines through the conductive plug.

[0012] In some embodiments which can comprise the above-mentioned embodiments, the transparent conductive layer in the non-transparent region is connected with each of the reference voltage lines.

[0013] In some embodiments which can comprise the above-mentioned embodiments, the transparent conductive layer further comprises a second transparent conductive layer disposed on a side of the first transparent conductive layer away from the substrate, the second transparent conductive layer in the transparent region comprises a plurality of second transparent conductive lines, the first transparent conductive lines are connected with part of the electrode blocks and the corresponding pixel driving units in the transparent region, and the second transparent conductive lines are connected with part of the electrode blocks and the corresponding pixel driving units in the transparent region.

[0014] In some embodiments which can comprise the above-mentioned embodiments, the second transparent conductive layer in the non-transparent region is connected with at least two reference voltage lines; preferably, the second transparent conductive layer is a plurality of layers, and the plurality of second transparent conductive layers are disposed in a stack.

[0015] In some embodiments which can comprise the above-mentioned embodiments, the first transparent conductive layer and the second transparent conductive layer each comprise an indium tin oxide layer.

[0016] In another aspect, embodiments of the present disclosure also provide a display panel comprising the array substrate described above.

[0017] The array substrate and display panel provided in the embodiments of this disclosure include a transparent area and a non-transparent area, and a substrate. An array layer and an electrode layer are stacked on the substrate. The array layer includes multiple pixel driving units located in the non-transparent area, and the electrode layer includes multiple spaced electrode blocks. Each pixel driving unit is connected to a corresponding electrode block. The array layer also includes a first conductive layer, which includes multiple spaced reference voltage lines. A transparent conductive layer is also disposed on the substrate, and the transparent conductive layer located in the non-transparent area is connected to at least two reference voltage lines. By using the transparent conductive layer in the non-transparent area to connect multiple reference voltage lines, the voltage of the reference voltage lines is balanced. Compared with setting reference voltage auxiliary lines in the second conductive layer within the array layer, the wiring space of the array layer can be avoided, thereby increasing the interface area of ​​the data lines and power lines in the array layer, reducing the resistance of the data lines and power lines, and thus reducing the voltage drop of the data lines and power lines, improving the performance of the display panel. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0019] Figure 1 A top view of the array substrate provided in an embodiment of this disclosure;

[0020] Figure 2 for Figure 1 Schematic diagram of cross-sectional structure in the AA direction Figure 1 ;

[0021] Figure 3 for Figure 1 Schematic diagram of cross-sectional structure in the AA direction Figure 2 ;

[0022] Figure 4 for Figure 1 A schematic diagram of the cross-sectional structure along the BB direction.

[0023] Explanation of reference numerals in the attached figures:

[0024] 1: Substrate;

[0025] 2: Array layer;

[0026] 3: Electrode layer;

[0027] 4: First transparent conductive layer;

[0028] 5: Conductive plug;

[0029] 6: Reference voltage auxiliary line;

[0030] 7: Second transparent conductive layer;

[0031] 8: planarization layer;

[0032] 11: first insulating layer;

[0033] 12: second insulating layer;

[0034] 13: third insulating layer;

[0035] 14: fourth insulating layer;

[0036] 15: fifth insulating layer;

[0037] 16: sixth insulating layer;

[0038] 21: pixel driving unit;

[0039] 22: first conductive layer;

[0040] 23: second conductive layer;

[0041] 24: third conductive layer;

[0042] 40: anode layer;

[0043] 41: avoidance port;

[0044] 211: source-drain electrode layer;

[0045] 212: gate electrode layer;

[0046] 221: reference voltage line;

[0047] 231: data line;

[0048] 232: power supply line;

[0049] A: transparent area;

[0050] B: non-transparent area.

[0051] The specific embodiments of the present disclosure have been shown by the above-described drawings, and will be described in more detail hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the present disclosure in any way, but to illustrate the concept of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0052] In order to make the purposes, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without any creative work fall within the scope of protection of the present disclosure.

[0053] The display panel comprises an array substrate and a light-emitting layer arranged in layers, the light-emitting layer comprises a pixel defining layer arranged in layers on the array substrate, the pixel defining layer has a plurality of pixel openings, each pixel opening is filled with a light-emitting material, and the light-emitting material in each pixel opening, together with an anode and a cathode, forms a pixel unit. The array substrate is used to control the lighting or turning off of each pixel unit to realize image display. The array substrate comprises a substrate, a first conductive layer, a second conductive layer and an insulating layer arranged in layers on the substrate, the insulating layer is between the first conductive layer and the second conductive layer, the first conductive layer comprises a plurality of reference voltage lines arranged in parallel and at intervals, and the reference voltage lines are used to provide stable reference voltages. The second conductive layer comprises a plurality of data lines arranged in parallel and at intervals, a plurality of power lines arranged in parallel and at intervals, and a plurality of reference voltage auxiliary lines. The array substrate further comprises a plurality of thin film transistors (TFTs). The data lines are connected to the thin film transistors to control the lighting or turning off of the corresponding pixel units through the thin film transistors. Each reference voltage auxiliary line is connected to two different reference voltage lines in the first conductive layer, thereby connecting the two reference voltage lines arranged in parallel and at intervals, forming a network-shaped reference voltage line arrangement structure, improving the voltage uniformity of each reference voltage line, and improving the display uniformity of the display panel.

[0054] However, the wiring space of the second conductive layer is limited, and the arrangement of the reference voltage auxiliary lines will inevitably occupy the wiring space of the power lines or the data lines. The wiring space of the power lines or the data lines is reduced, the line width of the power lines or the data lines is reduced, the resistance of the power lines or the data lines is increased, the voltage drop of the power lines or the data lines is increased, and the display performance of the display panel is affected.

[0055] The array substrate and the display panel provided by the embodiments of the present disclosure comprise a transparent region and a non-transparent region adjacent to the transparent region, and further comprise a substrate, an array layer and an electrode layer arranged in layers on the substrate, the array layer comprises a plurality of pixel driving units in the non-transparent region; a transparent conductive layer is further arranged on the substrate, and the transparent conductive layer in the non-transparent region is connected to at least two reference voltage lines in the array layer; the transparent conductive layer in the non-transparent region is used to connect a plurality of reference voltage lines to balance the voltage of the reference voltage lines; compared with the arrangement of the reference voltage auxiliary lines in the second conductive layer in the array layer, the wiring space of the second conductive layer in the array layer can be avoided, and the interface area of the data lines and the power lines in the second conductive layer is increased, the resistance of the data lines and the power lines is reduced, the voltage drop of the data lines and the power lines is reduced, and the performance of the display panel is improved.

[0056] The display panel provided by the embodiment of the present disclosure comprises an array substrate and a light-emitting layer which are arranged in layers, the light-emitting layer comprises a pixel defining layer covering the array substrate, the pixel defining layer is provided with a plurality of pixel openings in an array, the light-emitting material is filled in each pixel opening, and the light-emitting material in each pixel opening cooperates with an anode and a cathode to form a pixel unit; the array layer of the array substrate is provided with a plurality of pixel driving units, that is, pixel circuits, each pixel driving unit is connected with an electrode block in the corresponding pixel unit and is used for controlling the pixel unit to light up or turn off.

[0057] Please refer to Figure 1 and Figure 2 The array substrate in the embodiment of the present disclosure comprises a transparent area and a non-transparent area adjacent to the transparent area, wherein the transparent area and the corresponding film layers of the transparent area are transparently arranged to enable light to pass through the display panel through the transparent area; and the pixel defining layer in the transparent area and the non-transparent area is provided with a pixel unit, so that the display panel corresponding to the transparent area and the non-transparent area can display images.

[0058] For example, the transparent area can be arranged opposite to an under-display camera (UDC) to enable the under-display camera to obtain external light through the display panel corresponding to the transparent area, thereby realizing the photographing function and improving the screen-to-body ratio. Of course, in other implementation manners, the transparent area can be arranged opposite to an under-display fingerprint recognition device, the under-display fingerprint recognition device can obtain user fingerprint information through the display panel corresponding to the transparent area, thereby realizing fingerprint recognition.

[0059] In the above implementation manner, the transparent area is adjacent to the non-transparent area, for example, the transparent area can be adjacent to the non-transparent area; of course, the non-transparent area can also surround or partially surround the outside of the transparent area, and the embodiment does not limit this.

[0060] The array substrate in the embodiment further comprises a substrate 1, an array layer 2 and an electrode layer 3, the array layer 2 and the electrode layer 3 are arranged in layers on the substrate 1, the array layer 2 is located between the electrode layer 3 and the substrate 1, the array layer 2 comprises a plurality of pixel driving units 21 located in the non-transparent area, the electrode layer 3 comprises a plurality of electrode blocks arranged at intervals, each electrode block is arranged opposite to a pixel unit, and each pixel driving unit 21 is connected with the corresponding electrode block to control the electrode block to be charged, thereby enabling the pixel unit corresponding to the electrode block to light up or turn off.

[0061] In the above implementation manner, the pixel driving unit 21 can comprise a thin film transistor, each thin film transistor is connected with the corresponding electrode block to control whether the electrode block is charged, thereby controlling the pixel unit corresponding to the electrode block to light up or turn off.

[0062] In the above implementation, the array layer 2 further comprises a first conductive layer 22, and the first conductive layer 22 comprises a plurality of spaced reference voltage lines 221. Correspondingly, the array substrate further comprises a transparent conductive layer disposed on the substrate 1, and the transparent conductive layer in the non-transparent region is connected to at least two reference voltage lines 221. In this way, the transparent conductive layer in the non-transparent region can balance the voltages of the two connected reference voltage lines 221, thereby improving the voltage uniformity of the reference voltage lines 221. The plurality of reference voltage lines 221 can be parallel and spaced.

[0063] In other implementations, the transparent conductive layer in the non-transparent region can be connected to each reference voltage line 221, so that each reference voltage line and the transparent conductive layer in the non-transparent region form a meshed connection structure, further balancing the voltages of the reference voltage lines and improving the voltage uniformity of the reference voltage lines, thereby improving the performance of the display panel. It should be noted that the projection of the transparent conductive layer on the substrate 1 covers the transparent region and the non-transparent region, and the transparent conductive layer in the non-transparent region is in the form of a plate.

[0064] Therefore, the array substrate provided by the embodiment comprises a transparent region and a non-transparent region adjacent to the transparent region, a substrate 1, an array layer 2 and an electrode layer 3 stacked on the substrate 1, the array layer 2 comprising a plurality of pixel driving units 21 in the non-transparent region, the electrode layer 3 comprising a plurality of spaced electrode blocks, each pixel driving unit 21 being connected to a corresponding electrode block, and a transparent conductive layer disposed on the substrate 1, the transparent conductive layer in the non-transparent region being connected to at least two reference voltage lines 221. The transparent conductive layer in the non-transparent region is used to connect the plurality of reference voltage lines 221, so as to balance the voltages of the reference voltage lines 221. Compared with the implementation of arranging the reference voltage auxiliary lines in the second conductive layer in the array layer 2, the wiring space of the second conductive layer can be avoided, thereby increasing the interface area of the data lines and the power lines in the second conductive layer, reducing the resistance of the data lines and the power lines, and improving the performance of the display panel.

[0065] In the above implementation, a conductive plug 5 is arranged between the transparent conductive layer in the non-transparent region and the first conductive layer 22, and the transparent conductive layer in the non-transparent region is connected to at least two reference voltage lines 221 through the conductive plug 5. In this way, the structure is simple and easy to manufacture.

[0066] For example, the electrode layer 3 corresponding to the transparent area can include a transparent conductive layer, and the material of the transparent conductive layer can include indium tin oxide (ITO), a transparent conductive polymer (such as polyaniline), etc., so as to improve the light transmittance of the display panel corresponding to the transparent area. That is, the electrode layer includes a plurality of electrode blocks arranged at intervals, and the electrode block located in the transparent area can be a transparent conductive layer. Correspondingly, the electrode layer 3 of the non-transparent area can also include a metal layer, and the material of the metal layer can include copper, silver, etc. Please refer to Figure 3 The array substrate includes a transparent area A and a non-transparent area B adjacent to the transparent area A, and the electrode layer 3 includes an anode. The anode layer 40 corresponding to the transparent area A is directly replaced by a transparent conductive layer, so that the transparent conductive layer is used as an anode in the transparent area A, and the transparent conductive layer in the non-transparent area B is used to connect a plurality of reference voltage lines 221 arranged in the first conductive layer 22, thereby further improving the light transmittance of the display panel corresponding to the transparent area.

[0067] In another embodiment, the pixel driving unit 21 connected with the electrode block corresponding to the transparent area A is arranged in the area of the non-transparent area B, so as to improve the light transmittance of the display panel corresponding to the transparent area A. Wherein, the transparent conductive layer includes a first transparent conductive layer 4, and the first transparent conductive layer 4 located in the transparent area A includes a first transparent conductive line. Each first transparent conductive line is connected with the electrode block of the transparent area A and the corresponding pixel driving unit 21, so as to realize the control of the electrode block corresponding to the transparent area A. That is, one end of the first transparent conductive line is connected with the electrode block corresponding to the transparent area A, and the other end of the first transparent conductive line is connected with the pixel driving unit 21 of the non-transparent area B, so as to realize the conduction of the pixel circuit of the pixel unit corresponding to the transparent area A.

[0068] Please refer to Figure 2 and Figure 4 In the above implementation, the array substrate can include: a substrate 1, the source-drain electrode layer 211, the first insulating layer 11, the third conductive layer 24 (the third conductive layer 24 can include the gate electrode layer 212), the second insulating layer 12, the first conductive layer 22, the third insulating layer 13, the fourth insulating layer 14, the second conductive layer 23 (the second conductive layer 23 can include a plurality of data lines 231 and a plurality of power lines 232, and the data line 231 and the source-drain electrode layer 211 in the third conductive layer 24 are connected), the planarization layer 8 and the electrode layer 3 are sequentially arranged on the substrate 1.

[0069] Wherein, the source-drain electrode layer 211 and the gate electrode layer 212 jointly constitute a pixel driving unit 21, which is used to control the corresponding pixel unit to be turned on or off.

[0070] The first transparent conductive layer 4 can be arranged at any position between the electrode layer 3 and the substrate 1. For example, the first transparent conductive layer 4 can be arranged between the first insulating layer 11 and the third conductive layer 24; or the first transparent conductive layer 4 can be arranged between the second insulating layer 12 and the first conductive layer 11; or the first transparent conductive layer 4 can be arranged between the fourth insulating layer 14 and the second conductive layer 23. It is worth mentioning that, in order to avoid the contact between the first transparent conductive layer 4 and the adjacent conductive layer, an insulating layer can be arranged between the first transparent conductive layer 4 and the adjacent conductive layer.

[0071] The array layer 2 of the embodiment of the present disclosure comprises a first conductive layer 22, a second conductive layer 23, a third conductive layer 24 (the third conductive layer 24 comprises a gate electrode layer 212), and a source-drain electrode layer 211. The first transparent conductive layer 4 can also be arranged between the array layer 2 and the electrode layer 3. In this way, the influence between the first transparent conductive layer 4 and the conductive layer or the electrical element in the array layer 2 can be avoided. For example, the first transparent conductive layer 4 can be arranged between the second conductive layer 23 and the planarization layer 8, or the first transparent conductive layer 4 can be arranged between the planarization layer 8 and the electrode layer 3.

[0072] In the embodiment of the present disclosure, the second conductive layer 23 of the array layer 2 is arranged on the side of the first conductive layer 22 away from the substrate 1. The second conductive layer 23 comprises a plurality of data lines 231, and the plurality of data lines 231 are arranged in parallel and at intervals. The first transparent conductive layer 4 of the non-transparent area B can be provided with a relief opening 41, and the projection of the data line 231 on the substrate 1 is located within the projection of the relief opening 41 on the substrate 1.

[0073] The projection of the data line 231 on the substrate 1 is located within the projection of the relief opening 41 on the substrate 1, which can ensure that the line width of the data line 231 is less than the width of the relief opening 41, so that the data line 231 has a certain distance from the first transparent conductive layer 4, which can prevent the formation of a capacitor between the first transparent conductive layer 4 and the data line 231, and avoid the mutual influence between the data signal and the first transparent conductive layer 4.

[0074] In the embodiment, the plurality of reference voltage lines 221 are arranged in parallel and at intervals along a first preset direction, and the corresponding data lines 231 can be arranged in parallel and at intervals along a second preset direction. Correspondingly, the first transparent conductive layer 4 is provided with a plurality of relief openings 41, each relief opening 41 extends in a direction parallel to the extension direction of the data line 231, and the plurality of relief openings are arranged in parallel and at intervals along the second preset direction. The plurality of relief openings 41 divide the first transparent conductive layer 4 into a plurality of reference voltage auxiliary lines 6 arranged in parallel and at intervals.

[0075] Further, the first preset direction is perpendicular to the second preset direction, that is, the reference voltage auxiliary line 6 is arranged perpendicularly to the reference voltage line 221. Each reference voltage auxiliary line 6 can be connected to each reference voltage line 221 through the conductive plug 5, so that the reference voltage auxiliary line 6 and the reference voltage line 221 form a mesh connection structure, further improving the voltage uniformity of each reference voltage line 221.

[0076] In the above implementation, the third insulating layer and the fourth insulating layer are further arranged between the first conductive layer 22 and the second conductive layer 23, and the second conductive layer 23 further includes a plurality of power lines 232, which are arranged in parallel and at intervals. The power line 232 can be arranged in parallel with the data line 231.

[0077] In the embodiment, the second conductive layer 23 is arranged between the first conductive layer 22 and the first transparent conductive layer 4. In the implementation in which the first transparent conductive layer 4 is connected to the reference voltage line 221 through the conductive plug 5, a plurality of vias are arranged on the second conductive layer 23, and the conductive plug 5 passes through the vias to be connected to the first transparent conductive layer 4 and the second conductive layer 23. Further, in order to avoid the connection between the conductive plug 5 and the second conductive layer 23, an insulating side wall can be arranged between the via and the conductive plug 5.

[0078] Please refer to Figure 4 In the embodiment of the present disclosure, the transparent conductive layer further includes a second transparent conductive layer 7 arranged on the side of the first transparent conductive layer 4 away from the substrate 1; the first transparent conductive layer 4 and the second transparent conductive layer 7 are arranged in a stack, and a fifth insulating layer 15 is further arranged between the first transparent conductive layer 4 and the second transparent conductive layer 7, and a sixth insulating layer 16 is arranged between the second transparent conductive layer 7 and the electrode layer 3. The second transparent conductive layer 7 is arranged in both the transparent area A and the non-transparent area B, the second transparent conductive layer 7 of the transparent area A includes a plurality of second transparent conductive lines, the first transparent conductive lines of the transparent area A are connected to part of the electrode blocks of the transparent area A and the pixel driving units 21 of the non-transparent area B, and the second transparent conductive lines of the transparent area A are connected to part of the electrode blocks of the transparent area A and the pixel driving units 21 of the non-transparent area B.

[0079] That is, the transparent area A includes a plurality of electrode blocks, part of the electrode blocks of the transparent area A are connected to part of the pixel driving units 21 of the non-transparent area B through the first transparent conductive lines of the first transparent conductive layer 4, to realize the control of the corresponding part of the electrode blocks of the transparent area A; and part of the electrode blocks of the transparent area A are connected to part of the pixel driving units 21 of the non-transparent area B through the second transparent conductive lines of the second transparent conductive layer 7, to realize the control of the corresponding part of the electrode blocks of the transparent area A. The density of the transparent area A is dispersed, which is convenient for the manufacture of the array substrate.

[0080] In other implementations, the second transparent conductive layer 7 corresponding to the non-transparent area B can be connected with at least two reference voltage lines 221 to balance the voltage of the connected two reference voltage lines 221. The second transparent conductive layer 7 corresponding to the non-transparent area B can also be connected with each reference voltage line 221, so that each reference voltage line 221 and the second transparent conductive layer 7 corresponding to the non-transparent area B form a meshed connection structure, further balancing the voltage of each reference voltage line 221, improving the voltage uniformity of the reference voltage line 221, and further improving the performance of the display panel.

[0081] In the embodiments of the present disclosure, the second transparent conductive layer 7 can be multiple, and the multiple second transparent conductive layers 7 are stacked. The more transparent conductive layers, the more dispersed the wiring can be, and the wiring density can be reduced. The number of layers of the second transparent conductive layer 7 can be set according to the display of the specific display panel. When the multiple second transparent conductive layers 7 are stacked, an insulating layer is further arranged between the adjacent two second transparent conductive layers 7, and the multiple second transparent conductive layers 7 after stacking are all located on the side of the first transparent conductive layer 4 away from the substrate 1.

[0082] In the above implementation, the multiple first transparent conductive lines of the first transparent conductive layer 4 of the transparent area A are used to be connected with the partial electrode blocks of the transparent area A and the corresponding partial pixel driving units 21, and the multiple second transparent conductive lines of the multiple second transparent conductive layers 7 of the transparent area A are used to be connected with the partial electrode blocks of the transparent area A and the corresponding partial pixel driving units 21, so as to realize the control of the electrode blocks corresponding to the transparent area A, and further reduce the wiring density.

[0083] In the embodiments of the present disclosure, the first transparent conductive layer 4 and the second transparent conductive layer 7 both include an indium tin oxide layer. Indium tin oxide, transparent conductive polymer (such as polyaniline), etc.

[0084] The embodiments of the present disclosure also provide a display panel, which includes the array substrate in the above embodiments.

[0085] The display panel provided by the embodiments of the present disclosure includes a transparent area A and a non-transparent area B, and further includes a substrate 1, an array layer 2 and an electrode layer 3 which are stacked on the substrate 1, the array layer 2 includes a plurality of pixel driving units 21 located in the non-transparent area B, the electrode layer 3 includes a plurality of electrode blocks which are arranged at intervals, each pixel driving unit 21 is connected with a corresponding electrode block; the substrate 1 is further provided with a transparent conductive layer; the array layer 2 further includes a first conductive layer 22, the first conductive layer 22 includes a plurality of reference voltage lines 221 which are arranged at intervals, the transparent conductive layer located in the non-transparent area B is connected with at least two reference voltage lines 221; the transparent conductive layer in the non-transparent area B is used to connect the plurality of reference voltage lines 221, so as to balance the voltage of the reference voltage lines 221; compared with the arrangement of a reference voltage auxiliary line in a second conductive layer 23 in the array layer 2, the wiring space of the second conductive layer 23 in the array layer 2 can be avoided, and then the interface area of a data line 231 and a power line 232 in the second conductive layer 23 is increased, the resistance of the data line 231 and the power line 232 is reduced, and then the voltage drop of the data line 231 and the power line 232 is reduced, and the performance of the display panel is improved.

[0086] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, but not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An array substrate, characterized by, The array substrate comprises a transparent region and a non-transparent region adjacent to the transparent region, and further comprises: a substrate; an array layer and an electrode layer which are stacked on the substrate, the array layer being between the electrode layer and the substrate, the array layer comprising a plurality of pixel driving units, and the electrode layer comprising a plurality of electrode blocks which are spaced apart from each other, each of the pixel driving units being connected to a corresponding electrode block; the array layer further comprises a first conductive layer, the first conductive layer comprising a plurality of reference voltage lines which are spaced apart from each other; the substrate is provided with a transparent conductive layer, the transparent conductive layer in the non-transparent region being connected to at least two of the reference voltage lines; the transparent conductive layer comprises a first transparent conductive layer, the first transparent conductive layer in the transparent region comprising a plurality of first transparent conductive lines, each of the first transparent conductive lines being connected to the electrode block in the transparent region and a corresponding pixel driving unit.

2. The array substrate according to claim 1, wherein the first transparent conductive layer is arranged between the array layer and the electrode layer.

3. The array substrate according to claim 2, wherein the array layer further comprises a second conductive layer, the second conductive layer being arranged on a side of the first conductive layer away from the substrate, and the second conductive layer comprising a plurality of data lines which are parallel and spaced apart from each other; the first transparent conductive layer in the non-transparent region is provided with a relief opening, and a projection of the data line on the substrate is located within a projection of the relief opening on the substrate.

4. The array substrate according to any one of claims 1-3, wherein a conductive plug is arranged between the transparent conductive layer and the first conductive layer, and the transparent conductive layer is connected to at least two of the reference voltage lines through the conductive plug.

5. The array substrate according to any one of claims 1-3, wherein the transparent conductive layer in the non-transparent region is connected to each of the reference voltage lines.

6. The array substrate according to any one of claims 2-3, wherein the transparent conductive layer further comprises a second transparent conductive layer which is arranged on a side of the first transparent conductive layer away from the substrate, and the second transparent conductive layer in the transparent region comprises a plurality of second transparent conductive lines, the first transparent conductive lines being connected to part of the electrode blocks in the transparent region and corresponding pixel driving units, and the second transparent conductive lines being connected to part of the electrode blocks in the transparent region and corresponding pixel driving units.

7. The array substrate according to claim 6, wherein the second transparent conductive layer in the non-transparent region is connected to at least two of the reference voltage lines.

8. The array substrate of claim 7, wherein, There are a plurality of second transparent conductive layers which are stacked.

9. The array substrate of claim 6, wherein, The first transparent conductive layer and the second transparent conductive layer each comprise an indium tin oxide layer.

10. A display panel, characterized by, The array substrate according to any one of claims 1-9.

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