Trench power semiconductor device with surround-type source region and method of manufacturing the same

Abstract

The application relates to a trench power semiconductor device with a surrounding source region, comprising a substrate region, a drift region, a base region, a source region, a shielding gate, a control gate, an insulating layer, a source electrode, a drain electrode and a metal gate; the drift region is connected with the substrate region, the direction of the substrate region pointing to the drift region is upward, the base region and the source region are sequentially arranged above the drift region; the control gate and the shielding gate are sequentially arranged on the side of the drift region from top to bottom and are connected with the drift region, the base region and the source region through the insulating layer; the source region comprises a P-type source region and an N-type source region; the P-type source region is arranged above the base region, the N-type source region is arranged at the joint of the side of the P-type source region and the insulating layer, one side of the N-type source region is connected with the insulating layer, so that the N-type source region is half surrounded by the P-type source region; the source electrode is arranged above the source region; the drain electrode is arranged below the substrate region; and the metal gate is arranged above the control gate. The scheme provided by the application can expand the interface of the avalanche current channel and improve the maximum avalanche resistance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to trench power semiconductor devices with enclosed source regions and methods for fabricating the same. Background Technology

[0002] Shielded gate trench field-effect transistors (SGTs) have been widely used in important low-voltage applications such as power management. This is because SGTs have high channel density and good charge compensation. Furthermore, their shielded gate structure effectively isolates the coupling between the metal gate and drain, significantly reducing transfer capacitance. This results in lower specific on-resistance, lower conduction and switching losses, and higher operating frequencies for SGTs.

[0003] In related technologies, a composite source structure of P-type and N-type source regions is used in transistors, where the P-type source region short-circuits the transistor's base region and the source. This type of source region structure typically employs an interdigitated bar structure, where the P-type and N-type source regions are arranged parallel to each other on the base region, and the P-type and N-type source regions equally share the contact area between the source region and the base region.

[0004] The aforementioned source region structure limits the area of ​​the source region that can receive avalanche current, thus limiting the maximum avalanche tolerance of the transistor. Summary of the Invention

[0005] To overcome the problems existing in related technologies, this application provides a trench-type power semiconductor device with an enclosed source region and its fabrication method, which can expand the interface of the avalanche current channel, reduce the avalanche current density, and thus improve the maximum avalanche tolerance.

[0006] The first aspect of this application provides a trench-type power semiconductor device with an enclosed source region, comprising:

[0007] Substrate region 1, drift region 2, substrate region 3, source region 4, shielding gate 5, control gate 6, insulating layer 7, source, drain 8, and metal gate;

[0008] The drift region 2 is connected to the substrate region 1, with the direction from the substrate region to the drift region as the top. The substrate region 3 and the source region 4 are sequentially disposed above the drift region 2. The control gate 6 and the shielding gate 5 are sequentially disposed from top to bottom on the side of the drift region 2, and are connected to the drift region 2, the substrate region 3 and the source region 4 respectively through the insulating layer 7.

[0009] The source region 4 includes a P-type source region 41 and an N-type source region 42; the P-type source region 41 is disposed above the substrate region 3, and the N-type source region 42 is disposed at the junction of the side of the P-type source region 41 and the insulating layer 7, with one side of the N-type source region 42 in contact with the insulating layer 7, such that the N-type source region 42 is partially surrounded by the P-type source region 41.

[0010] The source electrode is disposed above the source region 4; the drain electrode 8 is disposed below the substrate region 1; and the metal gate electrode is disposed above the control gate 6.

[0011] In one embodiment, the drift region 2 has a first top surface 21, a second top surface 22, and a third top surface 23; wherein the distances between the first top surface 21, the second top surface 22, and the third top surface 23 and the substrate region 1 gradually increase;

[0012] The first top surface 21 is connected to the bottom surface of the shielding grid 5 through the insulating layer 7; the second top surface 22 is connected to the bottom of the substrate region 3; the third top surface 23 is flush with the top surface of the source region 4, so that the substrate region 3 and the source region 4 are both located in the recess formed by the second top surface 22 and the third top surface 23 in the drift region 2.

[0013] In one embodiment, the width ratio and length ratio of the P-type source region 41 and the N-type source region 42 are both 2:1.

[0014] In one embodiment, the area ratio of the second top surface 22 to the third top surface 23 is 1:1.

[0015] In one embodiment, the doping concentrations of both the P-type source region 41 and the N-type source region 42 are heavily doped.

[0016] In one embodiment, the substrate region 1 is doped with N-type doping and the doping concentration of the substrate region 1 is a heavily doped concentration.

[0017] The drift region 2 is N-type doped, and the doping concentration of the drift region 2 is light doping concentration;

[0018] The substrate region 3 is p-type doped, and the doping concentration of the substrate region 3 is medium.

[0019] Both the shielding gate 5 and the control gate 6 are P-type doped; both the shielding gate 5 and the control gate 6 are heavily doped.

[0020] A second aspect of this application provides a method for fabricating a trench-type power semiconductor device with an enclosed source region, for fabricating a trench-type power semiconductor device with an enclosed source region as described in any of the preceding claims, comprising:

[0021] The substrate region is fabricated using semiconductor materials;

[0022] A drift region is epitaxially formed on the substrate region;

[0023] A matrix region is formed on the drift region by ion implantation or diffusion.

[0024] A groove is etched on one side of the drift region;

[0025] Oxide, polysilicon, oxide, and polysilicon are sequentially deposited in the trench to form an insulating layer, a shielding gate, and a control gate;

[0026] An N-type source region is formed by local doping at the location where the insulating layer is attached to the substrate region, and a P-type source region is formed by doping around the N-type source region, such that the N-type source region is partially surrounded by the P-type source region.

[0027] A source electrode is fabricated above the P-type source region and the N-type source region;

[0028] A metal gate is formed above the trench;

[0029] A drain electrode is fabricated at the bottom of the substrate region.

[0030] In one embodiment, forming a substrate region on the drift region by ion implantation or diffusion includes:

[0031] The substrate region is formed by local doping in the first region of the drift region using ion implantation or diffusion; the third top surface of the drift region is formed by doping in the second region of the drift region using the same semiconductor material as the drift region.

[0032] In one embodiment, after epitaxially forming the drift region on the substrate region, the process includes:

[0033] The drift region is etched to form the second top surface of the drift region;

[0034] The formation of the matrix region on the drift region by ion implantation or diffusion includes:

[0035] The substrate region is formed on the second top surface by ion implantation or diffusion.

[0036] In one embodiment, in the step of sequentially depositing oxide, polysilicon, oxide, and polysilicon in the trench to form an insulating layer, a shielding gate, and a control gate, the polysilicon is heavily doped polysilicon.

[0037] The technical solution provided in this application may include the following beneficial effects:

[0038] This application provides a trench-type power semiconductor device with an enclosed source region. The source region includes a P-type source region and an N-type source region. Unlike existing source region structures, the P-type and N-type source regions are arranged parallel to each other on the substrate region, and the P-type and N-type source regions share the interface area between the source region and the substrate region in an interdigitated strip structure. In this application, the P-type source region semi-encloses the N-type source region, forming an enclosed source region structure. This expands the interface of the avalanche current channel, dispersing the avalanche current flow to the expanded PN junction surface. This reduces the avalanche current density when the device is forward-blocking or forward-conducting, effectively improving the direction of avalanche current flow when the power semiconductor device is in blocking or conducting states. Therefore, under the condition of a fixed total avalanche current, the voltage drop through the P-type source region is reduced, i.e., the parallel resistance of the source region PN junction is reduced, suppressing the turn-on of parasitic transistors, thereby increasing the maximum avalanche tolerance and improving the reliability of the power semiconductor device.

[0039] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0040] The above and other objects, features and advantages of this application will become more apparent from the more detailed description of exemplary embodiments thereof in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments thereof.

[0041] Figure 1 This is a schematic diagram of the structure of a trench power semiconductor device with an enclosed source region shown in an embodiment of this application;

[0042] Figure 2 This is a schematic diagram of the interdigitated bar structure shown in the embodiments of this application;

[0043] Figure 3 This is another structural schematic diagram of a trench power semiconductor device with an enclosed source region shown in an embodiment of this application;

[0044] Figure 4 This is a schematic flowchart illustrating the fabrication method of a trench-type power semiconductor device with an enclosed source region according to an embodiment of this application;

[0045] Figure 5 This is another schematic flowchart illustrating the fabrication method of a trench-type power semiconductor device with an enclosed source region as shown in the embodiments of this application. Detailed Implementation

[0046] Preferred embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0047] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0048] It should be understood that although the terms "first," "second," "third," etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0049] Example 1

[0050] In related technologies, the source region structure typically employs an interdigitated bar structure, where P-type and N-type source regions are arranged parallel to each other on the substrate region, with the P-type and N-type source regions equally sharing the interface area between the source region and the substrate region. This source region structure limits the area available for receiving avalanche current, thus restricting the transistor's maximum avalanche tolerance.

[0051] To address the aforementioned issues, this application provides a trench-type power semiconductor device with an enclosed source region, which can expand the interface of the avalanche current channel, reduce the avalanche current density, and thereby improve the maximum avalanche tolerance.

[0052] The technical solutions of the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0053] Figure 1 This is a schematic diagram of the structure of a trench power semiconductor device with an enclosed source region, as shown in an embodiment of this application.

[0054] Figure 2 This is a schematic diagram of the interdigitated bar structure shown in the embodiments of this application.

[0055] See Figure 1 The trench power semiconductor device having an enclosed source region includes:

[0056] Substrate region 1, drift region 2, substrate region 3, source region 4, shielding gate 5, control gate 6, insulating layer 7, source, drain 8, and metal gate;

[0057] The drift region 2 is connected to the substrate region 1, with the direction from the substrate region to the drift region as the top. The substrate region 3 and the source region 4 are sequentially disposed above the drift region 2. The control gate 6 and the shielding gate 5 are sequentially disposed from top to bottom on the side of the drift region 2, and are connected to the drift region 2, the substrate region 3 and the source region 4 respectively through the insulating layer 7.

[0058] The source region 4 includes a P-type source region 41 and an N-type source region 42; the P-type source region 41 is disposed above the substrate region 3, and the N-type source region 42 is disposed at the junction of the side of the P-type source region 41 and the insulating layer 7, with one side of the N-type source region 42 in contact with the insulating layer 7, such that the N-type source region 42 is partially surrounded by the P-type source region 41.

[0059] See Figure 2 In existing source region structures, P-type source region 41 and N-type source region 42 adopt an interdigitated strip structure, that is, P-type source region 41 and N-type source region 42 are arranged in parallel on the substrate region 3. However, in this embodiment, P-type source region 41 no longer adopts the long strip structure in the traditional source region structure, but is set as a rectangular structure with a concave part, and the concave part faces the control gate 6. N-type source region 42 is set in the concave part, so that one side of N-type source region 42 is in contact with the insulating layer 7, and the other side is in contact with P-type source region 41, forming a source region structure in which N-type source region 42 is semi-enclosed by P-type source region 41.

[0060] In this embodiment of the application, preferably, the width ratio and length ratio of the P-type source region 41 and the N-type source region 42 are both 2:1; see also Figure 1 The width ratio of the P-type source region 41 to the N-type source region 42 is 2:1, which is a:b = 2:1 in the figure; the length ratio of the P-type source region 41 to the N-type source region 42 is 2:1, which is c:d = 2:1 in the figure.

[0061] It should be noted that the above description of the width ratio and length ratio of the P-type source region 41 and the N-type source region 42 is only an example given in the embodiments of this application, and is not intended to be the only limitation of this application. In actual application, the width ratio and length ratio can be adjusted according to the actual situation.

[0062] The source electrode is disposed above the source region 4; the drain electrode 8 is disposed below the substrate region 1; and the metal gate electrode is disposed above the control gate 6.

[0063] In this embodiment, the doping concentration of both the P-type source region 41 and the N-type source region 42 is a heavy doping concentration;

[0064] The substrate region 1 is doped with N-type doping, and the doping concentration of the substrate region 1 is a heavily doped concentration.

[0065] The drift region 2 is N-type doped, and the doping concentration of the drift region 2 is light doping concentration;

[0066] The substrate region 3 is p-type doped, and the doping concentration of the substrate region 3 is medium.

[0067] Both the shielding gate 5 and the control gate 6 are P-type doped; both the shielding gate 5 and the control gate 6 are heavily doped.

[0068] It should be noted that, in practical applications, the doping type of the shielding gate 5 and the control gate 6 can also be N-type doping.

[0069] In this embodiment, the light doping concentration ranges from 1×10⁻⁶. 15 cm -3 Up to 5×10 16 cm -3 The doping concentration ranges from 1×10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 The range of heavily doped concentration is 1×10. 19 cm -3 Up to 5×10 20 cm -3 .

[0070] This application provides a trench-type power semiconductor device with an enclosed source region. The source region includes a P-type source region and an N-type source region. Unlike existing source region structures, this device has the P-type and N-type source regions arranged parallel to each other on the substrate region, with the P-type and N-type source regions sharing the interface area between the source region and the substrate region in an interdigitated strip structure. In this application, the P-type source region semi-encloses the N-type source region, forming an enclosed source region structure. This expands the interface of the avalanche current channel, dispersing the avalanche current flow to the expanded PN junction surface. This reduces the avalanche current density when the device is forward-blocking or forward-conducting, effectively improving the direction of avalanche current flow when the power semiconductor device is in blocking or conducting states. Therefore, under the condition of a fixed total avalanche current, it reduces the voltage drop through the P-type source region, i.e., reduces the parallel resistance of the source region PN junction, suppresses the turn-on of parasitic transistors, and thus improves the maximum avalanche tolerance and the reliability of the power semiconductor device.

[0071] Example 2

[0072] Based on the trench power semiconductor device with an enclosed source region shown in Embodiment 1 above, this application provides another trench power semiconductor device with an enclosed source region, in which part of the substrate region is replaced by a drift region, so that a portion of the avalanche current can also flow directly from the drift region to the P-type source region.

[0073] The technical solutions of the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0074] Figure 3 This is another structural schematic diagram of a trench power semiconductor device with an enclosed source region shown in an embodiment of this application.

[0075] See Figure 3 The trench power semiconductor device having an enclosed source region includes:

[0076] Substrate region 1, drift region 2, substrate region 3, source region 4, shielding gate 5, control gate 6, insulating layer 7, source, drain 8, and metal gate;

[0077] The drift region 2 is connected to the substrate region 1, with the direction from the substrate region to the drift region as the top. The substrate region 3 and the source region 4 are sequentially disposed above the drift region 2. The control gate 6 and the shielding gate 5 are sequentially disposed from top to bottom on the side of the drift region 2, and are connected to the drift region 2, the substrate region 3 and the source region 4 respectively through the insulating layer 7.

[0078] The source region 4 includes a P-type source region 41 and an N-type source region 42; the P-type source region 41 is disposed above the substrate region 3, and the N-type source region 42 is disposed at the junction of the side of the P-type source region 41 and the insulating layer 7, with one side of the N-type source region 42 in contact with the insulating layer 7, such that the N-type source region 42 is partially surrounded by the P-type source region 41.

[0079] The drift region 2 has a first top surface 21, a second top surface 22, and a third top surface 23; wherein the distances between the first top surface 21, the second top surface 22, and the third top surface 23 and the substrate region 1 gradually increase;

[0080] The first top surface 21 is connected to the bottom surface of the shielding grid 5 through the insulating layer 7; the second top surface 22 is connected to the bottom of the substrate region 3; the third top surface 23 is flush with the top surface of the source region 4, so that the substrate region 3 and the source region 4 are both located in the recess formed by the second top surface 22 and the third top surface 23 in the drift region 2.

[0081] In traditional trench power semiconductor devices, the widths of the source region and the substrate region are the same as the width of the trench power semiconductor device. However, in the embodiments of this application, the widths of the source region 4 and the substrate region 3 are both smaller than the width of the trench power semiconductor device. That is, the source region 4 and the substrate region 3 only cover part of the drift region 2, so that part of the drift region 2 at the top of the trench power semiconductor device is directly connected to the P-type source region 41.

[0082] Preferably, the area ratio of the second top surface 22 to the third top surface 23 is 1:1, that is, in this scheme, the width of the source region 4 and the substrate region 3 is half the width of the trench power semiconductor device.

[0083] It should be noted that the above description of the area ratio of the second top surface 22 to the third top surface 23 is only an example given in the embodiments of this application and does not constitute the only limitation of this application.

[0084] This application provides a trench power semiconductor device with an enclosed source region. In its source region structure, the P-type source region semi-encloses the N-type source region. By dispersing the avalanche current flow through the junction of the expanded P-type and N-type source regions, the parallel resistance of the PN junction is reduced. By suppressing the turn-on of parasitic transistors, the avalanche tolerance is improved. By replacing part of the substrate region with a drift region, the total avalanche current is further diverted directly from the drift region to the P-type source region through shunting. By reducing the on-state voltage drop of the PN junction, it is more difficult for parasitic transistors to turn on, fundamentally improving the maximum avalanche tolerance of the device.

[0085] Example 3

[0086] Corresponding to the aforementioned trench-type power semiconductor device structure embodiments, this application also provides a method for fabricating a trench-type power semiconductor device with an enclosed source region and corresponding embodiments.

[0087] Figure 4 This is a schematic flowchart illustrating the fabrication method of a trench-type power semiconductor device with an enclosed source region, as shown in the embodiments of this application.

[0088] See Figure 4 The method for fabricating the trench-type power semiconductor device with an enclosed source region includes:

[0089] 301. Fabricating the substrate region using semiconductor materials;

[0090] In the embodiments of this application, the substrate region is prepared using N-type heavily doped semiconductor material, that is, the doping type of the substrate region is N-type doping, and the doping concentration of the substrate region is the heavy doping concentration.

[0091] 302. A drift region is epitaxially formed on the substrate region;

[0092] In the embodiments of this application, different epitaxial processes can be used according to actual needs, including but not limited to: vapor phase epitaxy (VPE) or chemical vapor deposition (CVD).

[0093] 303. A matrix region is formed on the drift region by ion implantation or diffusion;

[0094] Ion implantation is a process of doping silicon materials. In practical applications, the power device is placed at one end of the ion implanter, and the dopant ion source is placed at the other end. At the dopant ion source, the dopant atoms are ionized, thus acquiring a certain charge. They are then accelerated to ultra-high speed by an electric field, penetrating the product surface and using their momentum to implant the dopant atoms into the power device, forming a doped region.

[0095] Diffusion is a process of incorporating pure impurity atoms into the surface of silicon materials. In practical applications, diborane or phosphine are usually used as ion sources, and pure impurity atoms are incorporated into the surface of silicon materials through intermittent diffusion or substitutional diffusion.

[0096] It should be noted that the embodiments of this application do not have strict limitations on the preparation method of the substrate region. In actual process, different processes described above can be selected to complete the preparation of the substrate region according to actual needs.

[0097] 304. Etch a groove on one side of the drift zone;

[0098] In this embodiment, a trench is etched on one side of the drift region using photolithography, and the residual photoresist is removed by wet etching or dry etching.

[0099] 305. Oxide, polysilicon, oxide, and polysilicon are sequentially deposited in the trench to form an insulating layer, a shielding gate, and a control gate;

[0100] In the embodiments of this application, the polycrystalline silicon is P-type or N-type heavily doped polycrystalline silicon.

[0101] 306. An N-type source region is formed by local doping at the location where the insulating layer is attached to the substrate region, and a P-type source region is formed by doping around the N-type source region, such that the N-type source region is partially surrounded by the P-type source region;

[0102] In the embodiments of this application, N-type source regions and P-type source regions are prepared on the substrate region using N-type heavily doped semiconductor materials and P-type heavily doped semiconductor materials, respectively.

[0103] 307. Fabricate a source electrode above the P-type source region and the N-type source region;

[0104] 308. A metal gate is formed above the trench;

[0105] 309. A drain electrode is formed at the bottom of the substrate region.

[0106] This application provides a method for fabricating a trench-type power semiconductor device with an enclosed source region. An N-type source region is formed by local doping at the location where an insulating layer is attached to the substrate region, and a P-type source region is formed by doping around the N-type source region. This results in the N-type source region being partially enclosed by the P-type source region, thereby expanding the interface of the avalanche current channel. This disperses the avalanche current flow to the expanded PN junction surface, reducing the avalanche current density when the device is forward-blocking or forward-conducting. This effectively improves the direction of avalanche current flow when the power semiconductor device is in blocking or conducting states. Thus, under the condition of a fixed total avalanche current, the voltage drop through the P-type source region is reduced, i.e., the parallel resistance of the source region PN junction is reduced, suppressing the turn-on of parasitic transistors, thereby increasing the maximum avalanche tolerance and improving the reliability of the power semiconductor device.

[0107] Example 4

[0108] Corresponding to the aforementioned Embodiment 2, this application also provides a method for fabricating a trench-type power semiconductor device with an enclosed source region and corresponding embodiments.

[0109] Figure 5 This is another schematic flowchart illustrating a method for fabricating a trench-type power semiconductor device with an enclosed source region, as shown in an embodiment of this application.

[0110] See Figure 5 The method for fabricating the trench-type power semiconductor device with an enclosed source region includes:

[0111] 401. Fabricating the substrate region using semiconductor materials;

[0112] In this embodiment, step 401 is the same as step 301 in the above embodiment 3, and will not be repeated here.

[0113] 402. A drift region is epitaxially formed on the substrate region;

[0114] In this embodiment, step 402 is the same as step 302 in the above embodiment 3, and will not be repeated here.

[0115] 403. The substrate region is formed by local doping in the first region of the drift region by ion implantation or diffusion.

[0116] In this embodiment, the width of the first region is smaller than the width of the drift region.

[0117] 404. On the second region of the drift region, a third top surface of the drift region is formed by doping with the same semiconductor material as the drift region;

[0118] In this embodiment, the long side of the second region is aligned and connected to the long side of the first region, so that the first region and the second region together cover a wide side of the drift area. Preferably, the size ratio of the first region to the second region is 1:1.

[0119] In this embodiment of the application, steps 403 and 404 can also be replaced by the following steps:

[0120] The drift region is etched to form the second top surface of the drift region;

[0121] The substrate region is formed on the second top surface by ion implantation or diffusion.

[0122] 405. An N-type source region is formed by local doping at the location where the insulating layer is attached to the substrate region, and a P-type source region is formed by doping around the N-type source region, so that the N-type source region is partially surrounded by the P-type source region;

[0123] 406. Etch a groove on one side of the drift zone;

[0124] In this embodiment, step 406 is the same as step 304 in the above embodiment 3, and will not be repeated here.

[0125] 407. Oxide, polysilicon, oxide, and polysilicon are sequentially deposited in the trench to form an insulating layer, a shielding gate, and a control gate;

[0126] In this embodiment, step 407 is the same as step 305 in the above embodiment 3, and will not be repeated here.

[0127] 408. Fabricate a source electrode above the P-type source region and the N-type source region;

[0128] 409. A metal gate is formed above the trench;

[0129] 410. A drain electrode is formed at the bottom of the substrate region.

[0130] In this embodiment, steps 408 to 410 are the same as steps 307 to 309 in the above embodiment 3, and will not be repeated here.

[0131] This application provides a method for fabricating a trench-type power semiconductor device with an enclosed source region. An N-type source region is formed by local doping at the location where an insulating layer is attached to the substrate region, and a P-type source region is formed by doping around the N-type source region. This results in the N-type source region being partially surrounded by the P-type source region, thereby expanding the interface of the avalanche current channel. This reduces the avalanche current density when the device is forward blocked or forward conducted, improving the flow direction of the avalanche current when the power semiconductor device is in the blocking or conducting state. Thus, under the condition of a fixed total avalanche current, the voltage drop through the P-type source region is reduced, that is, the parallel resistance of the PN junction in the source region is reduced, the turn-on of the parasitic transistor is suppressed, and the maximum avalanche tolerance is improved.

[0132] In addition, by replacing part of the substrate region with the drift region, the total avalanche current is directly diverted from the drift region to the P-type source region through shunting. By reducing the on-state voltage drop of the PN junction, the parasitic transistor becomes more difficult to turn on, fundamentally improving the maximum avalanche tolerance of the device.

[0133] The solution of this application has been described in detail above with reference to the accompanying drawings. In the above embodiments, the descriptions of each embodiment have different emphases; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Those skilled in the art should also understand that the actions and modules involved in the specification are not necessarily essential to this application. Furthermore, it is understood that the steps in the method of this application embodiment can be adjusted, combined, and deleted according to actual needs, and the modules in the device of this application embodiment can be combined, divided, and deleted according to actual needs.

[0134] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0135] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A trench-type power semiconductor device having an enclosed source region, characterized in that, include: Substrate region (1), drift region (2), substrate region (3), source region (4), shielding gate (5), control gate (6), insulating layer (7), source, drain (8), and metal gate; The drift region (2) is connected to the substrate region (1), with the direction from the substrate region to the drift region as the top. The substrate region (3) and the source region (4) are sequentially disposed above the drift region (2). The control gate (6) and the shielding gate (5) are sequentially disposed from top to bottom on the side of the drift region (2), and are connected to the drift region (2), the substrate region (3) and the source region (4) respectively through the insulating layer (7). The source region (4) includes a P-type source region (41) and an N-type source region (42); the P-type source region (41) is disposed above the substrate region (3), and the N-type source region (42) is disposed at the junction of the side of the P-type source region (41) and the insulating layer (7). One side of the N-type source region (42) is connected to the insulating layer (7), so that the N-type source region (42) is partially surrounded by the P-type source region (41). The source electrode is disposed above the source region (4); the drain electrode (8) is disposed below the substrate region (1); and the metal gate electrode is disposed above the control gate (6). The widths of the source region and the substrate region are both smaller than the width of the trench power semiconductor device, and the top of the trench power semiconductor device has a portion of the drift region that is directly connected to the P-type source region.

2. The trench power semiconductor device with an enclosed source region according to claim 1, characterized in that, The drift region (2) has a first top surface (21), a second top surface (22) and a third top surface (23); wherein the distance between the first top surface (21), the second top surface (22) and the third top surface (23) and the substrate region (1) gradually increases; The first top surface (21) is connected to the bottom surface of the shielding grid (5) through the insulating layer (7); the second top surface (22) is connected to the bottom of the substrate region (3); the third top surface (23) is flush with the top surface of the source region (4), such that the substrate region (3) and the source region (4) are both located in the recess formed by the second top surface (22) and the third top surface (23) in the drift region (2).

3. The trench power semiconductor device with an enclosed source region according to claim 1, characterized in that, The width ratio and length ratio of the P-type source region (41) and the N-type source region (42) are both 2:

1.

4. The trench power semiconductor device with an enclosed source region according to claim 2, characterized in that, The area ratio of the second top surface (22) to the third top surface (23) is 1:

1.

5. The trench power semiconductor device with an enclosed source region according to claim 1, characterized in that, The doping concentrations of both the P-type source region (41) and the N-type source region (42) are heavy doping concentrations.

6. The trench power semiconductor device with an enclosed source region according to claim 5, characterized in that, The substrate region (1) is N-type doped, and the doping concentration of the substrate region (1) is a heavily doped concentration. The drift region (2) is N-type doped, and the doping concentration of the drift region (2) is light doping concentration; The substrate region (3) is P-type doped, and the doping concentration of the substrate region (3) is medium. The shielding gate (5) and the control gate (6) are both P-type doped; the doping concentrations of the shielding gate (5) and the control gate (6) are both heavily doped.

7. A method for fabricating a trench-type power semiconductor device with an enclosed source region, characterized in that, For fabricating a trench-type power semiconductor device with an enclosed source region as described in any one of claims 1-6, comprising: The substrate region is fabricated using semiconductor materials; A drift region is epitaxially formed on the substrate region; A matrix region is formed on the drift region by ion implantation or diffusion. A groove is etched on one side of the drift region; Oxide, polysilicon, oxide, and polysilicon are sequentially deposited in the trench to form an insulating layer, a shielding gate, and a control gate; An N-type source region is formed by local doping at the location where the insulating layer is attached to the substrate region, and a P-type source region is formed by doping around the N-type source region, such that the N-type source region is partially surrounded by the P-type source region. A source electrode is fabricated above the P-type source region and the N-type source region; A metal gate is formed above the trench; A drain electrode is fabricated at the bottom of the substrate region.

8. The method for fabricating a trench-type power semiconductor device with an enclosed source region according to claim 7, characterized in that, The formation of the matrix region on the drift region by ion implantation or diffusion includes: The substrate region is formed by local doping in the first region of the drift region using ion implantation or diffusion; the third top surface of the drift region is formed by doping in the second region of the drift region using the same semiconductor material as the drift region.

9. The method for fabricating a trench-type power semiconductor device with an enclosed source region according to claim 7, characterized in that, After the drift region is epitaxially formed on the substrate region, the process includes: The drift region is etched to form the second top surface of the drift region; The formation of the matrix region on the drift region by ion implantation or diffusion includes: The substrate region is formed on the second top surface by ion implantation or diffusion.

10. The method for fabricating a trench-type power semiconductor device with an enclosed source region according to claim 7, characterized in that, In the process of sequentially depositing oxide, polysilicon, oxide, and polysilicon in the trench to form an insulating layer, a shielding gate, and a control gate, the polysilicon is heavily doped polysilicon.

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