Vertical power metal oxide semiconductor field effect transistor and preparation method thereof

Abstract

The present invention relates to a vertical power metal oxide semiconductor field effect transistor and a preparation method thereof. The vertical power metal oxide semiconductor field effect transistor comprises a unit cell array composed of at least one first unit cell and at least one second unit cell, wherein the first unit cell and the second unit cell both comprise: a heavily doped substrate, an epitaxial layer, a first well region, a source region, a gate oxide layer, a polysilicon layer, an insulating layer, a source metal layer, and a drain metal layer, and the second unit cell is also provided with a second well region of a second conductivity type, the second well region being arranged in the epitaxial layer and being attached to the gate oxide layer. The vertical power metal oxide semiconductor field effect transistor can reduce electromagnetic radiation and electromagnetic conduction without affecting the performance such as switching speed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, in particular to a vertical power metal oxide semiconductor field effect transistor and a preparation method thereof. Background Art

[0002] A vertical power metal oxide semiconductor field effect transistor (VDMOSFET) is a field effect transistor that can be widely used in analog circuits and digital circuits. In order to reduce the conduction loss and switching loss of the vertical power metal oxide semiconductor field effect transistor and increase the switching speed, the size of the vertical power metal oxide semiconductor field effect transistor is generally reduced. However, when improving the above performance, the source-drain oscillation and gate-source oscillation of the vertical power metal oxide semiconductor field effect transistor will be caused, which will lead to excessive electromagnetic conduction and electromagnetic radiation of the vertical power metal oxide semiconductor field effect transistor. It is difficult to solve the contradictory relationship between the high switching speed and low electromagnetic conduction and electromagnetic radiation of the vertical power metal oxide semiconductor field effect transistor. Summary of the invention

[0003] Based on this, it is necessary to provide a vertical power metal oxide semiconductor field effect transistor and a preparation method thereof to address the above problems. The vertical power metal oxide semiconductor field effect transistor can reduce electromagnetic radiation and electromagnetic conduction without affecting the switching speed.

[0004] The present invention provides a vertical power metal oxide semiconductor field effect transistor, comprising a unit cell array consisting of at least one first unit cell and at least one second unit cell, wherein the first unit cell and the second unit cell both comprise:

[0005] A heavily doped substrate having a first conductivity type;

[0006] an epitaxial layer, the epitaxial layer covering the surface of the heavily doped substrate and having a first conductivity type;

[0007] a first well region, the first well region being disposed in the epitaxial layer and having a second conductivity type, the second conductivity type being different from the first conductivity type;

[0008] a source region, the source region being disposed in the first well region and having a first conductivity type;

[0009] A gate oxide layer, the gate oxide layer covers the epitaxial layer away from the heavily doped substrate surface and extends from one source region to another adjacent source region;

[0010] A polysilicon layer, the polysilicon layer covering a surface of the gate oxide layer away from the epitaxial layer;

[0011] an insulating layer, the insulating layer covering the polysilicon layer and a portion of the surface of the source region away from the epitaxial layer, the insulating layer being provided with a contact hole penetrating to the epitaxial layer;

[0012] a source metal layer, the source metal layer covering the first well region, the insulating layer and a surface of the source region away from the epitaxial layer, the source metal layer being connected to the epitaxial layer through a contact hole; and

[0013] A drain metal layer is disposed on a surface of the heavily doped substrate away from the epitaxial layer;

[0014] A second well region of a second conductivity type is also provided in the second unit cell. The second well region is provided in the epitaxial layer and adheres to the gate oxide layer.

[0015] In one embodiment, a well depth of the second well region is equal to a well depth of the first well region.

[0016] In one embodiment, a central axis of the second well region coincides with a central axis of the gate oxide layer.

[0017] In one embodiment, the width of the first unit cell is X1, the width of the second unit cell is X2, and X1:X2 is 1:1.95-1:2.05.

[0018] In one embodiment, the X1 is 4 μm-20 μm.

[0019] In one embodiment, the second unit cell comprises two or more adjacently arranged units;

[0020] And / or, comprising two or more second unit cells arranged at intervals.

[0021] In one embodiment, among the plurality of second unit cells arranged at intervals, the same number of the first unit cells are arranged between every two adjacent second unit cells;

[0022] And / or, different numbers of the first single cells are arranged between every two adjacent second single cells.

[0023] In one embodiment, the same number of the first single cells are disposed between every two adjacent second single cells, and the number of the first single cells is 1 or 2.

[0024] A method for preparing the vertical power metal oxide semiconductor field effect transistor as described above, characterized in that it comprises the following steps:

[0025] providing a heavily doped substrate;

[0026] forming an epitaxial layer on a surface of the heavily doped substrate;

[0027] forming a second well region having a second conductivity type in the epitaxial layer;

[0028] Sequentially forming a gate oxide layer and a polysilicon layer on a surface of the epitaxial layer away from the heavily doped substrate, etching the gate oxide layer and the polysilicon layer to form gate region patterns of a first unit cell and a second unit cell in a unit cell array, wherein the gate oxide layer of the second unit cell is aligned with the second well region;

[0029] forming a first well region on a surface of the epitaxial layer not covered by the gate region pattern;

[0030] forming a source region in the first well region;

[0031] forming an insulating layer on the surface of the polysilicon layer and a portion of the source region away from the epitaxial layer, and providing a contact hole penetrating to the epitaxial layer on the insulating layer;

[0032] forming a source metal layer in the contact hole and on the surface of the first well region, the insulating layer and the source region away from the epitaxial layer; and

[0033] A drain metal layer is formed on a surface of the heavily doped substrate away from the epitaxial layer.

[0034] Another method for preparing the vertical power metal oxide semiconductor field effect transistor as described above comprises the following steps:

[0035] providing a heavily doped substrate;

[0036] forming an epitaxial layer on a surface of the heavily doped substrate;

[0037] forming a second well region and a first well region having a second conductivity type in the epitaxial layer;

[0038] forming a source region in the first well region;

[0039] Sequentially forming a gate oxide layer and a polysilicon layer on a surface of the epitaxial layer away from the heavily doped substrate, etching the gate oxide layer and the polysilicon layer to form gate region patterns of a first unit cell and a second unit cell in a unit cell array, wherein the gate oxide layer of the second unit cell is aligned with the second well region;

[0040] forming an insulating layer on the surface of the polysilicon layer and a portion of the source region away from the epitaxial layer, and providing a contact hole penetrating to the epitaxial layer on the insulating layer;

[0041] forming a source metal layer in the contact hole and on the surface of the first well region, the insulating layer and the source region away from the epitaxial layer; and

[0042] A drain metal layer is formed on a surface of the heavily doped substrate away from the epitaxial layer.

[0043] In the vertical power metal oxide semiconductor field effect transistor of the present invention, the second unit cell includes a second well region. Since the second well region does not affect the size of the vertical power metal oxide semiconductor field effect transistor, the switching speed and other performance of the vertical power metal oxide semiconductor field effect transistor are not affected during the switching process of the vertical power metal oxide semiconductor field effect transistor. At the same time, the second well region forms a parasitic capacitor, which cooperates with the gate-drain capacitor (Cgd) and the gate-source capacitor (Cgs) in the unit cell to reduce source-drain oscillation and gate-source oscillation, thereby reducing electromagnetic conduction and electromagnetic radiation. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic structural diagram of a vertical power metal oxide semiconductor field effect transistor according to an embodiment of the present invention;

[0045] Figure 2-Figure 9 A schematic diagram of the steps of the method for preparing the vertical power metal oxide semiconductor field effect transistor provided by the present invention.

[0046] In the figure, 10, the first unit cell; 101, the heavily doped substrate; 102, the epitaxial layer; 103, the first well region; 103a, the deep junction; 103b, the channel region; 104, the source region; 105, the gate oxide layer; 106, the polysilicon layer; 107, the insulating layer; 108, the source metal layer; 109, the drain metal layer; 20, the second unit cell; 201, the second well region. DETAILED DESCRIPTION

[0047] In order to facilitate the understanding of the present invention, the vertical power metal oxide semiconductor field effect transistor and its preparation method provided by the present invention will be described more comprehensively with reference to the relevant embodiments below. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0048] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0050] like Figure 1 As shown, a vertical power metal oxide semiconductor field effect transistor according to an embodiment of the present invention includes a unit cell array consisting of at least one first unit cell 10 and at least one second unit cell 20. The first unit cell 10 and the second unit cell 20 both include: a heavily doped substrate 101, an epitaxial layer 102, a first well region 103, a source region 104, a gate oxide layer 105, a polysilicon layer 106, an insulating layer 107, a source metal layer 108 and a drain metal layer 109.

[0051] Among them, the heavily doped substrate 101 has a first conductivity type, and the heavily doped substrate 101 can be formed based on a silicon substrate, and the silicon substrate can be grown by a CZ single crystal method. For example, an N-type heavily doped silicon substrate can be obtained by heavily doping the silicon substrate with N-type; a P-type heavily doped silicon substrate can be obtained by heavily doping the silicon substrate with P-type. The doping degree of the heavily doped substrate 101 can be determined as needed, for example, the resistivity of the heavily doped substrate 101 can be between 0.5 mΩ×cm and 5 mΩ×cm.

[0052] The epitaxial layer 102 is covered on the surface of the heavily doped substrate 101 and has a first conductivity type, for example, an N-type epitaxial layer 102, a P-type epitaxial layer 102, and the epitaxial layer 102 can cover the entire surface area of ​​the heavily doped substrate 101. The thickness and doping concentration of the epitaxial layer 102 can be determined according to the withstand voltage requirements of the vertical power metal oxide semiconductor field effect transistor. The thickness of the epitaxial layer 102 can range from 2μm to 150μm.

[0053] The first well region 103 is arranged in the epitaxial layer 102 and has a second conductivity type, which is different from the first conductivity type. Specifically, the second conductivity type can be P type or N type; when the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, the second conductivity type is N type.

[0054] It should be noted that, in this embodiment, the first well region 103 is composed of a deep junction 103 a and a channel region 103 b , and the well depth of the first well region 103 is equal to the sum of the depth of the deep junction 103 a and the depth of the channel region 103 b .

[0055] The source region 104 is disposed in the first well region 103 and has the first conductivity type. The source region 104 may be disposed in the channel region 103 b and has the heavily doped first conductivity type.

[0056] The gate oxide layer 105 is covered on the epitaxial layer 102 away from the surface of the heavily doped substrate 101 , and extends from one source region 104 to another adjacent source region 104 . It can be understood that the gate oxide layer 105 is in contact with the source region 104 .

[0057] The polysilicon layer 106 is covered on the surface of the gate oxide layer 105 away from the epitaxial layer 102 . The polysilicon layer 106 is gate polysilicon.

[0058] The insulating layer 107 covers the polysilicon layer 106 and part of the source region 104 away from the surface of the epitaxial layer 102. The insulating layer 107 is provided with a contact hole penetrating to the epitaxial layer 102. It can be understood that the contact hole plays a connecting role, specifically connecting the source metal layer 108 with the first well region 103, the source region 104, etc.

[0059] The source metal layer 108 covers the surface of the first well region 103, the insulating layer 107 and the source region 104 away from the epitaxial layer 102. The source metal layer 108 is connected to the epitaxial layer 102, the first well region 103, the source region 104 and the insulating layer 107 through contact holes. The function of the source metal layer 108 is to lead out the source to form a source metal electrode.

[0060] The drain metal layer 109 is covered on the surface of the heavily doped substrate 101 away from the epitaxial layer 102. The function of the drain metal layer 109 is to lead out the drain to form a drain electrode, which is convenient for wire bonding and welding processes.

[0061] In particular, the second unit cell 20 of the present invention is also provided with a second well region 201 with a second conductivity type. The second well region 201 is arranged in the epitaxial layer 102 and is attached to the gate oxide layer 105. The second well region 201 forms a parasitic capacitor. The parasitic capacitor cooperates with the gate-drain capacitor and the gate-source capacitor in the unit cell to avoid gate-drain oscillation and gate-source oscillation, thereby reducing electromagnetic conduction and electromagnetic radiation.

[0062] It can be understood that the well depth of the second well region 201 is less than or equal to the thickness of the epitaxial layer 102 . In one embodiment, the thickness of the epitaxial layer 102 is 2 μm-150 μm.

[0063] In the second unit cell 20 , since each of the first unit cell 10 and the second unit cell 20 needs to withstand a withstand voltage, in order to maintain the overall withstand voltage consistency and simplify the preparation process, in one embodiment, the well depth of the second well region 201 is equal to the well depth of the first well region 103 .

[0064] In one embodiment, the depth of the first well region 103 is 2 μm-150 μm, and correspondingly, the depth of the second well region 201 is 2 μm-150 μm.

[0065] In order to better optimize the capacitance and improve the oscillation characteristics, in one embodiment, the central axis of the second well region 201 coincides with the central axis of the gate oxide layer 105 .

[0066] The present invention does not further limit the shape of the second well region 201. In one embodiment, the shape of the second well region 201 is columnar or stripe.

[0067] In the vertical power metal oxide semiconductor field effect transistor of the present invention, the width of the first unit cell 10 is X1, the width of the second unit cell 20 is X2, X1:X2 is 1:1.95-1:2.05, in order to make each first unit cell 10 and the second unit cell 20 have the same withstand voltage, preferably, X1:X2 is 1:2. In one embodiment, X1 is 4μm-20μm.

[0068] In one embodiment, the vertical power MOSFET of the present invention includes two or more second unit cells 20 disposed adjacent to each other, and / or includes two or more second unit cells 20 disposed at intervals.

[0069] It can be understood that when the number of the second single cells 20 is 2, the first single cell 10 may not be set between the two second single cells 20, or more than two first single cells 10 may be set. When the number of the second single cells 20 is 3, 4, 5 or more, there are three distribution situations of the second single cells 20 in the vertical power metal oxide semiconductor field effect transistor, namely: in the first situation, all the second single cells 20 in the vertical power metal oxide semiconductor field effect transistor are adjacently arranged; in the second situation, some of the second single cells 20 in the vertical power metal oxide semiconductor field effect transistor are adjacently arranged, and some of the second single cells 20 are spaced apart; in the third situation, all the second single cells 20 in the vertical power metal oxide semiconductor field effect transistor are spaced apart.

[0070] Furthermore, when the number of second single cells 20 is 3, 4, 5 or the like, among the multiple second single cells 20 arranged at intervals, the same number of first single cells 10 are arranged between every two adjacent second single cells 20, and / or different numbers of first single cells 10 are arranged between every two adjacent second single cells 20.

[0071] At this time, there are various distribution situations of the second unit cells 20 in the vertical power MOSFET, for example:

[0072] Case 1: some of the second unit cells 20 in the vertical power metal oxide semiconductor field effect transistor are arranged adjacent to each other, and some of the second unit cells 20 are arranged at intervals. When arranged at intervals, the same number of first unit cells 10 are arranged between every two adjacent second unit cells 20;

[0073] Case 2: some of the second unit cells 20 in the vertical power metal oxide semiconductor field effect transistor are arranged adjacent to each other, and some of the second unit cells 20 are arranged at intervals. When arranged at intervals, different numbers of first unit cells 10 are arranged between every two adjacent second unit cells 20.

[0074] Case 3: In the vertical power metal oxide semiconductor field effect transistor, some second unit cells 20 are arranged adjacent to each other, and some second unit cells 20 are arranged at intervals. When the intervals are arranged, the number of first unit cells 10 arranged between every two adjacent second unit cells 20 may be the same or different;

[0075] Case 4: All second unit cells 20 in the vertical power metal oxide semiconductor field effect transistor are arranged at intervals, and the same number of first unit cells 10 are arranged between every two adjacent second unit cells 20;

[0076] Case 5: All second unit cells 20 in the vertical power metal oxide semiconductor field effect transistor are arranged at intervals, and different numbers of first unit cells 10 are arranged between every two adjacent second unit cells 20;

[0077] Case 6: All the second unit cells 20 in the vertical power metal oxide semiconductor field effect transistor are arranged at intervals, and the number of the first unit cells 10 arranged between every two adjacent second unit cells 20 may be the same or different.

[0078] It can be understood that in the above-mentioned situations three and six, the number of first single cells 10 arranged between every two adjacent second single cells 20 can be regular or irregular. For example, when the vertical power metal oxide semiconductor field effect transistor includes 5 second single cells 20, 2, 3, 2, and 3 first single cells 10 can be arranged in sequence between every two adjacent second single cells 20; 2, 3, 3, and 2 first single cells 10 can also be arranged in sequence; 2, 3, 4, and 2 first single cells 10 can also be arranged in sequence.

[0079] When the second single cells 20 are arranged at intervals, compared with when different numbers of first single cells 10 are arranged between every two adjacent second single cells 20, when the same number of first single cells 10 are arranged between every two adjacent second single cells 20, it can be ensured that the on-resistance of the vertical power metal oxide semiconductor field effect transistor is smaller and the flow resistance is larger. Therefore, in order to ensure that the vertical power metal oxide semiconductor field effect transistor can improve the oscillation performance of the device under the premise of smaller on-resistance, preferably, the same number of first single cells 10 are arranged between every two adjacent second single cells 20, and the number of first single cells 10 is more than 1, preferably 1 or 2. Further preferably, in the vertical power metal oxide semiconductor field effect transistor of the present invention, the second single cells 20 are arranged at intervals, and the same number of first single cells 10 are arranged between every two adjacent second single cells 20, and the number of first single cells 10 is more than 1, preferably 1 or 2.

[0080] In the vertical power metal oxide semiconductor field effect transistor of the present invention, since the second unit cell 20 does not affect the size of the vertical power metal oxide semiconductor field effect transistor, the switching speed and other performance of the vertical power metal oxide semiconductor field effect transistor are not affected during the switching process of the vertical power metal oxide semiconductor field effect transistor; at the same time, the second well region 201 forms a parasitic capacitor with the gate oxide layer 105 and the epitaxial layer 102, and the parasitic capacitor cooperates with the gate-drain capacitance and the gate-source capacitance in the unit cell to avoid gate-drain oscillation and gate-source oscillation, thereby reducing electromagnetic conduction and electromagnetic radiation.

[0081] The present invention also provides a first method for preparing the vertical power metal oxide semiconductor field effect transistor as described above, comprising the following steps, the schematic diagram of the steps is as follows: Figure 2-Figure 5 , Figure 8-Figure 9 As shown:

[0082] S1, providing a heavily doped substrate 101;

[0083] S2, forming an epitaxial layer 102 on the surface of the heavily doped substrate 101;

[0084] S3, forming a second well region 201 having a second conductivity type in the epitaxial layer 102;

[0085] S4, forming a gate oxide layer 105 and a polysilicon layer 106 in sequence on the surface of the epitaxial layer 102 away from the heavily doped substrate 101, etching the gate oxide layer 105 and the polysilicon layer 106 to form gate region patterns of the first unit cell 10 and the second unit cell 20 in the unit cell array, and the gate oxide layer 105 of the second unit cell 20 is aligned with the second well region 201;

[0086] S5, forming a first well region 103 on the surface of the epitaxial layer 102 not covered by the gate region pattern;

[0087] S6, forming a source region 104 in the first well region 103;

[0088] S7, forming an insulating layer 107 on the surface of the polysilicon layer 106 and a portion of the source region 104 away from the epitaxial layer 102, and providing a contact hole penetrating to the epitaxial layer 102 on the insulating layer 107;

[0089] S8, forming a source metal layer 108 in the contact hole and on the surface of the first well region 103, the insulating layer 107 and the source region 104 away from the epitaxial layer 102; and

[0090] S9 , forming a drain metal layer 109 on a surface of the heavily doped substrate 101 away from the epitaxial layer 102 .

[0091] In step S1 , the heavily doped substrate 101 may be formed based on a silicon substrate. In one embodiment, providing the heavily doped substrate 101 includes: heavily doping the silicon substrate with N-type to obtain the N-type heavily doped substrate 101 ; or heavily doping the silicon substrate with P-type to obtain the P-type heavily doped substrate 101 .

[0092] In step S2 , the epitaxial layer 102 may be formed by an epitaxial growth method such as chemical vapor deposition. During the epitaxial growth, the resistivity of the epitaxial layer 102 may be controlled by controlling the doping dose.

[0093] Step S3 specifically includes the following steps: forming a trench on the surface of the epitaxial layer 102 away from the heavily doped substrate 101, filling the trench by epitaxial growth and doping with impurities of the second conductivity type to form a second well region 201 of the second conductivity type.

[0094] In one embodiment, the step of forming a groove on the surface of the epitaxial layer 102 away from the heavily doped substrate 101 includes: forming a barrier layer on the surface of the epitaxial layer 102 away from the heavily doped substrate 101, disposing a layer of photoresist on the barrier layer, and forming the groove by photolithography and etching.

[0095] It can be understood that when the second conductivity type is P type, in one embodiment, the impurities include at least one of phosphine (PH3) or phosphorus trichloride (PCl3); when the second conductivity type is N type, the impurities include at least one of diborane (B2H6) or boron trichloride (BCl3).

[0096] It should be noted that the doping concentration of the second conductive type impurities depends on the withstand voltage and the turn-on voltage of the vertical power metal oxide semiconductor field effect transistor.

[0097] In step S4 , the material of the gate oxide layer 105 includes silicon dioxide, and the gate oxide layer 105 can be made by thermal oxidation.

[0098] In step S5, the step of forming the first well region 103 includes: injecting impurities of the second conductivity type into the epitaxial layer 102 not covered by the gate region pattern, and forming the first well region 103 consisting of a deep junction 103a and a channel region 103b through annealing.

[0099] Step S6 specifically includes the following steps: defining the shape of the source region 104 by a mask process, then implanting impurities of the first conductivity type, and performing annealing to form the source region 104 .

[0100] In step S7 , the material of the insulating layer 107 includes at least one of silicon dioxide and silicon nitride, and the insulating layer 107 is made by methods such as chemical vapor deposition.

[0101] One or more contact holes may be formed on the insulating layer 107 . In a specific implementation, an oxide layer is deposited on the surface of the insulating layer 107 away from the polysilicon layer 106 , and then photolithography and etching are performed based on a defined contact hole pattern. The remaining oxide layer serves as the insulating layer 107 .

[0102] In step S8 , the source metal layer 108 may be formed by depositing metal. In one embodiment, the metal includes at least one of aluminum, titanium, titanium nitride or tungsten.

[0103] In step S9 , the drain metal layer 109 may be formed by deposition or other methods. In one embodiment, the metal includes at least one of aluminum or copper.

[0104] The present invention also provides a second method for preparing the vertical power metal oxide semiconductor field effect transistor as described above, comprising the following steps, the schematic diagram of the steps is as follows: Figure 2-Figure 3 , Figure 6-Figure 9As shown, it can be understood that the preparation method is different from the first method for preparing a vertical power metal oxide semiconductor field effect transistor in that, while forming the second well region 201, the first well region 103 and the source region 104 are formed, and then the gate oxide layer 105 and the polysilicon layer 106 are formed; or, while forming the second well region 201, the first well region 103 is formed, and then the gate oxide layer 105 and the polysilicon layer 106 are formed, and finally the source region 104 is formed in the first well region 103.

[0105] The present invention is further described in detail below in conjunction with specific examples and comparative examples. It is understood that the instruments and raw materials used in the following examples are relatively specific and may not be limited thereto in other specific examples.

[0106] Example 1

[0107] Embodiment 1 provides a vertical power metal oxide semiconductor field effect transistor, including a strip-shaped parallel-arranged unit cell array consisting of a first unit cell 10 and two second unit cells 20, wherein the first unit cell 10 and the second unit cell 20 each include:

[0108] N+ type heavily doped substrate 101 with a thickness of 725 μm;

[0109] An N-type epitaxial layer 102 with a thickness of 725 μm, the N-type epitaxial layer 102 covers the surface of the N+ heavily doped substrate 101;

[0110] A P-type first well region 103 with a well depth of 45 μm, the P-type first well region 103 is arranged in the N-type epitaxial layer 102, and is composed of a P+ type deep junction 103a with a depth of 45 μm and a P-type channel region 103b with a depth of 1.5 μm;

[0111] An N+ type source region 104 with a thickness of 0.6 μm, the N+ type source region 104 being disposed in the P- type channel region 103 b;

[0112] A gate oxide layer 105 , the gate oxide layer 105 is covered on the N-type epitaxial layer 102 away from the surface of the N+ type heavily doped substrate 101 , and extends from one N+ type source region 104 to another adjacent N+ type source region 104 ;

[0113] A polysilicon layer 106 , the polysilicon layer 106 covers a surface of the gate oxide layer 105 away from the N-type epitaxial layer 102 ;

[0114] The insulating layer 107 covers the polysilicon layer 106 and a portion of the N+ type source region 104 away from the surface of the N-type epitaxial layer 102 , and a contact hole penetrating to the N-type epitaxial layer 102 is provided on the insulating layer 107 ;

[0115] A source metal layer 108, the source metal layer 108 covers the surface of the P+ type first well region 103, the insulating layer 107 and the N+ type source region 104 away from the N-type epitaxial layer 102, and the source metal layer 108 is connected to the N-type epitaxial layer 102 through a contact hole; and

[0116] The drain metal layer 109 is disposed on a surface of the heavily doped substrate 101 away from the epitaxial layer 102 .

[0117] Among them, the second unit cell 20 is also provided with a P+ type second well region 201 with a well depth of 45μm. The P+ type second well region 201 is arranged in the N-type epitaxial layer 102 and is attached to the gate oxide layer 105, and the central axis of the P+ type second well region 201 coincides with the central axis of the gate oxide layer 105.

[0118] One P+ type first well region 103 is disposed between each of the P+ type second well regions 201 .

[0119] Example 2

[0120] The vertical power MOSFET provided in Example 2 is similar to that in Example 1, except that the well depth of the first well region 103 is 43 μm, and the well depth of the second well region 201 is 40 μm.

[0121] Example 3

[0122] The vertical power MOSFET provided in Example 3 is similar to that in Example 1, except that the distance between the center axis of the second well region 201 and the gate oxide layer 105 is 0.5 μm.

[0123] Example 4

[0124] The vertical power metal oxide semiconductor field effect transistor provided in Example 4 refers to Example 1, except that one and two first unit cells 10 are sequentially arranged between the second unit cells 20 .

[0125] Example 5

[0126] The vertical power metal oxide semiconductor field effect transistor provided in Example 5 refers to Example 1, except that no first unit cell 10 is arranged between the second unit cells 20 and one first unit cell 10 is arranged.

[0127] Example 6

[0128] The vertical power MOSFET provided in Example 6 is similar to that in Example 1, except that the width of the first well region 103 is 4 μm, and the width of the second well region 201 is 5 μm.

[0129] Comparative Example 1

[0130] The vertical power MOSFET provided in Comparative Example 1 refers to that in Example 1, except that all the second unit cells 20 are replaced by the first unit cells 10 .

[0131] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A vertical power metal oxide semiconductor field effect transistor, comprising a unit cell array consisting of at least one first unit cell and at least one second unit cell, wherein the first unit cell and the second unit cell each comprise: A heavily doped substrate having a first conductivity type; an epitaxial layer, the epitaxial layer covering the surface of the heavily doped substrate and having a first conductivity type; a first well region, the first well region being disposed in the epitaxial layer and having a second conductivity type, the second conductivity type being different from the first conductivity type; a source region, the source region being disposed in the first well region and having a first conductivity type; A gate oxide layer, the gate oxide layer covers the epitaxial layer away from the heavily doped substrate surface and extends from one source region to another adjacent source region; A polysilicon layer, the polysilicon layer covering a surface of the gate oxide layer away from the epitaxial layer; an insulating layer, the insulating layer covering the polysilicon layer and a portion of the surface of the source region away from the epitaxial layer, the insulating layer being provided with a contact hole penetrating to the epitaxial layer; a source metal layer, the source metal layer covering the first well region, the insulating layer and a surface of the source region away from the epitaxial layer, the source metal layer being connected to the epitaxial layer through a contact hole; and A drain metal layer is disposed on a surface of the heavily doped substrate away from the epitaxial layer; It is characterized in that a second well region of a second conductivity type is also provided in the second unit cell, and the second well region is provided in the epitaxial layer and adheres to the gate oxide layer.

2. The vertical power metal oxide semiconductor field effect transistor according to claim 1, characterized in that: A well depth of the second well region is equal to a well depth of the first well region.

3. The vertical power metal oxide semiconductor field effect transistor according to claim 1, characterized in that: A central axis of the second well region coincides with a central axis of the gate oxide layer.

4. The vertical power metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The width of the first unit cell is X1, the width of the second unit cell is X2, and X1:X2 is 1:1.95-1:2.

05.

5. The vertical power metal oxide semiconductor field effect transistor according to claim 4, characterized in that: The X1 is 4 μm-20 μm.

6. The vertical power metal oxide semiconductor field effect transistor according to any one of claims 1 to 5, characterized in that: comprising two or more adjacently arranged said second unit cells; And / or, comprising two or more second unit cells arranged at intervals.

7. The vertical power metal oxide semiconductor field effect transistor according to claim 6, characterized in that: Among the plurality of second single cells arranged at intervals, the same number of the first single cells are arranged between every two adjacent second single cells; And / or, different numbers of the first single cells are arranged between every two adjacent second single cells.

8. The vertical power metal oxide semiconductor field effect transistor according to claim 7, characterized in that: The same number of the first single cells is arranged between every two adjacent second single cells, and the number of the first single cells is 1 or 2.

9. A method for preparing a vertical power metal oxide semiconductor field effect transistor according to any one of claims 1 to 8, characterized in that: The following steps are involved: providing a heavily doped substrate; forming an epitaxial layer on a surface of the heavily doped substrate; forming a second well region having a second conductivity type in the epitaxial layer; Sequentially forming a gate oxide layer and a polysilicon layer on a surface of the epitaxial layer away from the heavily doped substrate, etching the gate oxide layer and the polysilicon layer to form gate region patterns of a first unit cell and a second unit cell in a unit cell array, wherein the gate oxide layer of the second unit cell is aligned with the second well region; forming a first well region on a surface of the epitaxial layer not covered by the gate region pattern; forming a source region in the first well region; forming an insulating layer on the surface of the polysilicon layer and a portion of the source region away from the epitaxial layer, and providing a contact hole penetrating to the epitaxial layer on the insulating layer; forming a source metal layer in the contact hole and on the surface of the first well region, the insulating layer and the source region away from the epitaxial layer; as well as A drain metal layer is formed on a surface of the heavily doped substrate away from the epitaxial layer.

10. A method for preparing a vertical power metal oxide semiconductor field effect transistor according to any one of claims 1 to 8, characterized in that: The following steps are involved: providing a heavily doped substrate; forming an epitaxial layer on a surface of the heavily doped substrate; forming a second well region and a first well region having a second conductivity type in the epitaxial layer; forming a source region in the first well region; Sequentially forming a gate oxide layer and a polysilicon layer on a surface of the epitaxial layer away from the heavily doped substrate, etching the gate oxide layer and the polysilicon layer to form gate region patterns of a first unit cell and a second unit cell in a unit cell array, wherein the gate oxide layer of the second unit cell is aligned with the second well region; forming an insulating layer on the surface of the polysilicon layer and a portion of the source region away from the epitaxial layer, and providing a contact hole penetrating to the epitaxial layer on the insulating layer; forming a source metal layer in the contact hole and on the surface of the first well region, the insulating layer and the source region away from the epitaxial layer; as well as A drain metal layer is formed on a surface of the heavily doped substrate away from the epitaxial layer.

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