Array substrate and display panel

Abstract

The embodiment of the present application discloses an array substrate and a display panel, including: a substrate, a thin film transistor, wherein the thin film transistor is arranged on the substrate, the thin film transistor includes an active layer, and a light shielding layer, wherein the light shielding layer is arranged on the substrate, the light shielding layer shields the active layer, and the material of the light shielding layer includes a silicon semiconductor material; using the light shielding layer to shield the active layer can greatly improve the light stability of the thin film transistor and extend the service life of the thin film transistor.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In the process of research and practice of the prior art, the inventors of the present application found that thin film transistors have become a hot spot for research and development in major scientific research institutions and panel companies due to their advantages such as simple process, low temperature deposition, high mobility, low operating voltage, transparency and good uniformity. Currently, common thin film transistor structures include top gate structure, bottom gate structure and back channel etching structure. In the above common thin film transistors, the light stability of the active layer is an important indicator affecting the life of existing thin film transistors. Therefore, providing a thin film transistor that can effectively block light will greatly increase the service life of existing thin film transistors. Summary of the invention

[0003] The embodiments of the present application provide an array substrate and a display panel, which can effectively shield light directed toward an active layer and increase the service life of a thin film transistor.

[0004] The present application provides an array substrate, comprising:

[0005] substrate;

[0006] A thin film transistor, the thin film transistor is arranged on the substrate; the thin film transistor comprises an active layer, and

[0007] A light shielding layer is provided on the substrate; the light shielding layer shields the active layer; and the material of the light shielding layer includes silicon semiconductor material.

[0008] Optionally, in some embodiments of the present application, the thin film transistor further comprises a gate disposed in a different layer from the active layer, and the gate is disposed on the active layer;

[0009] Optionally, in some embodiments of the present application, the light-shielding layer and the active layer are arranged in different layers, and the active layer is arranged above the light-shielding layer.

[0010] Optionally, in some embodiments of the present application, the array substrate further includes a buffer layer and a passivation layer; the thin film transistor further includes a gate insulating layer, an interlayer dielectric layer, a source electrode and a drain electrode;

[0011] Optionally, in some embodiments of the present application, the buffer layer is disposed on the light shielding layer; the active layer is disposed on the buffer layer; the gate insulating layer is disposed on the active layer; and the gate is disposed on the gate insulating layer;

[0012] Optionally, in some embodiments of the present application, the interlayer dielectric layer covers the active layer, the gate insulating layer and the gate, and the interlayer dielectric layer is provided with a first through hole and a second through hole;

[0013] Optionally, in some embodiments of the present application, the source electrode contacts part of the active layer through the first through hole, and the drain electrode contacts part of the active layer through the second through hole; and the passivation layer is disposed on the interlayer dielectric layer.

[0014] Optionally, in some embodiments of the present application, the thin film transistor further comprises a gate disposed in a different layer from the active layer, and the active layer is disposed on the gate;

[0015] Optionally, in some embodiments of the present application, the light shielding layer and the active layer are provided in different layers, and the active layer is formed above the light shielding layer.

[0016] Optionally, in some embodiments of the present application, the array substrate further includes a passivation layer and an electrode; the thin film transistor further includes a gate insulating layer, a source electrode and a drain electrode;

[0017] Optionally, in some embodiments of the present application, the gate insulating layer is disposed on the gate; the source electrode and the drain electrode are disposed on the active layer in the same layer;

[0018] Optionally, in some embodiments of the present application, the passivation layer covers the gate insulating layer, the light shielding layer, the active layer, the source electrode and the drain electrode; and a through hole is provided on the passivation layer;

[0019] Optionally, in some embodiments of the present application, the electrode contacts the drain through the through hole.

[0020] Optionally, in some embodiments of the present application, the thin film transistor further comprises a gate disposed in a different layer from the active layer, and the active layer is disposed on the gate;

[0021] Optionally, in some embodiments of the present application, the light shielding layer and the active layer are provided in different layers, and the light shielding layer is provided above the active layer.

[0022] Optionally, in some embodiments of the present application, the array substrate further includes a first passivation layer, a color resist and a second passivation layer; the thin film transistor further includes a gate insulating layer, a source electrode and a drain electrode;

[0023] Optionally, in some embodiments of the present application, the gate insulating layer is disposed between the gate and the active layer; the source electrode and the drain electrode are disposed in the same layer and connected to the active layer;

[0024] Optionally, in some embodiments of the present application, the first passivation layer covers the source, the drain, the gate insulation layer and the active layer; the color resistance is arranged on the first passivation layer; the second passivation layer is arranged on the color resistance; and the light shielding layer is arranged on the second passivation layer.

[0025] Optionally, in some embodiments of the present application, the material of the light-shielding layer also includes a light-shielding metal material; and the light-shielding layer covers the active layer.

[0026] Optionally, in some embodiments of the present application, the array substrate further includes a passivation layer; the thin film transistor further includes a gate insulating layer, a source electrode and a drain electrode;

[0027] Optionally, in some embodiments of the present application, the gate insulating layer is disposed between the gate and the active layer;

[0028] Optionally, in some embodiments of the present application, the passivation layer covers the source electrode, the drain electrode, the gate insulating layer and the active layer; and the light shielding layer is disposed on the passivation layer.

[0029] Optionally, in some embodiments of the present application, the material of the light-shielding layer also includes a light-shielding metal material; and the light-shielding layer covers the active layer.

[0030] Correspondingly, the present application also relates to a display panel, which includes an opposite substrate, an array substrate such as the above embodiment, and a liquid crystal layer arranged between the array substrate and the opposite substrate.

[0031] The embodiment of the present application uses a light-shielding layer to shield the active layer, which can greatly improve the light stability of the thin-film transistor and extend the service life of the thin-film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 is a schematic diagram of a first structure of an array substrate in an embodiment of the present application;

[0034] Figure 2 is a schematic diagram of a second structure of an array substrate according to an embodiment of the present application;

[0035] Figure 3 is a transfer current characteristic curve diagram of the array substrate of an embodiment of the present application;

[0036] Figure 4 is a third structural schematic diagram of the array substrate of the embodiment of the present application;

[0037] Figure 5 is the absorption spectrum of the array substrate of the embodiment of the present application;

[0038] Figure 6 This is a fourth structural schematic diagram of the array substrate of an embodiment of the present application.

[0039] Explanation of the reference numerals: array substrate 100, thin film transistor 11, gate 111, gate insulating layer 112, active layer 113, source 114, drain 115, interlayer dielectric layer 116, substrate 12, light shielding layer 13, electrode 14, through hole 15, first through hole 151, second through hole 152, buffer layer 16, passivation layer 17, first passivation layer 171, second passivation layer 172, color resist 18. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words such as "upper" and "lower" used generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0041] The present application provides an array substrate, which is described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0042] Embodiment 1

[0043] See also Figure 1 This embodiment provides an array substrate 100 , which includes a substrate 12 , a thin film transistor 11 and a light shielding layer 13 .

[0044] The thin film transistor 11 is disposed on a substrate 12. The thin film transistor 11 includes an active layer 113 and a light shielding layer 13, and the light shielding layer 13 is disposed on the substrate 12. The light shielding layer 13 shields the active layer 113. The material of the light shielding layer 13 includes a silicon semiconductor material.

[0045] In the traditional top-gate structure, in order to ensure the light stability of the thin film transistor, a light shielding layer needs to be set at the bottom of the active layer. Generally, an opaque metal is used as the light shielding layer. Because the metal has a low resistance, the buffer layer needs to be thickened to fully insulate.

[0046] In this embodiment, the light shielding layer 13 is made of silicon semiconductor, which has low light transmittance and can effectively shield light, thereby improving the light stability of the thin film transistor 11. Since silicon semiconductor has a high resistance, even if the thickness of the buffer layer 16 is reduced, for example, from 4000 angstroms to 1000 angstroms, good insulation properties can be guaranteed. In addition, the silicon semiconductor layer can be formed by plasma enhanced chemical vapor deposition, and the active layer 113 mask can be used for patterning, saving the cost of one mask.

[0047] Optionally, the material of the active layer 113 includes metal oxides such as indium gallium zinc oxide (IGZO), indium gallium zinc titanium oxide (IGZTO), indium zinc oxide (IZO), and indium gallium tin oxide (IGTO).

[0048] Optionally, the thin film transistor 11 further includes a gate 111 disposed in a different layer from the active layer 113 , and the gate 111 is disposed on the active layer 113 .

[0049] Optionally, the light shielding layer 13 and the active layer 113 are arranged in different layers, and the active layer 113 is arranged above the light shielding layer 13 .

[0050] Optionally, the array substrate 100 further includes a buffer layer 16 and a passivation layer 17. The thin film transistor 11 further includes a gate insulating layer 112, an interlayer dielectric layer 116, a source electrode 114 and a drain electrode 115.

[0051] Optionally, the buffer layer 16 is disposed on the light shielding layer 13. The active layer 113 is disposed on the buffer layer 16. The gate insulating layer 112 is disposed on the active layer 113. The gate 111 is disposed on the gate insulating layer 112.

[0052] Optionally, the interlayer dielectric layer 116 covers the active layer 113, the gate insulating layer 112 and the gate 111. The interlayer dielectric layer 116 is provided with a first through hole 151 and a second through hole 152.

[0053] Optionally, the source electrode 114 contacts a portion of the active layer 113 through the first through hole 151 , and the drain electrode 115 contacts a portion of the active layer 113 through the second through hole 152 . The passivation layer 17 is disposed on the interlayer dielectric layer 116 .

[0054] In this embodiment, the materials forming the above-mentioned interlayer dielectric layer 116, buffer layer 16, gate insulation layer 112 and passivation layer 17 include but are not limited to dielectric materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), new organic insulating materials such as polysiloxane materials, acrylic materials, or polyimide materials, or high dielectric constant materials such as aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc.

[0055] In this embodiment, the materials for forming the source 114, the drain 115 and the gate 111 may be commonly used metal materials, such as Ag, Cu, Al, Mo, etc. It may also be a multilayer metal, such as MoNb / Cu / MoNb, etc. It may also be an alloy material of the above metals, such as AlNd, MoNb, etc. It may also be a metal and a transparent conductive oxide (such as ITO, AZO, etc.), or a stacked structure formed by them, such as ITO / Ag / ITO, etc.

[0056] Embodiment 2

[0057] See also Figure 2 This embodiment provides an array substrate 100 , which includes a substrate 12 , a thin film transistor 11 and a light shielding layer 13 .

[0058] The thin film transistor 11 is disposed on a substrate 12. The thin film transistor 11 includes an active layer 113 and a light shielding layer 13, and the light shielding layer 13 is disposed on the substrate 12. The light shielding layer 13 shields the active layer 113. The material of the light shielding layer 13 includes a silicon semiconductor material.

[0059] Optionally, the thin film transistor 11 further includes a gate electrode 111 which is disposed in a different layer from the active layer 113 , and the active layer 113 is disposed on the gate electrode 111 .

[0060] Optionally, the light shielding layer 13 and the active layer 113 are provided in different layers, and the active layer 113 is formed above the light shielding layer 13 .

[0061] In the traditional bottom-gate structure, indium gallium zinc oxide (IGZO) is usually used as the active layer. As product specifications continue to advance, the requirements for the mobility of the active layer are getting higher and higher. Generally, the mobility of the active layer material is improved by increasing the indium content, but this will lead to a decrease in the band gap of the active layer and poor light stability of the thin film transistor. Therefore, the thin film transistor has higher requirements for light shielding. The transfer current characteristic curve is as follows: Figure 3 As shown, Figure 3 The left side in the middle is the transfer current characteristic curve when no shading layer is added, and the right side is the transfer current characteristic curve when the shading layer is added.

[0062] In this embodiment, a silicon semiconductor layer is disposed below the active layer 113 to improve the light stability of the thin film transistor 11. The silicon semiconductor layer can be patterned using the photomask of the active layer 113 without the need for a new photomask.

[0063] In this embodiment, the material of the active layer 113 includes metal oxides such as indium gallium zinc oxide (IGZO), indium gallium zinc titanium oxide (IGZTO), indium zinc oxide (IZO), and indium gallium tin oxide (IGTO).

[0064] Optionally, the array substrate 100 further includes a passivation layer 17 and an electrode 14. The thin film transistor 11 further includes a gate insulating layer 112, a source electrode 114 and a drain electrode 115.

[0065] Optionally, the gate insulating layer 112 is disposed on the gate 111. The source electrode 114 and the drain electrode 115 are disposed on the active layer 113 in the same layer.

[0066] Optionally, the passivation layer 17 covers the gate insulating layer 112, the light shielding layer 13, the active layer 113, the source electrode 114 and the drain electrode 115. A through hole 15 is provided on the passivation layer 17.

[0067] Optionally, the electrode 14 contacts the drain electrode 115 through the through hole 15 .

[0068] In this embodiment, the materials forming the above-mentioned passivation layer 17 and the gate insulating layer 112 include but are not limited to dielectric materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), new organic insulating materials such as polysiloxane materials, acrylic materials, or polyimide materials, or high dielectric constant materials such as aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc.

[0069] In this embodiment, the materials for forming the source 114, the drain 115, the gate 111 and the electrode 14 may be commonly used metal materials, such as Ag, Cu, Al, Mo, etc. It may also be a multilayer metal, such as MoNb / Cu / MoNb, etc. It may also be an alloy material of the above metals, such as AlNd, MoNb, etc. It may also be a metal and a transparent conductive oxide (such as ITO, AZO, etc.), or a stacked structure formed by them, such as ITO / Ag / ITO, etc.

[0070] Embodiment 3

[0071] See also Figure 4 This embodiment provides an array substrate 100 , which includes a substrate 12 , a thin film transistor 11 and a light shielding layer 13 .

[0072] The thin film transistor 11 is disposed on a substrate 12. The thin film transistor 11 includes an active layer 113 and a light shielding layer 13, and the light shielding layer 13 is disposed on the substrate 12. The light shielding layer 13 shields the active layer 113. The material of the light shielding layer 13 includes a silicon semiconductor material.

[0073] Optionally, the thin film transistor 11 further includes a gate electrode 111 which is disposed in a different layer from the active layer 113 , and the active layer 113 is disposed on the gate electrode 111 .

[0074] Optionally, the light shielding layer 13 and the active layer 113 are provided in different layers, and the light shielding layer 13 is provided above the active layer 113 .

[0075] Optionally, the array substrate 100 further includes a first passivation layer 171 , a color resist 18 and a second passivation layer 172 . The thin film transistor 11 further includes a gate insulating layer 112 , a source electrode 114 and a drain electrode 115 .

[0076] Optionally, the gate insulating layer 112 is disposed between the gate 111 and the active layer 113. The source electrode 114 and the drain electrode 115 are disposed in the same layer and connected to the active layer 113.

[0077] Optionally, the first passivation layer 171 covers the source electrode 114, the drain electrode 115, the gate insulating layer 112 and the active layer 113. The color resist 18 is disposed on the first passivation layer 171. The second passivation layer 172 is disposed on the color resist 18. The light shielding layer 13 is disposed on the second passivation layer 172.

[0078] In the embodiment of the present application, the material of the light shielding layer 13 is amorphous silicon, which is a light absorbing material and can absorb most of the light with a wavelength less than 640 nanometers. The absorption spectrum is shown in FIG. Figure 5 This part of light has high energy and has a greater impact on the device.

[0079] In this embodiment, a light-shielding layer 13 is added on the second passivation layer 172. The material of the light-shielding layer 13 is amorphous silicon. At the same time, the light-shielding layer 13 is patterned by a mask to ensure that the channel of the thin-film transistor 11 is covered by the light-shielding layer 13. This can greatly reduce the diffuse reflection of light from the black matrix (BM) of the opposite substrate or the influence of external light on the light stability of the device. The technical solution provided in this embodiment can also be applied to all devices with back-channel etched structures, including back-channel etched oxide thin-film transistors 11, back-channel etched amorphous silicon thin-film transistors 11, and back-channel etched organic thin-film transistors 11.

[0080] In this embodiment, the material of the active layer 113 includes amorphous silicon (a-Si) and indium gallium zinc oxide (IGZO).

[0081] In this embodiment, the materials forming the above-mentioned first passivation layer 171, the second passivation layer 172 and the gate insulating layer 112 include but are not limited to dielectric materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), new organic insulating materials such as polysiloxane materials, acrylic materials, or polyimide materials, or high dielectric constant materials such as aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc.

[0082] In this embodiment, the source 114, the drain 115 and the gate 111 may be formed of commonly used metal materials, such as Ag, Cu, Al, Mo, etc. They may also be multilayer metals, such as MoNb / Cu / MoNb, etc. They may also be alloy materials of the above metals, such as AlNd, MoNb, etc.

[0083] In some embodiments, the material of the light shielding layer 13 further includes a light shielding metal material. The light shielding layer 13 covers the active layer 113 .

[0084] In this embodiment, the metal material of the light shielding layer 13 includes Mo, Cu, Al, or a multi-layer structure of Mo / Cu, MoTi / Cu, Mo / Al / Mo, etc., and the thickness is between 100 angstroms and 3000 angstroms.

[0085] Embodiment 4:

[0086] See also Figure 6 This embodiment provides an array substrate 100 , which includes a substrate 12 , a thin film transistor 11 and a light shielding layer 13 .

[0087] The thin film transistor 11 is disposed on a substrate 12. The thin film transistor 11 includes an active layer 113 and a light shielding layer 13, and the light shielding layer 13 is disposed on the substrate 12. The light shielding layer 13 shields the active layer 113. The material of the light shielding layer 13 includes a silicon semiconductor material.

[0088] Optionally, the thin film transistor 11 further includes a gate electrode 111 which is disposed in a different layer from the active layer 113 , and the active layer 113 is disposed on the gate electrode 111 .

[0089] Optionally, the light shielding layer 13 and the active layer 113 are provided in different layers, and the light shielding layer 13 is provided above the active layer 113 .

[0090] Optionally, the array substrate 100 further includes a passivation layer 17 . The thin film transistor 11 further includes a gate insulating layer 112 , a source electrode 114 and a drain electrode 115 .

[0091] Optionally, the gate insulating layer 112 is disposed between the gate 111 and the active layer 113 .

[0092] Optionally, the passivation layer 17 covers the source electrode 114 , the drain electrode 115 , the gate insulating layer 112 and the active layer 113 . The light shielding layer 13 is disposed on the passivation layer 17 .

[0093] Optionally, the difference between this embodiment and the third embodiment is that the color resist 18 and the second passivation layer 172 are removed, and the present embodiment can be used for a substrate of a non-color filter array.

[0094] In this embodiment, an amorphous silicon layer is added on the passivation layer 17 as a light-shielding layer 13, and the light-shielding layer 13 is patterned by a mask to ensure that the channel of the thin film transistor 11 is covered by the light-shielding layer 13, thereby greatly reducing the diffuse reflection of light from the black matrix (BM) of the opposite substrate or the influence of external light on the light stability of the device. The technical solution provided in this embodiment can also be applied to all devices with back-channel etched structures, including back-channel etched oxide thin film transistors 11, back-channel etched amorphous silicon thin film transistors 11, and back-channel etched organic thin film transistors 11.

[0095] In this embodiment, the material of the active layer 113 includes amorphous silicon (a-Si) and indium gallium zinc oxide (IGZO).

[0096] In this embodiment, the materials forming the above-mentioned passivation layer 17 and the gate insulating layer 112 include but are not limited to dielectric materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), new organic insulating materials such as polysiloxane materials, acrylic materials, or polyimide materials, or high dielectric constant materials such as aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc.

[0097] In this embodiment, the source 114, the drain 115 and the gate 111 may be formed of commonly used metal materials, such as Ag, Cu, Al, Mo, etc. They may also be multilayer metals, such as MoNb / Cu / MoNb, etc. They may also be alloy materials of the above metals, such as AlNd, MoNb, etc.

[0098] In some embodiments, the material of the light shielding layer 13 further includes a light shielding metal material. The light shielding layer 13 covers the active layer 113 .

[0099] In this embodiment, the metal material of the light shielding layer 13 includes Mo, Cu, Al, or a multi-layer structure of Mo / Cu, MoTi / Cu, Mo / Al / Mo, etc., and the thickness is between 100 angstroms and 3000 angstroms.

[0100] Correspondingly, the present application also relates to a display panel, which includes an opposite substrate, an array substrate such as the above embodiment, and a liquid crystal layer arranged between the array substrate and the opposite substrate.

[0101] The opposite substrate includes a base and a black matrix arranged on the base, wherein the black matrix is ​​arranged on a side of the base facing the liquid crystal layer.

[0102] The above is a detailed introduction to an array substrate provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A thin film transistor, the thin film transistor is arranged on the substrate; the thin film transistor comprises an active layer, and a light shielding layer, the light shielding layer being arranged on the substrate; The light shielding layer shields the active layer; The material of the light shielding layer includes silicon semiconductor material; The thin film transistor further comprises a gate electrode disposed in a different layer from the active layer, and the active layer is disposed on the gate electrode; The light shielding layer and the active layer are arranged in different layers, and the light shielding layer is arranged above the active layer; The array substrate further includes a first passivation layer, a color resist and a second passivation layer; the thin film transistor further includes a gate insulating layer, a source electrode and a drain electrode; The gate insulating layer is disposed between the gate and the active layer; The source electrode and the drain electrode are arranged in the same layer and connected to the active layer; The first passivation layer covers the source electrode, the drain electrode, the gate insulating layer and the active layer; The color resist is disposed on the first passivation layer, and a portion of the color resist covers a portion of the first passivation layer corresponding to the active layer; The second passivation layer is disposed on the color resist; The light shielding layer is disposed on the second passivation layer; The material of the light shielding layer includes amorphous silicon.

2. The array substrate according to claim 1, characterized in that: The material of the light-shielding layer also includes a light-shielding metal material; the light-shielding layer covers the active layer.

3. A display panel, characterized in that: The display panel includes an opposite substrate, the array substrate according to claim 1 or 2, and a liquid crystal layer arranged between the array substrate and the opposite substrate.

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