A memory device based on wrinkled two-dimensional material and its preparation method and application

Abstract

The present invention discloses a storage device based on a wrinkled two-dimensional material, and its preparation method and application. The storage device includes a substrate, on which a two-dimensional material layer with a wrinkled structure is provided, wherein the two-dimensional material layer is transferred to the substrate through a polymer layer, and the formation process of the wrinkled structure includes the following steps: the two-dimensional material layer is adhered between the polymer layer and the substrate, first subjected to heat treatment, and then subjected to quenching treatment, and the polymer layer and the substrate have different thermal expansion coefficients. The present invention combines heat treatment and quenching treatment, utilizing the different thermal expansion coefficients of the polymer and the substrate to form a wrinkled structure on the two-dimensional material layer. The storage device prepared based on this type of wrinkled two-dimensional material has the advantages of multiple resistance states, large storage window, high switching ratio, high stability and good repeatability. The material preparation method of the present invention is simple, the storage device structure is simple, and the storage function can be realized using only a single layer of material, further improving the system's integration.

Description

Technical Field

[0001] The present invention belongs to the technical field of storage devices, and in particular relates to a storage device based on wrinkled two-dimensional materials, and a preparation method and application thereof. Background Art

[0002] With the rapid development of 5G, the Internet of Things, and artificial intelligence (AI) technologies, storage cells will become a crucial component of the future big data era. Currently, solid-state drives (SSDs) are the most popular memory architecture due to their high reliability, including multi-level storage, excellent on / off ratio, and long duration. However, SSDs based on bulk materials face challenges in achieving further size reductions consistent with Moore's Law and difficulty integrating them into flexible electronics. In this regard, two-dimensional (2D) materials are considered promising candidates for fabricating ultra-small and thin memory devices. However, existing fabrication methods for 2D-based memory devices are cumbersome and require demanding conditions, significantly hindering their application in memory devices. Methods such as floating gate control, heterostructures, functionalized gate electrodes, and interface confinement are commonly used as carrier confinement mechanisms in memory devices. Although the resulting memory devices exhibit promising performance in terms of multi-bit, on / off ratio, and duration, they typically involve multi-step fabrication processes, making them difficult to scale up. On the other hand, the introduction of functional dielectric layers (e.g., negative capacitors or ferroelectric materials) provides another pathway for carrier capture in memory, but the additional interface and local characteristics introduced may degrade device performance. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the above-mentioned prior art. To this end, the present invention provides a memory device having the characteristic of being simple to manufacture.

[0004] The present invention provides a method for preparing a memory device.

[0005] The present invention also proposes applications of the above storage device.

[0006] In a first aspect of the present invention, a storage device is proposed, comprising a substrate on which is provided a two-dimensional material layer with a wrinkled structure, wherein the two-dimensional material layer is transferred to the substrate through a polymer layer, and the formation process of the wrinkled structure comprises the following steps: the two-dimensional material layer is adhered between the polymer layer and the substrate, first subjected to heat treatment, and then subjected to sudden cooling treatment, wherein the polymer layer and the substrate have different thermal expansion coefficients.

[0007] A storage device according to an embodiment of the present invention has at least the following beneficial effects: the present invention combines heat treatment and quenching treatment, and utilizes the different thermal expansion coefficients of the polymer layer and the substrate to form tensile and compressive stresses on the two-dimensional material layer during the quenching (rapid cooling) process, and finally forms a wrinkle structure on the two-dimensional material layer. The obtained two-dimensional material layer with a wrinkle structure is used to prepare a storage device (such as a transistor device). The present invention has universality and extensiveness. Compared with the storage devices realized by other methods in the prior art, the preparation method of the present invention is simple, the storage device structure is simpler, and the storage function can be realized by using only a single layer of material, which further improves the system's integration.

[0008] The straining mechanism of the two-dimensional material in this invention involves heat treatment and rapid cooling, which can form nanoscale wrinkled structures. For example, in some embodiments, wrinkles of approximately 300 nm in width and 3 nm in height can be formed. The polymer layer employed in this invention is generally a high molecular weight polymer (such as polyethylene terephthalate), which has improved thermal stability. Therefore, the heat treatment and rapid cooling processes only induce nanoscale strain in the two-dimensional material. Furthermore, the polymer layer in this invention exhibits improved adhesion to the two-dimensional material layer, making it easier to control the microstructure of the two-dimensional material layer.

[0009] The memory device fabricated by this invention exhibits multiple controllable resistance states, a large storage window, a high on / off ratio, and excellent device stability and repeatability. Furthermore, the device exhibits both linear and nonlinear resistance state variations. This invention utilizes wrinkles in a two-dimensional material layer to construct a memory device, which has implications for the future development of flexible, ultra-thin electronic devices, big data algorithms, computer systems, and artificial intelligence.

[0010] In some embodiments of the present invention, the heat treatment and quenching treatment process includes heating the stacked structure to a temperature T1 and then cooling the stacked structure to a temperature T2 within a time t1.

[0011] In some preferred embodiments of the present invention, T1 = 50-300°C.

[0012] In some preferred embodiments of the present invention, the temperature T2 is (-20) to 40°C.

[0013] In some preferred embodiments of the present invention, the t1≤3 min.

[0014] In some preferred embodiments of the present invention, the t1≤1 min.

[0015] In some more preferred embodiments of the present invention, the t1≤45s.

[0016] In some more preferred embodiments of the present invention, the t1≤30s.

[0017] In some more preferred embodiments of the present invention, the t1≤25s.

[0018] In some more preferred embodiments of the present invention, the t1≤20s.

[0019] In some more preferred embodiments of the present invention, the t1≤15s.

[0020] In some more preferred embodiments of the present invention, the t1≤10s.

[0021] In some more preferred embodiments of the present invention, the t1≤5s.

[0022] In some embodiments of the present invention, the two-dimensional material layer includes at least one of a semiconductor or an insulating material.

[0023] Through the above-mentioned implementation, the two-dimensional semiconductor material in the present invention has a wrinkled structure, and the wrinkled carriers are bounded on the two-dimensional semiconductor material to prepare a high-performance storage device to realize the storage function of the device. This is a new way to realize high-performance controllable storage devices, which is simple and easy.

[0024] In some preferred embodiments of the present invention, the two-dimensional material layer includes at least one of two-dimensional MoS2, WS2, WSe2 or h-BN.

[0025] Among them, h-BN is hexagonal boron nitride.

[0026] In some preferred embodiments of the present invention, the memory device is a transistor, and the two-dimensional material layer is a two-dimensional semiconductor material.

[0027] Through the above-mentioned embodiments, the present invention can realize the formation of a nanoscale wrinkle structure on a two-dimensional material layer, and the preparation method is simple and easy; and the formation of the wrinkle structure is conducive to the use of semiconductor two-dimensional materials to construct storage devices.

[0028] In some more preferred embodiments of the present invention, the two-dimensional semiconductor material includes two-dimensional MoS2, the substrate is a silicon substrate, and the silicon substrate is SiO2 / Si.

[0029] In some preferred embodiments of the present invention, the thickness of the two-dimensional material layer is h=0.7-50 nm.

[0030] In some more preferred embodiments of the present invention, the thickness of the two-dimensional material layer is h=0.7-10 nm.

[0031] In some preferred embodiments of the present invention, the two-dimensional material layer includes a plurality of two-dimensional material sheets, and the sheet diameter r of the two-dimensional material sheet is 1 to 1000 μm.

[0032] It should be noted that the sheet diameter in this article refers to the size of the two-dimensional material sheet on a two-dimensional plane.

[0033] In some more preferred embodiments of the present invention, the diameter of the two-dimensional material sheet r is 1 to 100 μm.

[0034] In some embodiments of the present invention, the substrate includes at least one of a silicon substrate, gold, tungsten, copper, graphene, or ITO.

[0035] Wherein, ITO is indium tin oxide.

[0036] In some preferred embodiments of the present invention, the silicon substrate is SiO2 / Si.

[0037] In some embodiments of the present invention, the polymer layer comprises polyethylene terephthalate.

[0038] Among them, polyethylene terephthalate: polyethylene terephthalate, PET. Among them, PET in this article refers to polyethylene terephthalate.

[0039] In some preferred embodiments of the present invention, the surface roughness of the polymer layer is less than 10 nm.

[0040] In some more preferred embodiments of the present invention, the surface roughness of the polymer layer is less than 3 nm.

[0041] According to the above embodiment, the polymer layer has an ultra-flat surface.

[0042] In some embodiments of the present invention, a metal electrode is provided on the two-dimensional material layer.

[0043] In some preferred embodiments of the present invention, the metal electrode includes at least one of Cu, Cr, Ti, Au, Pd or Ni.

[0044] According to a second aspect of the present invention, a method for preparing the above-mentioned storage device is proposed, which includes the steps of forming a wrinkled structure on a two-dimensional material layer: the two-dimensional material layer is adhered between a polymer layer and a substrate, first subjected to heat treatment, and then subjected to sudden cooling treatment to form a wrinkled structure on the two-dimensional material layer.

[0045] A storage device according to an embodiment of the present invention has at least the following beneficial effects: the present invention provides a new implementation method for high-performance controllable storage devices, in order to realize simple and easy storage devices in ultra-thin. The present invention combines heat treatment and quenching treatment, and utilizes the different thermal expansion coefficients of the polymer layer and the substrate to form tensile and compressive stresses on the two-dimensional material layer during the quenching (rapid cooling) process, and finally forms a wrinkle structure on the two-dimensional material layer. The obtained two-dimensional material layer with a wrinkle structure is used to prepare a storage device (such as a transistor device). The present invention has universality and extensiveness. Compared with the storage devices realized by other methods in the prior art, the preparation method of the present invention is simple, the storage device structure is simpler, and the storage function can be realized by using only a single layer of material, which further improves the system's integration.

[0046] The straining mechanism of the two-dimensional materials described herein involves heat and rapid cooling, which can form nanoscale wrinkled structures. For example, in some embodiments, wrinkles approximately 300 nm wide and 3 nm high can be formed. The polymer layer employed in the present invention is typically a high-molecular-weight polymer (such as polyethylene terephthalate), which exhibits enhanced thermal stability. Therefore, the heat treatment and rapid cooling processes only induce nanoscale strain in the two-dimensional material. Furthermore, the polymer layer described herein exhibits enhanced adhesion to the two-dimensional material layer, enabling easier control of the microstructure of the two-dimensional material layer.

[0047] The memory device fabricated by this invention exhibits multiple controllable resistance states, a large storage window, a high on / off ratio, and excellent device stability and repeatability. Furthermore, the device exhibits both linear and nonlinear resistance state variations. This invention utilizes wrinkles in a two-dimensional material layer to construct a memory device, which has implications for the future development of flexible, ultra-thin electronic devices, big data algorithms, computer systems, and artificial intelligence.

[0048] In some embodiments of the present invention, the preparation method further comprises removing the polymer layer after the wrinkled structure is formed.

[0049] In some preferred embodiments of the present invention, the polymer layer is removed by dissolving it with a solvent.

[0050] In some more preferred embodiments of the present invention, the heat-treated laminated structure is quickly placed in a solvent at a temperature of T3 for a quenching treatment, and then placed for a time t2, so that the solvent dissolves and removes the polymer layer.

[0051] In some more preferred embodiments of the present invention, the T3 = (-25) ~ 40°C.

[0052] In some more preferred embodiments of the present invention, the solvent is dichloromethane.

[0053] In some more preferred embodiments of the present invention, t2 = 6 to 10 h.

[0054] In some more preferred embodiments of the present invention, t2=6h.

[0055] In some embodiments of the present invention, the preparation method further comprises:

[0056] S1, preparing a two-dimensional material layer on a growth substrate by chemical vapor deposition;

[0057] S2, laminating the polymer layer on the two-dimensional material layer and heating the two-dimensional material layer to transfer the two-dimensional material layer from the growth substrate to the polymer layer;

[0058] S3, laminating the side of the two-dimensional material layer facing away from the polymer layer to the surface of the substrate to obtain a stacked structure consisting of the polymer layer, the two-dimensional material layer and the substrate.

[0059] In some preferred embodiments of the present invention, in step S1, a single layer of two-dimensional semiconductor material MoS2 is grown on a silicon substrate by chemical vapor deposition using Na2MoO4 as a raw material.

[0060] In some preferred embodiments of the present invention, the growth substrate includes at least one of a glass wafer, a silicon wafer, or a mica wafer.

[0061] The third aspect of the present invention proposes the application of the above-mentioned storage device in the field of electronic equipment, big data algorithms or artificial intelligence technology.

[0062] In some embodiments of the present invention, application of the above-mentioned memory device in flexible ultra-thin electronic devices is proposed. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which:

[0064] Figure 1 This is an optical microscope photograph of the two-dimensional MoS2 layer obtained in step I of Example 1 of the present invention;

[0065] Figure 2 Schematic diagram of the transfer process involved in the two-dimensional MoS2 layer in Example 1 of the present invention, Figure 2 a is a schematic diagram of the PET layer and the two-dimensional MoS2 layer attached to the silicon substrate. Figure 2 b is a schematic diagram of the stacked structure placed in dichloromethane. Figure 2 c is a schematic diagram of the state of the two-dimensional MoS2 layer obtained in step VIII;

[0066] Figure 3The two-dimensional MoS2 layer obtained in step VIII of Example 1 of the present invention is shown in the scanning electron microscope test result diagram and the atomic force microscope test result diagram;

[0067] Figure 4 is a schematic structural diagram of the memory device prepared in Example 1 of the present invention;

[0068] Figure 5 1 is a graph showing the test results of the current response characteristics of the memory device when pulse voltages of different amplitudes are applied to the gate electrode of the memory device in Example 1 of the present invention;

[0069] Figure 6 1 is a graph showing the test results of the current response characteristics of the memory device in Example 1 of the present invention, in which pulse voltages of the same amplitude but different times are applied to the gate electrode of the memory device;

[0070] Figure 7 1 is a graph showing the test results of the current response characteristics of the memory device in Example 1 of the present invention when pulse voltages of the same amplitude but different frequencies are applied to the gate electrode;

[0071] Figure 8 is a scanning electron microscope image of the two-dimensional MoS2 layer obtained in step VII of Comparative Example 1 of the present invention;

[0072] Figure 9 This is the transfer characteristic curve of the transistor prepared with the wrinkle-free two-dimensional MoS2 layer in Comparative Example 1 of the present invention. DETAILED DESCRIPTION

[0073] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0074] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0075] In the description of the present invention, "several" means more than one, "plurality" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" in the description is solely for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, implicitly specifying the number of the indicated technical features, or implicitly specifying the order of the indicated technical features.

[0076] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0077] In the description of the present invention, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the exemplary expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0078] Example 1

[0079] This embodiment discloses a memory device, in the form of a transistor, comprising a substrate on which is disposed a two-dimensional material layer having a wrinkled structure. The two-dimensional material layer is transferred to the substrate via a polymer layer. The wrinkled structure is formed by laminating the two-dimensional material layer between the polymer layer and the substrate, performing a heat treatment, and then performing a quenching treatment. The polymer layer and the substrate have different thermal expansion coefficients. The two-dimensional material layer comprises two-dimensional MoS2 with a thickness of 0.7 to 5 nm and comprises multiple two-dimensional material sheets, each having a sheet diameter of 10 to 100 μm.

[0080] This embodiment prepares the above-mentioned memory device (that is, the above-mentioned transistor), and the specific process includes:

[0081] (I) Grow a single layer of two-dimensional semiconductor material MoS2 in a growth substrate using chemical vapor deposition: first, spin-coat a 1 mol / L Na2MoO4 aqueous solution on a first glass sheet, and then paste a second glass sheet on top of the first glass sheet coated with Na2MoO4, and heat the temperature to 660°C; then place the pasted first and second glass sheets in the middle of a tubular CVD furnace tube, and place S powder at the front end of the furnace tube; heat the furnace tube to 750°C and maintain for 10 minutes, while introducing Ar at a flow rate of 80 sccm; after the furnace tube cools to room temperature, take it out to obtain a single layer of MoS2 (two-dimensional MoS2 layer) on the surface of the second glass sheet.

[0082] (II) Cut the PET layer (polymer layer) into 1×1 mm 2 and place one side of the cut PET layer on a glass slide.

[0083] (III) Use a glass slide to place the other side of the PET layer close to the two-dimensional MoS2 layer prepared in step I.

[0084] (IV) Heat the two-dimensional MoS2 layer and the PET layer to 65°C.

[0085] (V) The glass slide, PET layer and two-dimensional MoS2 layer are extracted from the growth substrate (i.e., the two-dimensional MoS2 layer is separated from the surface of the second glass slide) and attached to the silicon substrate (SiO2 / Si) to obtain a stacked structure, such as Figure 2 As shown in a.

[0086] (VI) Heat the silicon substrate, two-dimensional MoS2 layer, PET layer and glass slide to 110°C.

[0087] (VII) Separate the glass slide and the PET layer, and quickly (within 10 s) place the silicon substrate, the two-dimensional MoS2 layer, and the PET layer from a high temperature (110 ° C) into dichloromethane at room temperature, and cool them to room temperature within about 10 s. Figure 2 As shown in b.

[0088] (VIII) After standing in dichloromethane for 6 hours to fully dissolve the PET layer, the silicon substrate (containing the two-dimensional MoS2 layer) is removed to obtain a two-dimensional semiconductor material (two-dimensional MoS2 layer) with a wrinkled structure, as shown in FIG. Figure 2 As shown in c.

[0089] (IX) Fabricating metal Cr / Au electrodes on the corresponding two-dimensional semiconductor material using photolithography. Specifically, laser direct writing is used for precise positioning and exposure, metal layer deposition, and acetone is used to dissolve the photoresist to remove excess metal, thereby fabricating metal Cr / Au electrodes on the two-dimensional material layer with a wrinkled structure.

[0090] Comparative Example 1

[0091] This comparative example prepares a transistor. The difference from Example 1 is that the cooling method of the stacked structure is different, specifically:

[0092] (VII) Separate the glass slide and the PET layer, and naturally cool the silicon substrate, the two-dimensional MoS2 layer, and the PET layer from a high temperature (110°C) to room temperature (cooling time is 10 to 30 minutes), place them in dichloromethane at room temperature, let them stand for 6 hours to fully dissolve the PET layer, and then remove the silicon substrate (containing the two-dimensional MoS2 layer).

[0093] Test example

[0094] This test example tests the microstructure and electrical characteristics of the two-dimensional material layer and transistor prepared in the examples and comparative examples, specifically:

[0095] The microstructure of the two-dimensional MoS2 layer obtained in step Ⅰ of Example 1 was tested using an optical microscope. Figure 1 .

[0096] The microstructure of the two-dimensional MoS2 layer obtained in step VIII of Example 1 was tested using a scanning electron microscope and an atomic force microscope. Figure 3 .Depend on Figure 3 It can be seen that some wrinkle structures are formed on the two-dimensional MoS2.

[0097] The electrical characteristics of the memory device obtained in Example 1 were tested using a probe station and a semiconductor analyzer:

[0098] 1) Apply pulse voltages of different amplitudes (20V to 80V) to the gate electrode of the memory device. The current response characteristics test results of the device are as follows: Figure 5 As shown in the figure, specifically: pulse voltages of different amplitudes (from 20V to 80V) are applied to the gate electrode of the device, and the source-drain current of the device is tested when the gate voltage is removed. The device current conductance decreases under positive gate voltage and increases under positive gate voltage, and the increase and decrease amplitudes are related to the applied pulse amplitude, proving that the device has a storage function. Figure 5 It can be seen that the switching ratio of the device reaches 10 6 , and exhibits multi-bit storage characteristics.

[0099] 2) Apply pulse voltages of the same amplitude but different times to the gate electrode of the memory device. The current response characteristics test results of the device are as follows: Figure 6 As shown, specifically: pulse voltages of the same amplitude are applied to the gate electrode of the device in sequence, and the source-drain current of the device is tested when the gate voltage is removed. The device current conductivity decreases under a positive gate voltage and increases under a positive gate voltage, and the increase and decrease amplitudes are related to the number of applied pulses, proving that the device has storage characteristics.

[0100] 3) Pulse voltages of the same amplitude but different frequencies are applied to the gate electrode of the memory device. The current response characteristics test results of the device are as follows: Figure 7 As shown, specifically: a pulse voltage of the same amplitude is applied to the gate electrode of the device, and the pulse frequency is changed, and the source-drain current of the device is tested when the gate voltage is removed. The device current conductance decreases under a positive gate voltage and increases under a positive gate voltage, and the increase and decrease amplitudes are related to the applied pulse frequency, proving that the device has storage characteristics.

[0101] The microstructure of the two-dimensional MoS2 layer obtained in step VII of comparative example 1 was tested using a scanning electron microscope. Figure 8 .

[0102] The transfer characteristic curve of the transistor prepared from the wrinkle-free two-dimensional semiconductor material obtained in Comparative Example 1 is tested. The test results are as follows: Figure 9 As shown, there is no obvious hysteresis phenomenon in the cyclic scanning of the curve. Therefore, the device prepared using wrinkle-free two-dimensional semiconductor materials does not have storage characteristics.

[0103] Therefore, by comparing the test results of Example 1 and Comparative Example 1, it can be seen that the sudden cooling treatment of the stacked structure affects the formation of wrinkles, and no wrinkle structure will be formed when the stacked structure is naturally cooled from high temperature to room temperature, and the device prepared from the wrinkle-free sample does not have storage characteristics.

[0104] In summary, the present invention uses a two-dimensional semiconductor material prepared by chemical synthesis as an active layer, uses a polymer layer to transfer it, and controls the rapid cooling process of the transfer step. Since the thermal expansion coefficients of the polymer layer used are different from those of the substrate, tensile and compressive stresses will be formed on the two-dimensional semiconductor material during the rapid cooling process, and finally a wrinkle structure will be formed on the two-dimensional semiconductor material. The obtained two-dimensional semiconductor material with a wrinkle structure is prepared into a transistor device (memory device). The performance is characterized by a semiconductor analyzer, and through comparative experiments, it is found that due to the presence of the wrinkles, the prepared memory device has multiple controllable resistance states, a large storage window, a high switching ratio, and excellent device stability and repeatability. In addition, the memory device has two characteristics of linear and nonlinear resistance state changes (the device exhibits linear resistance change characteristics at a voltage of 40V. The device exhibits nonlinear resistance change characteristics at a voltage of 80V). The present invention uses wrinkles in two-dimensional semiconductor materials to construct memory devices, which has certain significance for the future development of flexible ultra-thin electronic devices, big data algorithms and artificial intelligence fields.

[0105] The straining mechanism of the two-dimensional material described herein involves heat treatment and rapid cooling, which can form nanoscale wrinkled structures. For example, in some embodiments, wrinkles approximately 300 nm wide and 3 nm high can be formed. The polymer layer employed in the present invention is typically a high-molecular-weight polymer (such as PET), which exhibits enhanced thermal stability. Therefore, the heat treatment and rapid cooling processes only induce nanoscale strain in the two-dimensional material. Furthermore, the polymer layer described herein exhibits enhanced adhesion to the two-dimensional material layer, enabling easier control of the microstructure of the two-dimensional material layer.

[0106] The present invention can realize the formation of nano-scale wrinkled structure on the two-dimensional material layer, and the preparation method is simple and easy; and the formation of the wrinkled structure is conducive to the use of semiconductor two-dimensional materials to construct storage devices: the two-dimensional semiconductor material has a wrinkled structure, and the wrinkled carriers are bound to prepare high-performance storage devices on the two-dimensional semiconductor material to realize the storage function of the device. It is a new way to realize high-performance controllable storage devices, which is simple and easy.

[0107] The present invention utilizes a polymer layer to transfer a two-dimensional material layer, and then introduces a heat treatment process to create wrinkles within the two-dimensional material layer. This preparation method is universal and widely applicable. Compared to existing storage devices implemented using other methods, the present invention offers a simpler preparation method and a simpler storage device structure. It can achieve storage functionality using only a single layer of material, further improving the system's integration capabilities.

[0108] It should be noted that, unless otherwise specified, “normal temperature” or “room temperature” herein refers to approximately 25° C.; and “about” or “approximately” for numerical values ​​herein means an error of ±2%.

[0109] While the embodiments of the present invention have been described in detail above with reference to the accompanying drawings, the present invention is not limited to the embodiments described above. Various modifications may be made within the scope of knowledge possessed by a person skilled in the art without departing from the spirit of the present invention. Furthermore, the embodiments of the present invention and the features thereof may be combined with one another unless there is a conflict.

Claims

1. A memory device, characterized in that: The storage device includes a substrate, on which is provided a two-dimensional material layer with a wrinkled structure, wherein the two-dimensional material layer is transferred to the substrate through a polymer layer, and the formation process of the wrinkled structure includes the following steps: making the two-dimensional material layer adhere between the polymer layer and the substrate, first subjecting it to heat treatment, and then to sudden cooling treatment, wherein the polymer layer and the substrate have different thermal expansion coefficients.

2. The memory device according to claim 1, wherein: The heat treatment and quenching treatment process includes heating the stacked structure consisting of the polymer layer, the two-dimensional material layer and the substrate to a temperature T1, and then cooling it to a temperature T2 within a time t1, wherein T1 = 50 ~ 300 ° C, T2 = (-20) ~ 40 ° C, and t1 ≤ 1 min.

3. The memory device according to claim 1, wherein: The two-dimensional material layer includes a semiconductor material.

4. The memory device according to claim 1, wherein: The two-dimensional material layer includes at least one of two-dimensional MoS2, WS2, WSe2 or h-BN.

5. The memory device according to claim 1, wherein: The memory device is a transistor, and the two-dimensional material layer is a two-dimensional semiconductor material.

6. The memory device according to claim 5, wherein: The two-dimensional semiconductor material includes two-dimensional MoS2, the substrate is a silicon substrate, and the silicon substrate is SiO2 / Si.

7. The memory device according to claim 1, wherein: The thickness of the two-dimensional material layer is h = 0.7~50 nm.

8. The memory device according to claim 7, wherein: The thickness of the two-dimensional material layer is h = 0.7~10 nm.

9. The memory device according to claim 1, wherein: The two-dimensional material layer includes a plurality of two-dimensional material sheets, and the sheet diameter r of the two-dimensional material sheet is 1 to 1000 μm.

10. The memory device according to claim 1, wherein: The substrate includes at least one of a silicon substrate, gold, tungsten, copper, graphene or ITO.

11. The memory device according to claim 10, wherein: The silicon substrate is SiO2 / Si.

12. The memory device according to claim 1, wherein: The polymer layer includes polyethylene terephthalate.

13. The memory device according to claim 12, wherein: The surface roughness of the polymer layer is less than 10 nm.

14. The memory device according to claim 1, wherein: A metal electrode is arranged on the two-dimensional material layer.

15. The memory device according to claim 14, wherein: The metal electrode includes at least one of Cu, Cr, Ti, Au, Pd or Ni.

16. A method for preparing a memory device according to any one of claims 1 to 15, characterized in that: The preparation method includes the steps of forming a wrinkle structure on a two-dimensional material layer: laminating the two-dimensional material layer between a polymer layer and a substrate, first subjecting the layer to a heat treatment, and then subjecting the layer to a quenching treatment to form a wrinkle structure on the two-dimensional material layer.

17. The method for preparing a memory device according to claim 16, wherein: The preparation method further comprises removing the polymer layer after the wrinkled structure is formed.

18. The method for preparing a memory device according to claim 17, wherein: The polymer layer can be removed by dissolving it with a solvent.

19. The method for preparing a memory device according to claim 18, wherein: The removal by solvent dissolution is as follows: the heat-treated stacked structure is quickly placed in a solvent at a temperature of T3 for quenching, and the polymer layer is removed by solvent dissolution for a time t2, wherein T3 = (-25) ~ 40 °C and t2 = 6 ~ 10 h.

20. The method for preparing a memory device according to claim 16, wherein: The preparation method further comprises: S1, preparing a two-dimensional material layer on a growth substrate by chemical vapor deposition; S2, laminating the polymer layer on the two-dimensional material layer and heating the two-dimensional material layer to transfer the two-dimensional material layer from the growth substrate to the polymer layer; S3, laminating the side of the two-dimensional material layer facing away from the polymer layer to the surface of the substrate to obtain a stacked structure consisting of the polymer layer, the two-dimensional material layer and the substrate.

21. Application of the storage device according to any one of claims 1 to 15 in the fields of electronic devices, big data algorithms, or artificial intelligence technology.

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