A load modulation balanced power amplifier and self-matching implementation method

Abstract

The present invention discloses a load-modulated balanced power amplifier and a self-matching implementation method, which includes a power divider, a phase compensation network, an input 3-dB orthogonal coupler, a balanced amplifier, a control amplifier and an output 3-dB orthogonal coupler; the balanced amplifier includes two upper and lower balanced sub-amplifiers; the present invention realizes the control of the output current size and relative phase of the control power amplifier and the balanced power amplifier by adaptively changing the gate bias size of the balanced amplifier according to the input power size, so as to achieve the purpose of impedance matching of the saturation point and the back-off point, and the phase compensation network increases the working bandwidth of the circuit, and solves the problems of complex traditional operations and discontinuous results. In the application background of the load-modulated balanced amplifier, the present invention adopts adaptive dynamic bias and impedance self-matching technology, which has the advantages of simple structure, strong practicality and easy promotion.

Description

Technical Field

[0001] The present invention belongs to the field of radio frequency microwave communication, and relates to a load modulation balanced power amplifier and a self-matching implementation method, in particular to a load modulation balanced amplifier design that realizes automatic impedance matching by dynamic bias voltage control. Background Art

[0002] In the field of mobile communications, in order to improve the spectrum utilization of limited frequency bands and transmit as much data as possible, RF transceiver systems usually need to perform complex modulation on the data, which makes the signals of modern communication systems usually have a very high peak-to-average power ratio (PAPR). Traditional linear amplifiers have an undistorted amplification effect for constant envelope signals, but the amplification efficiency is very low for signals with high peak-to-average power ratios with drastic envelope changes. Therefore, in order to ensure the overall efficiency of the transmitter, it is generally required that the power amplifier can operate within a larger power dynamic range, that is, maintain high efficiency in the saturation and back-off ranges. In recent years, research on load-modulated amplifiers for high peak-to-average power ratio signal applications has been very hot, and load-modulated amplifiers represented by Doherty and Outphasing structures have gradually become the mainstream of industry applications. However, the above amplifiers can usually only work in narrowband.

[0003] Recently, the industry has proposed a new load modulation amplifier, namely the load modulated balanced amplifier (LMBA). Similar to the above two amplifiers, the load modulation balanced amplifier can achieve high-efficiency amplification of the modulated signal when the power is backed off, and has a certain broadband effect, so it has attracted strong attention from researchers of RF microwave power amplifiers. The working principle of this load modulation type amplifier is to decompose the modulated signal into two orthogonal signals with equal amplitudes (90 degrees phase difference) by inputting a 3-dB orthogonal coupler, and inject the additional control signal into the isolation port of the output 3-dB orthogonal coupler to achieve load impedance modulation of the through end and the coupled end of the output 3-dB orthogonal coupler. After passing through a 3-dB orthogonal coupler, the phase of the modulated signal at the output port is consistent, and it is superimposed on the output port together with the power of the control signal.

[0004] Traditional load-modulated balanced amplifiers require a separate control signal to connect the isolated port of the output 3-dB orthogonal coupler, and at the same time, the impedance is modulated by changing the amplitude and phase of the control signal, which increases the complexity of the operation to a certain extent. Based on the above background, the present invention proposes a new load-modulated balanced amplifier architecture, which converts the original dual-input signal into a single-input signal, and the control amplifier can still play a load modulation role and fit the optimal impedance trajectory curve as much as possible. By adjusting the circuit bias, the impedance of the circuit saturation and fallback states is automatically matched, thereby eliminating the need for a complex output matching structure. This design scheme also improves the linearity and gain stability of the circuit, is flexible in operation, and has a simple structure. Summary of the invention

[0005] One purpose of the present invention is to propose a load modulation balanced power amplifier to solve the problem of complex control signal operation in traditional load modulation balanced amplifiers. This theory innovates the dual-input structure of traditional load modulation balanced amplifiers. Based on the change law of the impedance trajectory curve, the amplitude and phase modulation of the control signal in load modulation are realized by setting the power distribution ratio of the power divider and the bias voltage. The impedance matching in different states is achieved through flexible adjustment of the bias, which has the advantages of simple operation and easy promotion.

[0006] A load-modulated balanced power amplifier comprises a power divider, a phase compensation network, an input 3-dB quadrature coupler, a balanced amplifier, a control amplifier and an output 3-dB quadrature coupler; the balanced amplifier comprises upper and lower balanced sub-amplifiers;

[0007] The power divider is used to distribute the power of a single input signal source to the balanced amplifier and the control amplifier; the input power provided to the control amplifier should be greater than the power flowing into the input ends of the upper and lower balanced sub-amplifiers, so that the control amplifier is saturated early;

[0008] The phase compensation network is used to adjust the output current phase difference between the control amplifier and the balance amplifier through the phase value that changes with the frequency, so that the modulation impedance trajectory always falls within the optimal value area of ​​load pulling, and provides a changing phase compensation value at different frequencies to fit the optimal impedance trajectory curve.

[0009] Preferably, the characteristic impedance of the phase compensation network is 50 ohms, and the phase variation range within the working frequency band is higher than that provided by a single series transmission line, which can meet the current relative phase requirements at different frequencies. When the termination impedance is 50 ohms, no reflection will be generated, and different phase compensation effects will only be generated for the signal of the input coupler at different frequencies.

[0010] The input end of the input 3-dB orthogonal coupler is connected to the output end of the phase compensation network, and the through end and the coupling end are respectively connected to the input end of the upper balanced amplifier and the input end of the lower balanced amplifier; the isolation end is connected to a 50 ohm resistor R3;

[0011] The input end of the output 3-dB orthogonal coupler is connected to a 50-ohm load R5, the through end and the coupling end are respectively connected to the output end of the down-channel balanced amplifier and the output end of the up-channel balanced amplifier, and the isolation end is connected to the output end of the control amplifier;

[0012] The input 3-dB quadrature coupler and the output 3-dB quadrature coupler make the phases of the two balanced sub-amplifiers consistent at the output port of the load modulated balanced power amplifier;

[0013] Preferably, the input 3-dB orthogonal coupler and the output 3-dB orthogonal coupler both adopt a two-stage bridge structure, which facilitates the connection of each power amplifier and avoids cross-line, while increasing the bandwidth of the coupler;

[0014] The upper and lower balanced sub-amplifiers have the same structure and are completely equal in size, and both include a balanced amplifier input matching circuit, an RC stabilization circuit, an adaptive bias control circuit, a transistor P2, a drain bias circuit, and a DC blocking capacitor C8; the input end of the balanced amplifier input matching circuit serves as the input end of each balanced sub-amplifier, and the output end is connected to the input end of the RC stabilization circuit, and the output end of the RC stabilization circuit is connected to the gate of the transistor; the input end of the adaptive bias control circuit is connected to a DC power supply, and the output end is connected to the gate of the transistor; the input end of the drain bias circuit is connected to a DC power supply, and the output end is connected to the drain of the transistor and then connected to one end of the DC blocking capacitor C8, and the other end of the DC blocking capacitor C8 serves as the output end of each balanced sub-amplifier;

[0015] The control amplifier comprises a control amplifier input matching circuit, an RC stabilization circuit, a gate bias circuit, a transistor P1, a drain bias circuit, a control amplifier output matching circuit, and a DC blocking capacitor C3; the input end of the control amplifier input matching circuit serves as the input end of the control amplifier, the output end of the control amplifier input matching circuit is connected to the input end of the RC stabilization circuit, and the output end of the RC stabilization circuit is connected to the gate of the transistor P1; the input end of the gate bias circuit is connected to a DC power supply, and the output end is connected to the output end of the RC stabilization circuit; the input end of the control amplifier output matching circuit is connected to one end of the drain bias circuit and then connected to the drain of the transistor P1, the other end of the drain bias circuit is connected to the DC power supply, the output end of the control amplifier output matching circuit is connected to one end of the DC blocking capacitor C3, and the other end of the DC blocking capacitor C3 serves as the output end of the control amplifier and is connected to the isolation end of the output 3-dB orthogonal coupler;

[0016] The balanced amplifier input matching circuit and the control amplifier input matching circuit are designed using a low-pass filter matching design method, and the low Q value design improves the circuit bandwidth;

[0017] The RC stabilization circuit is composed of a parallel RC circuit and is used to improve the stability of the amplifier and avoid self-excitation during the actual test process;

[0018] The adaptive bias control circuit is used to dynamically adjust the gate bias voltage according to the input power.

[0019] Preferably, the adaptive bias control circuit comprises a resistor R6, a grounding capacitor C9, a series microstrip line L17, a diode, a grounding capacitor C10 and a grounding resistor R7; one end of the resistor R6 is connected to a DC power supply V Gs , the other end is connected to one end of the grounding capacitor C9 and one end of the series microstrip line L17. The other end of the series microstrip line L17 is connected to the cathode of the diode, and then the output end of the RC stabilization circuit is connected to the gate of the transistor. The anode of the diode is connected to one end of the grounding capacitor C10 and one end of the grounding resistor R7. The other end of the other end of the grounding capacitor C9, the other end of the grounding capacitor C10 and the other end of the grounding resistor R7 are grounded.

[0020] The gate bias circuit of the control amplifier biases the control transistor P1 to class AB;

[0021] The gate bias voltage of the balanced amplifier is dynamically adjusted with the input power to achieve automatic matching of the load impedance in the back-off and saturation states.

[0022] The through-end and coupled-end impedances of the output 3-dB quadrature coupler are also balanced amplifier load impedances, and their relationship with the amplitude and phase of the control amplifier is:

[0023]

[0024]

[0025] Among them I c is the current flowing from the output of the control amplifier into the output 3-dB quadrature coupler isolation terminal, I b is the current flowing from the output of the balanced amplifier into the through-end or coupled end of the output 3-dB orthogonal coupler, φ is the relative phase between the current at the isolation end of the output 3-dB orthogonal coupler and the current at the through-end of the output 3-dB orthogonal coupler, Z b represents the load impedance of the balanced amplifier, θ represents the phase of the reflection coefficient of the load impedance of the balanced amplifier, Z0 represents the characteristic impedance of the output 3-dB orthogonal coupler, and j represents a complex number;

[0026] From the above equations (1)-(2), it is found that the modulation of the load impedance of the balanced amplifier is mainly affected by the current ratio I c / I b and the influence of relative phase φ. Under the single input structure proposed by the present invention, φ can be considered as unchanged, so the research on load impedance modulation of balanced amplifier turns to the main variable I c / I b By observing formulas (1)-(2), it can be found that the current ratio I c / I b The change of reflects both the amplitude and phase modulation of the impedance. Therefore, the current ratio I can be adjusted by adjusting the power divider and the bias voltage. c / I b of control to achieve the impedance matching effect of the back-off point and the saturation point.

[0027] Another object of the present invention is to provide a method for realizing self-matching of a load-modulated balanced power amplifier, which is characterized by being realized by the following steps:

[0028] Step 1: Design an RC stabilization circuit and continuously adjust the values ​​of resistors R4, R2 and capacitors C2, C7 so that the stability parameter is greater than 1 in the full frequency band;

[0029] Step 2: According to the set operating frequency and bias size, determine the input and output impedance of the control amplifier transistor and the optimal input impedance of the balance amplifier transistor for subsequent matching;

[0030] Step 3: Design the control amplifier input matching circuit, control amplifier output matching circuit, and balanced amplifier input matching circuit according to the transistor saturation impedance;

[0031] Step 4: Design an input 3-dB orthogonal coupler and an output 3-dB orthogonal coupler, wherein the phases of the through end and the coupling end of the input 3-dB orthogonal coupler and the output 3-dB orthogonal coupler are 90 degrees apart, and the amplitudes of the two signals are equal; the isolation port of the input 3-dB orthogonal coupler is connected to a 50-ohm resistor, and the input port of the output 3-dB orthogonal coupler is connected to a 50-ohm load;

[0032] Step 5: Design a power divider with three-port impedance of 50 ohms. The power divider divides the single input signal into two signals unequally. The specific power division ratio is determined according to the debugging results. The two signals are respectively sent to the input port of the control amplifier and the input port of the phase compensation network connected to the input 3-dB orthogonal coupler;

[0033] Step 6: Design an adaptive bias control circuit. The forward diode rectifies the input power flowing into the gate of the transistor and converts it into a change in gate voltage through the series resistor R6.

[0034] Step 7: Combine and debug the debugged control amplifier input matching circuit, control amplifier output matching circuit, balanced amplifier input matching circuit, RC stabilization circuit, adaptive bias control circuit, transistors P1 and P2, input 3-dB orthogonal coupler, output 3-dB orthogonal coupler and power divider, and then fit the optimal impedance trajectory of load pulling by changing the impedance. Specifically:

[0035] 1) Saturated load impedance of transistor P2

[0036] In the case of single input, in order to improve the impedance in the low power area, P control / P balance is greater than the threshold a, where a is a value set by experience of technicians in this field, and a>1. control Indicates the output power of the control amplifier, P balance Indicates the output power of the balanced sub-amplifier, requiring the control amplifier to saturate early and the balanced sub-amplifier to start late. Therefore, the control amplifier is first biased in class AB and the two balanced sub-amplifiers are biased in class C. On this basis, the output current I of the control amplifier is analyzed. c and balance sub-amplifier output current I b changes.

[0037] Assuming an ideal linear model for the amplifier current, the current is normalized according to the drive level:

[0038]

[0039]

[0040] To simplify the description, the ratio β is set to I b,max / I c,max , I c,max Indicates the maximum value of the control amplifier output current, I b,max It represents the maximum value of the output current of the balanced sub-amplifier, k1 represents the driving level when P2 is turned on, and k2 represents the driving level when P1 is saturated. In general, k1≤k2.

[0041] When the control amplifier and the two balanced sub-amplifiers are saturated, the output power of the entire circuit reaches the maximum value, and the corresponding saturated load impedance Z b,sat It can be expressed as:

[0042]

[0043] Where θ represents the phase of the reflection coefficient of the balanced amplifier load impedance, Z0 represents the characteristic impedance of the output 3-dB orthogonal coupler, and j represents a complex number;

[0044] Total output power Pall It is the sum of the output power of the control amplifier and the two-way balanced sub-amplifier. The general expression is:

[0045]

[0046] Among them I c Represents the control amplifier output current; I b Represents the output current of the balanced sub-amplifier, Re(Z b ) represents the load impedance Z b The real part of .

[0047] Simplifying the above formula (6), we can get the total saturated output power P sat :

[0048]

[0049] The expression of total saturated output power is only related to the parameters β and φ. According to the transistor datasheet, the total power P of transistors P1 and P2 can be obtained. sat Under this goal, the rationality and efficiency of the comprehensive data are maximized, and the optimal values ​​of β and φ are repeatedly compared with the results of load traction. When the values ​​of β and φ are determined, the saturated load impedance Z can be obtained. b,sat .

[0050] 2) The back-off impedance of transistor P2

[0051] Defined that β remains unchanged during the entire modulation process, the value of φ can be considered unchanged, so as to further analyze the low-power stage of P2. At the moment when the drive level is k2, transistor P1 is just saturated, and the output current of the control amplifier reaches the maximum value I c,max , balance sub-amplifier output current The modulated back-off point load impedance Z b,back for:

[0052]

[0053] The total output power of the control amplifier and the balanced amplifier in the back-off state can be obtained as:

[0054]

[0055] The fallback range can be compared by P sat and P back Find:

[0056]

[0057] Given OBO, P back It can be determined that only This monomial is unknown. By solving formula (10), we can get Z b,back To ensure that Z obtained in this way b,back It is achievable. Analyze the load impedance Z at the back-off point. b,back The real and imaginary parts of :

[0058]

[0059] The real part of the impedance must be a positive number to have actual physical meaning, so the implicit constraint of equation (11) is:

[0060]

[0061] This is equivalent to the minimum back-off power being the saturated control power, which also conforms to I c and I b The physical meaning of the current model.

[0062] 3) By changing the gate voltage through the adaptive bias control circuit, the output current size and relative phase of the control amplifier and the balance amplifier can be controlled to ensure Z b,sat and Z b,back The matching can maintain high efficiency in the fallback state and obtain high output power and high efficiency in saturation.

[0063] Step 8: Design a phase compensation network based on the relative phase difference between the two currents of the control amplifier and the balanced amplifier at different frequencies, and then further combine the phase compensation network with the network in step 7 above to debug the complete circuit.

[0064] The working principle of the impedance self-matching load modulation balanced power amplifier proposed in the present invention is as follows: by controlling the power division ratio and the adaptive bias control circuit, the control amplifier is saturated in advance, and the impedance reflection coefficient amplitude is increased at low power, so as to achieve the purpose of increasing the load impedance at low power and thus improving the efficiency. As the output power of the balanced amplifier gradually increases, I c / I b The value of decreases, which makes the reflection coefficient amplitude of the load impedance decrease and the phase gradually increase, which conforms to the impedance trajectory law obtained by load pulling. This is also the general practice of single-input load modulation balanced amplifier. Since the impedance matching at low power and the impedance matching at saturation are both related to the gate bias of the balanced amplifier, the control of the adaptive gate bias can not only achieve impedance matching in these states, but also improve the gain linearity of the circuit.

[0065] The beneficial effects of the present invention are as follows: utilizing the power-to-current variation ratio, adopting an adaptive bias control circuit to achieve modulation of impedance amplitude and phase, replacing the traditional dual-input structure. The phase compensation network connected to the input end of the input 3-dB orthogonal coupler is used to compensate for the dispersion effect of the microstrip line. In the case of broadband matching, the bandwidth of the circuit is only affected by the coupler. The design of the two-stage bridge further improves the bandwidth of the circuit. The modulation of the balanced amplifier impedance does not require the participation of the output matching network, achieving the purpose of load modulation and simplifying the overall circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 It is a structural schematic diagram of the impedance self-matching load modulation balanced power amplifier in the present invention.

[0067] Figure 2 It is a schematic diagram of the structure of the phase compensation network in the present invention and the simulation of phase shift using simulation software.

[0068] Figure 3 It is a schematic diagram of the adaptive bias control circuit in the present invention and the use of simulation software to simulate the dynamic adjustment of the gate voltage with input power.

[0069] Figure 4 It is a schematic diagram of simulating the amplifier modulation impedance trajectory of the present invention within a wide frequency band (3.4 GHz-3.9 GHz) using simulation software.

[0070] Figure 5 It is a schematic diagram of the results of simulating the present invention in a wide frequency band (3.4 GHz-3.9 GHz) using simulation software. DETAILED DESCRIPTION

[0071] The following are specific embodiments of the present invention and the accompanying drawings to further describe the technical solution of the present invention, but the present invention is not limited to these embodiments.

[0072] Figure 1 The structure diagram of the impedance self-matching load modulation balanced power amplifier in the present invention is shown, and the power amplifier includes a power divider, a phase compensation network, two balanced sub-amplifier circuits, one control amplifier circuit and two 3-dB orthogonal couplers. The balanced sub-amplifier circuit includes a broadband input matching circuit, an RC stabilization circuit, an adaptive bias control circuit, a drain bias circuit and a DC blocking capacitor; the control amplifier circuit includes a broadband input matching circuit, an RC stabilization circuit, a gate bias circuit, a broadband output matching circuit, a drain bias circuit and a DC blocking capacitor.

[0073] The power divider is a Wilkinson power divider with a more compact structure. It specifically includes a microstrip line L1, a microstrip line L2 and a resistor R1; one end of the microstrip line L1 is connected to one end of the microstrip line L2 and then connected to a single input signal source, the other end of the microstrip line L1 is connected to one end of the resistor R1 and then connected to a control amplifier; the other end of the microstrip line L2 is connected to the other end of the resistor R1 and then connected to the input end of the phase compensation network.

[0074] The phase compensation network adopts a structure of a combination of microstrip lines and capacitors. Figure 2 As shown, the relative phase φ of the two currents is changed; at different frequencies, a variable phase compensation value is provided to fit the optimal impedance trajectory curve. It specifically includes a series microstrip line L3, a series capacitor C4, a parallel short-circuited microstrip line L4, a series capacitor C5 and a series microstrip line L5; one end of the series microstrip line L3 is connected to a signal output by the power divider, the other end of the series microstrip line L3 is connected to one end of the series capacitor C4, the other end of the series capacitor C4 is connected to one end of the parallel short-circuited microstrip line L4 and one end of the series capacitor C5, the other end of the series capacitor C5 is connected to one end of the series microstrip line L5, the other end of the series microstrip line L5 is connected to the input end of the input 3-dB orthogonal coupler, and the other end of the parallel short-circuited microstrip line L4 is grounded.

[0075] The 3-dB orthogonal coupler is a two-stage 3-dB orthogonal coupler, and the multi-stage structure further improves the bandwidth range. The structural order of the input coupler is microstrip line L6, microstrip line L7, microstrip line L8, microstrip line L9, microstrip line L10, microstrip line L11 and microstrip line L12; the structural order of the output 3-dB orthogonal coupler is microstrip line L28, microstrip line L29, microstrip line L30, microstrip line L31, microstrip line L32, microstrip line L33 and microstrip line L34;

[0076] One end of the microstrip line L6 is connected to one end of the microstrip line L7, and the connection is connected to the output end of the phase compensation network, that is, the output end of the series microstrip line L5; the other end of the microstrip line L7 is connected to one end of the microstrip line L8 and the microstrip line L10, and the other end of the microstrip line L10 is connected to the microstrip line L11, and the connection is the coupling port of the coupler, which is connected to the input end of a balanced amplifier; the other end of the microstrip line L11 is connected to the microstrip line L12, and the connection is the through end of the coupler, which is connected to the input end of another balanced amplifier; the other end of the microstrip line L12 is connected to the other end of the microstrip line L8 and then connected to one end of the microstrip line L9, and the other end of the microstrip line L9 is connected to the other end of the microstrip line L6, and a 50-ohm resistor R3 is connected to the interface, and the other end of R3 is grounded;

[0077] One end of microstrip line L28 is connected to microstrip line L29; the other end of microstrip line L29 is connected to microstrip line L30 and one end of microstrip line L32, the other end of microstrip line L32 is connected to microstrip line L33, and is also connected to the output end of the control amplifier; the other end of microstrip line L33 is connected to microstrip line L34, and the connection point is connected to a 50 ohm load R5, and the other end of R5 is grounded; the other end of microstrip line L34 is connected to the other end of microstrip line L30 and then to one end of microstrip line L32, and the other end of microstrip line L31 is connected to the other end of microstrip line L28.

[0078] The broadband input and output matching circuits are constructed by using a low-Q Chebyshev step broadband matching method. In order to make the structure more universal and solve the frequency limitation problem of lumped components, a series low-impedance microstrip line is used to replace the series inductor, and a series high-impedance microstrip line is used to replace the parallel capacitor, and finally a microstrip line structure with alternating high and low impedance is formed. The matching circuit structure of all series microstrip lines simplifies the layout while expanding the bandwidth.

[0079] The control amplifier broadband input matching circuit has a structure sequence of a series capacitor C1, a series microstrip line L19, a series microstrip line L20 and a series microstrip line L21; the input end of the series DC blocking capacitor C1 is connected to the connection point of the microstrip line L1 and the resistor R1. The output end of the series DC blocking capacitor C1 is connected to the input end of the series microstrip line L19, the output end of the series microstrip line L19 is connected to the series microstrip line L20, the other end of the series microstrip line L20 is connected to the input end of the series microstrip line L21, and the other end of the series microstrip line L21 is connected to the input end of the RC stabilization circuit.

[0080] The control amplifier RC stabilization circuit is composed of parallel resistors and capacitors, and lossy components are added to the transistor input end, thereby improving the stability of the amplifier.

[0081] The control amplifier gate bias circuit biases the transistor to class AB and is composed of a parallel microstrip line with one end connected to the power supply and ground and the other end connected to the input end of the RC stabilization circuit, and is used to provide a gate bias voltage.

[0082] The structural order of the control amplifier broadband output matching circuit is a series microstrip line L24, a series microstrip line L25, a series microstrip line L26, and a series microstrip line L27; the drain of the control amplifier transistor P1 is connected to the input end of the series microstrip line L24, the output end of the series microstrip line L24 is connected to the input end of the series microstrip line L25, the other end of the series microstrip line L25 is connected to the series microstrip line L26, the output end of the series microstrip line L26 is connected to the input end of the series microstrip line L27, the output end of the series microstrip line L27 is connected to the series DC blocking capacitor C3, and the output end of the series DC blocking capacitor C3 is simultaneously connected to the output 3-dB orthogonal coupler microstrip line L32 and the microstrip line L33.

[0083] The control amplifier drain bias circuit is composed of a parallel microstrip line with one end connected to the power supply and ground and the other end connected to the drain of the transistor P1, and is used to provide a drain DC voltage.

[0084] The structure sequence of the balanced amplifier broadband input matching circuit is a series capacitor C6, a series microstrip line L13, a series microstrip line L14, a series microstrip line L15 and a series microstrip line L16; the input end of the series DC blocking capacitor C6 is connected to the connection point of the microstrip line L10 and the microstrip line L11, and the input end of the balanced amplifier DC blocking capacitor C6 is connected to the connection point of the microstrip line L11 and the microstrip line L12. The output end of the series DC blocking capacitor C6 is connected to the input end of the series microstrip line L13, the output end of the series microstrip line L13 is connected to the series microstrip line L14, the other end of the series microstrip line L14 is connected to the input end of the series microstrip line L15, the output end of the series microstrip line L15 is connected to the series microstrip line L16, and the other end of the series microstrip line L16 is connected to the input end of the RC stabilization circuit.

[0085] The structure sequence of the balanced amplifier adaptive bias control circuit is resistor R6, grounding capacitor C9, series microstrip line L17, diode, grounding capacitor C10 and grounding resistor R7; one end of resistor R6 is connected to a DC power supply, the other end is connected to the other end of grounding capacitor C9 and then connected to series microstrip line L17, the other end of L17 is connected to the cathode of the diode, the anode of the diode is connected to the other end of the grounding capacitor C10 and the grounding resistor R7. The node where the microstrip line L7 is connected to the cathode of the diode is simultaneously connected to the output end of the stabilization circuit and the gate of the transistor.

[0086] The drain of the balanced amplifier transistor P2 is connected to the input end of the DC blocking capacitor C8, the other end of C8 is connected to the junction of the microstrip line L28 and the microstrip line L29, and the output end of the other DC blocking capacitor C8 is connected to the microstrip line L28 and the microstrip line L31. The transistor type, bias size and matching structure of the two balanced amplifiers are exactly the same.

[0087] When the load-modulated balanced amplifier is designed to operate in the 3.4GHz-3.9GHz frequency band, the gate bias size is changed through an adaptive bias control circuit, so that the output current ratio of the control power amplifier and the balanced power amplifier can be controlled, and automatic matching of the output impedance can be achieved, so that high-efficiency output can be achieved in a wider dynamic range.

[0088] The above-mentioned design method of an impedance self-matching load modulation balanced power amplifier is implemented by the following steps:

[0089] Step 1: Design an RC stabilization circuit, and continuously adjust the values ​​of the resistor and capacitor so that the stability parameter is greater than 1 in the full frequency band. Specifically, the circuit simulation software can be used to analyze and compare the amplifier stability before and after adding the RC stabilization circuit. In this example, the control amplifier selects a 50 ohm resistor and a 2.5pF capacitor in parallel as the final form of the stabilization circuit, and the balanced amplifier selects a 50 ohm resistor and a 4pF capacitor in parallel as the final form of the stabilization circuit.

[0090] Step 2: Determine the input and output impedance of the transistor for subsequent matching. The specific method is: use the scalable transistor model in the GaN_HEMT process provided by the foundry company and the previously designed stable circuit to bring it into the load-pull and source-pull templates of the specific circuit simulation software, select the compromise frequency point in the entire working frequency band, and obtain the optimal range of input impedance, output impedance, and output impedance at power back-off. At the same time, it is observed that as the frequency increases, the phase of the balanced amplifier output impedance reflection coefficient becomes larger and larger, and the impedance trajectory is closer to the real axis. This is the theoretical basis for our subsequent design of the phase compensation network.

[0091] Step 3: Use the optimal input impedance obtained in step 2 to make a broadband input matching circuit. The input matching circuit uses a microstrip line with alternating high and low impedance, and presents a step-type broadband matching path on the Smith diagram to achieve broadband matching. The specific method is to use Chebyshev and other well-known matching techniques to match the capacitors and inductors, and then use Richards transformation to solve the impedance and electrical length of the microstrip line.

[0092] Step 4: Design a two-stage 3-dB orthogonal coupler, requiring the coupling degree to be close to -3dB within the working frequency band, the isolation degree to be less than -20dB within the working frequency band, and the coupled end signal phase leading the through end signal by 90 degrees. Use the odd-even mode analysis method to obtain the impedance value of each bridge arm, and use simulation software to measure the port characteristics.

[0093] Step 5: Design a Wilkinson power divider with 50 ohm impedance at all three ports. Generate the basic structure of the power divider using the model in the simulation software according to the set operating frequency and bandwidth. By analyzing the load modulation process, it can be found that the control amplifier should be saturated in advance at low power, so the power ratio flowing into the control amplifier should be increased.

[0094] Step 6: Design an adaptive bias control circuit, and use the forward rectification effect of the diode to convert the input RF signal into a DC current flowing from the positive electrode to the negative electrode of the diode. The parallel capacitor C10 affects the RF power flowing to the diode and thus affects the current increment. The current is converted into the transistor gate voltage through the resistor R6.

[0095] Step 7: Combine and debug the debugged broadband input and output matching circuit, RC stabilization circuit, adaptive bias control circuit, bias circuit, transistor, 3-dB orthogonal coupler circuit and power divider. During the debugging process, adjust capacitor C10, resistor R6 and resistor R7 to achieve gate bias control so that the impedance change trajectory fits the optimal impedance trajectory of load pulling as much as possible. Design the phase compensation network according to the relative phase difference of the two currents at different frequencies. After combining the phase compensation network with the above network, debug the complete circuit. The specific steps are:

[0096] 2) Saturation optimal impedance of P2

[0097] First, we analyze the start-up order of the control amplifier and the balanced amplifier in the case of single input: In order to increase the impedance in the low power area, P should be kept control / P balance At a higher value, the control amplifier is required to saturate early and the balanced amplifier is turned on later. Therefore, the control amplifier is first biased in class AB and the two balanced amplifiers are biased in class C. On this basis, the control amplifier output current I is analyzed. c and balanced amplifier output current I b changes.

[0098] Assuming the PA current is an ideal linear model, the current is normalized according to the drive level:

[0099]

[0100]

[0101] To simplify the description, the ratio β is set to I b,max / I c,max , k1 represents the driving level when P2 is turned on, and k2 represents the driving level when P1 is saturated. In general, k1≤k2.

[0102] When all three amplifiers are saturated, the output power of the entire circuit reaches its maximum value, and the corresponding saturation impedance Z b,sat It can be expressed as:

[0103]

[0104] The total output power is the sum of the output powers of the three amplifiers, and the general expression is:

[0105]

[0106] Simplifying the above formula, we can get the saturation power P sat :

[0107]

[0108] The expression of saturated output power is only related to the parameters β and φ. According to the transistor datasheet, the sum of the power of the three transistors can be obtained. Under this goal, the rationality and efficiency of the comprehensive data are maximized, and the optimal values ​​of β and φ are repeatedly compared with the optimal values ​​obtained in step 2 to find the optimal values. When the values ​​of β and φ are determined, the saturated optimal impedance can be obtained.

[0109] 2) P2's back-off impedance

[0110] The parameters β and φ obtained above are considered to have the same definition of β and φ in the whole modulation process, and the value of φ can be considered to have not changed. Then we can further analyze the low power stage of P2. At the moment when the driving level is k2, the control amplifier is saturated, I c The maximum value I has been reached c,max , I b The value of can be expressed as Modulated load impedance Z b,back for:

[0111]

[0112] The output power at this time can be obtained as:

[0113]

[0114] The fallback range can be compared by P sat and P back Find:

[0115]

[0116] Given OBO, P back It can be determined that only This monomial is unknown, and by solving it, we can get Z b,back To ensure that Z obtained in this way b,back It is achievable, analyzing the real and imaginary parts of the back-off impedance:

[0117]

[0118] The real part of impedance must be a positive number to have actual physical meaning, so the implicit constraint in the above formula is:

[0119]

[0120] This is equivalent to the minimum back-off power being the saturated control power, which also conforms to I c and I b The physical meaning of the current model.

[0121] 3) In actual design, it is necessary to reasonably select the fallback range and obtain Z b,sat and Z b,back Finally, impedance matching is performed by changing β, φ, k1 and k2, which can be achieved by changing the power split ratio and gate bias. Since the determination of the two impedances is obtained by analyzing the current relationship, they are both related to the bias and are not independent of each other in the process of change. The bias condition of achieving high impedance to improve efficiency at low power will lead to gain compression, output power reduction and shift of the saturation impedance point. Therefore, it is considered to add an adaptive bias control circuit to change the gate voltage and achieve Z at the same time. b,sat and Z b,back Matching. At low power, the balanced power amplifier is placed in deep Class C bias to increase the impedance reflection coefficient. As the power amplifier is turned on, the gate bias is increased to increase the conduction angle of the balanced power amplifier to achieve optimal matching at saturation.

[0122] At other frequency points that are not at the center frequency, due to the change in the electrical length of the microstrip line, the matching situation of each power amplifier changes, resulting in a change in the relative phase φ, and the impedance point shifts. The most direct way to correct the impedance point is to compensate for the change in phase. The phase compensation network added before the control amplifier or the input 3-dB orthogonal coupler has the opposite phase change law. In this invention, the phase change before the input 3-dB orthogonal coupler conforms to the general law that the electrical length of the microstrip line changes with frequency. The phase of a single series microstrip line can only achieve a change of about 20 degrees in the range of 3GHz-4GHz. Figure 2 The phase compensation network shown can provide a 45-degree change in the range of 3 GHz-4 GHz, which can meet the phase change requirements of the circuit and further widen the frequency band.

[0123] Figure 3 The structure diagram of the adaptive bias control circuit and the bias voltage variation range obtained by simulation software are shown in Figure 2. in The RF AC signal is rectified into a positive DC current. The size of capacitor C10 affects the current increment. The current increment is converted into a voltage increment through the series resistor R6. The λ / 4 microstrip line L17 is open-circuited for the RF signal. Capacitor C9 is a bypass capacitor. V x is the dynamically changing gate bias voltage. Software simulation proves that this structure can achieve dynamic adjustment of gate bias voltage with input power.

[0124] Figure 4 The impedance change trajectory observed at different frequencies after the complete circuit is connected. It can be observed that the impedance basically falls within the load-pulling area, and the impedance at low power is higher than the impedance at saturation; under the action of the phase compensation network, the phase of the impedance gradually increases with the increase of frequency.

[0125] Figure 5 The figure shows the simulation result obtained by the circuit simulation software of the present invention. From the simulation results, it can be seen that in the frequency range of 3.4GHz-3.9GHz, the saturated output power is greater than 47dBm, the saturated output efficiency is greater than 65%, and the 6dB back-off efficiency is greater than 55%. The above results show that the function of the load modulation balanced amplifier is realized.

[0126] The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention. It is obvious to those skilled in the art that various modifications to these embodiments can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown in the present application, but will conform to the widest range consistent with the principles and novel features disclosed in the present application.

Claims

1. A load-modulated balanced power amplifier, characterized in that It includes a power divider, a phase compensation network, an input 3-dB orthogonal coupler, a balanced amplifier, a control amplifier and an output 3-dB orthogonal coupler; the balanced amplifier includes two upper and lower balanced sub-amplifiers; the upper and lower balanced sub-amplifiers both include a balanced amplifier input matching circuit, an RC stabilization circuit, an adaptive bias control circuit, a transistor P2, a drain bias circuit, and a DC blocking capacitor C8; the input end of the balanced amplifier input matching circuit serves as the input end of each balanced sub-amplifier, the output end is connected to the input end of the RC stabilization circuit, and the output end of the RC stabilization circuit is connected to the gate of the transistor; the input end of the adaptive bias control circuit is connected to a DC power supply, and the output end is connected to the gate of the transistor; the input end of the drain bias circuit is connected to a DC power supply, and the output end is connected to the drain of the transistor and then connected to one end of the DC blocking capacitor C8, and the other end of the DC blocking capacitor C8 serves as the output end of each balanced sub-amplifier; The power divider is used to distribute the power of a single input signal source to the balanced amplifier and the control amplifier; the input power provided to the control amplifier should be greater than the power flowing into the input ends of the upper and lower balanced sub-amplifiers, so that the control amplifier is saturated early; The phase compensation network is used to adjust the output current phase difference between the control amplifier and the balance amplifier through the phase value that changes with the frequency, so that the modulation impedance trajectory always falls within the optimal value region of the load pull, and provides a changing phase compensation value at different frequencies to fit the optimal impedance trajectory curve; The input end of the input 3-dB orthogonal coupler is connected to the output end of the phase compensation network, and the through end and the coupling end are respectively connected to the input end of the upper balanced amplifier and the input end of the lower balanced amplifier; the isolation end is connected to a 50 ohm resistor R3; The input end of the output 3-dB orthogonal coupler is connected to a 50-ohm load R5, the through end and the coupling end are respectively connected to the output end of the down-channel balanced amplifier and the output end of the up-channel balanced amplifier, and the isolation end is connected to the output end of the control amplifier; The input 3-dB quadrature coupler and the output 3-dB quadrature coupler make the phases of the two balanced sub-amplifiers consistent at the output port of the load modulated balanced power amplifier; The adaptive bias control circuit is used to dynamically adjust the gate bias voltage according to the input power; the adaptive bias control circuit includes a resistor R6, a grounding capacitor C9, a series microstrip line L17, a diode, a grounding capacitor C10 and a grounding resistor R7; one end of the resistor R6 is connected to a DC power supply V GS , the other end is connected to one end of the grounding capacitor C9 and one end of the series microstrip line L17, the other end of the series microstrip line L17 is connected to the cathode of the diode, and then the output end of the RC stabilization circuit is connected to the gate of the transistor, the anode of the diode is connected to one end of the grounding capacitor C10 and one end of the grounding resistor R7; the other end of the other end of the grounding capacitor C9, the other end of the grounding capacitor C10 and the other end of the grounding resistor R7 are grounded; The gate bias circuit of the control amplifier biases the control transistor P1 to class AB; The gate bias voltage of the balanced amplifier is dynamically adjusted with the input power to achieve automatic matching of the load impedance in the fallback and saturation states; The control amplifier comprises a control amplifier input matching circuit, an RC stabilization circuit, a gate bias circuit, a transistor P1, a drain bias circuit, a control amplifier output matching circuit, and a DC blocking capacitor C3; the input end of the control amplifier input matching circuit serves as the input end of the control amplifier, the output end of the control amplifier input matching circuit is connected to the input end of the RC stabilization circuit, and the output end of the RC stabilization circuit is connected to the gate of the transistor P1; the input end of the gate bias circuit is connected to a DC power supply, and the output end is connected to the output end of the RC stabilization circuit; the input end of the control amplifier output matching circuit is connected to one end of the drain bias circuit and then connected to the drain of the transistor P1, the other end of the drain bias circuit is connected to the DC power supply, the output end of the control amplifier output matching circuit is connected to one end of the DC blocking capacitor C3, the other end of the DC blocking capacitor C3 serves as the output end of the control amplifier, and is connected to the isolation end of the output 3-dB orthogonal coupler.

2. A load modulated balanced power amplifier as claimed in claim 1, characterized in that The characteristic impedance of the phase compensation network is 50 ohms.

3. A load modulated balanced power amplifier as claimed in claim 1, characterized in that The input 3-dB orthogonal coupler and the output 3-dB orthogonal coupler both adopt a two-stage bridge structure.

4. A load modulated balanced power amplifier as claimed in claim 1, characterized in that The through-end and coupled-end impedances of the output 3-dB quadrature coupler are also balanced amplifier load impedances, and their relationship with the amplitude and phase of the control amplifier is: Among them I c is the current flowing from the output of the control amplifier into the output 3-dB quadrature coupler isolation terminal, I b is the current flowing from the output of the balanced amplifier into the through-end or coupled end of the output 3-dB orthogonal coupler, φ is the relative phase between the current at the isolation end of the output 3-dB orthogonal coupler and the current at the through-end of the output 3-dB orthogonal coupler, Z b represents the load impedance of the balanced amplifier, θ represents the phase of the reflection coefficient of the load impedance of the balanced amplifier, Z0 represents the characteristic impedance of the output 3-dB orthogonal coupler, and j represents a complex number; From the above equations (1)-(2), it can be seen that the modulation of the load impedance of the balanced amplifier is mainly affected by the current ratio I c / I b and the relative phase φ; in the single input structure, φ is considered unchanged, so the current ratio I is adjusted by adjusting the power divider and the bias voltage. c / I b of control to achieve the impedance matching effect of the back-off point and the saturation point.

5. A method for realizing self-matching of a load-modulated balanced power amplifier as described in any one of claims 1 to 4, characterized in that The method comprises the following steps: Step 1: Design an RC stabilization circuit and continuously adjust the values ​​of resistors R4, R2 and capacitors C2, C7 so that the stability parameter is greater than 1 in the full frequency band; Step 2: According to the set operating frequency and bias size, determine the input and output impedance of the control amplifier transistor and the optimal input impedance of the balance amplifier transistor for subsequent matching; Step 3: Design the control amplifier input matching circuit, control amplifier output matching circuit, and balanced amplifier input matching circuit according to the transistor saturation impedance; Step 4: Design an input 3-dB orthogonal coupler and an output 3-dB orthogonal coupler, wherein the phases of the through end and the coupling end of the input 3-dB orthogonal coupler and the output 3-dB orthogonal coupler are 90 degrees apart, and the amplitudes of the two signals are equal; the isolation port of the input 3-dB orthogonal coupler is connected to a 50-ohm resistor, and the input port of the output 3-dB orthogonal coupler is connected to a 50-ohm load; Step 5: Design a power divider with three-port impedance of 50 ohms. The power divider divides the single input signal into two signals unequally. The specific power division ratio is determined according to the debugging results. The two signals are respectively sent to the input port of the control amplifier and the input port of the phase compensation network connected to the input 3-dB orthogonal coupler; Step 6: Design an adaptive bias control circuit. The forward diode rectifies the input power flowing into the gate of the transistor and converts it into a change in gate voltage through the series resistor R6. Step 7: Combine and debug the debugged control amplifier input matching circuit, control amplifier output matching circuit, balanced amplifier input matching circuit, RC stabilization circuit, adaptive bias control circuit, transistors P1 and P2, input 3-dB orthogonal coupler, output 3-dB orthogonal coupler and power divider, and then fit the optimal impedance trajectory of load pulling by changing the impedance; specifically: 1) Saturated load impedance of transistor P2 In the case of single input, in order to improve the impedance in the low power area, P control / P balance Greater than the threshold a, where P control Indicates the output power of the control amplifier, P balance Indicates the output power of the balanced sub-amplifier, requiring the control amplifier to be saturated early and the balanced sub-amplifier to be turned on late; therefore, first set the control amplifier bias to class AB and the two balanced sub-amplifiers bias to class C; Assuming an ideal linear model for the amplifier current, the current is normalized according to the drive level: To simplify the description, the ratio β is set to I b,max / I c,max , I c,max Indicates the maximum value of the control amplifier output current, I b,max represents the maximum value of the output current of the balanced sub-amplifier, k1 represents the drive level when P2 is turned on, and k2 represents the drive level when P1 is saturated; When the control amplifier and the two balanced sub-amplifiers are saturated, the output power of the entire circuit reaches the maximum value, and the corresponding saturated load impedance Z b,sat It is expressed as: Where θ represents the phase of the reflection coefficient of the balanced amplifier load impedance, Z0 represents the characteristic impedance of the output 3-dB orthogonal coupler, and j represents a complex number; Total output power P all is the sum of the output power of the control amplifier and the two balanced sub-amplifiers: Among them I c Represents the control amplifier output current; I b Represents the output current of the balanced sub-amplifier, Re(Z b ) represents the load impedance Z b The real part of Simplifying the above formula (6), we can get the total saturated output power P sat : According to the transistor datasheet, the total saturated output power P of transistors P1 and P2 is obtained. sat , and then repeatedly compare with the load-pull result to find the optimal value of β and φ, and then get the saturated load impedance Z b,sat ; 2) The back-off impedance of transistor P2 Define that β remains unchanged during the entire modulation process, and the value of φ is considered unchanged, so as to further analyze the low-power stage of P2; at the moment when the drive level is k2, the transistor P1 is just saturated, and the control amplifier output current reaches the maximum value I c,max , balance sub-amplifier output current The modulated back-off point load impedance Z b,back for: It is further obtained that the total output power of the control amplifier and the balanced amplifier in the back-off state is: The fallback range OBO is compared with P sat and P back Find: Given an OBO, it is known that P back Under the premise of And determine Z b,back The real and imaginary parts of Back-off point load impedance Z b,back The real and imaginary parts of : 3) By changing the gate voltage through the adaptive bias control circuit, the output current size and relative phase of the control amplifier and the balance amplifier can be controlled to ensure Z b,sat and Z b,back Matching; Step 8: Design a phase compensation network based on the relative phase difference between the two currents of the control amplifier and the balanced amplifier at different frequencies, and then combine the phase compensation network with the above network to debug the complete circuit.

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