Circuitry borrowing for memory arrays

Abstract

The present application relates directly to circuitry access for a memory array. In one example, a host device may transmit an access command associated with data in a first memory segment to a memory device. The first memory segment may be located between a second memory segment and a third memory segment. A first set of circuitry shared by the first and second memory segments may be operated using a driver associated with the first memory segment and a driver associated with the second memory segment. A second set of circuitry shared by the first and third memory segments may be operated using a driver associated with the first memory segment and a driver associated with the third memory segment. Access operations may be performed based on the operation of the first and second sets of circuitry.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to PCT application No. PCT / US2020 / 040915, filed by Martinelli et al. on July 6, 2020, entitled “CIRCUITRY BORROWING FOR MEMORY ARRAYS,” which claims priority to U.S. patent application No. 16 / 508,772, filed by Martinelli et al. on July 11, 2019, entitled “CIRCUITRY BORROWING FOR MEMORY ARRAYS,” each of which is assigned to its assignee, and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] TECHNICAL FIELD

[0002] The field relates to circuitry borrowing for memory arrays. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states in the memory device. For example, binary devices most commonly store one of two states, typically represented by a logic 1 or a logic 0. Other devices can store more than two states. To access stored information, a component of the device can read or sense at least one stored state in the memory device. To store information, a component of the device can write or program a state into the memory device.

[0005] There are various types of memory devices, including hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices (e.g., DRAM) can lose their stored state when disconnected from an external power source. FeRAM can achieve densities similar to volatile memory, but can have non-volatile properties due to the use of ferroelectric capacitors as storage devices.

[0006] A memory device may include a memory array, which may further include multiple sub-arrays. In some cases, the memory array may include circuitry associated with input, output, and other operations for exchanging or interpreting information between the various memory cells in the sub-arrays. A memory device may have various constraints on locating such circuitry within the memory array. Summary of the Invention

[0007] An apparatus is described. The apparatus may include: a memory array comprising a plurality of memory banks; a plurality of sets of shared circuitry, each of which is common to a respective first memory bank of the plurality of memory banks and a respective second memory bank of the plurality of memory banks; and a plurality of sets of drivers, each of which corresponds to a respective memory bank of the plurality of memory banks. Each set of drivers in the plurality of sets of drivers may include: a respective driver of a first type coupled to a respective first set of shared circuitry in the plurality of sets of shared circuitry, the respective first set of shared circuitry being common to the respective memory bank and a first other memory bank of the plurality of memory banks; and a respective driver of a second type coupled to a respective second set of shared circuitry in the plurality of sets of shared circuitry, the respective second set of shared circuitry being common to the respective memory bank and a second other memory bank of the plurality of memory banks.

[0008] Another apparatus is described. The apparatus may include: a memory array including a first memory segment located between a second memory segment and a third memory segment; a first set of circuitry configured to selectively couple with the first memory segment and the second memory segment; a first set of drivers associated with the first memory segment, wherein a first subset of the first set of drivers is configured to generate a first type of control signal for the first set of circuitry and a second subset of the first set of drivers is configured to generate a second type of control signal for the second set of circuitry; a second set of drivers associated with the second memory segment, wherein a subset of the second set of drivers is configured to generate the second type of control signal for the first set of circuitry; and a third set of drivers associated with the third memory segment, wherein a subset of the third set of drivers is configured to generate the first type of control signal for the second set of circuitry.

[0009] A method is described. The method may include: identifying a first memory bank of a memory array for an access operation, the first memory bank being located between a second memory bank of the memory array and a third memory bank of the memory array; based at least in part on the identification, operating a first set of circuitry shared by the first and second memory banks using a driver associated with the first memory bank and a driver associated with the second memory bank; based at least in part on the identification, operating a second set of circuitry shared by the first and third memory banks using a driver associated with the first memory bank and a driver associated with the third memory bank; and performing the access operation based at least in part on operating the first set of circuitry and operating the second set of circuitry.

[0010] Another method is described. The method may include: identifying a first memory segment of a memory array for an access operation, the first memory segment being located between a second memory segment of the memory array and a third memory segment of the memory array; generating a first type of control signal using a first set of drivers associated with the first memory segment; generating a second type of control signal using a second set of drivers associated with the first memory segment; generating an additional control signal of the second type using a third set of drivers associated with the second memory segment; generating an additional control signal of the first type using a fourth set of drivers associated with the third memory segment; operating a first set of sense amplifiers using the control signals of the first type generated by the first set of drivers and the additional control signals of the second type generated by the third set of drivers; operating a second set of sense amplifiers using the additional control signals of the first type generated by the fourth set of drivers and the control signals of the second type generated by the second set of drivers; and performing the access operation based at least in part on operating the first set of sense amplifiers and operating the second set of sense amplifiers. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Illustrated is an example of a system supporting circuitry borrowing for a memory array according to examples as disclosed herein.

[0012] Figure 2 Illustrated is an example of a memory die supporting circuitry borrowing for a memory array according to examples as disclosed herein.

[0013] Figure 3 Illustrated is an example of a memory layout that supports circuitry borrowing for a memory array according to examples as disclosed herein.

[0014] Figure 4 Illustrated is an example of a memory tile supporting circuitry borrowing according to examples as disclosed herein.

[0015] Figure 5 Illustrated is an example of a memory array supporting circuitry borrowing according to examples as disclosed herein.

[0016] Figure 6 Illustrated is an example block diagram 600 of a memory device 605 supporting circuitry borrowing for a memory array as disclosed herein.

[0017] Figure 7 Illustrated is an example of a flow chart illustrating a method of supporting circuitry borrowing for a memory array according to examples as disclosed herein.

[0018] Figure 8 Illustrated is an example of a flow chart illustrating a method of supporting circuitry borrowing for a memory array according to examples as disclosed herein. DETAILED DESCRIPTION

[0019] This disclosure describes systems and techniques related to circuitry borrowing for a memory device. For example, a memory device may include multiple memory tiles (e.g., slabs), each of which includes an array layer and a circuit layer. For each memory tile, the array layer may include multiple memory cells, and the circuit layer may include circuitry corresponding to operating the multiple memory cells of the array layer, such as decoding circuitry, multiplexing circuitry, driver circuitry, sensing circuitry, or other circuitry specific to the memory tile. The memory device may also include data path circuitry shared by the multiple memory tiles (e.g., corresponding to operating the multiple memory tiles, corresponding to data exchange between the multiple memory tiles and input / output components) and distributed across the circuit layers of two or more of the multiple memory tiles. Thus, in some examples, a memory device may include various types of circuitry distributed across circuit layers of multiple memory tiles, where tile-specific circuitry is included in the circuit layer of the corresponding memory tile and data path circuitry is distributed across the remaining space of the circuit layers of the memory tiles (e.g., in space in the circuit layers not occupied by tile-specific circuitry).

[0020] In some cases, memory tiles within an array can be organized into groups for simultaneous access, and such groups can be referred to as banks or sectors. For example, tiles can be organized into rows and columns within a memory array (which in some cases can be referred to as a quilted architecture), and rows of tiles within the array can be referred to as sectors. In some cases, circuitry (e.g., circuitry that controls the timing of sensing components) can be shared or "borrowed" by adjacent memory tiles (either within the same sector or across sectors (e.g., by tiles within adjacent sectors)). For example, when memory cells within different tiles of a sector are accessed simultaneously, shared circuitry is used to operate adjacent tiles within the sector. Additionally or alternatively, circuitry used to operate a first sector when accessing the first sector can also be used to operate a second sector when accessing the second sector (e.g., where the second sector is adjacent to the first sector). Thus, circuitry can be borrowed or shared (e.g., shared) between tiles within the same sector and also between sectors within the same array.

[0021] Control signal drivers are used to drive shared circuitry in a given segment. For example, control signal drivers may control timing signals for sense amplifiers or other circuitry that may be shared across segment boundaries. The control signal drivers may be located below a segment or on the "bottom side" of a memory tile. In some cases, at the edge of a memory tile array, a full set of control signal drivers (e.g., two sets of drivers) may be positioned to control all signals in a memory tile at or near the edge, with no drivers positioned at other edges of the array of memory tiles. Using multiple control signal drivers that share circuitry at the edge of the array can compromise spacing and ultimately impact die size.

[0022] According to the techniques disclosed herein, a memory array can have several sets of shared circuitry for a memory segment, the sets of shared circuitry including some control signals borrowed from the memory segment above (e.g., in the first adjacent row of tiles) and some control signals borrowed from the memory segment below (e.g., in the second adjacent row of tiles). The memory array can include multiple segments and multiple sets of shared circuitry. Each set of shared circuitry can be shared by two memory segments. Each segment can have a set of drivers, and the drivers can be divided into two groups (or two types).

[0023] For example, for a first segment, a first type of driver can be used by a set of shared circuitry shared by the first segment and a second segment located above the first segment. A second type of driver can be used by a set of shared circuitry shared by the first segment and a third segment located below the first segment. Thus, there are no longer two sets of drivers at the edge of the memory array (e.g., there can be only one driver or one set of drivers at both edges) and space is saved in the edge memory tiles.

[0024] The features of this disclosure were initially described in reference Figures 1 to 3 The features of the present disclosure are described in the context of the memory system and memory die described in the present disclosure. Figure 4 These and other features of the present disclosure are described in the context of circuitry for memory arrays. Figures 5 to 8 The described circuitry for a memory array is further illustrated and described with reference to device diagrams and flow charts.

[0025] Figure 1 Illustrated is an example of a system 100 that utilizes one or more memory devices according to examples as disclosed herein. The system 100 can include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 with the memory device 110. The system 100 can include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0026] System 100 may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, a laptop, a tablet, a smartphone, a cellular phone, a wearable device, a networked device, or the like. Memory device 110 may be a component of the system configured to store data for one or more other components of system 100.

[0027] At least portions of system 100 may be examples of host devices. Such host devices may be examples of devices that use memory to execute processes, such as computing devices, mobile computing devices, wireless devices, graphics processing devices, computers, laptop computers, desktop computers, smartphones, cellular phones, wearable devices, networked devices, some other fixed or portable electronic devices, and the like. In some cases, a host device may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 105. In some cases, external memory controller 105 may be referred to as a host or host device. In some examples, system 100 is a graphics card. In some cases, the host device may transmit access commands associated with data for a first memory segment to memory device 110. The first memory segment may include a respective set of subarrays (e.g., tiles, slices) of memory device 110. The first memory segment may be located between a second memory segment and a third memory segment. A first set of circuitry shared by the first and second memory segments may be operated using a driver associated with the first memory segment and a driver associated with the second memory segment. A second set of circuitry shared by the first and third memory segments can be operated using a driver associated with the first memory segment and a driver associated with the third memory segment. Access operations can be performed on the first memory segment based on operating the first and second sets of circuitry. This pattern of segments, shared circuitry, and driver access can be repeated across any number of memory segments. A host device can receive data for a first sub-array or tile based on coupling a first sensing component or portion thereof to a first I / O line or bus and coupling a second sensing component or portion thereof to a second I / O line or bus.

[0028] In some cases, memory device 110 may be a standalone device or component configured to communicate with other components of system 100 and provide physical memory addresses / space potentially used or referenced by system 100. In some instances, memory device 110 may be configured to operate with at least one or more different types of systems 100. Signaling between components of system 100 and memory device 110 may be operable to support modulation schemes used to modulate signals, different pin designs for communicating signals, different packaging of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions, and / or other factors.

[0029] The memory device 110 may be configured to store data for components of the system 100. In some cases, the memory device 110 may act as a slave device to the system 100 (e.g., responding to and executing commands provided by the system 100 through the external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0030] System 100 may further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may communicate electronically with each other using a bus 140.

[0031] The processor 120 may be configured to control at least portions of the system 100. The processor 120 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these types of components. In such cases, the processor 120 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or a system-on-a-chip (SoC), among other examples.

[0032] BIOS component 125 may be a software component including BIOS operating as firmware that may initialize and run the various hardware components of system 100. BIOS component 125 may also manage the flow of data between processor 120 and various components of system 100 (e.g., peripheral components 130, I / O controller 135, etc.). BIOS component 125 may include a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0033] Peripheral component 130 can be any input device or output device, or an interface for such a device, that can be integrated into or with system 100. Examples can include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a Peripheral Component Interconnect (PCI) or a special graphics port. Peripheral component 130 can be other components that are understood by those skilled in the art to be peripheral devices.

[0034] I / O controller 135 may manage data transfer between processor 120 and peripheral components 130, input device 145, or output device 150. I / O controller 135 may manage peripheral devices that are not integrated into or with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0035] Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. This may include a user interface or an interface with or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130 or may be managed by I / O controller 135.

[0036] Output 150 may represent a device or signal external to system 100 that is configured to receive output from system 100 or any of its components. Examples of output 150 may include a display, an audio speaker, another processor on a printed device or printed circuit board, etc. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130 or may be managed by I / O controller 135.

[0037] The components of system 100 may be composed of general-purpose or special-purpose circuitry designed to perform their functions. This may include various circuit elements configured to perform the functions described herein, for example, conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements. In some cases, components of system 100 (e.g., memory device 110) may include sensing elements, I / O buses or lines, drivers, or shunts configured to perform the functions described herein.

[0038] The memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 may include multiple memory segments and memory tiles, as described herein. The memory array 170 may be a collection (e.g., a grid) of memory cells, where each memory cell is configured to store at least one bit of digital data. This is described in more detail below (including with reference to FIG. 1 ). Figure 2 ) Characteristics of the memory array 170 and / or memory cells.

[0039] In various examples, the device memory controller 155 of the memory device 110 or one or more local memory controllers 165 of the memory device 110 may be configured to perform or operate in association with input / output components of the memory device 110 (e.g., for information transfer associated with access commands). In some examples, the memory device 110 may receive an access command associated with data of the memory device 110. In some cases, the memory device 110 may receive (e.g., prior to receiving the access command) an activate command that indicates an address range (e.g., a column address range) for the access command as corresponding only to a subset of subarrays within a bank of the memory device. In some cases, the memory device 110 may also receive (e.g., prior to receiving the activate command) a command to operate the memory device 110 according to a power mode or configuration (e.g., a reduced power mode). When operating in the reduced power mode, the memory device 110 may be configured to activate only the indicated subset of subarrays within the target bank (and deactivate other subarrays within the target bank). Thus, among other benefits, the memory device 110 may place or otherwise maintain one portion of a target bank in a deactivated mode while performing access operations on other portions of the target bank, thereby saving power.

[0040] In some examples, memory device 110 may receive an access command associated with a first memory segment of memory device 110. The first memory segment may be located between a second memory segment and a third memory segment. Device memory controller 155 may be coupled to several sets of drivers and provide control signals to each set of drivers for several sets of shared circuitry shared by the respective memory segments. For example, a first set of circuitry may be shared by the first and second memory segments using a driver associated with the first memory segment and a driver associated with the second memory segment. A second set of circuitry may be shared by the first and third memory segments using a driver associated with the first memory segment and a driver associated with the third memory segment. Access operations associated with data for the first segment may be performed based at least in part on operating the first set of circuitry and operating the second set of circuitry.

[0041] Memory device 110 may be an example of a two-dimensional (2D) array of memory cells or an example of a three-dimensional (3D) array of memory cells. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other or stacked adjacent to each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a stack, tier, layer, or die. A 3D memory device may include any number of stacked memory dies 160-N (e.g., two high, three high, four high, five high, six high, seven high, eight high). This may increase the number of memory cells that can be positioned on a substrate compared to a single 2D memory device, which in turn may reduce production costs or increase the performance of the memory array, or both. In a certain 3D memory device, different stacks may share at least one common access line, such that some stacks may share at least one of a word line, a digit line, and / or a plate line.

[0042] The device memory controller 155 may include circuits or components configured to control the operation of the memory device 110. As such, the device memory controller 155 may include hardware, firmware, or software that enables the memory device 110 to execute commands, and may be configured to receive, transmit, or execute commands, data, or control information related to the memory device 110. The device memory controller 155 may be configured to communicate with an external memory controller 105, one or more memory dies 160, or the processor 120. In some cases, the memory device 110 may receive data and / or commands from the external memory controller 105. For example, the memory device 110 may receive a write command that instructs the memory device 110 to store specific data on behalf of a component of the system 100 (e.g., the processor 120), or a read command that instructs the memory device 110 to provide specific data stored in the memory die 160 to a component of the system 100 (e.g., the processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating and transmitting signals to the external memory controller 105, logic, decoders, amplifiers, filters, and the like.

[0043] A local memory controller 165 (e.g., local to the memory die 160) can be configured to control the operation of the memory die 160. Furthermore, the local memory controller 165 can be configured to communicate with (e.g., receive and transmit data and / or commands to) the device memory controller 155. The local memory controller 165 can support the device memory controller 155 in controlling the operation of the memory device 110, as described herein. In some cases, the memory device 110 does not include a device memory controller 155, and either the local memory controller 165 or the external memory controller 105 can perform the various functions described herein. Thus, the local memory controller 165 can be configured to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 105 or the processor 120.

[0044] The external memory controller 105 can be configured to enable information, data, and / or commands to be passed between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 can act as a liaison between the components of the system 100 and the memory device 110, so that the components of the system 100 do not need to know the details of the operation of the memory device. The components of the system 100 can present requests (e.g., read commands or write commands) to the external memory controller 105, which the external memory controller 105 can satisfy. The external memory controller 105 can convert or translate the communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 can include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 can include a common data clock that generates a common (source) data clock signal.

[0045] Components of system 100 can use a plurality of channels 115 to exchange information with memory device 110. In some examples, channels 115 can enable communication between external memory controller 105 and memory device 110. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, a channel 115 can include a first terminal comprising one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. A pin can be an example of a conductive input or output point of a device of system 100, and a pin can be configured to function as part of a channel.

[0046] In some cases, the pins or pads of the terminals may be part of a signal path of channel 115. Additional signal paths may be coupled to the terminals of the channels to route signals within components of system 100. For example, memory device 110 may include signal paths (e.g., signal paths internal to memory device 110 or its components (e.g., internal to memory die 160)) that route signals from the terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0047] Lanes 115 (and associated signal paths and terminals) can be dedicated to conveying specific types of information. In some cases, lanes 115 can be aggregated lanes and, therefore, can include multiple individual lanes. For example, data lanes 190 can be ×4 (e.g., including four signal paths), ×8 (e.g., including eight signal paths), ×16 (e.g., including sixteen signal paths), and so on. Signals conveyed through the lanes can be signaled using double data rate (DDR). For example, some symbols of a signal can be registered on the rising edge of a clock signal, and other symbols of the signal can be registered on the falling edge of the clock signal. Signals conveyed through the lanes can also be signaled using single data rate (SDR). For example, one symbol of a signal can be registered for each clock cycle.

[0048] In some cases, channels 115 may include one or more command and address (CA) channels 186. CA channels 186 may be configured to communicate commands between external memory controller 105 and memory device 110, the commands including control information associated with the commands (e.g., address information). For example, CA channels 186 may include a read command with the address of the desired data. In some cases, CA channels 186 may register on rising and / or falling clock signal edges. In some cases, CA channels 186 may include any number of signal paths (e.g., eight or nine signal paths) to decode address and command data.

[0049] In some cases, channel 115 may include one or more clock signal (CK) channels 188. CK channels 188 may be configured to pass one or more common clock signals between external memory controller 105 and memory device 110. Each clock signal may be configured to oscillate between a high state and a low state and coordinate the actions of external memory controller 105 and memory device 110. In some cases, the clock signals may be differential outputs (e.g., a CK_t signal and a CK_c signal), and the signal paths of CK channels 188 may be configurable accordingly. In some cases, the clock signals may be single-ended. CK channels 188 may include any number of signal paths. In some cases, clock signals CK (e.g., a CK_t signal and a CK_c signal) may provide a timing reference for command and addressing operations of memory device 110 or other system-wide operations of memory device 110. Therefore, clock signal CK may be variously referred to as control clock signal CK, command clock signal CK, or system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, etc.).

[0050] In some cases, channels 115 may include one or more data (DQ) channels 190. Data channels 190 may be configured to communicate data and / or control information between the external memory controller 105 and the memory device 110. For example, data channels 190 may communicate information to be written to the memory device 110 or information to be read from the memory device 110 (e.g., bidirectionally).

[0051] In some cases, the channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may include any number of signal paths.

[0052] In some cases, the other channels 192 may include one or more write clock signal (WCK) channels. Although the "W" in WCK may nominally stand for "write," the write clock signal WCK (e.g., the WCK_t signal and the WCK_c signal) may generally provide a timing reference for access operations of the memory device 110 (e.g., a timing reference for both read and write operations). Therefore, the write clock signal WCK may also be referred to as the data clock signal WCK. The WCK channel may be configured to pass a common data clock signal between the external memory controller 105 and the memory device 110, which may be configured to coordinate access operations (e.g., write operations or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., the WCK_t signal and the WCK_c signal), and thus the signal path of the WCK channel may be configurable. The WCK channel may include any number of signal paths. The data clock signal WCK may be generated by a data clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, etc.).

[0053] In some cases, the other channels 192 may include one or more error detection code (EDC) channels. The EDC channels may be configured to pass error detection signals (eg, checksums) to improve system reliability. The EDC channels may include any number of signal paths.

[0054] The channel 115 can use a variety of different architectures to couple the external memory controller 105 with the memory device 110. Examples of various architectures can include a bus, a point-to-point connection, a crossbar, a high-density interposer such as a silicon interposer, or a channel formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path can at least partially include a high-density interposer such as a silicon interposer or a glass interposer.

[0055] Various modulation schemes may be used to modulate the signals communicated via channel 115. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate the signals communicated between external memory controller 105 and memory device 110. A binary symbol modulation scheme may be an example of an M-ary modulation scheme where M is equal to two. Each symbol of a binary symbol modulation scheme may be configured to represent one bit of digital data (e.g., a symbol may represent a logic 1 or a logic 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and / or others.

[0056] In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals communicated between the external memory controller 105 and the memory device 110. A multi-symbol modulation scheme may be an example of an M-ary modulation scheme where M is greater than or equal to three. Each symbol of a multi-symbol modulation scheme may be configured to represent more than one bit of digital data (e.g., a symbol may represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM3, PAM4, PAM8, quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and / or others. A multi-symbol signal (e.g., a PAM3 signal or a PAM4 signal) may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one bit of information. Alternatively, multi-symbol modulation schemes and symbols may be referred to as non-binary, multi-bit, or high-order modulation schemes and symbols.

[0057] In some examples, memory die 160 may include one or more memory arrays 170, and memory array 170 may include multiple memory tiles. In some cases, memory tiles within memory array 170 may be organized into groups for parallel access, and such groups may be referred to as banks or sectors. In some cases, memory tiles may be organized into rows and columns within memory array 170, which may be referred to as a quilted architecture, and rows of memory array 170 may be sectors. Each of the memory tiles may include an array layer and a circuit layer. For each memory tile, the array layer may include a plurality of memory cells (e.g., a sub-array, a portion of the memory array 170), and the circuit layer may include circuitry corresponding to (e.g., dedicated to, specific to, primarily assigned to) the plurality of memory cells of the array layer, such as decoding circuitry, multiplexing circuitry, driver circuitry, sensing circuitry, or other circuitry specific to the memory tile (although in some cases, the circuitry specific to the memory tile may be accessed by one or more adjacent tiles via multiplexing or other switching circuitry along with one or more interconnects). The memory device may also include data path circuitry shared by the plurality of memory tiles (e.g., corresponding to a bank of an operating memory tile, corresponding to data exchange between a bank of a memory tile and a local memory controller 165, usable for the plurality of memory tiles and selectively usable for one or more of the plurality of memory tiles simultaneously) and distributed across circuit layers of two or more of the plurality of memory tiles (e.g., circuit layers for all of the plurality of memory tiles, circuit layers for a subset of the plurality of memory tiles). In some cases, the sets of shared circuitry may include sets of data path circuitry configured to communicate information associated with access operations for memory cells in respective first memory banks and memory cells in respective second memory banks. Thus, in some examples, memory die 160 may include various types of circuitry distributed across the circuit layers of multiple memory tiles, with tile-specific circuitry included in the circuit layer of the corresponding memory tile, and data path circuitry (e.g., bank-specific circuitry) distributed across the remaining space of the circuit layers of the memory tiles (e.g., in the space of the circuit layers not occupied by tile-specific circuitry). In some examples, one or more local I / O lines may be shared between memory tiles, which may support various techniques for selectively activating and deactivating (e.g., maintaining deactivated) subsets of memory tiles to support various page size modes or reduced power modes.

[0058] Figure 2 Illustrated is an example of aspects of a memory die 200 according to examples as disclosed herein. The memory die 200 may be a reference Figure 11 , a memory die 200 is a memory device that stores one or more memory cells 205. The memory die 200 may be a memory chip, a memory device, or an electronic memory apparatus. The memory die 200 may include one or more memory cells 205 that are programmable to store different logical states. Each memory cell 205 may be programmed to store two or more states. For example, a memory cell 205 may be configured to store one bit of information (e.g., a logic 0 and a logic 1) at the same time. In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of information (e.g., a logic 00, a logic 01, a logic 10, or a logic 11) at the same time. In some examples, the memory cells 205 of the memory die 200 may include multiple memory segments, wherein each of the segments includes or otherwise corresponds to multiple tiles or blocks.

[0059] Memory cell 205 can store a state (e.g., a polarization state or dielectric charge) representing digital data. In an FeRAM architecture, memory cell 205 can include a capacitor 240 comprising a ferroelectric material to store a charge and / or polarization representing a programmable state. In a DRAM architecture, memory cell 205 can include a capacitor 240 comprising a dielectric material to store a charge representing a programmable state. In other memory architectures, memory die 200 according to the described techniques can implement other types of memory elements or storage elements. For example, memory die 200 can include a memory cell 205 having a configurable material memory element (e.g., in place of the illustrated capacitor 240) that stores a logic state as a material property of the material memory element. Such material properties can include programmable resistance (e.g., for a phase change material memory element that can be programmed with different resistances in PCRAM applications), programmable threshold voltage (e.g., for a material memory element that can be programmed with different threshold voltages, such as through write operations with different current pulse durations, amplitudes, or polarities), and other properties that can be selectively programmed to store a logic state.

[0060] Operations such as reading and writing can be performed on memory cell 205 by activating or selecting access lines, such as word line 210, digit line 215, and / or plate line 220. In some cases, digit line 215 may also be referred to as a bit line. References to access lines, word lines, digit lines, plate lines, or the like are interchangeable without impacting understanding or operation. Activating or selecting word line 210, digit line 215, or plate line 220 may include applying a voltage to the corresponding line.

[0061] The memory die 200 may include access lines (e.g., word lines 210, digit lines 215, and plate lines 220) arranged in a grid-like pattern. Memory cells 205 may be positioned at the intersections of the word lines 210, digit lines 215, and / or plate lines 220. By biasing the word lines 210, digit lines 215, and plate lines 220 (e.g., applying a voltage to the word lines 210, digit lines 215, or plate lines 220), a single memory cell 205 may be accessed at the intersection of the word lines, digit lines, and plate lines.

[0062] Access to the memory cells 205 may be controlled by a row decoder 225, a column decoder 230, and a plate driver 235. For example, the row decoder 225 may receive a row address from the local memory controller 265 and activate the word lines 210 based on the received row address. The column decoder 230 may receive a column address from the local memory controller 265 and activate the digit lines 215 based on the received column address. The plate driver 235 may receive a plate address from the local memory controller 265 and activate the plate lines 220 based on the received plate address. For example, the memory die 200 may include a plurality of word lines 210 labeled WL_1 through WL_M, a plurality of digit lines 215 labeled DL_1 through DL_N, and a plurality of plate lines labeled PL_1 through PL_P, where M, N, and P depend on the size of the memory array. Thus, by activating a word line 210, a digit line 215, and a plate line 220 (e.g., WL_1, DL_3, and PL_1), a memory cell 205 located at the intersection of the word line, the digit line, and the plate line can be accessed. The intersection of a word line 210 and a digit line 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of a memory cell 205. In some cases, the intersection of a word line 210, a digit line 215, and a plate line 220 can be referred to as the address of a memory cell 205.

[0063] A memory device including memory die 200 may receive an access command (e.g., from a host device). In some cases, the access command may indicate an address range for the access command as corresponding to a first sub-array of memory die 200. In such cases, the access command may be associated with data for the first sub-array. Sensing component 250, or a portion thereof, may couple with components of memory die 200 based on receiving the access command and sense the logic state stored by memory cell 205.

[0064] In some cases, an access command may indicate an address range for the access command as corresponding to one or more subarrays of memory die 200 (e.g., corresponding to a memory segment of memory die 200). In such cases, the access command may be associated with data of the memory segment. The host device may transmit an access command associated with data of a first memory segment. The first memory segment may be located between a second memory segment and a third memory segment. A first set of circuitry shared by the first and second memory segments may be operated using a driver associated with the first memory segment and a driver associated with the second memory segment. A second set of circuitry shared by the first and third memory segments may be operated using a driver associated with the first memory segment and a driver associated with the third memory segment. The access operation may be performed based on operating the first and second sets of circuitry. The sensing component 250, or a portion thereof, may couple with the first and second sets of circuitry upon receiving the access command and sense the logic states stored by the memory cells.

[0065] Memory cell 205 may include a logic storage component (e.g., capacitor 240 or other storage element or memory element (e.g., configurable material)) and a switching component 245. Capacitor 240 may be an example of a ferroelectric capacitor. A first node of capacitor 240 may be coupled to switching component 245 and a second node of capacitor 240 may be coupled to plate line 220. Switching component 245 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes electronic communication between two components. However, in various examples, a memory architecture supporting the described techniques may or may not include switching component 245 as part of the respective memory cell 205 or otherwise associated with the respective memory cell. In some cases, plate line 220 may be coupled to a cell plate reference voltage (e.g., Vpl) or may be ground or a chassis ground voltage (e.g., Vss). In some cases, plate line 220 may refer to a plate or electrical node common to all memory cells 205, or a plate or electrical node common to a subset of memory cells 205 or a subset of plate lines, or another electrical node coupled to a plate line driver.

[0066] Memory cell 205 can be selected or deselected by activating or deactivating switching element 245 or otherwise activating an associated access line. Capacitor 240 can be placed in electronic communication with digit line 215 using switching element 245. For example, capacitor 240 can be isolated from digit line 215 when switching element 245 is deactivated, and can be coupled to digit line 215 when switching element 245 is activated. In some cases, switching element 245 is a transistor and its operation can be controlled by applying a voltage to the transistor gate, where the voltage difference between the transistor gate and the transistor source is greater than or less than the transistor's threshold voltage. In some cases, switching element 245 can be a p-type transistor or an n-type transistor. Word line 210 can be in electronic communication with the gate of switching element 245 and switching element 245 can be activated / deactivated based on the voltage applied to word line 210.

[0067] The word line 210 can be a conductive line in electronic communication with the memory cell 205 for performing access operations on the memory cell 205. In some architectures, the word line 210 can be in electronic communication with the gate of the switching element 245 of the memory cell 205 and can be configured to control the switching element 245 of the memory cell. In some architectures, the word line 210 can be in electronic communication with a node of a capacitor of the memory cell 205 and the memory cell 205 may not include a switching element.

[0068] The digit line 215 can be a conductive line that connects the memory cell 205 to the sensing element 250. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during portions of an access operation. For example, the word line 210 and the switching element 245 of the memory cell 205 can be configured to selectively couple and / or isolate the capacitor 240 of the memory cell 205 from the digit line 215. In some architectures, the memory cell 205 can be in electronic communication (e.g., constant) with the digit line 215.

[0069] Plate line 220 may be a conductive line in electronic communication with memory cell 205 for performing an access operation on memory cell 205. Plate line 220 may be in electronic communication with a node (e.g., the bottom of the cell) of capacitor 240. Plate line 220 may be configured to cooperate with digit line 215 to bias capacitor 240 during an access operation of memory cell 205.

[0070] Sensing component 250 can be configured to determine the state (e.g., polarization state or charge) stored on capacitor 240 of memory cell 205 and determine the logic state of memory cell 205 based on the detected state. In some cases, the charge stored by memory cell 205 can be relatively small. As such, sensing component 250 can include one or more sense amplifiers to amplify the signal output by memory cell 205. The sense amplifiers can detect small changes in charge on digit line 215 during a read operation and can generate a signal corresponding to a logic 0 or logic 1 based on the detected charge. During a read operation, capacitor 240 of memory cell 205 can output a signal (e.g., discharge the charge) to its corresponding digit line 215. The signal can cause the voltage of digit line 215 to change. Sensing component 250 can be configured to compare the signal received from memory cell 205 across digit line 215 with reference signal 255 (e.g., a reference voltage). Sensing component 250 can determine the stored state of memory cell 205 based on the comparison. For example, in binary signaling, if digit line 215 has a higher voltage than reference signal 255, sensing component 250 can determine that the stored state of memory cell 205 is a logic 1, and if digit line 215 has a lower voltage than reference signal 255, sensing component 250 can determine that the stored state of memory cell 205 is a logic 0. Sensing component 250 can include various transistors or amplifiers to detect and amplify differences in signals. The detected logic state of memory cell 205 can be provided as an output of sensing component 250 (e.g., to input / output component 260) and can be indicated to another component of memory device 110 including memory die 200, such as device memory controller 155 (e.g., directly or using local memory controller 265). In some cases, sensing component 250 can be in electronic communication with row decoder 225, column decoder 230, and / or plate driver 235.

[0071] The sensing component 250 may include any number of sense amplifiers. The sense amplifiers may be configured to sense data from the corresponding memory tile and one or more adjacent memory tiles. For example, the sense amplifiers may be included in a circuit layer of the corresponding memory tile and may be configured to couple with memory cells in the array layer of the corresponding memory tile, but may also be configured to couple with memory cells included in adjacent memory tiles (e.g., via multiplexing circuitry or other switching circuitry or interconnects), where the adjacent memory tiles may be located in the same segment as the corresponding memory tile or in a different segment. For example, the sensing component 250, or a portion thereof, may be configured to sense data from the first subarray of the memory die 200 or the second subarray of the memory die 200 based on an activation command indicating that the address range for the access command corresponds to the first subarray or the second subarray. In such a case, the sensing component 250 may be activated. In some cases, the sensing component 250 may be deactivated based on the access command corresponding to the first subarray or the second subarray of the memory die 200.

[0072] The detected logic state of memory cell 205 may be provided as an output of sensing component 250 (e.g., to input / output component 260), which may be used to indicate the detected logic state (e.g., directly or using local memory controller 265) to another component of memory device 110 that includes memory die 200, such as device memory controller 155. Input / output component 260, or other components between sensing component 250 and input / output component 260, may include various components or circuitry that support the transfer of information between memory cell 205 (e.g., by way of sensing component 250, a sense amplifier of sensing component 250) and local memory controller 265. Such components or circuitry may be referred to as data path circuitry and may support operations such as signal amplification, redundancy, error detection, error correction, and other operations.

[0073] The local memory controller 265 may control the operation of the memory cell 205 through various components such as the row decoder 225, the column decoder 230, the plate driver 235, and the sensing component 250. The local memory controller 265 may be a reference Figure 1 105 (or a reference to an external memory controller 105). Figure 1The device memory controller 155 (described herein) receives one or more commands and / or data; translates the commands and / or data into information that can be used by the memory die 200; performs one or more operations on the memory die 200; and passes data from the memory die 200 to the external memory controller 105 (or device memory controller 155) in response to performing the one or more operations. The local memory controller 265 can generate row address signals, column and address signals, and / or plate line address signals to activate the target word line 210, the target digit line 215, and the target plate line 220. The local memory controller 265 can also generate and control various voltages or currents used during the operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein can be adjusted or varied and can be different for the various operations discussed in the operation of the memory die 200.

[0074] In some cases, the local memory controller 265 can be configured to perform or control a precharge operation on the memory die 200. The precharge operation can include precharging one or more components and / or access lines of the memory die 200 to one or more predetermined voltage levels. In some examples, the memory cells 205 and / or portions of the memory die 200 can be precharged between different access operations. In some examples, the digit lines 215 and / or other components can be precharged prior to a read operation.

[0075] In some cases, the local memory controller 265 can be configured to perform or control a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, a memory cell 205 of the memory die 200 can be programmed to store a desired logic state. In some cases, multiple memory cells 205 can be programmed during a single write operation. The local memory controller 265 can identify a target memory cell 205 on which a write operation is to be performed. The local memory controller 265 can identify a target word line 210, a target digit line 215, and / or a target plate line 220 in electronic communication with the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 265 can activate the target word line 210, the target digit line 215, and / or the target plate line 220 (e.g., by applying a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. Local memory controller 265 may apply a particular signal (e.g., voltage) to digit line 215 and a particular signal (e.g., voltage) to plate line 220 during a write operation to store a particular state in capacitor 240 of memory cell 205, the particular state indicating a desired logic state.

[0076] In some cases, the local memory controller 265 can be configured to perform a read operation (e.g., a sense operation) on one or more memory cells 205 of the memory die 200. During a read operation, the logic state stored in the memory cells 205 of the memory die 200 can be determined. In some cases, multiple memory cells 205 can be sensed during a single read operation. The local memory controller 265 can identify the target memory cell 205 on which the read operation is performed. The local memory controller 265 can identify the target word line 210, target digit line 215, and / or target plate line 220 in electronic communication with the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 265 can activate the target word line 210, target digit line 215, and / or target plate line 220 (e.g., apply a voltage to the word line 210, digit line 215, or plate line 220) to access the target memory cell 205. The target memory cell 205 may transmit a signal to the sensing component 250 in response to biasing the access line. The sensing component 250 (e.g., a sense amplifier of the sensing component 250) may amplify the signal. The local memory controller 265 may activate the sensing component 250 (e.g., latch the sense amplifier of the sensing component 250) and thereby compare the signal received from the memory cell 205 with the reference signal 255. Based on that comparison, the sensing component 250 may determine the logic state stored on the memory cell 205. In some examples, as part of a read operation, the local memory controller 265 may communicate the logic state stored on the memory cell 205 to the external memory controller 105 or the device memory controller 155. In some examples, other operations, such as signal amplification, redundancy operations, or error correction operations, may be performed between sensing the logic state of the memory cell 205 and communicating the information to or from the external memory controller 105 or the device memory controller 155 (e.g., via the input / output component 260).

[0077] In some memory architectures, accessing a memory cell 205 can degrade or corrupt the logical state stored in the memory cell 205. For example, a read operation performed on a ferroelectric memory cell can corrupt the logical state stored in the ferroelectric capacitor. In another example, a read operation performed in a DRAM architecture can partially or completely discharge the capacitor of the target memory cell. The local memory controller 265 can perform a rewrite operation or a refresh operation to restore the memory cell to its original logical state. The local memory controller 265 can rewrite the logical state to the target memory cell after the read operation. In some cases, the rewrite operation can be considered part of the read operation. In addition, activating a single access line (e.g., word line 210) can disturb the state stored in some memory cells that are electronically connected to that access line. Therefore, a rewrite operation or a refresh operation can be performed on one or more memory cells that may not have been accessed.

[0078] In some examples, the memory die 200 may include multiple memory tiles or slices, wherein each of the memory tiles of the memory die 200 includes an array layer and a circuit layer. For each memory tile, the array layer may include multiple memory cells 205 and the circuit layer may include circuitry corresponding to (e.g., dedicated to, specific to, primarily assigned to) the multiple memory cells of the array layer, such as decoding circuitry, sensing circuitry, or other circuitry specific to the memory tile (e.g., row decoder 225, column decoder 230, sensing component 250). The memory device may also include data path circuitry (e.g., input / output component 260, local memory controller 265) shared by the multiple memory tiles and distributed across the circuit layers of two or more of the multiple memory tiles. Thus, in some examples, memory die 200 may include various types of circuitry distributed across circuit layers of multiple memory tiles, with tile-specific circuitry included in the circuit layer of the corresponding memory tile, and data path circuitry (e.g., library-specific circuitry) distributed across the memory tiles (e.g., in space in the circuit layer not occupied by tile-specific circuitry).

[0079] Figure 3 An example of a memory layout 300 that supports circuitry borrowing for a memory array within a memory device according to examples as disclosed herein is illustrated. The memory layout 300 may be included in a memory die (e.g., a reference Figure 1 The memory die 160 described or referenced Figure 2Memory layout 300 illustrates an example in which a set of tile paths 310 (e.g., tile paths 310-a-1 through 310-aq) can be selectively coupled with a data path 350 using a tile multiplexer 340.

[0080] The data path 350 can be communicatively coupled to the local memory controller 265-a via a data path bus 351 (e.g., a data bus) to support various access operations described herein (e.g., read operations, write operations, rewrite operations, refresh operations, exchanging data or information with a host of a memory device including the memory layout 300). In some examples, the data path 350, the tile multiplexer 340, or both can be considered to be included in an input / output component (e.g., reference to FIG. Figure 2 2. In some examples, the data path 350 may be viewed as communicating between the array of memory cells 205 and the input / output components 260 described above. In some examples, circuitry or operations related to transferring information with the memory array may be associated with the local memory controller 265-a, and the data path 350 may be an example of circuitry configured to handle data or information communicated between the memory array and the local memory controller 265-a (e.g., where the local memory controller 265-a is part of or otherwise performs input / output related functions of the memory device). In some instances, the local memory controller 265-a may be configured to control the timing (e.g., timing of the sense amplifier array 320-a, timing of the sense amplifier 325-a) or triggering of various operations or components of the tile paths 310, tile multiplexers 340, and data paths 350, which may include control signaling communicated via a control bus 266-a having one or more signal paths, the control bus being shared by all tile paths 310-a-1 to 310-aq and data paths 350 (e.g., shared by memory segments or memory banks associated with the tile paths 310-a-1 to 310-aq) or otherwise corresponding to all tile paths and the data paths.

[0081] In the example of memory layout 300, the interconnections between components are illustrated by buses (e.g., data buses, control buses) that can support the transfer of multiple bits of information. For example, data path bus 351 can be associated with the transfer of u bits of data between data path 350 and local memory controller 265-a. In some examples, the transfer of the number of bits of data associated with the bus of memory layout 300 can correspond to a number of discrete conductive signal paths (e.g., traces, wires, lines). For example, data path bus 351 can be associated with u individual conductors or conductive traces between data path 350 and local memory controller 265-a. In other examples, components communicating via the bus in memory layout 300 can support a multi-level communication scheme, a multi-symbol communication scheme, a burst communication scheme, or some other signal modulation scheme that supports the transfer of a specific number of bits of data. For example, when the data path 350 and the local memory controller 265-a support a multi-symbol modulation scheme (e.g., a PAM3 scheme, a PAM4 scheme), the data path bus 351 may have fewer than u discrete signal paths to support communication for u bits of data transfer. Although aspects of the bus of the memory layout 300 may be described with reference to read operations or write operations, the bus of the memory layout 300 may be a bidirectional bus that supports both read operations and write operations in some examples. Thus, each end of a given bus of the memory layout 300 may be configured with a signal receiver, a signal driver, or both a signal receiver and a signal driver.

[0082] The tile paths 310-a may illustrate circuit paths that support communicating, multiplexing, modifying, or otherwise processing signals between the memory cells 205 (not shown) of a particular memory tile and the data paths 350. In some examples, each of the tile paths 310-a may include or otherwise be associated with a unique or dedicated array of memory cells 205 corresponding to the respective tile path 310 or memory tile (e.g., a sub-array of memory cells 205, memory cells 205 located in an array layer of a memory tile). Each of the tile paths 310-a may also be associated with a corresponding tile bus 311-a configured to communicate one or more signals (e.g., carrying p bits of information) between the respective tile path 310-a and the tile multiplexer 340. In various examples, a tile bus 311 may be referred to as a local I / O bus or line for a memory tile or tile path 310-a, or may refer to a group of more than one local I / O bus or line for a memory tile or tile path (e.g., where the respective tile bus 311-a is subdivided for various multiplexing or routing operations). Although specific details are illustrated with reference to tile path 310-a-1, such details may be repeated in each of tile paths 310-a-2 through 310-aq.

[0083] In the example of memory layout 300, each of tile paths 310-a may include or otherwise correspond to a set of digit lines 215-a (e.g., digit lines 215-a-11 through 215-a-1m of tile path 310-a-1, a set of m digit lines 215-a), which may be reference digit lines. Figure 2 Examples of digit lines 215 are described. For example, each of the digit lines 215-a of the tile path 310-a-1 can be coupled to a corresponding switching component 245 of each of a group of memory cells 205 (e.g., the tile path 310-a-1 or a column of memory cells 205 corresponding to the tile path 310-a-1), where the corresponding switching component 245 can be configured to selectively couple the storage component (e.g., capacitor 240, material storage component, another type of memory storage component) of the memory cell 205 to the digit line 215-a. Thus, the tile path 310-a-1 or each of the memory cells 205 corresponding to the tile path 310-a-1 can be coupled to one of the digit lines 215-a-11 through 215-a-1m. In various examples, such coupling between memory cell 205 and digit line 215-a can be direct (e.g., directly along a conductive path or access line) or indirect (e.g., via circuit components or signal processing circuitry). For example, digit line 215-a can include or otherwise be associated with signal development circuitry such as amplifiers, cascodes, charge transfer sense amplifiers (CTSAs), and amplifying capacitors, among other things.

[0084] For each of the tile paths 310-a, a row of memory cells 205 of the tile path 310-a can be selected or selectively activated by activating a word line 210 (not shown) included in or otherwise corresponding to the tile path 310-a (e.g., included in a memory tile corresponding to the tile path 310-a). For example, activating tile path 310-a-1 or the word line 210 corresponding to tile path 310-a-1 can couple a row or page of capacitors 240, material memory elements, or other types of memory storage elements of the corresponding memory cells 205 with a corresponding one of the digit lines 215-a-11 through 215-a-1m. In various examples, the tile paths 310 may or may not include a driver, buffer, or multiplexer (e.g., referring to FIG. 2 ). Figure 2 The depicted row decoder 225 or a portion thereof) is used to selectively activate the word line 210 or other select line.

[0085] For each of the tile paths 310-a, various digital lines in a set of m digital lines 215-a may be selectively coupled to or routed to a corresponding sense amplifier array 320-a of the tile path 310-a using a digital line multiplexer 315-a. For example, tile path 310-a-1 may include a sense amplifier array 320-a-1 having n sense amplifiers 325-a (e.g., sense amplifiers 325-a-11 through 325-a-1n). Thus, the digital line multiplexer 315-a-1 may be configured to selectively couple or map between the m signal paths associated with the digital lines 215-a-11 through 215-a-1m and the n signal paths associated with the sense amplifier array 320-a-1 (e.g., n sense amplifiers 325-a). In some examples, the sense amplifier array 320-a may be considered to be included in the reference Figure 2 The functions or circuitry of the sensing component 250 are described herein or otherwise refer to the functions or circuitry.

[0086] Sense amplifier 325-a may include circuitry configured to latch a signal indicative of the logic state stored by memory cell 205, such as sets of cross-coupled transistors that latch an output based on a comparison of a read signal from memory cell 205 with a reference signal. In some examples, sense amplifier 325-a or some other portion of sense amplifier array 320-a may include circuitry configured to generate or form such a read signal (e.g., based at least in part on selective coupling with memory cell 205) or to generate or form such a reference signal. In some examples, sense amplifier 325-a may also be configured to generate or form a write signal to digit line 215-a or memory cell 205 (e.g., based at least in part on a write command from local memory controller 265-a).

[0087] The digit line multiplexer 315-a, sense amplifier array 320-a, and other circuitry corresponding to a given memory tile may be located at a circuit layer or circuit level of the memory tile (e.g., reference Figure 4 The circuit level 450 of the memory tile 400 described herein may be located in the circuit level 450 of the memory tile 400, and the corresponding memory cells 205 of the memory tile may be located in the array layer or array level of the memory tile (e.g., referring to FIG. Figure 4tiers of memory tiles 400 described herein). In some cases, a circuit layer or circuit level may be located below (e.g., closer to the substrate than) the array layer or array level of a memory tile. In some cases, aspects of a line or bus as described herein (e.g., all or part of a line or bus) may be located in a circuit layer or circuit level of one or more memory tiles, a routing layer or routing level (e.g., one or more metallization layers) of one or more memory tiles, a routing layer or routing level of a memory segment or bank, or various combinations thereof. In various examples, the array layer or array level may be between the circuit layer or circuit level and the one or more routing layers or routing levels. In some examples, one or more sockets (e.g., vias, conductive plugs) may provide interconnection between components at different layers or levels of a memory tile or memory bank. In some cases, the sockets may be located between memory tiles within an array (e.g., in the gaps between different memory tiles).

[0088] Control signal drivers that output control signals and control the timing signals for the sense amplifiers 325-a may also be located at or below the array level (e.g., at the circuit level) of the memory tile. In some cases, the control bus 266 or the local memory controller 265 may provide inputs to one or more control signal drivers. In some cases, a set of drivers may be common to or otherwise correspond to respective memory segments of a memory tile and coupled to a set of shared circuitry via conductors (e.g., conductive wires, sockets). In some cases, a set of drivers may include a first type of driver (e.g., configured to generate a first type of control signal or a first set of control signals) and a second type of driver (e.g., configured to generate a second type of control signal or a second set of control signals). The first type of driver may be coupled to a first set of shared circuitry that is common to the respective memory segment and the second memory segment. The second type of driver may be coupled to a second set of shared circuitry that is common to the respective memory segment and the third memory segment. In some cases, the first set of shared circuitry includes a first set of sense amplifiers 325-a. A first subset of the first set of sense amplifiers 325-a underlies the memory tiles of the corresponding memory bank, and a second subset of the first set of sense amplifiers 325-a underlies the memory tiles of the second memory bank. The second set of shared circuitry may include a second set of sense amplifiers 325-a. A first subset of the second set of sense amplifiers 325-a underlies the memory tiles of the corresponding memory bank, and a second subset of the second set of sense amplifiers 325-a underlies the memory tiles of the third memory bank. Additionally or alternatively, the first set of shared circuitry may include data path circuitry shared by (borrowed between) memory tiles of the corresponding memory segment and memory tiles of the second memory segment, and the second set of shared circuitry may include data path circuitry shared by (borrowed between) memory tiles of the corresponding memory segment and memory tiles of the second memory segment, and the second set of shared circuitry may include data path circuitry shared by (borrowed between) memory tiles of the corresponding memory segment and memory tiles of the third memory segment.

[0089] Each of the sense amplifiers 325-a can be configured to receive a signal from a respective memory cell 205 via a respective digit line 215-a according to a particular selection, mapping, or other configuration of the respective digit line multiplexer 315-a. For example, when the digit line multiplexer 315-a-1 is configured to couple the sense amplifier array 320-a-1 with a subset of the digit lines 215-a-11 through 215-a-1m (e.g., a portion or subset of a row, a portion or subset of a page when n<m), the digit line multiplexer 315-a-1 can receive a signal (e.g., from the local memory controller 266-a via the control bus 265-a) to couple a particular subset of the digit lines 215-a-11 through 215-a-1m according to a particular access operation. In some examples, the memory layout may include a sense amplifier 325 for each of the digit lines 215 in the tile path 310 (eg, where n=m), in which case the digit line multiplexer 315 may be omitted from the tile path 310 .

[0090] Sense amplifier array 320-a (e.g., each of sense amplifiers 325-a) may output a signal (e.g., when performing the function of a read operation) indicating the logic state stored by the corresponding memory cell 205. In some examples, the output of sense amplifier 325-a may be associated with a relatively narrow or small voltage swing (e.g., a relatively small range of voltages for indicating a set of logic states compared to a voltage swing used in a portion of data path 350 or at the output) when reading a set of logic states that may be stored by memory cell 205. Using a relatively narrow voltage swing at the sense amplifier 325-a can mitigate the risk of signal interference (e.g., due to capacitive or other cross-coupling or crosstalk) of simultaneously transmitted signals or data states stored in the memory cell 205, and can also support corresponding components or circuit systems that occupy a relatively small area, or relatively thin dielectric separation between components or conductors of the tile path 310-a (e.g., between sense amplifiers 325-a, between conductive lines of a bus to or from the tile path 310-a, between memory cells 205), or relatively low charge accumulation or signal attenuation (e.g., associated with capacitive loads, such as the inherent capacitance of an access line between the memory cell 205 and the data path 350), or relatively low charge leakage or power consumption in the tile path 310-a (e.g., associated with charge leakage between components of the memory layout 300, associated with charge leakage across portions that are electrically isolated by dielectric portions, associated with powering voltage sources or drivers to operate the memory layout 300).

[0091] In some examples, the sense amplifier array 320 may further include a sense amplifier selection component or multiplexer (not shown) that can be configured to select, enable, activate, latch, or route signals from a subset (e.g., less than all) of the sense amplifiers 325 of the sense amplifier array 320 (e.g., based on a column address associated with an access command). For example, such a selection component or multiplexer can select or activate half of the sense amplifiers 325 of the sense amplifier array 320, a quarter of the sense amplifiers 325 of the sense amplifier array 320, and so on (e.g., in response to signaling received from the control bus 266-a). When supporting a read operation, for example, the output of such a sense amplifier array 320 can therefore be configured to output fewer bits of data than the number of sense amplifiers 325 in the sense amplifier array 320.

[0092] In some examples, the sense amplifier array 320 of one tile path 310, or a portion thereof, can be configured to selectively couple with that of another tile path 310. In a partial power or partial operating mode of a memory device, for example, the memory layout 300 can support selective activation, deactivation, or idleness of particular memory tiles or tile paths 310. In such examples, the sense amplifier array 320 of a deactivated or idle memory tile, or a portion thereof (e.g., a subset of the sense amplifiers 325), can be shared, shunted, or otherwise coupled with an activated memory tile (e.g., the array of memory cells 205 of an activated memory tile, the sense amplifier array 320 of an activated memory tile). Thus, in some examples, the sense amplifier array 320 or a set of sense amplifiers 325 may be primarily dedicated to a particular memory tile or tile path 310, but in some situations (e.g., particular operating modes), the sense amplifier array 320 or a set of sense amplifiers 325 may be shared with another memory tile or tile path 310 (e.g., an adjacent memory tile or tile path 310). In other examples, the sense amplifier array 320 may be included in or otherwise considered part of the data path 350.

[0093] In some examples, the sense amplifier array 320 or another portion of the tile path 310 may include a buffering function or circuitry (e.g., a row buffer, a page buffer, a prefetch buffer). To support aspects of read operations, for example, such a buffer may be configured to maintain or store signals corresponding to detected logic states that are not delivered to the tile multiplexer 340 in a given operation (e.g., a subset of rows, a subset of pages). In various examples, such a buffering function may be configured to deliver the stored signals to the tile multiplexer 340 at a later time or use such stored signals to support a write-back or rewrite command (e.g., rewriting the detected logic states to the memory cells 205).

[0094] Thus, in some examples, the side of the sense amplifier array 320 electrically coupled toward the data path 350 (e.g., coupled to the corresponding tile bus 311-a) can be configured to support data transfer for a smaller number of bits (e.g., where p < n) than the side of the sense amplifier array 320 electrically coupled toward the digit lines 215 or memory cells 205 of the corresponding memory array. In other examples, such a selection component or multiplexer can be omitted, and the side of the sense amplifier array 320 electrically coupled toward the data path 350 can be configured to support data transfer for the same number of bits (e.g., where p = n) as the side of the sense amplifier array 320 electrically coupled toward the digit lines 215 or memory cells 205 of the corresponding memory array.

[0095] A set of tile paths 310-a (e.g., sense amplifier array 320-a) or various portions thereof can be selectively coupled to data paths 350 using a tile multiplexer 340. In the example of the memory layout 300, the tile multiplexer 340 is coupled to a respective tile bus 311-a (e.g., tile buses 311-a-1 through 311-aq, a set of local I / O buses or lines) for each of the tile paths 310-a, where each of the tile buses 311-a can be configured to carry p bits of information. Thus, with each of the p bits of information carried on a different signal path, the tile multiplexer 340 can be configured to selectively couple or map the (p×q) signal paths on the array side of the tile multiplexer 340. On the data path side, the tile multiplexer 340 can be configured to carry r bits of information (e.g., corresponding to r digital lines 215-a, corresponding to r memory cells 205), and if each of the r bits of information is carried on a different signal path, the tile multiplexer 340 can be configured to selectively couple or map the r signal paths. In other words, the tile multiplexer 340 can be configured to selectively couple or map the (p×q) signal paths associated with the tile bus 311-a with the r signal paths associated with the data path 350 (e.g., the tile multiplexer bus 341). In some instances, the circuit path between the tile path 310-a and the data path 350 (e.g., the circuit between the sense amplifier array 320-a and the data sense amplifier component 360 (including the tile bus 311-a, the tile multiplexer 340, and the tile multiplexer bus 341)) may be referred to as a column path circuit.

[0096] In various examples, the tile multiplexer 340 can receive signals (e.g., from the local memory controller 265) to couple the data path 350 to a particular tile path 310-a or to portions of more than one tile path 310-a, depending on a particular access operation. In one example, the tile multiplexer 340 can be configured to access memory tiles one at a time, such that the data path 350 couples r signal paths from a single memory tile (e.g., r digital lines 215-a from a single tile bus 311-a). In another example, the tile multiplexer 340 can be configured to access memory tiles multiple at a time, such that the data path 350 couples a subset of r signals from one memory tile (e.g., the first tile bus 311-a) to another subset of r signals from another memory tile (e.g., the second tile bus 310-a). For example, a tile multiplexer bus 341 can refer to a collection of primary I / O lines, one or more of which can be shared across a group of memory tiles or tile paths 310-a (e.g., a column of memory tiles, a row of memory tiles), and the primary I / O lines can be selectively coupled (e.g., through a portion of a tile multiplexer 340) with local I / O lines corresponding to one or more of the group of memory tiles or tile paths 310-a. In some examples, the tile multiplexer 340 can support accessing memory tiles one at a time and multiple at a time, and selection between the two can be made at the local memory controller 265 to support specific access operations, specific operating modes, or specific configurations in a given application or installation.

[0097] Although tile multiplexer 340 is illustrated as a single component, in some examples, various functions or subcomponents of tile multiplexer 340 may be distributed in different portions of memory layout 300 (e.g., as a distributed transistor network or selector network). For example, selective coupling, mapping, or routing at a first granularity or regularity may be implemented by a first set of subcomponents that may be part of data path 350, and selective coupling, mapping, or routing at a second granularity or regularity may be implemented by a second set of subcomponents that may be distributed across tile paths 310-a-1 through 310-aq. Thus, tile path 310-a may include various circuitry dedicated to or otherwise corresponding to operating a corresponding memory tile in a group of memory tiles, data path 350 may include various circuitry dedicated to or otherwise corresponding to operating all tiles in a group of memory tiles, and various portions of tile multiplexer 340 may or may not be considered part of tile paths 310-a-1 through 310-aq or data path 350.

[0098] The data path 350 may illustrate an example of circuitry corresponding to a plurality of memory tiles (e.g., all tiles in tile paths 310-a-1 through 310-aq) that is configured to transfer information or provide various management of information associated with access operations for the plurality of memory tiles. According to the described techniques for circuit segmentation, components of the data path 350 may be located in circuit layers or circuit hierarchies of two or more of the plurality of memory tiles. In the example of the memory layout 300, the data path 350 includes a data sense amplifier component 360, a redundancy repair component 365, and an error correction component 370. In other examples of memory layouts, the data path 350 may include more or fewer components or components that are divided into various other subcomponents or sub-functions. Furthermore, while the data path 350 illustrates a single path between the tile multiplexer bus 341 and the data path bus 351, other examples of the data path 350 may have more than one path (e.g., a read path and a write path) between the tile multiplexer bus 341 and the data path bus 351. Thus, in some examples, the data path 350 may include circuitry configured to multiplex the read or write pipelines of the memory layout 300.

[0099] The data sense amplifier component 360 can be referred to as the "front end" of the data path 350 and can include circuitry configured to amplify signals received at the data path 350 via the tile multiplexer bus 341. For example, to support various read operations, signals communicated from one or more tile paths 310-a via the tile multiplexer 340 can have a first voltage swing (e.g., a partial swing or low swing corresponding to reading a memory cell 205, a partial swing or low swing corresponding to a latch voltage of a sense amplifier 325-a, or a partial swing or low swing corresponding to a set of logic states that can be stored by the memory cell 205). To support various operations or processes of the data path 350, the data sense amplifier component 360 can amplify such signals to produce signals having a second voltage swing (e.g., a full swing or high swing) that is greater than the first voltage swing. Using relatively wider or larger voltage swings in the data path 350 can support more robust signal transmission through the data path 350 or to the local memory controller 265, which can be related to relatively lower sensitivity to interference, relatively lower sensitivity to voltage drops or signal degradation along resistive signal paths, relatively lower sensitivity to various charge leakage paths in the data path 350, and other characteristics associated with relatively larger voltage swings.

[0100] In some examples, the data sense amplifier component 360 may include a single amplifier for each signal path of the tile multiplexer bus 341 (e.g., a 1:1 correspondence between an amplifier and a memory cell 205 or bit of information being transferred, a set of r amplifiers). Thus, the data sense amplifier component 360 may include one or more circuit elements for each memory cell 205 or each bit of information accessed in the memory array involved in a given access operation. This granularity or regularity may be referred to as a "bit slice" of the data path 350, where each bit slice of the data path includes one or more circuit elements repeated for each bit or memory cell 205 involved in the access operation supported by the data path 350.

[0101] In some examples, the data sense amplifier component 360 can be used to support read operations rather than write operations, and therefore, the data sense amplifier component 360 can be bypassed in some access operations (e.g., another option is to couple the tile multiplexer bus 341 with the write driver of the data path 350 (not shown)). In some examples, the data sense amplifier component 360 can be omitted from the data path 350, such as when the sense amplifier array 320 or the sense amplifier 325 is configured to output a full swing or high swing output (e.g., to the data path 350), where full swing can refer to a voltage swing that is the same as a voltage swing used in a portion of the data path 350 or at the output.

[0102] The redundant repair component 365 can be configured to replace or reroute data read from or otherwise written to a digit line 215 or memory cell 205 that is known to be faulty or suspected of being faulty (e.g., as identified from an array detection operation, an error correction operation, or a manufacturing verification operation). In a read operation, for example, the redundant repair component 365 can be configured to ignore bits received from the data sense amplifier component 360 or ignore the signal path from the data sense amplifier component 360, and reroute or otherwise reconfigure the signal to account for the faulty digit line 215 or memory cell 205. In a write operation, for example, the redundant repair component 365 can be configured to reroute or otherwise reconfigure the write signal or data to avoid writing bits to the faulty digit line 215 or memory cell 205. Thus, the bus on the array side of the redundant repair component 365 can be configured to carry more bits than the bus on the opposite side of the redundant repair component 365 (e.g., where s>t). In one example, the memory layout 300 can be configured to transfer one redundant bit of information per byte on the datapath bus 351 (eg, one redundant bit of information for every eight bits), although this ratio can be configured to other ratios based on various design tradeoffs.

[0103] The error correction component 370 can be configured to detect or correct various data corruptions or errors, and in some cases can restore data before transmission via the data path bus 351 (e.g., during a read operation). Such error detection and correction can rely on one or more error correction codes, such as block codes, convolutional codes, Hamming codes, low-density parity check codes, turbo codes, polar codes, and others. These processes, operations, and techniques may be referred to as ECC processes, ECC operations, ECC techniques, or simply ECC in some cases. In some examples, the error correction component 370 may include or be referred to as in-line ECC. In a read operation, for example, the error correction component 370 may perform error correction operations on data read from the memory array (e.g., as read from one or more tile paths 310-a or otherwise communicated) in accordance with the read operation. The error correction component 370 may generate corrected data (e.g., in a correction subcomponent) or an indication of a detected error (e.g., in a detection subcomponent). Error correction component 370 can output data that, in various circumstances, can be data read from a memory array or data that has been corrected.

[0104] In one example of performing an ECC operation, the error correction component 370 can calculate a "symptom code" for incoming read data (e.g., as received from the redundancy repair component 365) and can compare the syndrome code to one or more corresponding parity bits accompanying the incoming read data (e.g., as read from the memory cell 205 of the same or different tile path 310-a). When the calculated syndrome code is not equal to one or more corresponding parity bits, the error correction component 370 can attempt to correct the incoming read data before forwarding it (e.g., via the data path bus 351), or signal a detected error (e.g., via the control bus 266-a), or both. In another example of performing an ECC operation, the error correction component 370 can calculate parity bits for incoming write data (e.g., as received from the local memory controller 265-a via the data path bus 351 for later comparison with the calculated syndrome code when reading the data), and the calculated parity bits can be written to the memory cells 205 of the same or different tile path 310-a as the incoming write data was written to. In one example, the memory layout 300 can be configured to transmit one parity bit or ECC bit of information per byte on the data path bus 351 (e.g., one parity bit of information for every eight bits), although such a ratio can be configured to other ratios based on various design tradeoffs.

[0105] In some examples, error correction component 370 may include logic circuitry to detect a memory cell 205 or digit line 215 associated with charge leakage, store an indication of such detection, and, where appropriate, invert a logic state to be written to the memory cell 205 or digit line 215, or invert a logic state to be read from the memory cell 205 or digit line 215, thereby mitigating the effects of charge leakage.

[0106] The data path 350 (e.g., data path bus 351) and tile path 310-a can be configured according to various multiplexing configurations, multiplexing configurations, and selective operations. For example, the number of bits associated with an access operation of the data path 350 (e.g., u bits of the data path bus 351) can correspond to the number of bits of an access command (e.g., a column access command, a column access strobe (CAS) command, or a prefetch command). According to various configurations of the memory layout 300, other buses of the memory layout 300 can be associated with a larger number of bits.

[0107] In one illustrative example, the data path 350 can be associated with 256 bits of information transmission (e.g., a 256-bit data packet or data burst), which in some examples can correspond to a data path bus 351 configured with 256 individual conductive traces (e.g., where u=256). The error correction component 370 can be configured with data transmission with one parity bit for every eight bits (e.g., on the data path bus 351), and thus the error correction component 370 can use a bus with 288 individual conductive traces (e.g., where t=288) to couple with the redundant repair component 365. The redundant repair component 365 can be configured with data transmission with one redundant bit for every eight bits (e.g., on the data path bus 351), and thus the redundant repair component 365 can use a bus with 320 individual conductive traces (e.g., where s=320) to couple with the data sense amplifier component 360.

[0108] In the example of a data path 350 that includes a data sense amplifier component 360, the data sense amplifier component 360 can be configured with an amplifier for each of the conductive traces (e.g., on either side of the data sense amplifier component 360) and thus can be coupled to the tile multiplexer 340 and the redundancy repair component 365 using a bus having the same number of conductive traces (e.g., where r=320). Thus, according to the illustrative example, the data path 350 can be configured to communicatively couple between a 320-bit or 320-conductor tile multiplexer bus 341 and a 256-bit or 256-trace data path bus 351. In other words, the data path 350 can be associated with a 25% addition (e.g., a 125% ratio of memory cells 205 accessed in a given access operation to data bits communicated with the local memory controller 265-a) to support redundancy and error correction operations for a group of memory tiles corresponding to tile paths 310-a-1 through 310-aq.

[0109] Continuing with the illustrative example, the tile paths 310-a and the tile multiplexer 340 can be configured with various multiplexing and multiplexing to support a 320-bit or 320-conductor tile multiplexer bus 341. For example, the memory layout 300 may include or correspond to a group or bank of 64 memory tiles (e.g., where q = 64). To support a given access operation, the tile multiplexer 340 can be configured to selectively couple half of the 64 corresponding tile paths 310-a (e.g., every other tile path 310-a according to the arrangement of the tile paths 310-a in a group or bank) to the tile multiplexer bus 341. Thus, the tile multiplexer bus 341 can couple 32 tile paths 310-a using corresponding 10-bit or 10-conductor tile buses 311-a (e.g., where p = 10). In some instances, such a configuration may be supported by tile paths 310-a or tile buses 311-a that each include or are otherwise associated with two local I / O buses or lines, each local I / O bus or line configured to convey five bits (e.g., each local I / O bus or line having five individual conductors or traces, each local I / O bus or line coupled to a different subset of the five sense amplifiers 325-a of the sense amplifier array 320).

[0110] Continuing with the illustrative example, the sense amplifier array 320-a can be configured with various multiplexing and multiplexing to support a 10-bit or 10-conductor tile bus 311-a. In one example, this configuration can correspond to a coupling with the sense amplifier array 320-a where each of the conductors of the respective tile bus 311-a is coupled with a single dedicated sense amplifier 325-a (e.g., where n=p=10). In another example, this configuration can correspond to a sense amplifier array 320-a where the conductors of the respective tile bus 311-a are selectively coupled with a subset of the sense amplifiers 325-a of the sense amplifier array 320-a (e.g., where n>p). For example, the sense amplifier arrays 320-a may each include 80 sense amplifiers 325 (e.g., where n=80), and the sense amplifier arrays 320-a may include a selection component or multiplexer configured to select one of eight subsets of ten sense amplifiers 325-a or to couple one of the eight subsets to a corresponding tile bus 311-a.

[0111] Continuing with the illustrative example, the memory cells 205 corresponding to a given tile path 310-a can be configured with various multiplexing and multiplexing to support the described coupling with the sense amplifier array 320-a. In one example, each of the tile paths 310-a can include or otherwise couple with 2,560 digit lines 215-a (e.g., where m=2,560). Depending on the different configurations of the memory layout 300, the digit line multiplexer 315-a can be configured to select one of 256 subsets of ten digit lines 215-a or couple one of the 256 subsets with a corresponding sense amplifier array 320-a (e.g., supporting a 10-bit or 10-conductor tile bus 311-a with a sense amplifier array 320-a having ten sense amplifiers 325-a), or the digit line multiplexer 315-a can be configured to select one of 32 subsets of 80 digit lines 215-a or couple one of the 32 subsets with a corresponding sense amplifier array 320-a (e.g., supporting a 10-bit or 10-conductor tile bus 311-a with a sense amplifier array 320-a having 80 sense amplifiers 325-a, the 80 sense amplifiers 325-a being arranged as eight selectable subsets of sense amplifiers 325-a).

[0112] In one example of the memory layout 300, each of the tile paths 310-a may also include or otherwise be associated with 2,048 word lines 210. Thus, according to the illustrative example, the memory layout 300 may include memory tiles that each have 5,242,880 memory cells 205. When the memory layout 300 refers to a segment or bank of a memory device having 64 memory tiles, the memory layout 300 may thus illustrate an arrangement that supports selective access to an array 335,544,320 memory cells 205 using a data path bus 351 associated with 256 bits of data transfer (e.g., 256 conductive traces).

[0113] In some examples, word lines 210 may be accessed together across multiple memory tiles (e.g., all or a subset of memory tiles within a bank or sector), or signals used to activate word lines 210 of different memory tiles may be shared or driven together. For example, in response to a particular prefetch or other access command, a page or row activation may correspond to the activation of 20,480 memory cells 205 or digit lines 215 (e.g., corresponding to 16,384 bits of data plus additional redundancy or parity bits), which may be distributed across 64 memory tiles, 32 memory tiles, 16 memory tiles, or some other number of memory tiles based on the particular multiplexing scheme of the memory layout 300 (e.g., according to different configurations of the digit line multiplexers 315-a or tile multiplexers 340). In other examples (e.g., according to various partial activation, partial deactivation, or other idling techniques), a particular prefetch or other access command may be associated with half that number of memory cells 205 or digit lines 215, one-quarter that number of memory cells 205 or digit lines 215, or some other amount. According to various examples of the described techniques, signals from such page or row activation may be selectively routed to various sense amplifier arrays 320-a of various tile paths 310-a.

[0114] In some examples, the data path 350 can be considered to end or terminate at a die data pad of a memory die, such as memory die 160 or memory die 200. Although the memory layout 300 illustrates an example in which a single data path 350 is coupled with the local memory controller 265-a, in other examples, the local memory controller 265, the local memory controller 165, or the device memory controller 155 can be selectively coupled with a set of more than one data path 350. In such examples, the memory die can include a data path multiplexer (not shown) configured to selectively couple the local memory controller 265, the local memory controller 165, or the device memory controller 155 with one or more of the corresponding data path buses to support various access operations.

[0115] Figure 4 1 illustrates an example layout of a memory tile 400 that supports circuitry borrowing for a memory array within a memory device according to examples as disclosed herein. The memory tile 400 illustrates a layout having levels (e.g., layers) relative to a thickness direction 401, which can refer to a direction perpendicular to a substrate or otherwise perpendicular to the plane of the memory cells 205. The memory tile 400 includes an example of an array level 410 and a circuit level 450, which can be shown relative to a substrate level 430. Although the memory tile 400 is illustrated with the array level 410 located above the circuit level 450 (e.g., relative to the substrate 430), in other examples or memory tiles 400, the array level 410 can be located below the circuit level 450. Furthermore, although one array level 410 and one circuit level 450 are shown in the example of memory tile 400 , other examples of memory tile 400 may include more than one array level 410 , or more than one circuit level 450 , or more than one array level 410 and more than one circuit level 450 .

[0116] The array level 410 includes a plurality of memory cells 205-b associated with word lines 210-b and digit lines 215-b that are configured to access the memory cells 205-b of the array level 410 (e.g., of the memory tile 400). For example, the array level 410 may include or be associated with k word lines 210-b (e.g., word lines 210-b-1 through 210-bk) and m digit lines 215-b (e.g., digit lines 215-b-1 through 215-bm) that are associated with memory cells 205-b-11 through 205-b-km (e.g., a number of (k×m) memory cells 205). In the illustrative example, the array level 410 may be associated with 2,048 word lines 210-b (e.g., where k=2,048) and 2,560 digit lines 215-b (e.g., where m=2,560), and thus may be associated with 5,242,880 memory cells 205-b. However, the described techniques may support memory tiles 400 having other numbers of memory cells 205, word lines 210, and digit lines 215.

[0117] Array level 410 is illustrated in a top view 411, showing word lines 210-b and digit lines 215-b intersecting respective memory cells 205-b. However, memory cells 205-b, word lines 210-b, and digit lines 215-b may be formed or located at different locations or sub-levels of memory tile 400 (e.g., in thickness direction 401). In one example, word lines 210-b may be located below memory cells 205-b (e.g., closer to substrate 430), and digit lines 215-b may be located below word lines 210-b. Furthermore, the array level may also include a plurality of plate lines 220 (not shown) or a common plate conductor, which may be formed or located at another location or sub-level of the memory tile 400 or array level 410. For example, a memory tile 400 or array level 410 may include a common plate conductor located above the memory cells 205-b (e.g., further away from the substrate 430) and shared by all of the memory cells 205-b of the array level 410 (e.g., of the memory tile 400), which may refer to a common electrical node for all of the memory cells 205-b (e.g., a common electrical node for the memory tile 400). In one example, an array of memory cells 205 that all share such a common electrical node or common plate may define the extent of the memory tile 400 (e.g., in terms of the number of word lines 210, the number of digit lines 215, or a dimension perpendicular to the thickness direction 401). However, in some instances, a memory tile 400 may be subdivided into sub-units having individually controllable board nodes, or multiple memory tiles 400 may share a single controllable board node, or such a common electrical node or common board of multiple individually controllable memory tiles 400 may be otherwise controlled to the same bias (e.g., commonly controlled).

[0118] Array levels 410 may be defined according to various constituent components in the thickness direction 401. In the depicted example having a common plate conductor above memory cell 205-b and digit line 215-b below word line 210-b, array level 410 may be defined in the thickness direction 401 by an illustrative extent that includes the common plate conductor and digit line 215-b and portions of array level 410 therebetween (e.g., word line 210-b and memory cell 205-b). In another example, the array level 410 can be defined by an illustrative extent of the memory cell 205-b in the thickness direction 401 (e.g., including various features specific to the respective memory cell 205-b, including storage elements such as capacitor 240 or configurable material memory elements, switching element 245 (if present), and other memory cell features), in which case the access lines or nodes (e.g., word line 210-b, digit line 215-b, and plate line 220) or the common plate conductor are considered to be outside (e.g., above or below) the array level 410. In some examples, the extent in the thickness direction 401 including the features of the memory cell 205-b can be considered to define the minimum extent of the array level 410 in the thickness direction 401.

[0119] The circuit level 450 may include various circuitry (e.g., tile-specific circuitry, circuitry corresponding primarily to the memory tile 400, circuitry corresponding to or primarily assigned to memory cells 205-b-11 through 205-b-km) configured to operate the memory cells 205-b of the array level 410. For example, the circuit level 450 may include various decoders, buffers, multiplexers, sense amplifiers, or other components that may be dedicated to the operation of the memory cells 205-b-11 through 205-b-km, and in various examples, such circuitry may not be used in the operation of other memory cells 205 in the same or adjacent segment (e.g., of another memory tile 400 (not shown)), or may be used in the operation of memory cells 205 of an adjacent memory tile 400 according to a particular operating mode. Circuit level 450 is illustrated in a top view 451 illustrating an example of a memory tile 400 including a word line decoder portion 460, a word line driver portion 465, a digit line decoder portion 470, and a digit line driver portion 475, although memory tile 400 may include circuit levels 450 having differently arranged components or more or fewer components primarily assigned to the operation of memory tile 400.

[0120] The word line decoder portion 460 and the word line driver portion 465 may correspond to the word lines 210-b-1 through 210-bk of the memory tile 400 and may be included in reference 400. Figure 22. The operation of the row decoder 225 described herein or otherwise referred to herein. Memory tile 400 illustrates an example in which circuit level 450 includes a word line decoder portion 460 and a word line driver portion 465 that correspond to different subsets of word lines 210-b-1 through 210-bk. For example, word line decoder portion 460-a and word line driver portion 465-a may correspond to word lines 210-b-1 through 210-b-(k / 2), and word line decoder portion 460-b and word line driver portion 465-b may correspond to word lines 210-b-(k / 2+1) through 210-bk. As illustrated, in some examples, word line decoder portion 460-a and word line driver portion 465-a may be located on an opposite end of memory tile 400 from word line decoder portion 460-b and word line driver portion 465-b (e.g., along the direction of word line 210-b).

[0121] The wordline decoder portion 460 and the wordline driver portion 465 can perform various operations associated with selective access or activation of wordline 210-b. For example, the wordline driver portion 465 can be configured to receive control signals (e.g., via the control bus 266) associated with access commands (e.g., read commands, write commands) corresponding to memory cells 205-b of the array level 410. In some examples, such access commands can be associated with commands to open a page of memory cells comprising a row of memory cells 205-b in the array level 410. The wordline driver portion 465 can also include components or circuitry (e.g., control buffers) for buffering associated with access commands. In some examples, the wordline driver portion 465 can include a voltage source for selectively activating the wordline 210-b, or can be in electronic communication with such a voltage source shared among multiple memory tiles 400. The word line decoder portion 460 may include various multiplexing components (eg, transistor networks) configured to couple a select voltage source with a selected one or more of the word lines 210 - b .

[0122] The digit line decoder portion 470 and the digit line driver portion 475 may correspond to the digit lines 215-b-1 through 215-bm of the memory tile 400 and may be included in reference 400. Figure 2310 . The operations of the column decoder 230, the sensing component 250, or the input / output component 260, or a combination thereof, described herein, or otherwise refer to such operations. In some examples, the digit line decoder portion 470 and the digit line driver portion 475 of the memory tile 400 may be collectively referred to as or may be associated with at least a portion of the tile path 310. The memory tile 400 illustrates an example in which the circuit level 450 includes a digit line decoder portion 470 and a digit line driver portion 475 that correspond to different subsets of the digit lines 215-b-1 through 215-bm. For example, the digit line decoder portion 470-a and the digit line driver portion 475-a may correspond to digit lines 215-b-1 through 215-b-(m / 2), and the digit line decoder portion 470-b and the digit line driver portion 475-b may correspond to digit lines 215-b-(m / 2+1) through 215-bm. As illustrated, in some examples, digit line decoder portion 470-a and digit line driver portion 475-a may be located on an end of memory tile 400 opposite digit line decoder portion 470-b and digit line driver portion 475-b (e.g., along the direction of digit line 215-b).

[0123] The digit line decoder portion 470 and the digit line driver portion 475 can perform various operations associated with selective access or activation of the digit line 215-b. For example, the digit line driver portion 475 can be configured to receive control signals associated with access commands (e.g., read commands, write commands) corresponding to the memory cells 205-b of the array level 410 (e.g., via the control bus 266). Additionally or alternatively, the digit line driver portion 475 can be configured to communicate data signals associated with access commands corresponding to the memory cells 205-b of the memory tile 400 (e.g., with the tile multiplexer 340, with the data path 350, via the tile bus 311, via the input / output component 260), and thus can include a transmitter, receiver, or transceiver associated with the tile bus 311. In other words, the memory tile 400 can be associated with a tile bus 311 connected to the digit line driver portions 475-a and 475-b (e.g., each coupled to a respective portion of the tile bus 311). In another example for defining the extent of the memory tile 400 (e.g., in terms of the number of word lines 210, the number of digit lines 215, or a dimension perpendicular to the thickness direction 401), all of the array memory cells 205 sharing the common tile bus 311 can define such extent. The digit line driver portion 475 can also include components or circuitry for buffering associated with access commands (e.g., a control buffer, a data buffer).

[0124] In some examples, the access command may be associated with a command to access or activate a subset of the digit lines 215-b of the memory tile 400, and each of the digit line decoder portions 470 may include a respective digit line multiplexer 315, or a portion thereof, that receives control signaling to perform the selective activation or connection via the control bus 266. In another example, each of the digit line driver portions 475 may include a respective sense amplifier array 320, or a portion thereof, that includes a plurality of sense amplifiers 325 (e.g., a respective subset or subarray of sense amplifiers 325) that may be selectively coupled to one of the digit lines 215-b (e.g., through the digit line multiplexer 315 of the respective digit line driver portion 475) in order to detect the logic state of a particular memory cell 205-b.

[0125] In some examples, the digit line driver portion 475 may include a voltage source for selectively activating or charging the digit line 215-b, or be in electronic communication with such a voltage source shared among multiple memory tiles. In some examples, the digit line driver portion 475 may include signal development components that develop, convert, or amplify signals to support detection of logic states from or writing logic states to the memory cells 205-b (e.g., the sense amplifier array 320 or between the sense amplifier array 320 and the memory cells 205-b).

[0126] In various examples, circuit levels 450 can be defined according to different constituent components in the thickness direction 401. In one example, circuit levels 450 can be defined in the thickness direction 401 by the furthest extent of circuitry corresponding to the operation of the memory tile 400 in the thickness direction 401 (e.g., the furthest extent of the union of tile-specific circuitry of the memory tile 400 in the thickness direction 401; the furthest extent shared by the word line decoder portion 460, the word line driver portion 465, the digit line decoder portion 470, and the digit line driver portion 475). In another example, the circuit level 450 can be defined in the thickness direction 401 by the extent in the thickness direction 401 of a portion of each type of circuit system corresponding to the operation of the memory tile 400 (e.g., the farthest extent of the intersection of the tile-specific circuit systems of the memory tile 400 in the thickness direction 401; the farthest extent shared by the word line decoder portion 460, the word line driver portion 465, the digit line decoder portion 470 and the digit line driver portion 475).

[0127] The memory tile 400 may also include or otherwise be associated with a routing hierarchy, which may be considered a routing hierarchy for the memory tile 400, a routing hierarchy for banks or segments of multiple (e.g., adjacent) memory tiles 400, a routing hierarchy for multiple banks or segments of a memory tile 400, or more generally a routing hierarchy for the memory die 160 or the memory die 200. For example, the memory tile 400 may include a routing hierarchy 420, which may be referred to as an “on-array” routing hierarchy, and a routing hierarchy 425, which may be referred to as a “below-array” routing hierarchy.

[0128] Routing levels 420 and 425 may include one or more levels or layers (e.g., stacked in the thickness direction 401) of conductive paths for routing signals or power (e.g., supplied voltage, supplied current) within the memory die. In one example, routing level 420 may include four layers of conductive paths, wherein two of the four layers each include multiple conductive paths perpendicular to word lines 210 (e.g., of array level 410), and two of the four layers each include multiple signal paths perpendicular to digit lines 215. In another example, routing level 425 may include three layers of conductive paths, wherein two of the three layers each include multiple conductive paths perpendicular to word lines 210, and one of the three layers includes multiple conductive paths perpendicular to digit lines 215. However, various arrangements of conductive paths may be used in routing levels 420 or 425, including layers with conductive paths in multiple directions or non-linear conductive paths. In some instances, one or more of the conductive paths of routing level 420 (e.g., a sublayer of routing level 420) may be formed from copper, and one or more of the conductive paths of routing level 425 (e.g., a sublayer of routing level 425) may be formed from tungsten, where such formation may include selective deposition or removal (e.g., etching) to form specific signal paths.

[0129] In some examples, an array level 410 or a circuit level 450 can be defined in the thickness direction 401 according to the relative positions of the routing layers. In one example, the array level 410 can correspond to a portion of the memory tile 400 between the routing level 420 and the routing level 425 (e.g., along the thickness direction 401). In another example, the circuit level 450 can correspond to a portion of the memory tile 400 between the routing level 425 and the substrate 430 or another routing level (not shown).

[0130] The memory tile 400 may also include conductors along the thickness direction 401, which may be referred to as "sockets" (not shown). The sockets may provide conductive paths between levels or layers of the memory tile 400, such as between adjacent levels (e.g., between the routing level 420 and the array level 410) or between non-adjacent levels (e.g., between the array level 410 and the circuit level 450). In various examples, the sockets may be located within the illustrative boundaries of the memory tile 400 (e.g., in a top view), outside the illustrative boundaries of the memory tile 400 (e.g., between memory tiles), or both.

[0131] As illustrated by the top view 451 of the circuit level 450, not all areas of the circuit level 450 of a memory tile 400 are occupied primarily by circuitry associated with the memory tile 400 (e.g., word line decoder portion 460, word line driver portion 465, digit line decoder portion 470, and digit line driver portion 475 collectively). Rather, the circuit level 450 also includes areas 480 useful for other purposes. In some examples, multiple memory tiles 400 (e.g., segments of memory tiles 400, quilts of memory tiles 400) can be associated with a data path 350, and the circuitry associated with the data path 350 can be distributed across respective areas 480 of multiple memory tiles 400.

[0132] Figure 5 Illustrated is an example of a memory array 500 that supports borrowing circuitry for a memory array according to examples as disclosed herein. The memory array 500 includes memory tiles 400-a that can be arranged in memory segments (e.g., segment 516, segment 518, segment 520). The memory array 500 can have any number of tiles and tile segments. For purposes of illustrating sharing or borrowing circuitry for memory segments 516, 518, 520, the top view is shown. Figure 5 4. Each memory tile 400-a may have various levels or layers (e.g., circuit level, array level, routing level) in the layout. For example, each of the memory tiles 400-a may include an array level 410 and a circuit level 450. In some cases, for each memory tile 400-a, the array level 410 includes a respective memory sub-array including a respective set of memory cells, a respective set of row decoding circuitry, and a respective set of column decoding circuitry. Figure 5 As depicted, circuit level 450 may include circuitry corresponding to operating the memory cells of array level 410, such as sensing circuitry or other circuitry specific to memory tile 400-a. Figure 4Additional examples of the various levels or layers and their potential configurations are described in more detail in .

[0133] The memory array 500 may include multiple sectors and multiple sets of shared circuitry. For example, the memory array 500 may include a row circuitry portion 501 and a column circuitry portion 502, shown for illustrative purposes as rectangular areas of respective memory tiles 400-a. The row circuitry portion 501 may include or otherwise refer to circuitry such as the word line decoder portion 460, the word line driver portion 465, or both, and the column circuitry portion 502 may include or otherwise refer to circuitry such as the digit line decoder portion 470, the digit line driver portion 475, or both, as referenced in the accompanying drawings. Figure 4 In some examples, one or more row circuitry portions 501, column circuitry portions 502, or portions of both may be included in a set of shared circuitry 546. In some examples, a set of shared circuitry 546 may include a sense amplifier array 320 (e.g., several sets of sense amplifiers 325) or other components shared or "borrowed" by adjacent memory tiles 400 or segments (e.g., first segment 516, second segment 518, third segment 520) in the memory array 500. In some cases, each set of shared circuitry 546 may be shared by two memory segments. Figure 5 , the first segment 516 and the second segment 518 may share shared circuitry 546 - a , and the first segment 516 and the third segment 520 may share shared circuitry 546 - b , as described in more detail below.

[0134] Control signal drivers (e.g., drivers 504-a-1, 504-a-2, 504-b-1, and 504-b-2), which may alternatively be referred to as buffers in some cases, are used to drive the shared circuitry 546 in a given memory bank. Drivers may also be located at the array level 410, below the memory banks, or at the "bottom side" of the memory tile 400-a (e.g., at the circuitry level 450). In some cases, the diagrams illustrated in FIG. Figure 5 Each driver in represents one or more drivers. The memory controller or control bus 266 can be coupled to several groups of drivers and configured to provide control signals to each group of drivers. The drivers 504 output control signals for the shared circuitry 546 via interconnects or conductive lines 538 and 540 and associated sockets 514. For example, the drivers 504 can output timing signals (e.g., phase) for the sense amplifiers 325 included in the group of shared circuitry 546 or otherwise control the timing signals. In some cases, the memory tiles 400 within corresponding memory segments of a group of driver memory tiles 400 can be shared and coupled to the group of shared circuitry via sockets 514.

[0135] In some cases, each segment may have (or correspond to) a set of drivers (located above or below a set of drivers), and the drivers may be divided into two groups (or types). The memory array 500 has several sets of shared circuitry 546 for the memory segments, which are operated using some control signals borrowed from the memory segment above and some control signals borrowed from the memory segment below. For example, a set of shared circuitry 546-a may be shared by a first segment 516 and a second segment 518 located above the first segment 516. A set of shared circuitry 546-a may be operated by a first type of driver 504-a-1 (corresponding to the first segment 516) and a second type of driver 504-b-1 (corresponding to the second segment 518). As another example, a set of shared circuitry 546-b may be shared by a first segment 516 and a third segment 520 located below the first segment 516. A set of shared circuitry 546 - b may be operated by a first type of driver 504 - a - 2 (corresponding to the third segment 520 ) and a second type of driver 504 - b - 2 (corresponding to the first segment 516 ).

[0136] When performing access operations on memory cells in segment 516, aspects of both the set of shared circuitry 546-a and the set of shared circuitry 546-b can be used, and thus each of the drivers 504-a-1, 504-a-2, 504-b-1, and 504-b-2 can be used. That is, when performing access operations on memory cells in a segment, the driver associated with the segment, the driver associated with the first (above) adjacent segment, and the driver associated with the second (below) adjacent segment can be utilized. In some cases, at least two types of drivers can be used. A first type of driver can be borrowed from the above adjacent segment and used in conjunction with a second type of driver from the access segment to operate the circuitry shared (e.g., common) by the access segment and the above adjacent segment. A second type of driver can be borrowed from the below adjacent segment and used in conjunction with the first type of driver from the access segment to operate the circuitry shared (e.g., common) by the access segment and the below adjacent segment. This pattern of driver grouping (e.g., into types, categories, which may be based on signals generated or output thereby) may be repeated across any number of segments, although for clarity may be omitted. Figure 5 The diagram is illustrated in the context of a less representative section.

[0137] In some cases, each set of drivers may occupy a corresponding area that overlaps with a corresponding memory segment. In some cases, each set of drivers may be included in one or more corresponding memory tiles of a corresponding memory segment. Respective drivers of a first type (e.g., driver 504-a-1 and driver 504-a-2) output a first type of control signal. Respective drivers of a second type (e.g., driver 504-b-1 and driver 504-b-2) output a second type of control signal.

[0138] A first type of control signal may be associated with a first set of functions or components of a set of shared circuitry 546, and a second type of control signal may be associated with a second set of functions or components of a set of shared circuitry 546. For example, the first type of control signal may include timing signals for a first set of functions performed by each set of shared circuitry 546, and the second type of control signal may include timing signals for a second set of functions performed by each set of shared circuitry 546. The first set of functions or components may be independent from the second set of functions or components, and thus the first type of control signal may be independent from the second type of control signal.

[0139] A set of shared circuitry 546 may include sets of data path circuitry (e.g., circuitry of data path 350) that communicate information associated with access operations to memory cells contained in respective memory segments (e.g., first memory segment 516, second memory segment 518). The data path circuitry may be shared by memory tiles (e.g., corresponding to operating memory tiles, corresponding to data exchange between memory tiles and input / output components), and may be distributed across the circuit layers 450 of two or more memory tiles. Figure 5 , conductive lines 542 and 544 may route (carry) signals from the controller to the driver inputs for the driver 504. Conductive lines 538 and 540 may route (carry) signals from the outputs of the driver 504 to the shared circuitry. Access to the memory cells 205 within the memory tile 400-a may be controlled by row decoders (e.g., respective row circuitry portion 501, respective word line decoder portion 460) and column decoders (e.g., respective column circuitry portion 502, respective column decoder portion 470), which may be coupled to, include, or otherwise associated with one or more sense amplifier arrays 320.

[0140] like Figure 5, one or more sockets 514 (e.g., vias, conductive plugs) can provide interconnections (e.g., routing or carrying signals) between components at different layers or levels of the memory tiles 400. The sockets 514 can be located between memory tiles 400 within the array 500 (e.g., in the gaps between different memory tiles 400). For example, the sockets 514 can provide interconnections for data path circuitry between sense amplifiers 325 (e.g., of the sense amplifier array 320) and control signal drivers (e.g., drivers 504-a-1, 504-a-2, 504-b-1, 504-b-2). The sense amplifiers 325 are each configured to sense logic states stored by memory cells included in a respective first memory segment (e.g., memory segment 516) and memory cells included in a respective second memory segment (e.g., memory segment 518).

[0141] In some cases, the second type of additional driver 504-b-3 may correspond to a first edge segment 528 of the memory array. In some cases, the second type of additional driver 504-b-3 may be coupled to a set of shared circuitry 546-c that is common to the first edge segment 528 and another memory segment (not shown) adjacent to the first edge segment 528. For example, since each memory segment may correspond to two sets of shared circuitry 546—one set shared with the memory segment above and one set shared with the memory segment below—the memory segment adjacent to the first edge segment 528 may not have an upper memory segment shared with it, and thus the first edge segment 528 may include or otherwise correspond to components that would otherwise be shared with the upper segment. For example, the first edge segment 528 may include or otherwise correspond to aspects of the set of shared circuitry 546-c (e.g., overlapping, located above, or below the aspect in area). As another example, the first edge segment 528 may include or otherwise correspond to an additional driver 504 - b - 3 of a second type that may support operation of a set of shared circuitry 546 - c when accessing a memory segment adjacent to the first edge segment 528 .

[0142] In some cases, the first edge segment 528 may lack (e.g., not include, have) one or more components that are included in other memory segments (e.g., memory segments 516, 518, 520) but are not used to support operation of a set of shared circuitry 546-c or are otherwise shared with underlying memory segments. For example, the first edge segment 528 may not include memory cells.

[0143] In some cases, the second type of additional driver 504-a-3 may correspond to a second edge segment 530 of the memory array. In some cases, the second type of additional driver 504-a-3 may be coupled to a second set of shared circuitry 546-d that is common to the second edge segment 530 and a second memory segment (not shown) adjacent to the second edge segment 530. For example, because each memory segment may correspond to two sets of shared circuitry 546—one set shared with the memory segment above and one set shared with the memory segment below—the memory segment adjacent to the second edge segment 530 may not have an upper memory segment shared with it, and thus the second edge segment 530 may include or otherwise correspond to components that would otherwise be shared with the upper segment. For example, the second edge segment 530 may include or otherwise correspond to aspects of (e.g., overlap with, be located above, or be located below) a set of shared circuitry 546-d. As another example, the second edge segment 530 may include or otherwise correspond to additional drivers 504 - a - 3 of a second type that may support operation of a set of shared circuitry 546 - d when accessing memory segments adjacent to the second edge segment 530 .

[0144] In some cases, the second edge segment 530 may lack (e.g., not include, have) one or more components that are included in other memory segments (e.g., memory segments 516, 518, 520) but are not used to support operation of a set of shared circuitry 546-d or are otherwise shared with underlying memory segments. For example, the second edge segment 530 may not include memory cells.

[0145] like Figure 5 , in some cases, first edge segment 528 may occupy an area that does not overlap with any drivers of the first type (e.g., no driver 504-a), and second edge segment 530 may occupy an area that does not overlap with any drivers of the second type (e.g., no driver 504-b). In some cases, additional drivers of the second type 504-b may be located below first edge segment 528. In some cases, additional drivers of the first type 504-a may be located below second edge segment 530.

[0146] As a result of the sharing or borrowing circuitry described herein, there are not two types of drivers 504-a and 504-b at either the edge segment 528 or the edge segment 530 of the memory array 500. Instead, only one borrowing type of driver is located at the first edge segment 528, and only another borrowing type of driver is located at the second edge segment 530. Thus, space is saved in the edge memory tiles of the memory array 500 (see driver 504-b-3 at edge segment 528 of array 500 and driver 504-a-3 at edge segment 530 of array 504).

[0147] Figure 6 A block diagram 600 is shown of a memory device 605 supporting circuitry for borrowing a memory array according to examples as disclosed herein. The memory device 605 may be a memory device 605 as described in reference Figures 1 to 5 Memory device 605 may include an identification manager 610, a control signal manager 615, a shared circuitry manager 620, and an access manager 625. Each of these modules may communicate with each other directly or indirectly (eg, via one or more buses).

[0148] Identification manager 610 can identify a first memory segment of a memory array for an access operation.The first memory segment can be located between a second memory segment of the memory array and a third memory segment of the memory array.

[0149] The control signal manager 615 may use a first set of drivers associated with the first memory segment to generate a first type of control signal.In some examples, the control signal manager 615 may use a second set of drivers associated with the first memory segment to generate a second type of control signal.

[0150] In some examples, the control signal manager 615 may use drivers associated with the second memory segment to generate additional control signals of the second type. In some examples, the control signal manager 615 may use drivers associated with the third memory segment to generate additional control signals of the first type. In some cases, the control signal manager 615 may use a third set of drivers associated with the second memory segment to generate additional control signals of the second type. In some examples, the control signal manager 615 may use a fourth set of drivers associated with the third memory segment to generate additional control signals of the first type.

[0151] In some examples, the control signal manager 615 may couple drivers associated with the first memory segment and a first subset of drivers associated with the second memory segment with the first set of circuitry based on identifying the first memory segment for an access operation.

[0152] In some examples, control signal manager 615 may couple drivers associated with the first memory segment and a second subset of drivers associated with the third memory segment to the second circuitry based on identifying the first memory segment for access operations. Shared circuitry manager 620 may operate a first set of circuitry shared by the first and second memory segments using the drivers associated with the first memory segment and the drivers associated with the second memory segment based on identifying the first memory segment for access operations.

[0153] In some examples, shared circuitry manager 620 may operate a second set of circuitry shared by the first and third memory segments using drivers associated with the first and third memory segments based on identifying the first memory segment for access operations.

[0154] In some examples, shared circuitry manager 620 may use a first set of circuitry to perform a first set of functions based on a first type of control signal and a second set of functions based on additional control signals of a second type.

[0155] In some examples, performing the access operation includes performing a first set of functions and a second set of functions. In some cases, the first set of functions is independent of the second set of functions.

[0156] In some cases, the first set of circuitry includes a first set of sense amplifiers, a first subset of the first set of sense amplifiers underlying the memory tiles of the first memory bank, and a second subset of the first set of sense amplifiers underlying the memory tiles of the second memory bank. In some cases, the second set of circuitry includes a second set of sense amplifiers, a first subset of the second set of sense amplifiers underlying the memory tiles of the first memory bank, and a second subset of the second set of sense amplifiers underlying the memory tiles of the third memory bank.

[0157] The shared circuitry manager 620 may operate the first set of sense amplifiers using control signals of a first type generated by the first set of drivers and additional control signals of a second type generated by the third set of drivers.

[0158] In some examples, shared circuitry manager 620 may operate the second set of sense amplifiers using additional control signals of the first type generated by the fourth set of drivers and control signals of the second type generated by the second set of drivers.

[0159] In some cases, a first subset of the first set of circuitry is contained in memory tiles within a first memory bank. In some cases, a second subset of the first set of circuitry is contained in memory tiles within a second memory bank.

[0160] In some cases, drivers associated with a first memory segment are contained in one or more memory tiles within the first memory segment. In some cases, drivers associated with a second memory segment are contained in one or more memory tiles within the second memory segment. In some cases, drivers associated with a third memory segment are contained in one or more memory tiles within the second memory segment.

[0161] The access manager 625 may perform access operations based on operating the first set of sense amplifiers and operating the second set of sense amplifiers.

[0162] Figure 7 A flowchart illustrating one or several methods 700 of supporting circuitry borrowing for a memory array according to aspects of the present disclosure is shown. The operations of the method 700 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 700 may be implemented by a memory device or components thereof as described herein. Figures 1 to 6 The memory device described performs. In some examples, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use special-purpose hardware to perform aspects of the described functions.

[0163] At 705, the memory device may identify a first memory segment of the memory array for an access operation, the first memory segment being located between a second memory segment of the memory array and a third memory segment of the memory array. The operation of 705 may be performed according to the methods described herein. In some examples, the operation may be performed as described in reference to Figure 6 Aspects of the operations of the access manager execution 705 are described.

[0164] At 710, the memory device may, based on the identification, operate a first set of circuit systems shared by the first memory segment and the second memory segment using a driver associated with the first memory segment and a driver associated with the second memory segment. The operations of 710 may be performed according to the methods described herein. In some examples, the first set of circuit systems may be shared by the first memory segment and the second memory segment using a driver associated with the first memory segment and a driver associated with the second memory segment. Figure 6 Aspects of the operations of the shared circuit system manager execution 710 are described.

[0165] At 715, the memory device may, based on the identification, use a driver associated with the first memory segment and a driver associated with the third memory segment to operate a second set of circuit systems shared by the first memory segment and the third memory segment. The operation of 715 may be performed according to the methods described herein. In some examples, the operation may be performed by a driver as described in reference to Figure 6 Aspects of the operations of the shared circuit system manager execution 715 are described.

[0166] At 720, the memory device may perform an access operation based on operating the first set of circuit systems and operating the second set of circuit systems. The operation of 720 may be performed according to the methods described herein. In some examples, the memory device may be configured as described in reference to Figure 6 Aspects of the operations of the access manager 720 are described.

[0167] In some examples, an apparatus as described herein may perform a method or methods, such as method 700. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: identifying a first memory segment of a memory array for an access operation, the first memory segment being located between a second memory segment of the memory array and a third memory segment of the memory array; based on the identification, operating a first set of circuitry shared by the first memory segment and the second memory segment using a driver associated with the first memory segment and a driver associated with the second memory segment; based on the identification, operating a second set of circuitry shared by the first memory segment and the third memory segment using a driver associated with the first memory segment and a driver associated with the third memory segment; and performing the access operation based on operating the first set of circuitry and operating the second set of circuitry.

[0168] Some examples of method 700 and the apparatus described herein may further include operations, features, means, or instructions for: generating a first type of control signal using a first subset of drivers associated with a first memory segment; generating a second type of control signal using a second subset of drivers associated with the first memory segment; generating additional control signals of the second type using drivers associated with the second memory segment; and generating additional control signals of the first type using drivers associated with a third memory segment.

[0169] Some instances of method 700 and the apparatus described herein may further include operations, features, means, or instructions for coupling, based on the identification, a first subset of drivers associated with the first memory segment and drivers associated with the second memory segment to a first set of circuit systems; and coupling, based on the identification, a second subset of drivers associated with the first memory segment and drivers associated with the third memory segment to a second set of circuit systems.

[0170] Some examples of method 700 and apparatus described herein may further include operations, features, means, or instructions for: using a first set of circuitry, performing a first set of functions based on a first type of control signal and performing a second set of functions based on an additional control signal of a second type, wherein performing the access operation includes performing the first set of functions and the second set of functions. In some examples of method 700 and apparatus described herein, the first set of functions may be independent of the second set of functions.

[0171] In some examples of method 700 and apparatus described herein, a first set of circuitry includes a first set of sense amplifiers, a first subset of the first set of sense amplifiers underlying memory tiles of a first memory segment, and a second subset of the first set of sense amplifiers underlying memory tiles of a second memory segment, and a second set of circuitry includes a second set of sense amplifiers. The first subset of the second set of sense amplifiers may underlying memory tiles of the first memory segment and the second subset of the second set of sense amplifiers may underlying memory tiles of a third memory segment.

[0172] In some examples of method 700 and apparatus described herein, a first subset of the first set of circuitry may be included in memory tiles within a first memory segment, and a second subset of the first set of circuitry may be included in memory tiles within a second memory segment.

[0173] In some examples of method 700 and the apparatus described herein, drivers associated with a first memory segment may be included in one or more memory tiles within the first memory segment, drivers associated with a second memory segment may be included in one or more memory tiles within the second memory segment, and drivers associated with a third memory segment may be included in one or more memory tiles within the second memory segment.

[0174] Figure 8 A flowchart illustrating one or several methods 800 of supporting circuitry borrowing for a memory array according to aspects of the present disclosure is shown. The operations of the method 800 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 800 may be implemented by a memory device or components thereof as described herein. Figures 1 to 6 The memory device described performs. In some examples, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use special-purpose hardware to perform aspects of the described functions.

[0175] At 805, the memory device may identify a first memory segment of the memory array for an access operation, the first memory segment being located between a second memory segment of the memory array and a third memory segment of the memory array. The operation of 805 may be performed according to the methods described herein. In some examples, the operation may be performed as described in reference to Figure 6 Aspects of the operations of the identification manager execution 805 are described.

[0176] At 810, a memory device may generate a first type of control signal using a first set of drivers associated with a first memory segment. The operations of 810 may be performed according to the methods described herein. In some examples, the control signal may be generated by a first set of drivers associated with a first memory segment. Figure 6 Aspects of the operation of the control signal manager execution 810 are described.

[0177] At 815, the memory device may generate a second type of control signal using a second set of drivers associated with the first memory segment. The operation of 815 may be performed according to the methods described herein. In some examples, the control signal may be generated by a second set of drivers associated with the first memory segment. Figure 6 Aspects of the operation of the control signal manager execution 815 are described.

[0178] At 820, the memory device may generate an additional control signal of the second type using a third set of drivers associated with the second memory segment. The operations of 820 may be performed according to the methods described herein. In some examples, the control signal may be generated by a controller such as described in reference to FIG. Figure 6 Aspects of the operation of the control signal manager execution 820 are described.

[0179] At 825, the memory device may use a fourth set of drivers associated with the third memory segment to generate additional control signals of the first type. The operations of 825 may be performed according to the methods described herein. In some examples, the control signal may be generated by a controller such as described in reference to FIG. Figure 6 Aspects of the operation of the control signal manager execution 825 are described.

[0180] At 830, the memory device may operate the first set of sense amplifiers using a first type of control signal generated by the first set of drivers and an additional second type of control signal generated by the third set of drivers. The operations of 830 may be performed according to the methods described herein. In some examples, the memory device may be configured as described in reference to FIG. Figure 6 Aspects of the operations of the shared circuit system manager execution 830 are described.

[0181] At 835, the memory device may operate the second set of sense amplifiers using additional control signals of the first type generated by the fourth set of drivers and control signals of the second type generated by the second set of drivers. The operations of 835 may be performed according to the methods described herein. In some examples, the memory device may be configured as described in reference to FIG. Figure 6 Aspects of the operations of the shared circuit system manager execution 835 are described.

[0182] At 840, the memory device may perform an access operation based on operating the first set of sense amplifiers and operating the second set of sense amplifiers. The operation of 840 may be performed according to the methods described herein. In some examples, the memory device may be configured as described in reference to FIG. Figure 6 Aspects of the operations of the access manager execution 840 are described.

[0183] In some examples, an apparatus as described herein may perform a method or methods, such as method 800. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: identifying a first memory segment of a memory array for an access operation, the first memory segment being located between a second memory segment of the memory array and a third memory segment of the memory array; generating a first type of control signal using a first set of drivers associated with the first memory segment; generating a second type of control signal using a second set of drivers associated with the first memory segment; generating an additional second type of control signal using a third set of drivers associated with the second memory segment; generating an additional first type of control signal using a fourth set of drivers associated with the third memory segment; operating a first set of sense amplifiers using the first type of control signal generated by the first set of drivers and the additional second type of control signal generated by the third set of drivers; operating a second set of sense amplifiers using the additional first type of control signal generated by the fourth set of drivers and the second type of control signal generated by the second set of drivers; and performing the access operation based on operating the first set of sense amplifiers and operating the second set of sense amplifiers.

[0184] It should be noted that the methods described above describe possible implementations, and that operations and steps may be rearranged or otherwise modified and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0185] An apparatus is described. The apparatus may include: a memory array comprising a plurality of memory banks; a plurality of sets of shared circuitry, each of which is common to a respective first memory bank in the plurality of memory banks and a respective second memory bank in the plurality of memory banks; and a plurality of sets of drivers, each of which corresponds to a respective memory bank in the plurality of memory banks. Each set of drivers in the plurality of sets may include: a respective driver of a first type coupled to a respective first set of shared circuitry in the plurality of shared circuitry, the respective first set of shared circuitry being common to the respective memory bank and a first other memory bank in the plurality of memory banks; and a respective driver of a second type coupled to a respective second set of shared circuitry in the plurality of shared circuitry, the respective second set of shared circuitry being common to the respective memory bank and a second other memory bank in the plurality of memory banks.

[0186] Some instances of the apparatus may include: additional drivers of a first type corresponding to a first edge segment at a first edge of a memory array, wherein the additional drivers of the first type may be coupled to a first set of shared circuitry in the group that may be common to the first edge segment and the first memory segment in the group; and additional drivers of a second type corresponding to a second edge segment at a second edge of the memory array, wherein the additional drivers of the second type may be coupled to a second set of shared circuitry in the group that may be common to the second edge segment and the second memory segment in the group.

[0187] In some examples, the first edge segment occupies an area that does not overlap with any drivers of the second type, and the second edge segment occupies an area that does not overlap with any drivers of the first type.

[0188] In some examples, additional drivers of the first type may be located under the first edge segment, and additional drivers of the second type may be located under the second edge segment.

[0189] In some examples, each set of drivers in the set occupies a respective area that overlaps with a respective memory segment.

[0190] In some examples, each memory segment in the set includes a respective memory tile, and each set of drivers in the set may be included in one or more of the respective memory tiles of the respective memory segment.

[0191] In some examples, each memory tile in a respective set of memory tiles includes a respective memory sub-array including a respective set of memory cells, a respective set of row decoding circuitry, and a respective set of column decoding circuitry.

[0192] In some examples, one of the sets of shared circuitry includes sets of sense amplifiers that can each be configured to sense logic states stored by memory cells included in a respective first memory segment and memory cells included in a respective second memory segment.

[0193] In some examples, one of the sets of shared circuitry includes sets of data path circuitry that can each be configured to communicate information associated with access operations to memory cells included in a respective first memory segment and memory cells included in a respective second memory segment.

[0194] In some examples, a respective driver of the first type may be configured to output a first type of control signal, and a respective driver of the second type may be configured to output a second type of control signal.

[0195] In some examples, the first type of control signals includes timing signals for a first set of functions performed by each set of shared circuitry, and the second type of control signals includes timing signals for a second set of functions performed by each set of shared circuitry.

[0196] In some examples, the first set of functions may be independent of the second set of functions.

[0197] Some examples of the apparatus may include a memory controller coupled with one of the sets of drivers and configured to provide control signals to each set of drivers in the set.

[0198] An apparatus is described. The apparatus may include a memory array including a first memory segment positioned between a second memory segment and a third memory segment. A first set of circuitry may be configured to selectively couple with the first memory segment and the second memory segment. A second set of circuitry may be configured to selectively couple with the first memory segment and the third memory segment. A first set of drivers may be associated with the first memory segment, wherein a first subset of the first set of drivers is configured to generate a first type of control signal for the first set of circuitry, and a second subset of the first set of drivers is configured to generate a second type of control signal for the second set of circuitry. A second set of drivers may be associated with the second memory segment, wherein a subset of the second set of drivers is configured to generate the second type of control signal for the first set of circuitry, and a third set of drivers may be associated with the third memory segment, wherein a subset of the third set of drivers is configured to generate the first type of control signal for the second set of circuitry.

[0199] In some examples, the first set of circuitry occupies an area overlapping the first memory bank and the second memory bank, and the second set of circuitry occupies an area overlapping the first memory bank and the third memory bank.

[0200] In some examples, a first set of drivers occupies an area overlapping the first memory segment, a second set of drivers occupies an area overlapping the second memory segment, and a third set of drivers occupies an area overlapping the third memory segment.

[0201] Any of a variety of different technologies and techniques may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one skilled in the art will understand that a signal may represent a signal bus, where the bus may have various bit widths.

[0202] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are said to be in electronic communication (or in conductive contact or connected or coupled) with one another if any conductive path exists between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact or connected or coupled) with one another may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that includes an intermediate component, such as a switch, transistor, or other component. In some cases, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components, such as a switch or transistor.

[0203] The term "coupling" refers to the condition of moving from an open-circuit relationship between components, in which signals are currently unable to pass between components via conductive paths, to a closed-circuit relationship between components in which signals can pass between components via conductive paths. When a component (e.g., a controller) couples other components together, the component begins to change by allowing signals to flow between the other components via conductive paths that previously did not permit signal flow.

[0204] The term "isolation" refers to a relationship between components where signals are no longer able to flow between them. Components are isolated from one another if an open circuit exists between them. For example, when a switch is open, two components separated by a switch positioned between them are isolated from one another. When a controller isolates two components, it effects a change that prevents signals from flowing between them using the conductive path that previously allowed signal flow.

[0205] As used herein, the term "layer" refers to a layer or sheet of a geometric structure. Each layer may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer may be a three-dimensional structure in which two dimensions are greater than the third, such as a thin film. A layer may comprise different elements, components, and / or materials. In some cases, a layer may be composed of two or more sublayers. In some figures of the accompanying drawings, two dimensions of a three-dimensional layer are depicted for illustrative purposes.

[0206] As used herein, the term "substantially" means that the modified characteristic (eg, a verb or adjective modified by the term substantially) need not be absolute but is close enough to realize the advantage of the characteristic.

[0207] The devices including memory arrays discussed herein can be formed on a semiconductor substrate (e.g., silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping means.

[0208] The switching element or transistor discussed herein may represent a field-effect transistor (FET) and include a three-terminal device comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via a conductive material (e.g., metal). The source and drain can be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority of carriers are signals), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority of carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate, the transistor can be "turned on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor gate, the transistor can be "turned off" or "deactivated."

[0209] The description set forth herein in conjunction with the accompanying drawings describes exemplary configurations and does not represent all possible embodiments that may be implemented or within the scope of the claims. As used herein, the term "exemplary" means "serving as an example, instance, or illustration" rather than "preferred" or "advantageous over other embodiments." The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described embodiments.

[0210] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0211] The various illustrative blocks and modules described herein in conjunction with the present disclosure may be implemented or executed using a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a combination of multiple microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration).

[0212] The functions described herein can be implemented by hardware, software executed by a processor, firmware, or any combination thereof. If implemented by software executed by a processor, the functions can be stored as one or more instructions or codes on a computer-readable medium or transmitted via the computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features that implement the functions can also be physically located at various locations, including parts that are distributed so that the functions are implemented at different physical locations. Moreover, as used herein, included in the claims, "or" as used in a list of items (for example, a list of items starting with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" could be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be construed in the same manner as the phrase "based at least in part on."

[0213] The description herein is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device comprising: a memory array comprising a plurality of memory banks; Multiple shared circuit systems; and a plurality of sets of drivers, each corresponding to a respective memory bank of the plurality of memory banks, wherein each set of drivers in the plurality of sets of drivers comprises: a respective driver of a first type coupled to a respective first set of shared circuitry of the plurality of sets of shared circuitry, the respective first set of shared circuitry being common to a respective first memory bank and a respective second memory bank of the plurality of memory banks; and A respective driver of a second type is coupled to a respective second set of shared circuitry of the plurality of sets of shared circuitry, the respective second set of shared circuitry being common to the respective first and third memory segments of the plurality of memory segments.

2. The memory device of claim 1 , further comprising: an additional driver of the first type corresponding to a first edge segment at a first edge of the memory array, wherein the additional driver of the first type is coupled to a first set of shared circuitry of the plurality of sets of shared circuitry, the first set of shared circuitry being common to the first edge segment and a first memory segment of the plurality of memory segments; and An additional driver of the second type corresponds to a second edge segment at a second edge of the memory array, wherein the additional driver of the second type is coupled to a second set of shared circuitry among the multiple sets of shared circuitry, the second set of shared circuitry being common to the second edge segment and a second memory segment among the multiple memory segments.

3. The memory device of claim 2, wherein: The first edge segment occupies an area that does not overlap with any drivers of the second type; and The second edge section occupies an area that does not overlap with any drivers of the first type.

4. The memory device of claim 2, wherein: The additional driver of the first type is located below the first edge section; and The additional driver of the second type is located below the second edge section.

5. The memory device of claim 1 , wherein: Each set of drivers in the plurality of sets of drivers occupies a respective area overlapping the respective memory segment.

6. The memory device of claim 1 , wherein: Each memory bank of the plurality of memory banks comprises a respective memory tile; and Each set of drivers in the plurality of sets of drivers is included in one or more of the respective memory tiles of the respective memory segment.

7. The memory device of claim 6, wherein: Each of the respective memory tiles includes a respective memory sub-array comprising a respective set of memory cells, a respective set of row decoding circuitry, and a respective set of column decoding circuitry.

8. The memory device of claim 6, wherein: The multiple sets of shared circuitry include multiple sets of sense amplifiers each configured to sense logic states stored by memory cells included in the respective first memory segment and memory cells included in the respective second memory segment.

9. The memory device of claim 6, wherein: The multiple sets of shared circuitry include multiple sets of data path circuitry each configured to communicate information associated with access operations to memory cells included in the respective first memory segment and memory cells included in the respective second memory segment.

10. The memory device of claim 1, wherein: The respective drivers of the first type are configured to output control signals of a first type; and The respective drivers of the second type are configured to output control signals of a second type.

11. The memory device of claim 10, wherein: The control signals of the first type include timing signals for a first set of functions performed by each set of shared circuitry; and The control signals of the second type include timing signals for a second set of functions performed by each set of shared circuitry.

12. The memory device of claim 11, wherein: The first set of functions is independent of the second set of functions.

13. The memory device of claim 1 , further comprising: A memory controller is coupled to the plurality of sets of drivers and is configured to provide a control signal to each set of drivers in the plurality of sets of drivers.

14. A memory device comprising: a memory array comprising a first memory segment located between a second memory segment and a third memory segment; a first set of circuitry configured to selectively couple with the first memory segment and the second memory segment; a second set of circuitry configured to selectively couple with the first memory segment and the third memory segment; a first set of drivers associated with the first memory segment, wherein a first subset of the first set of drivers is configured to generate a first type of control signal for the first set of circuitry and a second subset of the first set of drivers is configured to generate a second type of control signal for the second set of circuitry; a second set of drivers associated with the second memory segment, wherein a subset of the second set of drivers is configured to generate control signals of the second type for the first set of circuitry; and A third set of drivers is associated with the third memory segment, wherein a subset of the third set of drivers is configured to generate control signals of the first type for the second set of circuitry.

15. The memory device of claim 14, wherein: The first set of circuitry occupies an area overlapping the first memory segment and the second memory segment; and The second set of circuitry occupies an area overlapping with the first and third memory banks.

16. The memory device of claim 14, wherein: The first set of drivers occupies an area overlapping the first memory segment; The second set of drivers occupies an area overlapping the second memory segment; and The third set of drivers occupies an area overlapping the third memory segment.

17. A method for memory operation, comprising: identifying a first memory bank of a memory array for an access operation, the first memory bank being located between a second memory bank of the memory array and a third memory bank of the memory array; Based at least in part on the identifying, operating a first set of circuitry configured for use by the first memory segment and the second memory segment, wherein operating the first set of circuitry includes using a driver associated with the first memory segment and a driver associated with the second memory segment; Based at least in part on the identifying, operating a second set of circuitry configured for use by the first memory segment and the third memory segment, wherein operating the second set of circuitry includes using a driver associated with the first memory segment and a driver associated with the third memory segment; and The access operation is performed based at least in part on operating the first set of circuitry and operating the second set of circuitry.

18. The method for memory operation according to claim 17, further comprising: generating a first type of control signal using a first subset of the drivers associated with the first memory segment; generating a second type of control signal using a second subset of the drivers associated with the first memory segment; generating an additional control signal of the second type using the driver associated with the second memory segment; and Additional control signals of the first type are generated using the driver associated with the third memory segment.

19. The method for memory operation according to claim 18, further comprising: coupling the first subset of the drivers associated with the first memory bank and the drivers associated with the second memory bank with the first set of circuitry based at least in part on the identifying; and Based at least in part on the identification, the second subset of the drivers associated with the first memory bank and the drivers associated with the third memory bank are coupled with the second set of circuitry.

20. The method for memory operation according to claim 18, further comprising: using the first set of circuitry, performing a first set of functions based at least in part on the control signals of the first type and performing a second set of functions based at least in part on the additional control signals of the second type, Executing the access operation includes executing the first set of functions and the second set of functions.

21. The method for memory operation of claim 20, wherein the first set of functions is independent of the second set of functions.

22. The method for memory operation according to claim 20, wherein: The first set of circuitry includes a first set of sense amplifiers, a first subset of the first set of sense amplifiers underlying memory tiles of the first memory bank, and a second subset of the first set of sense amplifiers underlying memory tiles of the second memory bank; and The second set of circuitry includes a second set of sense amplifiers, a first subset of the second set of sense amplifiers underlying memory tiles of the first memory bank, and a second subset of the second set of sense amplifiers underlying memory tiles of the third memory bank.

23. The method for memory operation according to claim 20, wherein: A first subset of the first set of circuitry is included in memory tiles within the first memory segment; and A second subset of the first set of circuitry is included in memory tiles within the second memory segment.

24. The method for memory operation according to claim 20, wherein: the driver associated with the first memory segment being included in one or more memory tiles within the first memory segment; The driver associated with the second memory segment is included in one or more memory tiles within the second memory segment; and The driver associated with the third memory segment is included in one or more memory tiles within the second memory segment.

25. A method for memory operation, comprising: identifying a first memory bank of a memory array for an access operation, the first memory bank being located between a second memory bank of the memory array and a third memory bank of the memory array; generating a first type of control signal using a first set of drivers in a first set of circuitry configured for use by the first memory segment; generating a second type of control signal using a second set of drivers in the first set of circuitry configured for use by the first memory segment; generating additional control signals of the second type using a third set of drivers in a second set of circuitry configured for use by the second memory segment; generating additional control signals of the first type using a fourth set of drivers in a third set of circuitry configured for use by the third memory segment; operating a first set of sense amplifiers using the control signals of the first type generated by the first set of drivers and the additional control signals of the second type generated by the third set of drivers; operating a second set of sense amplifiers using the additional control signals of the first type generated by the fourth set of drivers and the control signals of the second type generated by the second set of drivers; and The access operation is performed based at least in part on operating the first set of sense amplifiers and operating the second set of sense amplifiers.

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