Apparatus with circuit positioning mechanism

Abstract

An apparatus includes: a substrate; a circuit assembly disposed on the substrate; and a location identifier layer on the circuit, wherein the location identifier layer includes one or more segment labels for indicating the physical location of the circuit assembly within the apparatus.

Description

Technical Field

[0001] The disclosed embodiments relate to devices, and more particularly to electronic devices having circuit positioning mechanisms. Background Technology

[0002] Electronic devices (such as silicon-based devices) frequently experience circuit defects that can develop during manufacturing, testing, and / or after deployment. For example, memory devices, often provided as internal semiconductor integrated circuits and / or external removable devices in computers or other electronic devices, may contain defective memory circuitry (e.g., memory cells). While different types of memory may exist, such as volatile and non-volatile memory, defective memory circuitry can occur regardless of the type. For example, volatile memory comprising random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), and / or synchronous dynamic random access memory (SDRAM) may contain defective memory transistors. Furthermore, non-volatile memory, such as flash memory (e.g., NAND and NOR), phase-change memory (PCM), resistive random access memory (RRAM), and / or magnetic random access memory (MRAM), may contain defective floating-gate transistors and / or other circuitry. Because such circuit defects can adversely affect other defect-free circuits, they are usually located and remedied / removed before the equipment is deployed.

[0003] Figure 1A is a schematic cross-sectional view of a conventional silicon device 100 (“Device 100”). Device 100 includes a silicon substrate 102 and a circuit component layer 106, which includes electronic circuit components (e.g., transistors). Device 100 further includes one or more metal layers (e.g., bottom metal layer 104 and / or top metal layer 106) connected to and routing electrical signals to / from the electronic circuit components. Device 100 also includes one or more insulating layers 110 (e.g., oxide material) disposed between the circuit component layer 106 and the metal layers. Thus, the insulating layer 110 provides a limiting connection between the circuit components and the metal layers and otherwise electrically insulates other portions of the circuit from the metal layers. Device 100 may include a passivation layer 112, which forms a top surface over the silicon substrate 102 and protects / isolates one or more of the metal layers and / or the circuit component layers 106 from / from the external environment.

[0004] To illustrate a conventional design, Figure 1B is a schematic top view of a portion of a silicon device (e.g., device 100). Figure 1C This is a top view of a conventional top metal layer (e.g., top metal layer 106). Figure 1DThis is a top view of a portion of a silicon device containing defective circuitry. Figure 1E This is an exemplary display showing a silicon device containing defective circuitry, and Figure 1F This is a top view of a portion of a silicon device containing surface defects. Referring together to Figures 1A to 1F, device 100 may include one or more defective circuits 120, such as unexpected short circuits, malfunctioning transistors, etc. However, locating defective circuits 120 is typically based on other circuit connections, which may be repetitive and / or numerous. As an illustrative example, when device 100 is a memory device, defective circuits 120 in memory circuitry (e.g., memory arrays) may be difficult to locate due to the repetitive arrangement of numerous individual cells. Defective circuits 120 can be located by counting a first set of markers 122 (e.g., word line markers / connectors) along one direction and a second set of markers 124 (e.g., bit line markers / connectors) along an orthogonal direction. As stated, such counting is difficult and often erroneous due to the extremely large number of memory cells and the repetitive nature of circuit connections.

[0005] The top metal layer 106 can further complicate efforts to locate defective circuitry 120. The top metal layer 106 may contain repeating patterns, such as mesh patterns or meandering patterns, as... Figures 1C to 1D As shown, they further introduce repetitive patterns that increase the difficulty of locating the defective circuit 120. The top metal layer 106 can be viewed during visual inspection and / or when viewing the device 100 using processing tools (e.g., microscope, laser / X-ray / UV camera, etc.). For example, the top metal layer 106 can be seen in a circuit viewer display 150 (e.g., emission microscope image). Due to... Figure 1E The repeating pattern simultaneously presented on the top metal layer 106 shown in the diagram can make it difficult to identify / reference potential fault locations 152 (e.g., hot spots) displayed on the circuit viewer display 150. Similarly, the repeating pattern makes it difficult to locate / reference surface defects 132 that may be present in / above / below the top metal layer 106, such as... Figure 1F As shown in the image. Summary of the Invention

[0006] In one aspect, this disclosure relates to an apparatus comprising: a substrate; a circuit assembly disposed on the substrate; and a location identifier layer over the circuit, wherein the location identifier layer comprises: a planar mesh structure having slots, one or more segment labels corresponding to the physical locations of the circuit assembly within the apparatus, wherein the one or more segment labels comprise one or more sets of filler material within the slots.

[0007] In another aspect, this disclosure relates to a method of manufacturing an apparatus, the method comprising: providing a substrate; forming a circuit assembly on the substrate; and attaching a location identifier layer on the circuit assembly, wherein the location identifier layer comprises: a planar mesh structure having slots, and one or more segment labels for indicating the physical location of the circuit assembly within the apparatus.

[0008] In another aspect, this disclosure relates to a semiconductor device comprising: a substrate; a first metal layer thereon; a circuit layer thereon and electrically coupled to the first metal layer, wherein the circuit layer includes a set of components arranged in a repeating pattern along a lateral plane; a top metal layer thereon, wherein the top metal layer includes: a mesh structure having slots, and a filler material within a set of said slots to provide visual reference for locating and identifying defects and / or components in said circuit layer; a top passivation layer thereon; and wherein: the filler material is visible and / or detectable through said top passivation layer. Attached Figure Description

[0009] Figure 1A is a schematic diagram of a silicon device.

[0010] Figure 1B is a schematic top view of a portion of a silicon device.

[0011] Figure 1C This is a top view of the standard top metal layer.

[0012] Figure 1D This is a top view of a part of a silicon device containing defective circuitry.

[0013] Figure 1E This is an exemplary display showing a portion of a silicon device containing defective circuitry.

[0014] Figure 1F This is a top view of a part of a silicon device that includes surface defects.

[0015] Figure 2A This is a block diagram of a device configured according to an embodiment of the present technology.

[0016] Figure 2B This is a schematic diagram of an integrated circuit device configured according to an embodiment of the present technology.

[0017] Figure 3A This is a schematic top view of a part of a device according to an embodiment of the present technology.

[0018] Figure 3B According to embodiments of the present technology Figure 3A The detailed view of segment 3B shown in the image.

[0019] Figure 3C According to embodiments of the present technology Figure 3B The detailed view of the 3C segment shown in the image.

[0020] Figure 4 This is a top view showing the surface characteristics of a portion of a device according to an embodiment of the present technology.

[0021] Figure 5 This is a display showing a portion of a device according to an embodiment of the present technology.

[0022] Figure 6 This is a flowchart illustrating an exemplary method of manufacturing an apparatus according to an embodiment of the present technology.

[0023] Figure 7 This is a schematic diagram of a system including a device according to an embodiment of the present technology. Detailed Implementation

[0024] As described in more detail below, the technology disclosed herein relates to electronic devices, systems having electronic devices, and related methods for locating circuitry therein. The device includes a location identifier layer that provides a reference for locating circuit components within the device. In some embodiments, the location identifier layer may be a metal layer containing a repeating pattern, such as a metal mesh containing boundaries (e.g., metal portions) and slots (e.g., areas / spaces enclosed by boundaries). The location identifier layer may include segment labels, such as symbols, letters, and / or numbers, for marking and identifying physical locations within the device. In other words, the segment labels may be easily recognizable writing or patterns that can serve as markers for identifying corresponding areas / zones. In some embodiments, segment labels may be formed by filling selected slots with a filler (e.g., dummy filler and / or oxide material) according to a predetermined pattern. Remaining slots may remain unfilled or may be filled with different filler materials (e.g., different oxide materials).

[0025] For illustrative purposes, the device will be described in the context of a flash memory device comprising one or more two-dimensional (2D) memory arrays. However, it should be understood that the techniques disclosed herein may be implemented in other contexts / implementations, such as for non-memory devices (e.g., processors or logic devices) and / or other memory devices (e.g., volatile memory devices and / or magnetic memory devices).

[0026] Figure 2AThis is a block diagram of a system 201 having a device (e.g., memory device 200) configured according to embodiments of the present technology. As shown, memory device 200 includes main memory 202 (e.g., NAND flash memory, NOR flash memory, chalcogenide PCM, etc.) and controller 206, which operatively couples main memory 202 to host device 208 (e.g., an upstream central processing unit (CPU)). Main memory 202 includes a plurality of memory regions or memory cells 220, each containing a plurality of memory cells 222. Memory cells 220 may be individual memory dies, memory planes within a single memory die, stacks of memory dies vertically connected to through-silicon vias (TSVs), or the like. For example, in one embodiment, each of the memory cells 220 may be formed from a semiconductor die and arranged together with other memory cell dies in a single device package (not shown). In other embodiments, a plurality of memory cells 220 may coexist on a single die and / or be distributed across multiple device packages. Memory cell 222 may include, for example, floating gates, charge traps, phase-change memory elements, ferroelectric memory elements, magnetoresistive memory elements, and / or other suitable memory elements configured to persistently or semi-persistently store data. Main memory 202 and / or individual memory cells 220 may also include other circuit components (not shown), such as multiplexers, decoders, buffers, read / write drivers, address registers, data outputs / data in registers, etc., for accessing and / or programming (e.g., writing) memory cell 222, and other functionalities, such as for processing information and / or communicating with controller 206.

[0027] Memory cells 222 can be arranged in rows 224 (e.g., each corresponding to a word line) and columns 226 (e.g., each corresponding to a bit line). Each word line may contain one or more memory pages, depending on the number of data states that the memory cells 222 of the word line are configured to store. For example, a single word line of a memory cell 222 where each memory cell 222 is configured to store one of two data states (e.g., an SLC memory cell configured to store one bit each) may contain a single memory page. Alternatively, a single word line of a memory cell 222 where each memory cell 222 is configured to store one of four data states (e.g., an MLC memory cell configured to store two bits each) may contain two memory pages. Furthermore, memory pages can be interleaved, such that a word line (e.g., an SLC memory cell) of each memory cell 222 configured to store one of two data states can span two memory pages in an "even-odd bitline architecture," wherein all memory cells 222 in the odd-numbered columns 226 of a single word line are grouped into a first memory page, and all memory cells 222 in the even-numbered columns 226 of the same word line are grouped into a second memory page. When the even-odd bitline architecture is used in word lines of memory cells 222 configured to store a large number of data states (e.g., memory cells configured as MLC, TLC, QLC, etc.), the number of memory pages per word line can be even higher (e.g., 4, 6, 8, etc.).

[0028] Each column 226 may contain a string of series-coupled memory cells 222 connected to a common source. Each string of memory cells 222 may be connected in series between a source-select transistor (e.g., a field-effect transistor) and a drain-select transistor (e.g., a field-effect transistor). The source-select transistors are typically coupled to a source-select line, and the drain-select transistors are typically coupled to a drain-select line.

[0029] In other embodiments, memory cells 222 may be arranged in different types of hierarchical and / or grouped arrangements compared to those shown in the illustrated embodiments. Furthermore, although shown in the illustrated embodiments with a specific number of memory cells, rows, columns, blocks, and memory units for illustrative purposes, the number of memory cells, rows, columns, blocks, and memory units may vary and may be proportionally larger or smaller than the number shown in the illustrated examples in other embodiments. For example, in some embodiments, memory device 200 may include only one memory unit 220. Alternatively, memory device 200 may include two, three, four, eight, 20, or more (e.g., 26, 32, 64, or more) memory units 220. Although memory cells 220 are shown in FIG. 2 as each comprising two memory blocks 228, in other embodiments, each memory cell 220 may comprise one, three, four, eight, or more (e.g., 26, 32, 64, 200, 228, 256, or more memory blocks). In some embodiments, each memory block 228 may comprise, for example, two 15 Each memory page within a block may contain, for example, 2 memory pages. 12 Each memory cell is 222 (e.g., "4k" pages).

[0030] Controller 206 may be a microcontroller, a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor. Controller 206 may include a processor 230 configured to execute instructions stored in memory. In the illustrated example, the memory of controller 206 includes embedded memory 232, configured to execute various processes, logic flows, and routines for controlling the operation of memory device 200, including managing main memory 202 and handling communication between memory device 200 and host device 208. In some embodiments, embedded memory 232 may include memory registers storing, for example, memory pointers, retrieved data, etc. Embedded memory 232 may include volatile and / or non-volatile memory (e.g., DRAM, SRAM, NAND, NOR, PCM) for storing memory registers, and may also include read-only memory (ROM) (e.g., for storing microcode). Although the memory device 200 has been shown to include a controller 206 in the example illustrated in Figure 2, in another embodiment of the art, the memory device may not include a controller and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory device).

[0031] In operation, controller 206 can directly write to or otherwise program (e.g., erase) various memory regions of main memory 202, for example, by writing to groups of memory pages and / or memory blocks 228. In NAND-based memory, write operations often involve programming memory cells 222 in selected memory pages with specific data values ​​(e.g., a string of data bits with logic 0 or logic 1 values). Erase operations are similar to write operations, except that erase operations reset the entire memory block 228 or multiple memory blocks 228 to the same data state (e.g., logic 1).

[0032] Controller 206 communicates with host device 208 via host device interface 210. In some embodiments, host device 208 and controller 206 may communicate via a serial interface, such as Serial Attached SCSI (SAS), Serial AT Attached (SATA), Peripheral Component Interconnect High Speed ​​(PCIe), or other suitable interfaces (e.g., parallel interfaces). Host device 208 may send various requests (in the form of, for example, data packets or data packet streams) to controller 206. Requests may contain commands for writing, erasing, returning information, and / or for performing specific operations (e.g., TRIM operations). Requests may also contain interrupts or other commands indicating a change in conditions (e.g., a power loss event) that may trigger an implementation of a power loss algorithm.

[0033] Host device 208 may be any of several electronic devices or components thereof capable of temporary or persistent storage of information using memory. For example, host device 208 may be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, tablet computer, digital reader, digital media player), or a component thereof (e.g., a central processing unit, coprocessor, dedicated memory controller, etc.). Host device 208 may be a networking device (e.g., a switch, router, etc.), or a recorder of digital images, audio, and / or video, a vehicle, an appliance, a toy, or any of several other products. In one embodiment, host device 208 may be directly connected to memory device 200, but in other embodiments, host device 208 may be indirectly connected to memory device 200 (e.g., via a network connection or via an intermediary device).

[0034] Various parts of system 201 and / or equipment may be implemented using integrated circuit devices. Figure 2BThis is a schematic cross-sectional view of an integrated circuit device 250 (“Device 250”) configured according to an embodiment of the present technology. Device 250 may have a substrate 252 and a circuit component layer 256, which may contain electronic circuit components (e.g., transistors, resistors, capacitors, etc.). Device 250 may further include one or more metal layers 254 coupled to the electronic circuit components (e.g., components within the circuit component layer 256) and routing electrical signals to / from the electronic circuit components. Device 250 also includes one or more insulating layers 260 (e.g., oxide materials) disposed between the circuit component layer 256 and the metal layers 254. Thus, the insulating layers 260 provide limited electrical connections between the circuit components and the metal layers 254 and otherwise electrically insulate other portions of the circuit from the metal layers. Device 250 may include a passivation layer 262, which forms a top surface over the silicon substrate 252, protecting device 250 from external environmental influences / isolating device 250 from the external environment.

[0035] As described in detail below, device 250 may include a location identifier layer 270 containing visual markers / indicators (i.e., segment labels 272) that identify different physical locations and / or areas of device 250. Segment labels 272 may contain symbols, letters, numbers, or combinations thereof written on the location identifier layer 270. The location identifier layer 270 may extend along a horizontal plane, and each of the segment labels 272 may identify a unique location / area along the horizontal plane. Therefore, segment labels 272 can be used to provide visual references for locating and / or identifying one or more circuit components and / or other physical aspects (e.g., defects) of device 250. In some embodiments, segment labels 272 may replace wordline markings as visual references for locating and / or identifying circuit components or other physical features.

[0036] In some embodiments, the location identifier layer 270 may be a metal layer, such as a top metal layer or different inner metal layers. For example, the location identifier layer 270 may include an electrically functional metal layer (e.g., a top metal layer) coupled to functional circuitry (e.g., circuitry components within circuitry component layer 256) and routing electrical signals to the functional circuitry and / or providing reference voltage connections, such as supply voltage and / or ground. Furthermore, the location identifier layer 270 may be non-functional for electrical connections. In other embodiments, the location identifier layer 270 may comprise other non-metallic materials, such as oxides or polymeric materials. In some embodiments, the location identifier layer 270 may be a planar structure with a repeating pattern (e.g., a mesh pattern) forming slots surrounded by the material of the location identifier layer 270 (e.g., metals and / or conductive materials). In some embodiments, as described in detail below, the segment label 272 may be formed based on, for example, filling the slots with dummy filler to indicate / form symbols, letters, etc. The dummy filler may comprise an oxide material used for segment label 272 without necessarily providing other functions (e.g., encapsulation and / or protection). In some embodiments, the dimensions of the slot (e.g., length and / or width) may be less than 100 µm. As an illustrative example, the slot may have a rectangular shape with a length of 4 µm and a width of 1 µm.

[0037] For illustrative purposes, the location identifier layer 270 is described with respect to the main memory 202 of FIG. 2 (e.g., memory cell 220 and memory cell 222 of FIG. 2 therein). However, it should be understood that the location identifier layer 270 may overlap with and provide markers / indicators for locating other circuitry (e.g., controller 206, logic circuitry, etc.). For example, segment labels 272 may be placed above, below, and / or adjacent to buffers, amplifiers, logic gates, traces, etc., in device 250.

[0038] Figure 3A This is a schematic top view of a portion of a device (e.g., apparatus 250) according to an embodiment of the present technology. As described above, apparatus 250 may include a location identifier layer 270 extending horizontally across apparatus 250. In some embodiments, the location identifier layer 270 may include segment labels 272 following one or more patterns across the location identifier layer 270. For example, segment labels 272 may include letters and / or numbers that increment along a corresponding direction (e.g., along width and / or length). Figure 3A As shown, the segment label 272 may contain numbers that increase along a first direction and letters that increase along a second direction orthogonal to the first direction.

[0039] As described above, the location identifier layer 270 may include segment labels 272 that can be used to describe locations / areas along a horizontal direction. For example, the location identifier layer 270 can be used to identify the physical location of one or more target circuits 302 (e.g., defective circuits / components) on device 250. Figure 3A In the example shown, the target circuit 302 is located above / below region 'AC66' and / or the first '6' therein. Therefore, compared to the conventional device described above, segment label 272 provides a simpler / more efficient positioning mechanism, thereby reducing potential user errors in locating the circuit. For example, segment label 272 can reduce or eliminate any counting necessary to specify the location of the target circuit 302 (e.g., for word lines and / or bit lines). Furthermore, segment label 272 can provide for locating and / or identifying the target circuit 302 and / or its repetitive (based on, for example, a group of components having similar or matching shapes, types, arrangements, and / or spacing) portions within the circuit system (e.g., Figure 2A The efficient mechanism associated with defects in memory cell 222).

[0040] To illustrate exemplary details of the segment label 272, according to an embodiment of the present technology, Figure 3B yes Figure 3A The detailed view of fragment 3B shown in the image, and Figure 3C yes Figure 3B Another detailed view of segment 3C shown in the image. See also... Figure 3B and 3C , Figure 2B The location identifier layer 270 may contain macrocells 310, each macrocell 310 containing a unique area or region within the location identifier layer 270, such as a lateral plane / surface traversing the location identifier layer 270. Each macrocell 310 may correspond to one of the segment labels 272.

[0041] In some embodiments, the location identifier layer 270 may comprise a metal layer / structure or portion thereof having a mesh design. For example, the location identifier layer 270 may include boundaries 312 (e.g., metal connectors) defining slots 314. Thus, segment labels 272 may be formed based on filling a set of slots 314 with identifier filler 320 (e.g., dummy filler) according to a predetermined pattern to indicate / write corresponding symbols, letters, and / or numbers. In other words, each of the segment labels 272 may comprise a set of slots 314 within a corresponding macrocell 310, the slots 314 being filled with dummy filler to form or display a unique set of letters, numbers, and / or symbols. Thus, the segment labels 272 can provide a visual reference for identifying and / or locating corresponding areas / regions containing any circuitry components and / or physical characteristics (e.g., defects) within the device 250. In some embodiments, other instances of slots 314 may remain unfilled or be filled with different materials. In some embodiments, the identifier filler 320 may have at least one physical characteristic, such as density, color, and / or composition.

[0042] In some embodiments, slot 314 may correspond to label pixels 330 and / or associated coordinates along a plane (e.g., a lateral / horizontal surface of device 250). Label pixels 330 may be used to indicate symbols, letters, and / or numbers of segment labels 272, similar to how symbols, letters, and / or numbers are displayed on a digital display. For example, each of the label pixels 330 may include a set of one or more of the slots 314 within the area represented by the segment label 272 (e.g., ...). Figure 3C (The four slots shown are four slots in total). Each of the label pixels 330 can be identified based on its relative position within the represented area and / or location identifier layer 270 (e.g., numbered and / or according to a coordinate system). A set of label pixels 330 may be filled with identifier filler 320 to form / display symbols, letters, and / or numbers for the corresponding segment label 272. In one or more embodiments, one or more of the slots 314 may be marked in each of the label pixels 330 (via different types of filler having different visual characteristics, such as color, density, composition, etc., or by leaving the slot unfilled) for visual identification of the corresponding pixel. In other words, each of the pixels 330 may contain a mark that can be used to visually identify the boundary of the corresponding pixel. Therefore, the label pixels 330 can be used to locate target circuitry.

[0043] In order to illustrate an exemplary defect relative to section label 272, Figure 4 This is a top view illustrating the surface characteristics of a portion of a device (e.g., apparatus 250) according to an embodiment of the present technology. Apparatus 250 may be included in... Figure 2BUnintended defects 402 in one or more structures above / below the location identifier layer 270 and / or the location identifier layer 270. For example, the device 250 may include a top metal layer, Figure 2B passivation layer 262, Figure 2B Insulation layer 260, Figure 2B Defect 402 in circuit component layer 256, etc.

[0044] In some embodiments, with or without a magnifying lens / device, defect 402 is visible to a human inspector. In some embodiments, defect 402 may be captured by a camera that detects light waves having wavelengths in the visible spectrum. When viewing defect 402, segment label 272 may be seen as adjacent to and / or overlapping with defect 402. Therefore, a human inspector can identify defect 402 as located in one or more areas corresponding to adjacent / overlapping segment labels 272 and / or label pixels 330. Thus, compared to conventional designs (e.g., Figure 1F Compared to the previous method, segment label 272 and / or label pixel 330 provide an improved positioning mechanism for human inspectors.

[0045] To further illustrate the exemplary defects relative to section label 272, Figure 5 This is a display illustrating a portion of a device according to an embodiment of the present technology. In some embodiments, Figure 2B The device 250 can be inspected using analytical tools such as emission microscopes, laser imaging devices, X-ray-based imagers, infrared-based imagers, etc. The analytical tools can detect and / or visualize internal defects 502 in the device 250 based on the propagation of a detection signal (e.g., light waves) through and / or reflection away from one or more parts of the device 250. For example, the analytical tools can display hot spots and / or electrical short circuits within the device 250 based on the detection of heat (i.e., radiated / reflected infrared signals).

[0046] In addition to detecting / visualizing internal defects 502, the analysis tool can also simultaneously depict segment labels. Because segment labels 272 contain different... Figure 3C Other surrounding slots 314 Figure 3C The identifier filler 320, therefore, compared to the surrounding slot 314, can differently affect the propagation / reflection of the detection signal for segment label 272. Thus, analysis tools can detect and visualize the differences between segment label 272 and the surrounding area, as well as internal defects 502. Therefore, compared to conventional designs (e.g., Figure 1D and / or Figure 1E In contrast, the segment label 272 containing identifier filler 320 provides an improved positioning mechanism for locating internal defects 502.

[0047] Figure 6This illustrates an apparatus for manufacturing embodiments of the present technology (e.g., Figure 2A The memory device 200, its portion, and / or Figure 2B A flowchart of an exemplary method 600 for the apparatus 250. Method 600 may include methods for manufacturing an apparatus containing... Figure 2B The process of the device with location identifier layer 270, wherein the location identifier layer 270 has Figure 2B Section label 272.

[0048] At frame 602, a substrate (e.g.) may be provided. Figure 2B The substrate 252 is used for manufacturing equipment. The substrate may contain semiconductor materials (e.g., silicon-based materials) and / or core materials (e.g., ceramics, glass, and / or epoxy materials), for example, for PCBs.

[0049] A metal layer (e.g., at frame 604) can be formed. Figure 2B Metal layer 254). A circuit layer (e.g., ...) can be formed at frame 606. Figure 2B The circuit component layer 256). In some embodiments, forming a circuit layer may include: providing one or more insulating layers (e.g., Figure 2B The insulating layer 260, as shown in box 608; and / or providing circuitry (e.g., components in circuitry layer 256, such as transistors, resistors, capacitors, etc.), as shown in box 610. In some embodiments, boxes 604 to 610 may include deposited material (e.g., insulating material, doped material, and / or conductive / metallic material), removed material (via, for example, etching and / or chemical mechanical planarization), and / or doped regions for forming semiconductor devices and / or integrated circuits. In some embodiments, boxes 604 to 610 may include attaching circuitry components to each other and / or the substrate.

[0050] At box 612, an identifier layer (e.g., ...) can be attached above the circuit layer. Figure 2B Location identifier layer 270, such as a metal mesh structure). In some embodiments, such as shown at box 614, a label may be generated for the identifier layer (e.g., Figure 2B (Section label 272). For example, Figure 3C The selected instance of slot 314 can be filled with Figure 3C The identifier filler 320 is used to form / display the numbers, letters, and / or symbols of the segment label 272. The location of the segment label 272 and / or the filled instances of the slot 314 may correspond to the location of circuit system components and / or grid systems on the substrate 252. The process of filling the slot 314 with the identifier filler 320 may be implemented before and / or after attaching the identification layer on the circuit layer.

[0051] In some embodiments, such as as shown at block 616, the attachment identification layer may include components that electrically couple the identification layer to one or more circuit system components in the circuit layer. For example, one or more circuit system components in the circuit layer may be directly connected to or in direct contact with one or more portions of the metal mesh structure. Furthermore, one or more circuit system components and the metal mesh structure may be coupled via another circuit system component and / or conductive structures (e.g., metal pillars, through-silicon vias (TSVs), wires, etc.). Therefore, the identification layer may be electrically coupled (via, for example, solder reflow and / or molten metal structures or portions thereof) to one or more circuit system components in the circuit layer and / or a reference voltage (e.g., source voltage or electrical ground).

[0052] At box 618, a top passivation layer can be formed above the identifier layer (e.g., Figure 2B (Passivation layer 262, encapsulation, etc.). In some embodiments, one or more physical properties of the top passivation layer may differ from the physical properties of the filler for the segment label 272 as described above. In some embodiments, the top passivation layer may have physical properties that allow light to pass through so that the segment label 272 in the location identifier layer 270 remains visible through the top passivation layer. In some embodiments, the top passivation layer, substrate 252, and / or identifier filler 320 may have physical properties that allow the segment label 272 to be visible through the top passivation layer and / or substrate, for example, when viewing the circuit component layer 256 using an analysis tool.

[0053] Figure 7 This is a schematic diagram of a system including a memory device according to an embodiment of the present technology. (See above reference) Figures 2A to 6 Any of the aforementioned memory devices can be incorporated into any of numerous larger and / or more complex systems, a representative example of which is... Figure 7 The system 780 is schematically shown in the diagram. System 780 may include a memory device 700, a power supply 782, a driver 784, a processor 786, and / or other subsystems or components 788. The memory device 700 may include components generally similar to those described in the reference above. Figures 2A to 6 The described memory device features characteristics, and may therefore include various features for executing direct read requests from a host device. The resulting system 780 can perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative systems 780 may include, but are not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, electrical appliances, and other products. Components of system 780 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). Components of system 780 may also include remote devices and any of a wide variety of computer-readable media.

[0054] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, embodiments from two or more of the methods may be combined.

[0055] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may show signals as single signals; however, those skilled in the art will understand that the signals may represent a bus of signals, wherein the bus may have multiple bit widths.

[0056] The devices discussed herein, including memory devices, can be formed on semiconductor substrates or dies such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In others, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0057] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this disclosure and the appended claims. Features implementing the functionality may also be physically located in various locations, including distributed implementations such that portions of the functionality are implemented at different physical locations.

[0058] As used herein, the word "or" included in the claims, such as in a list of items (e.g., a list of items ending with phrases such as "at least one of" or "one or more of"), indicates a list of inclusion, such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be considered a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be considered in the same manner as the phrase "at least partially based on".

[0059] As should be understood from the foregoing, specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the invention. More specifically, numerous specific details have been set forth in the foregoing description to provide a thorough and achievable description of embodiments of the present technology. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with memory systems and devices have not been shown or described in detail to avoid obscuring other aspects of the present technology. Generally, it should be understood that various other devices, systems, and methods besides those specific embodiments disclosed herein are within the scope of the present technology.

Claims

1. An electronic device comprising: Substrate; Circuit components, which are disposed on the substrate; and A location identifier layer, situated above the circuit, wherein the location identifier layer comprises: A planar mesh structure containing narrow slots. One or more segment labels configured to provide a visual positional reference for the physical location of the circuit components within the electronic device, wherein the one or more segment labels include filler material within one or more sets of slots.

2. The electronic device according to claim 1, wherein: The location identifier layer is a metal mesh; and The filler material is a dummy filler.

3. The electronic device of claim 2, wherein the metal mesh is conductive and includes a top metal layer.

4. The electronic device of claim 3, wherein the top metal layer is electrically coupled to one or more of the circuit components.

5. The electronic device of claim 4, wherein the top metal layer is configured to provide a power supply voltage or a ground connection to the coupled circuit assembly.

6. The electronic device of claim 1, wherein each of the segment labels (1) corresponds to a macrocell containing a unique region in the location identifier layer, and (2) contains a unique set of numbers, letters, symbols or combinations thereof for identifying the unique region.

7. The electronic device of claim 6, wherein one or more of the slots correspond to pixels selectively filled with the filler material to provide the unique set of numbers, letters, symbols or combinations thereof.

8. The electronic device of claim 7, wherein the pixel corresponds to coordinates for further positioning the circuit component.

9. The electronic device according to claim 1, wherein: The circuit components are disposed on the surface of the substrate; and The planar mesh structure overlaps with and extends parallel to the surface.

10. The electronic device of claim 1, further comprising: A top passivation layer is placed above the location identifier layer; and in: The one or more segment labels are visible through the top passivation layer.

11. The electronic device according to claim 10, wherein: The top passivation layer comprises a first material; and The one or more segment labels contain a second material having at least one physical property different from the first material.

12. The electronic device of claim 11, wherein the second material has a density, color, composition, or combination thereof different from the first material.

13. The electronic device of claim 10, wherein the visual position reference is a visual reference used to locate physical features, defects, or combinations thereof within the electronic device.

14. The electronic device of claim 1, wherein the electronic device comprises a semiconductor device.

15. The electronic device of claim 14, wherein the semiconductor device is a memory device.

16. A method of manufacturing equipment, the method comprising: Provide substrate; A circuit assembly is formed on the substrate; as well as A location identifier layer is attached above the circuit assembly, wherein the location identifier layer comprises: A planar mesh structure, containing slots, and One or more segment labels are used to provide a visual location reference for the physical location of the circuit components within the device.

17. The method of claim 16, further comprising filling a set of the slots with a filler material according to a predetermined pattern to form the one or more segment labels.

18. The method of claim 16, wherein: The location identifier layer is a metal mesh; and The attachment of the location identifier layer includes one or more of the location identifier layer electrically coupled to the circuit component.

19. The method of claim 16, further comprising: A first metal layer is formed on the substrate; as well as A top passivation layer is formed on top of the location identifier layer; in: The location identifier layer includes a top metal layer; and The circuit assembly includes: At least one insulating layer is formed on top of the first metal layer, and The circuit assembly is formed on at least one insulating layer, wherein at least one of the circuit assemblies is electrically coupled to the first metal layer.

20. A semiconductor device comprising: Substrate; A first metal layer is placed on the substrate; A circuit layer that is above and electrically coupled to the first metal layer, wherein the circuit layer comprises a set of components arranged in a repeating pattern along a transverse plane. A top metal layer, which is above the circuit layer, wherein the top metal layer comprises: A mesh structure containing slots, and A filler material within a set of said slots to provide a visual location reference when locating and identifying defects and / or components in said circuit layer; A top passivation layer is formed on top of the top metal layer; and in: The filler material is visible and / or detectable through the top passivation layer.

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