Memory systems and data processing systems

Abstract

Embodiments of the present disclosure relate to a memory system and a data processing system. A data processing system includes: a memory system for storing data and information; and a host that communicates with the memory system and includes a submission queue for queuing commands to be processed by the memory system, the host being configured to provide the memory system with a submission queue tail pointer indicating the tail of the submission queue and command information about the command, wherein the memory system is configured to: receive the command information about the command, perform a pre-operation on the command based on the command information, and obtain the command from the submission queue based on the result of the pre-operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2020-0118428, filed on September 15, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the disclosed technology relate to a memory system and a data processing system including a memory system. Background Art

[0004] The computer environment paradigm has transitioned to ubiquitous computing, which allows computing systems to be used anywhere, anytime. As a result, the use of portable electronic devices (such as mobile phones, digital cameras, and laptop computers) has increased rapidly. These portable electronic devices typically use a memory system having one or more memory devices for storing data. The memory system can be used as a primary memory device or an auxiliary memory device of the portable electronic device.

[0005] Since the memory system does not require a mechanical driving part, the memory system provides advantages such as excellent stability and durability, high information access speed, and low power consumption, etc. Examples of memory systems having such advantages include universal serial bus (USB) memory devices, memory cards with various interfaces, and solid state drives (SSDs). Summary of the invention

[0006] Various embodiments are directed to providing a memory system capable of performing pre-operations for processing a command even before a host acquires the command after ringing a doorbell.

[0007] Various embodiments are directed to providing a memory system capable of reducing a processing time of a command by performing a pre-operation and successfully providing a response to a host.

[0008] The technical problems to be achieved by this embodiment are not limited to the above technical problems, and other technical problems can be inferred from the following embodiments.

[0009] According to an embodiment, a data processing system includes: a memory system for storing data and information; and a host, communicating with the memory system and including a submission queue for queuing commands to be processed by the memory system, the host being configured to provide the memory system with a submission queue tail pointer indicating the tail of the submission queue and command information about the command, wherein the memory system is configured to: receive command information about the command; perform a pre-operation on the command based on the command information; and obtain the command from the submission queue based on the result of the pre-operation. According to an embodiment, a memory device is configured to store data; a host interface, communicating with the host and configured to receive a submission queue tail pointer and command information about a command corresponding to the tail pointer from the host, perform a pre-operation on the command based on the command information, and obtain the command from the submission queue of the host based on the result of the pre-operation; a command queue, configured to queue the obtained command; and a processor, communicating with the memory device and configured to control the memory device to process the command queued in the command queue. According to the present disclosure, a memory system can be provided that is capable of performing a pre-operation for processing a command even before the host obtains the command after ringing the doorbell.

[0010] According to the present disclosure, a memory system capable of reducing the processing time of a command by performing a pre-operation and successfully providing a response to a host can be provided.

[0011] Effects obtained in the present disclosure are not limited to the above-mentioned effects, and other unmentioned effects will be clearly understood by those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram illustrating a data processing system according to an embodiment of the disclosed technology.

[0013] Figure 2 is a diagram used to illustrate the operation of the command queue interface.

[0014] Figure 3 is a diagram illustrating a doorbell register further storing command information according to an embodiment of the disclosed technology.

[0015] Figure 4 is a diagram illustrating the operation of a data processing system according to an embodiment of the disclosed technology.

[0016] FIG. 5A to FIG. 5C is a diagram for explaining a preliminary operation according to an embodiment of the disclosed technology. DETAILED DESCRIPTION

[0017] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that in the following description, only parts necessary for understanding the operation according to the present disclosure will be described, and descriptions of other parts except these parts will be omitted to avoid obscuring the subject matter of the present disclosure.

[0018] Figure 1 is a diagram schematically illustrating an example of a data processing system 100 including a memory system 110 according to an embodiment of the disclosed technology.

[0019] refer to Figure 1 , data processing system 100 may include a host 102 operably coupled to a memory system 110 that communicates with the host 102 .

[0020] The host 102 may include any of various portable electronic devices such as a mobile phone, an MP3 player, a laptop computer, or any of various non-portable electronic devices such as a desktop computer, a game console, a television (TV), or a projector.

[0021] The host 102 may include at least one operating system (OS), which may manage and control the overall functions and operations of the host 102, and provide operations between the host 102 and the user using the data processing system 100 or the memory system 110. The OS may support functions and operations corresponding to the user's purpose of use and usage. For example, depending on the portability of the host 102, the OS may be divided into a general OS and a mobile OS. Depending on the user's environment, the general OS may be divided into a personal OS and an enterprise OS.

[0022] The memory system 110 may be operated to store data for the host 102 in response to a request from the host 102. Non-limiting examples of the memory system 110 may include a solid state drive (SSD), a multimedia card (MMC), a secure digital (SD) card, a universal serial bus (USB) device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media card (SMC), a personal computer memory card international association (PCMCIA) card, or a memory stick. The MMC may include an embedded MMC (eMMC), a reduced size MMC (RS-MMC), a micro-MMC, etc. The SD card may include a mini-SD card and / or a micro-SD card.

[0023] The memory system 110 may be embodied as various types of storage devices. Examples of such storage devices may include, but are not limited to, volatile memory devices (such as dynamic random access memory (DRAM) and static RAM (SRAM)) and non-volatile memory devices (such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric RAM (MRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM or ReRAM), or flash memory). The flash memory may have a three-dimensional (3D) stacked structure.

[0024] Non-limiting application examples of the memory system 110 may include: a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a 3D TV, a smart TV, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a storage device constituting a data center, a device capable of sending / receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, a radio frequency identification (RFID) device, or one of various components constituting a computing system.

[0025] The memory system 110 may communicate with the host 102 by using a command queue interface supporting a protocol such as NVMe. The command queue interface may support an interface between the host 102 and the memory system 110 based on a queue pair including a submission queue SQ for inputting a requested command and a completion queue CQ for recording a processing result of a command.

[0026] Figure 2 is a diagram used to explain the operation of the command queue interface.

[0027] The host 102 may generate a queue pair including a submission queue 1022 and a completion queue 1024. When there are multiple cores in the host 102, a queue pair of the submission queue 1022 and the completion queue 1024 may be generated to correspond to one of the multiple cores. According to an embodiment, the queue pair may be stored in a memory of the host 102.

[0028] The memory system 110 may include a doorbell register 202 to perform command queue interface operations. The memory system 110 communicates with the host 102 using a doorbell-based host interface that allows the host 102 to place descriptors on a memory ring for the memory system and issue pointer update writes to the memory system 110, which are referred to as "doorbells."

[0029] The doorbell register 202 may be a register for controlling a queue pair generated by the host 102 . Figure 2 One doorbell register 202 is shown as an example, but when there are multiple cores in the host 102, the same number of doorbell registers 202 as the number of cores may be included in the memory system 110. The doorbell register 202 may store a submission queue tail pointer 2022 indicating the tail of the submission queue 1022 and a completion queue head pointer 2024 indicating the head of the completion queue 1024. The memory system 110 may access the submission queue 1022 and the completion queue 1024 with reference to the doorbell register 202 to perform a command queue interface operation with the host 102.

[0030] In step S1, the host 102 may queue a command in the submission queue 1022 to request the memory system 110 to execute the command. In step S2, the host 102 may update the submission queue tail pointer 2022 and provide the updated submission queue tail pointer 2022 to the memory system 110. The memory system 110 may store the updated submission queue tail pointer 2022 in the doorbell register 202.

[0031] In step S3, the memory system 110 may fetch commands from the commit queue 1022. In step S4, the memory system 110 may process the fetched commands.

[0032] In step S5, after the command has been processed, the memory system 110 may record the completion of the command processing in the completion queue 1024. For example, the memory system 110 may write a completion queue entry in the completion queue 1024. In this case, the completion queue head pointer 2024 may be incremented. In step S6, the memory system 110 may generate an interrupt signal.

[0033] In step S7, the host 102 may complete the command. In step S8, the host 102 may provide the updated completion queue head pointer 2024 to the memory system 110. For example, the memory system 110 may store the updated completion queue head pointer 2024 in the doorbell register 202.

[0034] Return to reference Figure 1, the memory system 110 may include a memory device 150 and a controller 130. The memory device 150 may store data for the host 102, and the controller 130 may control the data to be stored in the memory device 150.

[0035] The controller 130 and the memory device 150 may be integrated into a single semiconductor device. For example, the controller 130 and the memory device 150 may be integrated into a semiconductor device to configure a solid-state drive (SSD). When the memory system 110 is implemented as an SSD, the operating speed of the host 102 connected to the memory system 110 may be increased. In addition, the controller 130 and the memory device 150 may be integrated into a semiconductor device to constitute a memory card. For example, the controller 130 and the memory device 150 may constitute a memory card (such as a personal computer memory card international association (PCMCIA) card, a compact flash memory (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC) including a reduced-size MMC (RS-MMC) and a micro-MMC, a secure digital (SD) card including a mini-SD card, a micro-SD card, and an SDHC card, or a universal flash storage (UFS) device).

[0036] The memory device 150 may be a nonvolatile memory device and may retain data stored therein even when power is not supplied. The memory device 150 may store data provided from the host 102 through a programming operation and provide the data stored therein to the host 102 through a read operation. The memory device 150 may include a plurality of memory blocks, each of the plurality of memory blocks may include a plurality of pages, and each of the plurality of pages may include a plurality of memory cells coupled to a word line. In an embodiment, the memory device 150 may be a flash memory. The flash memory may have a 3-dimensional (3D) stacked structure.

[0037] The controller 130 may control the memory device 150 in response to a request from the host 102. For example, the controller 130 may provide data read from the memory device 150 to the host 102, and store data provided from the host 102 in the memory device 150. For this operation, the controller 130 may control a read operation, a program operation, and an erase operation of the memory device 150.

[0038] The controller 130 may include a host interface (I / F) 132 , a processor 134 , a register 138 , a memory interface (I / F) 142 , and a memory 144 , which are electrically connected to each other to be operable or communicative through an internal bus.

[0039] The host I / F 132 may be configured to process commands and data of the host 102 and communicate with the host 102 through an interface protocol such as Peripheral Component Interconnect Express (PCIe).

[0040] The host I / F 132 may be driven by firmware called a host interface layer (HIL) to exchange data with the host.

[0041] The host I / F 132 may be a reference Figure 2 The command queue interface described above can support an interface connection between the host 102 and the memory system 110.

[0042] The memory I / F 142 may be used as a memory / storage interface for interfacing the controller 130 with the memory device 150 so that the controller 130 controls the memory device 150 in response to a request from the host 102. When the memory device 150 is a flash memory or specifically a NAND flash memory, the memory I / F 142 may generate a control signal for the memory device 150 and process data to be provided to the memory device 150 under the control of the processor 134. The memory I / F 142 may be used as an interface (e.g., a NAND flash memory interface) for processing commands and data between the controller 130 and the memory device 150. Specifically, the memory I / F 142 may support data transmission between the controller 130 and the memory device 150.

[0043] The memory I / F 142 may be driven by firmware called a flash interface layer (FIL).

[0044] The processor 134 may control the overall operation of the memory system 110. The processor 134 may drive firmware to control the overall operation of the memory system 110. The firmware may be referred to as a flash translation layer (FTL). Also, the processor 134 may be implemented as a microprocessor or a central processing unit (CPU).

[0045] The processor 134 may drive the FTL and perform foreground operations corresponding to requests received from the host. For example, the processor 134 may control a write operation of the memory device 150 in response to a write request from the host, and control a read operation of the memory device 150 in response to a read request from the host.

[0046] In addition, the controller 130 may perform background operations on the memory device 150 through the processor 134 implemented as a microprocessor or a CPU. For example, the background operations performed on the memory device 150 may include a garbage collection (GC) operation, a wear leveling (WL) operation, a map refresh operation, or a bad block management operation.

[0047] The memory 144 may be used as a working memory of the memory system 110 and the controller 130, and stores data for driving the memory system 110 and the controller 130. The controller 130 may control the memory device 150 to perform a read operation, a program operation, and an erase operation in response to a request from the host 102. The controller 130 may provide the data read from the memory device 150 to the host 102, and may store the data provided from the host 102 in the memory device 150. The memory 144 may store data required by the controller 130 and the memory device 150 to perform these operations. For example, the memory 144 may include a command (CMD) queue 136 that queues commands obtained from the host 102.

[0048] The memory 144 may be implemented by a volatile memory. For example, the memory 144 may be implemented by a static random access memory (SRAM) or a dynamic random access memory (DRAM). The memory 144 may be provided inside the controller 130 or outside the controller 130 . Figure 1 The memory 144 is illustrated as being provided within the controller 130. In an embodiment, the memory 144 may be embodied by an external volatile memory having a memory interface for transferring data between the memory 144 and the controller 130.

[0049] The registers 138 may include a doorbell register 202. For example, the registers 138 may include the same number of doorbell registers 202 as the number of cores of the host 102. Figure 2 As described, doorbell register 202 may store data used to perform command queue interface operations. Figure 1 An example is shown in which the register 138 is separated from the processor 134. However, according to an embodiment, the register 138 may also be included in the processor 134.

[0050] According to an embodiment of the disclosed technology, the doorbell register 202 may also store command information and Figure 2 Described submission queue tail pointer 2022 and completion queue head pointer 2024.

[0051] Figure 3 A doorbell register 202 is shown that also stores command information (CMD INFO) 2026 in addition to a submission queue tail pointer 2022 and a completion queue head pointer 2024 in accordance with an embodiment of the disclosed technology.

[0052] The host 102 may send the updated submission queue tail pointer 2022 together with the command information 2026 about the command corresponding to the submission queue tail pointer 2022 to the memory system 110. The command corresponding to the submission queue tail pointer 2022 refers to the command queued at the position indicated by the submission queue tail pointer 2022 in the submission queue 1022. The memory system 110 may store the updated submission queue tail pointer 2022 together with the command information 2026 in the doorbell register 202.

[0053] According to an embodiment of the disclosed technology, the memory system 110 may obtain command information 2026 about commands that have been queued in the submission queue 1022 of the host 102 but have not yet been acquired. Hereinafter, commands that have been queued in the submission queue 1022 of the host 102 but have not yet been acquired in the memory system 110 will be referred to as unacquired commands. The host I / F 132 may perform pre-operations based on the obtained command information 2026, such as allocating a buffer for the unacquired commands and determining the order in which the unacquired commands are queued in the command queue.

[0054] By utilizing the memory system 110's ability to perform pre-operations on unacquired commands, the processing speed of commands can be increased. For example, the specification of the memory system 110 may require that a fault response be provided when a command from the host 102 is not processed within a predetermined processing time. The command processing time may be counted from when the doorbell rings, for example, when the submission queue tail pointer 2022 indicating the location where the corresponding command has been queued is stored in the doorbell register 202.

[0055] It may take some time until the doorbell corresponding to a certain command rings and then the command is acquired. If the memory system 110 can obtain command information only after acquiring the command and interpreting the acquired command, the memory system does not perform any operation for the command in the unacquired state, which results in a waste of the predetermined processing time. In particular, when the submission queue tail pointer 2022 increases faster than the speed at which the memory system 110 acquires commands, for commands queued relatively late in the submission queue, the time from the time the doorbell rings to the time the commands queued relatively late are acquired may further increase. Therefore, the memory system 110 may not process the commands queued relatively late within the predetermined processing time, and thus the memory system 110 may eventually provide a failure response to the host 102.

[0056] According to the embodiments of the disclosed technology, since the memory system 110 can perform pre-operations on unobtained commands, the commands can be processed without wasting the predetermined processing time. Therefore, the memory system 110 can not only increase the processing speed of the commands, but also provide the response expected by the host 102 by observing the predetermined processing time.

[0057] According to an embodiment, the command information 2026 may store information about the command corresponding to the submission queue tail pointer 2022. According to an embodiment, the command information 2026 may include: the starting address information of the data block to be processed by the command, the size information of the data block, the input / output type information of the command, and the identifier information about the queue that has queued the command. The starting address information and the size information may be collectively referred to as address information. The input / output type of the command may be a read type or a write type. When the host 102 includes a plurality of submission queues 1022, the identifier information about the queue may indicate the submission queue 1022 that has queued the command.

[0058] In some implementations, even if the command information 2026 includes all of the start address information, size information, input / output type information, and identifier information about the queue, the size of the command information 2026 may be only about several bytes to several dozen bytes. For example, as the performance of the host I / F 132 increases, the host 102 may provide several GB of data per second to the memory system 110. Therefore, even if the host 102 provides the command information 2026 included in the doorbell register 202, it has little effect on the increase in the time required until the doorbell rings.

[0059] Figure 4 is a diagram illustrating the operation of the data processing system 100 according to an embodiment of the present disclosure.

[0060] In step S402 , the host 102 may queue the command in the submission queue 1022 and update the submission queue tail pointer 2022 .

[0061] In step S404, the host 102 may ring the doorbell through the host I / F 132. For example, the host 102 may store the updated submission queue tail pointer 2022 in the doorbell register 202 and store command information 2026 about the command corresponding to the submission queue tail pointer 2022.

[0062] In step S406, the host I / F 132 may perform a pre-operation for processing the command based on the command information 2026. For example, as a pre-operation, the host I / F 132 may determine the processing order between the unacquired commands and allocate a buffer for the unacquired commands. FIG. 5A to FIG. 5CThe pre-operation according to the embodiment of the present disclosure is described in detail.

[0063] In step S408, the host I / F 132 may fetch commands from the submission queue 1022. For example, the host I / F 132 may fetch commands by providing a memory read request to the host 102. The host I / F 132 may queue the fetched commands in an internal command queue. The host I / F 132 may queue unfetched commands in a CMD queue (CMDQ) 136 based on the processing order determined in step S406.

[0064] In step S410, the processor 134 may process the commands queued in the CMD queue 136. In a first example, the processor 134 may receive write data from the memory of the host 102 in order to process the write command, buffer the data into the buffer allocated in step S406, and program the buffered data in the memory device 150. In a second example, the processor 134 may load data from the memory device 150 in order to process the read command, buffer the data into the allocated buffer, and provide the buffered data to the host 102.

[0065] In step S412, the host I / F 132 may record the completion of the command processing in the completion queue 1024 after processing the command. For example, the host I / F 132 may write a completion queue entry in the completion queue 1024. In this case, the completion queue head pointer 2024 may be incremented.

[0066] In step S414 , the host I / F 132 may provide an interrupt signal to the host 102 .

[0067] In step S416, the host 102 may complete the command.

[0068] In step S418, the host 102 may provide the updated completion queue head pointer 2024 to the memory system 110. The host I / F 132 may store the updated completion queue head pointer 2024 in the doorbell register 202.

[0069] FIG. 5A to FIG. 5C is a diagram for explaining a preliminary operation according to an embodiment of the disclosed technology.

[0070] FIG. 5A to FIG. 5C A CMD queue 136 and a command information (CMDInfo.) queue 536 that may be stored in memory 144 are shown.

[0071] CMD queue 136 can be as shown in reference Figure 1The description queues commands acquired from the host 102. The CMD Info. queue 536 may queue command information regarding commands that have not been acquired.

[0072] Figure 5A A state is shown in which no command is queued in the CMD queue 136 and command information about the unacquired command is queued in the CMD Info. queue 536. For example, the host 102 may ring a doorbell in the order of the first command to the fourth command. The host I / F 132 may queue the first to fourth command information corresponding to the first to fourth commands, respectively, in the CMD Info. queue 536 in the order in which the doorbell is rung.

[0073] The host I / F 132 may perform a pre-operation on the non-acquired command based on the command information 2026 about the non-acquired command.

[0074] In the first example of the pre-operation, the host I / F 132 may determine the order of processing the non-acquired commands based on the address information included in the command information 2026 about the non-acquired commands.

[0075] In the second example of pre-operation, the host I / F 132 may allocate a buffer for an unobtained command based on address information to the memory 144. For example, the host I / F 132 may determine the size of the buffer to be allocated by referring to size information of a data block of an unobtained command.

[0076] Figure 5B It is shown that the order of processing the unacquired commands is changed by the host I / F 132 .

[0077] For example, when the address of the first data block to be processed by the first command and the address of the third data block to be processed by the third command are continuous with each other, the host I / F 132 can change the processing order of the second command and the third command so that the first command and the third command can be processed continuously.

[0078] When queuing commands acquired from the submit queue 1022 in the CMD queue 136, the host I / F 132 may queue the commands in the order determined by the CMD Info.queue 536. For example, the host I / F 132 may acquire the non-acquired commands in the order in which they have been queued in the submit queue 1022, but when queuing the acquired commands in the CMD queue 136, the host I / F 132 may adjust the order between the commands queued in the CMD queue 136 by referring to the order determined by the CMD Info.queue 536.

[0079] Figure 5CFIG. 1 shows that the acquired commands are queued in the CMD queue 136 according to the order of change. For example, the CMD queue 136 may be queued in the same order as Figure 5B The first to fourth commands are queued in the order of the first command, the third command, the second command, and the fourth command in the same order as the command processing order determined in the process.

[0080] According to an embodiment of the disclosed technology, when the host 102 rings the doorbell, the host I / F 132 may receive the command information 2026 and the submission queue tail pointer 2022. The host I / F 132 may perform a pre-operation on the unobtained command by using the command information 2026. For example, the pre-operation may include a buffer allocation operation for the unobtained command and an operation to determine the processing order of the unobtained command. After acquiring the unobtained command, the host I / F 132 may process the acquired command based on the result of the pre-operation.

[0081] When performing a pre-operation on a command that is not acquired, the host I / F 132 can skip performing a buffer allocation operation after acquiring the command. Therefore, the processing time of the acquired command can be shortened. In addition, the host I / F 132 can process the command based on the processing order determined before acquiring the command. Therefore, the command can be processed efficiently.

[0082] While embodiments and various features of the disclosed technology have been described, variations and improvements to the disclosed embodiments and other embodiments may be made based on what has been described and shown.

Claims

1. A data processing system, comprising: Memory systems for storing data and information; as well as a host in communication with the memory system and including a submission queue for queuing one or more commands to be processed by the memory system, the host providing a submission queue tail pointer indicating a tail of the submission queue and command information regarding the one or more commands to the memory system, wherein the memory system receives the command information about the one or more commands, performs a pre-operation on the one or more commands based on the command information, and obtains the one or more commands from the submission queue according to a first order, and The memory system further includes a command information queue configured to queue the command information about the one or more commands in a second order relative to the submission queue tail pointer before the pre-operation. 2 . The data processing system of claim 1 , wherein the pre-operation comprises an operation performed before obtaining the one or more commands and processing the one or more commands.

3. The data processing system of claim 1 , wherein the memory system further queues the fetched command in a command queue included in the memory system, processes the queued command, and provides a completion response to a completion queue of the host. 4 . The data processing system of claim 1 , wherein the command information comprises at least one of address information, command type information, or submission queue identifier information. 5 . The data processing system of claim 1 , wherein the memory system performs the pre-operation by determining a processing order of the one or more commands. 6 . The data processing system of claim 5 , wherein the memory system further fetches the one or more commands according to the first order in which the one or more commands were queued in the submission queue.

7. The data processing system of claim 5, wherein the memory system further queues the one or more commands in a command queue according to the processing order that is different from the first order.

8. The data processing system according to claim 4, wherein the address information includes at least one of start address information of a data block to be processed by the command or size information of the data block. 9 . The data processing system according to claim 8 , wherein the memory system performs the pre-operation by allocating a buffer included in the memory system for the command based on the size information of the data block.

10. A memory system comprising: Memory devices, storing data; a host interface that communicates with a host and receives a submission queue tail pointer and command information about one or more commands corresponding to the submission queue tail pointer from the host, performs a pre-operation on the one or more commands based on the command information, and obtains the one or more commands from the submission queue of the host according to a first order; Command queue, which queues the acquired commands; as well as a processor that communicates with the memory device and controls the memory device to process the acquired commands queued in the command queue, and The memory system further includes a command information queue configured to queue command information about the one or more commands in a second order relative to the submission queue tail pointer before the pre-operation.

11. The memory system of claim 10, wherein the host interface further provides a completion response to a completion queue of the host in response to completion of processing of the acquired command. 12 . The memory system of claim 10 , wherein the command information comprises at least one of address information, command type information, or submission queue identifier information.

13. The memory system of claim 12, wherein the host interface further receives additional command information about the one or more commands from the host, and the additional command information comprises at least one of address information, command type information, or submission queue identifier information. 14 . The memory system of claim 13 , wherein the host interface performs the pre-operation by determining a processing order of the one or more commands based on the address information of each of the one or more commands.

15. The memory system of claim 14, wherein the host interface further fetches the one or more commands according to the first order in which the one or more commands were queued in the submission queue.

16. The memory system of claim 14, wherein the host interface further queues the one or more commands in the command queue according to the processing order that is different from the first order. 17 . The memory system according to claim 12 , wherein the address information comprises at least one of start address information of a data block to be processed by the command or size information of the data block. 18 . The memory system of claim 17 , wherein the host interface performs the pre-operation by allocating a buffer included in the memory system for the one or more commands based on the size information of the data block.

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