Hardware Behavior Description Method for Superconducting Digital Circuit Cell Library

Abstract

The present invention provides a method for describing the hardware behavior of a superconducting digital circuit cell library, including: defining global variables and initializing the program; executing in parallel the rules for triggering actions of each superconducting device in the superconducting digital circuit cell to be developed, implementing corresponding triggering actions based on the triggering conditions of each superconducting device, where each rule only includes the triggering action of one superconducting device, and the triggering conditions of each superconducting device include the input of a signal or the triggering of the previous superconducting device; and outputting corresponding results based on the triggering actions of each superconducting device. The method for describing the hardware behavior of the superconducting digital circuit cell library of the present invention describes the superconducting SFQ digital circuit logic cell library based on a novel split rule, forming independent rules that can jump freely or run in parallel between the rules. Therefore, it can adapt to more actual working conditions of the circuit, thereby improving the accuracy of parameter extraction and effectively enhancing the reliability of circuit design.

Description

Technical Field

[0001] The present invention relates to the field of superconducting digital circuit design, and particularly to a method for describing the hardware behavior of a superconducting digital circuit cell library. Background Art

[0002] A hardware description language is a standard descriptive text for the structure and behavior of a circuit system. It is a language for describing digital circuits and systems in a formalized way and is widely used in the fields of semiconductor integrated circuit hardware design and simulation. According to the different scales of circuits, digital circuit designers can use this language to express their design ideas layer by layer from the upper-level circuit to the lower-level circuit. As the bottom-level circuit, the gate-level unit is the cornerstone of the entire circuit system, so accurate hardware description is required. For superconducting digital circuit units using superconducting principles and technologies, their working states also need to be accurately described in hardware language. Currently, the domestic research in this field is still blank.

[0003] Superconducting digital circuits work based on superconducting Josephson junctions. Among them, superconducting RSFQ (Rapid Single Flux Quantum) circuits have important applications in high-performance computers, quantum computing, space exploration, etc. due to their advantages of high speed and low power consumption. Different from semiconductor CMOS chip design, in order to perform large-scale / super-large-scale simulations of superconducting RSFQ circuits, each unit needs to provide a corresponding model, describe the digital behavior of the unit in Verilog HDL hardware language, and write time parameters such as the setup / hold time and delay time of the unit under different bias current conditions into the model to complete the timing simulation of the circuit. Therefore, providing accurate unit timing parameters plays a key role in the simulation reliability of large-scale / super-large-scale superconducting RSFQ circuits.

[0004] Currently, people mainly use the superconducting simulation tool pscan2 to perform analog / digital simulations of gate-level and small-scale superconducting RSFQ circuits, and write a gate-level description language suitable for the pscan2 tool according to the circuit structure and working principle of each unit to complete the extraction of corresponding timing parameters. As Figure 1 shown, a superconducting Josephson transmission line is composed of a first Josephson junction J1, a second Josephson junction J2, a third Josephson junction J3, and a fourth Josephson junction J4. Signals are input from the left AI end and transmitted to the AO end output through the sequential triggering of the 4 junctions. Among them, L1-L7 are superconducting loop inductances, LJ1-LJ4 and LI1-LI6 are parasitic inductances, and I1 and I2 are bias currents. The existing description method allows multiple Josephson junctions to exist in one rule, and each junction is triggered in the order of J1→J2→J3→J4. The description language is as follows:

[0005] rule jtlpass(get(AI) AND (TCURR > 5))

[0006] inc(J1),

[0007] inc(J2),

[0008] inc(J3),

[0009] inc(J4),

[0010] set(A0);

[0011] Since under one rule, when performing circuit function checks, it is necessary to wait for 4 statements to be executed sequentially before entering other rules, and it is impossible to jump out of this rule during this period. Therefore, it has imposed great limitations on the accuracy and flexibility of circuit descriptions, resulting in inaccurate extraction of timing parameters and circuit operating margin parameters; the superconducting digital circuit cell library established based on the above rules will increase the risk of failure of large-scale circuits in practical applications. Summary of the Invention

[0012] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for describing the hardware behavior of a superconducting digital circuit cell library to solve problems such as low accuracy and poor flexibility in the description of superconducting digital circuits in the prior art.

[0013] To achieve the above object and other related objects, the present invention provides a method for describing the hardware behavior of a superconducting digital circuit cell library, and the method for describing the hardware behavior of the superconducting digital circuit cell library at least includes:

[0014] Define global variables and perform program initialization;

[0015] Execute in parallel the rules for triggering actions of each superconducting device in the superconducting digital circuit cell to be developed, and implement corresponding triggering actions based on the triggering conditions of each superconducting device. Each rule only includes the triggering action of one superconducting device, and the triggering conditions of each superconducting device include the input of a signal or the triggering of the previous superconducting device;

[0016] Output corresponding results based on the triggering actions of each superconducting device.

[0017] Optionally, the superconducting digital circuit cell to be developed includes a cell without a flux storage function and a cell with a flux storage function.

[0018] More optionally, the cell without a flux storage function includes one or more combinations of Josephson transmission lines, splitters, and current collectors.

[0019] More optionally, the unit with a magnetic flux storage function includes one or more combinations of D flip-flops, AND gates, OR gates, NOT gates, XOR gates, and non-destructive readout units.

[0020] Optionally, the triggering sequence of each superconducting device is determined based on the signal transmission path.

[0021] More optionally, the superconducting device includes a Josephson junction.

[0022] Optionally, the method for describing the hardware behavior of the superconducting digital circuit unit library further includes: in each rule, if the triggering process of the current superconducting device exceeds a preset time, it is determined that the circuit is not working properly.

[0023] More optionally, the step of calculating the time of the triggering process includes, after the triggering condition is satisfied and before the current superconducting device performs the triggering action, assigning the current running time of the program to the corresponding global variable, and after the current superconducting device performs the triggering action, calculating the difference between the current running time of the program and the corresponding global variable, so as to obtain the time of the triggering process of the current superconducting device.

[0024] Optionally, after it is determined that the circuit is not working properly, a prompt with the label of the current superconducting device is displayed to determine the position of the device with an error in the superconducting digital circuit unit to be developed.

[0025] As described above, the method for describing the hardware behavior of the superconducting digital circuit unit library of the present invention has the following beneficial effects:

[0026] The method for describing the hardware behavior of the superconducting digital circuit unit library of the present invention describes the superconducting SFQ digital circuit logic unit library based on a new split rule, forming independent rules that can jump freely or run in parallel between rules. Therefore, it can adapt to more actual working conditions of the circuit, thereby improving the accuracy of parameter extraction and effectively enhancing the reliability of circuit design. Description of the Drawings

[0027] Figure 1 Schematic diagram of the circuit structure shown as a superconducting Josephson transmission line.

[0028] Figure 2 Schematic diagram of the circuit structure shown as a superconducting D flip-flop.

[0029] Figure 3 Schematic diagram of the signal timing of the clock input terminal TI.

[0030] Figure 4 Schematic diagram of the signal timing of the data input terminal AI.

[0031] Figure 5 Schematic diagram of the signal timing of the output terminal TO.

[0032] Figure 6 A schematic diagram of an analog waveform when XI = 0.7 is shown for the clock input terminal TI, the data input terminal AI, and the output terminal TO.

[0033] Figure 7 Shown as Figure 6 A partial enlarged schematic diagram of the virtual box in

[0034] Figure 8 Another schematic diagram of an analog waveform when XI = 0.7 is shown for the clock input terminal TI, the data input terminal AI, and the output terminal TO.

[0035] Figure 9 Shown as Figure 8 A partial enlarged schematic diagram of the virtual box in Detailed implementation manners

[0036] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] Please refer to Figures 1 to 9 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components during actual implementation. The types, quantities, and ratios of the components during actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0038] The present invention provides a method for describing the hardware behavior of a superconducting digital circuit cell library. The method for describing the hardware behavior of the superconducting digital circuit cell library includes:

[0039] Define global variables and perform program initialization;

[0040] Parallelly execute the rules for triggering actions of each superconducting device in the superconducting digital circuit cell to be developed, and implement corresponding triggering actions based on the triggering conditions of each superconducting device. Each rule only includes the triggering action of one superconducting device, and the triggering conditions of each superconducting device include the input of a signal or the triggering of the previous superconducting device;

[0041] Output corresponding results based on the triggering actions of each superconducting device.

[0042] Specifically, the superconducting digital circuit units to be developed mainly include: 1) units without flux storage function and 2) units with flux storage function. Among them, the structures and functions of the units without flux storage function are relatively simple, including but not limited to one or more combinations of Josephson transmission lines, splitters, and current collectors, which will not be elaborated one by one here; while the units with flux storage function have more complex structures, logic functions, and timing parameters, including but not limited to one or more combinations of D flip-flops, AND gates, OR gates, NOT gates, XOR gates, and non-destructive readout units, which will not be elaborated one by one here.

[0043] As an example, in this embodiment, based on the transmission path (signal flow direction) of the signal (flux quantum), the order of triggering of each superconducting device is determined. Based on the logical relationship, when the triggering of a latter superconducting device is related to the triggering of a former superconducting device, the triggering of the former superconducting device is used as the triggering condition for the latter superconducting device.

[0044] As an implementation manner of the present invention, the hardware behavior description method of the superconducting digital circuit unit library further includes: in each rule, if the triggering process of the current superconducting device exceeds a preset time, it is determined that the circuit is operating abnormally. As an example, the preset time is defined as d_JJ*TQ, where d_JJ and TQ are variables, and both d_JJ and TQ are assigned values in the excitation file, usually being 1 cycle time (in actual applications, the times of d_JJ and TQ can be set according to needs).

[0045] As another implementation manner of the present invention, the steps of calculating the time of the triggering process include, after the triggering condition is satisfied and before the current superconducting device performs the triggering action, assigning the current running time of the program to the corresponding global variable, and after the current superconducting device performs the triggering action, calculating the difference between the current running time of the program and the corresponding global variable, thereby obtaining the time of the triggering process of the current superconducting device.

[0046] As another implementation manner of the present invention, after it is determined that the circuit is operating abnormally, a prompt with the label of the current superconducting device is displayed to determine the position of the device where an error occurs in the superconducting digital circuit unit to be developed.

[0047] As an example, in this embodiment, the superconducting device is a Josephson junction. In actual use, the range of superconducting devices can be set based on actual needs, including but not limited to structures in which multiple Josephson junctions are connected in series or parallel, which will not be listed one by one here.

[0048] The principle of the present invention will be described below in conjunction with two specific superconducting digital circuit units.

[0049] Embodiment 1

[0050] This embodiment is for Figure 1The superconducting Josephson transmission line shown is described as follows:

[0051] external tbegin = 0;

[0052] rule j1pass(get(AI) AND (TCURR > 5)) tbegin = tcurr, inc(J1), exit("slow J1", tcurr - tbegin > d_JJ * TQ);

[0053] rule j2pass(inc(J1) AND (TCURR > 5)) tbegin = tcurr, inc(J2), exit("slow J2", tcurr - tbegin > d_JJ * TQ);

[0054] rule j3pass(inc(J2) AND (TCURR > 5)) tbegin = tcurr, inc(J3), exit("slow J3", tcurr - tbegin > d_JJ * TQ);

[0055] rule j2pass(inc(J3) AND (TCURR > 5)) tbegin = tcurr, inc(J4), exit("slow J4", tcurr - tbegin > d_JJ * TQ);

[0056] rule Output(inc(J4) AND (TCURR > 5) set(AO);

[0057] First, define global variables and initialize the program, setting the global variable tbegin = 0.

[0058] Then, 4 rules can run in parallel. When the trigger conditions are met, the corresponding Josephson junctions are triggered. The trigger conditions of each Josephson junction may be related to the triggering of Josephson junctions in other rules, that is, the triggering of the previous Josephson junction is the trigger condition for the next Josephson junction.

[0059] Specifically, in the first rule, when the AI signal arrives and the current running time of the program TCURR > 5 (5 is a preset value, which can be set according to actual needs), the current running time tcurr of the program is assigned to the global variable tbegin, and then the triggering action of the first Josephson junction J1 is executed. After the triggering is completed, a judgment is made. If the time during the triggering process (tcurr - tbegin) exceeds the preset time (d_JJ * TQ), the program determines that the circuit is not working properly, exits and displays "slow J1" to indicate that the circuit is not working properly and the problem location is the first Josephson junction J1. In the second rule, when the first Josephson junction J1 completes the triggering and the current running time of the program TCURR > 5, the current running time tcurr of the current program is assigned to the global variable tbegin, and then the triggering action of the second Josephson junction J2 is executed. After the triggering is completed, a judgment is made. Similarly, the third rule and the fourth rule correspond to the third Josephson junction J3 and the fourth Josephson junction J4, which will not be elaborated here one by one. Since the triggering of the first Josephson junction J1, the second Josephson junction J2, the third Josephson junction J3, and the fourth Josephson junction J4 has a sequential order in the circuit structure, the triggering of the previous Josephson junction can be used as the triggering condition for the next Josephson junction, and each rule uses the same global variable. In actual use, different global variables can be set respectively, not limited to this embodiment.

[0060] Finally, when the fourth Josephson junction J4 completes the triggering and the current running time of the program TCURR > 5, an AO signal is output at the AO terminal.

[0061] Each rule of the present invention includes a triggering action of a junction, forming independent rules. The rules can jump freely or run in parallel. Therefore, in essence, it can adapt to more actual working conditions of the circuit, thereby improving the accuracy of parameter extraction and effectively enhancing the reliability of circuit design.

[0062] Embodiment 2

[0063] As Figure 2As shown, the superconducting D flip-flop includes a fifth Josephson junction J5, a sixth Josephson junction J6, a seventh Josephson junction J7, and an eighth Josephson junction J8. Among them, the first end of the fifth Josephson junction J5 is connected to the data input terminal AI and a first bias current IA1 is loaded, and the second end is grounded; the first end of the sixth Josephson junction J6 is connected to the clock input terminal TI and a second bias current IT1 is loaded, and the second end is grounded; the first end of the seventh Josephson junction J7 is connected to the first end of the sixth Josephson junction J6, and the second end is connected to the output terminal TO; the first end of the eighth Josephson junction J8 is connected to the output terminal TO, and the second end is grounded; there are loop inductances (L8, L10, L11, and L16) and parasitic inductances (LJ5, LJ6, LJ8, L9, L12 to L15, LIA1, and LIT1) on the connection lines between the connection terminals, which will not be elaborated here one by one. Its function is: when the AI signal arrives first, the flux quantum is stored in the circuit loop. At this time, when the TI signal arrives, it will release the flux quantum and generate a TO pulse output; conversely, when the AI signal does not arrive, the TI signal cannot generate an output at the TO terminal.

[0064] Using the method of the present invention for Figure 2 The D flip-flop shown is described as follows:

[0065]

[0066] First, define global variables and initialize the program. Let the global variable state = 0. When the current running time TCURR of the program < 5, state = 0.

[0067] Then, 4 rules for triggering the Josephson junction run in parallel. Initialize and assign values to the global variables in each rule, and then execute the corresponding rules.

[0068] Specifically, initialize the global variable tbegin_Tin, and let the global variable tbegin_Tin = 0. Execute the rule corresponding to the sixth Josephson junction J6. The whitebox value controls whether rule verification of the circuit is required in the simulation. whitebox = 1 means yes, whitebox = 0 means no, and the default value is 1, which is set in the excitation file of the top-level circuit and will not be elaborated here one by one; at the same time, when there is a signal excitation at the clock input port TI, the trigger condition is met. Before the sixth Josephson junction J6 is triggered, assign the current running time tcurr of the current program to the global variable tbegin_Tin, and then execute the trigger action of the sixth Josephson junction J6. After the trigger is completed, make a judgment. If the time during the trigger process > d_JJ * TQ, the program determines that the circuit is not working properly, exits and displays "slow J6".

[0069] Specifically, initialize the global variable tbegin_Ain and set the global variable tbegin_Ain = 0. Execute the rule corresponding to the fifth Josephson junction J5. When the global variable state = 0 and there is a signal input at the data input port AI, the triggering condition is satisfied and triggering occurs. Details are not elaborated here.

[0070] Specifically, initialize the global variable tbegin_S1 and set the global variable tbegin_S1 = 0. Execute the rule corresponding to the eighth Josephson junction J8. When the global variable state = 1 and the sixth Josephson junction J6 has completed triggering, the triggering condition is satisfied. The eighth Josephson junction J8 triggers and outputs a signal at the output terminal TO, and the global variable state (circuit state) returns to the 0 state. Details are not elaborated here.

[0071] Specifically, initialize the global variable tbegin_S0 and set the global variable tbegin_S0 = 0. Execute the rule corresponding to the seventh Josephson junction J7. When the global variable state = 0 and the sixth Josephson junction J6 has completed triggering, the triggering condition is satisfied and triggering occurs. Details are not elaborated here.

[0072] Finally, after executing the rule corresponding to the eighth Josephson junction J8, output the signal TO.

[0073] When the circuit is working, the arrival of the input signal and / or the triggering of the previous Josephson junction serve as the triggering condition for the next Josephson junction; at the same time, each rule can only contain the triggering action of one junction, so that the entire description system is both associated and independent. As Figure 3 shown is the signal timing diagram of the clock input terminal TI, as Figure 4 shown is the signal timing diagram of the data input terminal AI, as Figure 5 shown is the signal timing diagram of the output terminal TO; at this time, the execution order of the description language rules of the present invention is as follows: First, trigger the sixth Josephson junction J6 based on the clock signal excitation of the clock input terminal TI; subsequently, since state = 0 and the sixth Josephson junction J6 is triggered, the seventh Josephson junction J7 is triggered, but no signal is output; as there is a signal input at the data input terminal AI, state remains 0, and the fifth Josephson junction J5 is triggered, and state is assigned the value 1; the clock signal excitation of the clock input terminal TI arrives again, triggering the sixth Josephson junction J6; at this time, state = 1 and the triggering condition of the sixth Josephson junction J6 is satisfied, and the eighth Josephson junction J8 is triggered and outputs a signal at the output terminal TO.

[0074] Compared with the existing description method where there are multiple knot-triggering actions in one rule, the unit library established by the present invention has higher precision in extracting timing parameters. Among them, the change in the setup / hold time of the signal is the most obvious. As shown in Table 1 below,

[0075]

[0076] For D flip-flops under different bias currents XI (relative values), the setup time extracted by using the D flip-flop described in the present invention is allowed to be negative. As Figure 6 shown is an analog waveform of the clock input terminal TI, data input terminal AI, and output terminal TO when XI = 0.7. Figure 7 For Figure 6 the partial enlarged view of the dashed box in Figure 8 it can be seen that for the setup time, when the signal at the data input terminal AI lags behind the signal at the clock input terminal TI by 1.6 ps, the signal at the output terminal TO can still be normally output. As Figure 9 shown is another analog waveform of the clock input terminal TI, data input terminal AI, and output terminal TO when XI = 0.7. Figure 8 For the partial enlarged view of the dashed box in

[0077] it can be seen that for the hold time, when the signal at the data input terminal AI and the signal at the second clock input terminal TI are close to only 3.5 ps, the arrival of the signal at the third clock input terminal TI can still cause the output terminal TO to produce an output. Generally speaking, the present invention can effectively explore the timing margin of the digital logic unit circuit in the unit library, reduce its requirements for timing, and has been verified through analog waveform simulation. In large-scale circuit development, the working conditions of superconducting SFQ logic units are relaxed, effectively increasing the flexibility and redundancy of scale-level circuit design.

[0078] In summary, the present invention provides a hardware behavior description method for a superconducting digital circuit cell library, including: defining global variables and initializing the program; executing in parallel the rules for triggering actions of each superconducting device in the superconducting digital circuit cell to be developed, implementing corresponding triggering actions based on the triggering conditions of each superconducting device, where each rule only includes the triggering action of one superconducting device, and the triggering conditions of each superconducting device include signal input or the triggering of the previous superconducting device; and outputting corresponding results based on the triggering actions of each superconducting device. The hardware behavior description method of the superconducting digital circuit cell library of the present invention describes the superconducting SFQ digital circuit logic cell library based on a novel split rule, forming independent rules that can jump freely or run in parallel between rules. Therefore, it can adapt to more actual circuit working conditions, thereby improving the accuracy of parameter extraction and effectively enhancing the reliability of circuit design. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0079] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A hardware behavior description method for a superconducting digital circuit cell library, characterized in that, The hardware behavior description method of the superconducting digital circuit cell library at least includes: Defining global variables and initializing the program; Parallelly executing the rules for triggering actions of each superconducting device in the superconducting digital circuit cell to be developed, implementing corresponding triggering actions based on the triggering conditions of each superconducting device, where each rule only includes the triggering action of one superconducting device, and the triggering conditions of each superconducting device include signal input or the triggering of the previous superconducting device; Outputting corresponding results based on the triggering actions of each superconducting device; The hardware behavior description method of the superconducting digital circuit cell library further includes: in each rule, if the triggering process of the current superconducting device exceeds the preset time, it is determined that the circuit is malfunctioning; the step of calculating the time of the triggering process includes, after the triggering condition is satisfied and before the current superconducting device executes the triggering action, assigning the current running time of the program to the corresponding global variable, and calculating the difference between the current running time of the program and the corresponding global variable after the current superconducting device executes the triggering action, so as to obtain the time of the triggering process of the current superconducting device.

2. The hardware behavior description method of the superconducting digital circuit cell library according to claim 1, characterized in that: The superconducting digital circuit cell to be developed includes cells without flux storage function and cells with flux storage function.

3. The hardware behavior description method of the superconducting digital circuit cell library according to claim 2, wherein: The cells without flux storage function include one or more combinations of Josephson transmission lines, splitters, and combiners.

4. The hardware behavior description method of the superconducting digital circuit cell library according to claim 3, characterized in that: The cells with flux storage function include one or more combinations of D flip-flops, AND gates, OR gates, NOT gates, XOR gates, and non-destructive readout units.

5. The hardware behavior description method of the superconducting digital circuit cell library according to claim 1, characterized in that: Determining the sequence of triggering of each superconducting device based on the signal transmission path.

6. The hardware behavior description method of the superconducting digital circuit cell library according to claim 1 or 5, characterized in that: The superconducting device includes a Josephson junction.

7. The hardware behavior description method of the superconducting digital circuit cell library according to claim 1, characterized in that: After determining that the circuit is malfunctioning, display a prompt with the label of the current superconducting device to determine the position of the device with an error in the superconducting digital circuit cell to be developed.

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