Three-dimensional storage device and manufacturing method thereof

Abstract

The present invention discloses a three-dimensional memory device and a method for manufacturing the same, comprising a substrate including a first region and a second region; a liner layer disposed between the substrate and a memory stack structure; and a memory stack structure comprising a plurality of alternating conductive layers and dielectric layers disposed on the substrate and extending from the first region to the second region. The memory stack structure on the second region comprises a stepped structure, wherein the steps of the stepped structure each comprise a conductive layer and a dielectric layer, and the sidewalls of the conductive layer are recessed from the sidewalls of the dielectric layer, exposing a portion of the bottom surface of the dielectric layer. The recessed sidewalls of the conductive layer from the sidewalls of the dielectric layer can reduce the risk of short circuits between the conductive layer and subsequently fabricated wordline contact plugs.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, in particular to a three-dimensional memory device and a manufacturing method thereof. Background Art

[0002] Memory plays an indispensable and important role in modern electronic products. In addition to storing user data, memory is also responsible for storing program code executed by the central processing unit and information that needs to be temporarily saved during calculations. Memory can be divided into volatile memory (volatile memory) and non-volatile memory (non-volatile memory). Common volatile memory includes dynamic random access memory (DRAM) and static random access memory (SRAM). The data in these memory disappears after power is removed and must be re-entered when power is next supplied. Non-volatile memory includes read-only memory (ROM) and flash memory. The data stored in these memory persists even after power is removed, so the previously stored valid data can be directly read after power is restored.

[0003] NAND flash memory, with its advantages of small size, low power consumption, fast write speed, and low manufacturing cost, is currently the most widely used non-volatile memory. With advances in semiconductor manufacturing processes, NAND flash memory has evolved from a planar structure to a three-dimensional (3D) stacked structure, achieving higher cell density per unit wafer area and meeting the demand for higher storage capacity. How to fabricate a 3D stacked structure while improving process margins to maintain stable yields remains an ongoing research topic in this field. Summary of the Invention

[0004] The present invention provides a three-dimensional memory device and a method for fabricating the same. The staircase structure is formed by trimming and etching a memory stack structure comprising alternating conductive and dielectric layers. Each step in the resulting staircase structure has a nose (a portion where the dielectric layer protrudes from the conductive layer). The nose reduces the risk of short circuits caused by misalignment during subsequent wordline contact plug fabrication.

[0005] An embodiment of the present invention provides a three-dimensional memory device, comprising a substrate including a first region and a second region; a liner layer disposed between the substrate and a memory stack structure; and a memory stack structure comprising a plurality of alternating conductive layers and dielectric layers, disposed on the substrate and extending from the first region to the second region, wherein the memory stack structure on the second region comprises a staircase structure, wherein steps of the staircase structure respectively comprise a conductive layer and a dielectric layer, and sidewalls of the conductive layer are recessed from sidewalls of the dielectric layer, exposing a portion of a bottom surface of the dielectric layer.

[0006] Another embodiment of the present invention provides a method for manufacturing a three-dimensional memory device, comprising the following steps. First, a substrate is provided, comprising a first region and a second region. Next, a memory stack structure is formed on the substrate, comprising a plurality of alternating conductive layers and a plurality of dielectric layers, extending from the first region to the second region. Next, a trimming-etching process is performed to form a staircase structure in the memory stack structure on the second region, wherein the steps of the staircase structure each comprise a conductive layer and a dielectric layer, and the sidewalls of the conductive layer are recessed from the sidewalls of the dielectric layer, exposing a portion of the bottom surface of the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings provide a deeper understanding of these embodiments and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all figures are schematic and relative sizes and proportions have been adjusted for ease of illustration and drawing. The same symbols in different embodiments represent corresponding or similar features.

[0008] Figures 1 to 10 Illustrated is a schematic diagram of steps of a method for fabricating a three-dimensional memory device according to an embodiment of the present invention.

[0009] The description of the accompanying drawings is as follows:

[0010] 100 substrate

[0011] 101 cushioning layer

[0012] 120 storage stacking structure

[0013] 122 conductive layer

[0014] 124 dielectric layer

[0015] 130 channel structure

[0016] 132 functional layers

[0017] 134 Filling layer

[0018] 140 Mask Layer

[0019] 150 Mask Layers

[0020] 160 ladder structure

[0021] 162 insulation layer

[0022] 164 interlayer dielectric layer

[0023] 166 word line contact plugs

[0024] 122a Top surface

[0025] 122b bottom

[0026] 122s sidewall

[0027] 124a Top surface

[0028] 124b bottom

[0029] 124n Nose step

[0030] 124s sidewall

[0031] P1 top angle

[0032] P2 bottom corner

[0033] P3 most prominent point

[0034] V1 vertical extension line

[0035] V2 vertical extension line

[0036] H Height

[0037] RS Depression

[0038] θ angle

[0039] E1 etching step

[0040] E2 trimming steps

[0041] L Length

[0042] R1 Zone 1

[0043] R2 Second Zone

[0044] ST steps

[0045] TK1 thickness

[0046] TK2 thickness

[0047] W Width DETAILED DESCRIPTION

[0048] To help those skilled in the art further understand the present invention, the following lists preferred embodiments of the present invention and, together with the accompanying drawings, describes in detail the components and intended effects of the present invention. It should be noted that the features of the following embodiments may be replaced, recombined, or combined to create other embodiments without departing from the spirit of the present invention.

[0049] As used herein, the terms "about," "approximately," "substantially," and "roughly" generally mean within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. The quantities or values exemplified in the embodiments are approximate quantities or values. In the absence of specific reference to "about," "approximately," "substantially," or "roughly," the meanings of "about," "approximately," "substantially," or "roughly" may be implied.

[0050] For ease of description, spatially relative terms such as "lower," "beneath," "under," "lower," "upper," "beneath," "above," and "higher" may be used in the specification to describe the relationship of one element or feature to another element or features, as shown in the figures. These spatially relative terms also encompass different orientations or positions of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used in the specification should be interpreted accordingly.

[0051] Figures 1 to 10 The figure shows a schematic diagram of the steps of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention. Figure 1 First, a substrate 100 is provided. Then, a memory stack structure 120 is formed on the substrate 100. Then, a channel structure 130 is formed in the memory stack structure 120. According to one embodiment of the present invention, a liner layer 101, such as a silicon oxide layer, may be provided between the substrate 100 and the memory stack structure 120. The channel structure 130 penetrates the memory stack structure 120 and the liner layer 101 and is in direct contact with the substrate 100.

[0052] The substrate 100 may be, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or other suitable materials. The substrate 100 may include a first region R1 and a second region R2 adjacent to each other, wherein the first region R1 may be, for example, a memory array region, and the second region R2 may be, for example, a wordline contact region.

[0053] The memory stack structure 120 includes a plurality of alternating conductive layers 122 and dielectric layers 124, extending from the first region R1 to the second region R2 of the substrate 100. The conductive layers 122 may include conductive materials such as, but not limited to, aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium-tungsten (Ti / W), titanium-titanium nitride (Ti / TiN), polysilicon (polysilicon), doped silicon, silicide, or any combination thereof. According to one embodiment of the present invention, the conductive layers 122 may include tungsten (W). The dielectric layers 124 may include dielectric materials such as, but not limited to, silicon oxide (SiOx), silicon nitride (SiN), silicon oxynitride (SiON), or any combination thereof. According to one embodiment of the present invention, the dielectric layers 124 may include silicon oxide.

[0054] The channel structure 130 may have a pillar shape (e.g., a cylindrical shape) and extend vertically (perpendicular to the surface of the substrate 100) through the memory stack structure 120 and the liner layer 101 on the second region R2. The channel structure 130 primarily includes a functional layer 132 disposed along the sidewalls of a channel hole (not shown) and a filling layer 134 that fills the remaining space in the channel hole. According to one embodiment of the present invention, the functional layer 132 may include a multilayer structure (not shown), such as a channel layer and an ONO composite layer composed of silicon oxide, silicon nitride, and silicon oxide, disposed between the channel layer and the sidewalls of the channel hole (not shown). The channel layer may include a semiconductor material, such as polycrystalline silicon. The filling layer 134 may include a dielectric material, such as silicon oxide. The intersection of the channel structure 130 and each conductive layer 122 represents the location of the memory cell. The conductive layer 122 serves as a word line, used to control the writing and reading of data in each memory cell.

[0055] Please refer to Figures 2 to 8 , illustrating the subsequent trim-etching process to form a staircase structure 160 in the memory stack structure 120 on the second region R2. The trim-etching process can be performed using a single mask layer or multiple mask layers, depending on the total number of layers in the memory stack structure 120. This article uses the trim-etching process using two mask layers (i.e., mask layer 140 and mask layer 150) as an example for illustration, but it should be understood that other mask layer counts are also within the scope of the present invention.

[0056] In detail, Figure 2 As shown, a patterned mask layer 140 (e.g., a photoresist layer) may be formed on the memory stack structure 120, and then an etching step E1 (e.g., dry etching and / or wet etching) is performed on the exposed portion of the memory stack structure 120 using the mask layer 140 as an etching mask to remove a portion of the stacked layers of the memory stack structure 120 (e.g., remove the exposed first pair of dielectric layers 124 and conductive layer 122), thereby obtaining a step ST on the upper half of the memory stack structure 120, which includes the conductive layer 122 and the dielectric layer 124 thereon. Then, as shown in FIG. Figure 3 As shown, the mask layer 140 is trimmed in a step E2 (eg, wet etching) to remove a portion of the mask layer 140 until the top surface of the dielectric layer 124 of the step ST is exposed from the mask layer 140 and has a predetermined width W. Subsequently, as shown Figure 4 As shown, the exposed portion of the storage stack structure 120 is etched in step E1 using the trimmed mask layer 140 as an etching mask to remove part of the stacked layers of the storage stack structure 120 (for example, the exposed first pair of dielectric layers 124 and conductive layer 122 are removed), thereby obtaining another step ST on the upper half of the storage stack structure 120.

[0057] like Figure 5 As shown, the cycle can be repeated Figure 2 、 Figure 3 and Figure 4 , thereby forming a plurality of steps ST on the upper half of the memory stack structure 120. Next, the remaining mask layer 140 is removed, and another patterned mask layer 150 (e.g., a photoresist layer) is formed on the memory stack structure 120. The mask layer 150 is used as an etching mask to perform an etching step E1 (e.g., dry etching and / or wet etching) on the exposed portion of the memory stack structure 120 to remove part of the stacked layers of the memory stack structure 120 (e.g., remove the exposed first pair of dielectric layers 124 and conductive layer 122), thereby obtaining a step ST on the lower half of the memory stack structure 120. Next, as Figure 6As shown, the mask layer 150 may be subjected to a trimming step E2 (eg, wet etching) to remove a portion of the mask layer 150 until the top surface of the dielectric layer 124 of the step ST is exposed from the mask layer 150 and has a predetermined width W. Then, as shown in FIG. Figure 7 As shown, the exposed portion of the memory stack structure 120 is etched using the trimmed mask layer 150 as an etching mask to perform an etching step E1 to remove a portion of the stacked layers of the memory stack structure 120 (e.g., the exposed first pair of dielectric layers 124 and conductive layer 122), thereby obtaining another step ST in the lower half. Figure 8 As shown, it can be repeated Figure 5 、 Figure 6 and Figure 7 The steps of step 150 are performed to obtain a plurality of steps ST located in the lower half of the memory stack structure 120, and then the remaining mask layer 150 is removed to obtain a stepped structure 160. Each step ST of the stepped structure 160 includes a conductive layer 122 and a dielectric layer 124 above the conductive layer 122. The stepped structure 160 may also be referred to as a word line fan-out structure.

[0058] Please refer to Figure 8 The upper right illustration of FIG. 1 shows an enlarged schematic diagram of one step ST of the stair structure 160. The height H of the step ST is approximately equal to the height between the top surface 124a of the dielectric layer 124 at the step ST and the top surface 124a of the dielectric layer 124 at the next step ST. The present invention can adjust the etching step E1 so that after etching step E1, the sidewalls 122s of the conductive layer 122 at the step ST are recessed from the sidewalls 124s of the dielectric layer 124 to form a recess RS, exposing a portion of the bottom surface 124b of the dielectric layer 124. The portion of the dielectric layer 124 that protrudes horizontally (parallel to the surface of the substrate 100) from the sidewalls 122s of the conductive layer 122 constitutes a step nosing portion 124n of the step ST.

[0059] Please continue to refer to Figure 8The upper right illustration of the figure shows a recess RS. The recess RS may include a top angle P1 and a bottom angle P2, which are approximately the locations where the upper and lower ends of the sidewall 122s of the conductive layer 122 intersect the dielectric layer 124, respectively. The step nose 124n may have a length L, and the length L may be defined as being approximately equal to the horizontal distance between a vertical extension line V1 passing through the most protruding point P3 of the sidewall 124s and a vertical extension line V2 passing through the top angle P1. The length L of the step nose 124n is preferably less than 1 / 4 of the height H of the step ST. According to some embodiments of the present invention, the thickness of the conductive layer 122 may be approximately 50 nm, the thickness of the dielectric layer 124 (the thickness TK1 of the portion covered by the conductive layer 122) may be approximately 30 nm, and the height H may be approximately 80 nm. The length L of the step nose 124n may be less than or equal to 20 nm and greater than or equal to 5 nm, for example, approximately 15 nm, but is not limited thereto.

[0060] The depth of the recess RS can be defined as the horizontal distance between any point on the sidewall 122s of the conductive layer 122, the top corner P1, or the bottom corner P2 and the vertical extension line V1. The present invention can also adjust the etching step E1 so that the upper portion (the portion close to the top corner P1) and the lower portion (the portion close to the bottom corner P2) of the recess RS have different depths. In some embodiments, such as Figure 8 As shown, the depth of the upper portion of the recess RS can be greater than the depth of the lower portion of the recess RS, and the sidewalls 122s of the conductive layer 122 can be inclined toward the conductive layer 122 from bottom to top, with an angle θ between the sidewalls 122s and the top surface 122a being greater than 90 degrees. According to some embodiments of the present invention, the etching step E1 can be adjusted to provide the sidewalls 122s of the conductive layer 122 with a curved profile.

[0061] In some embodiments, to ensure that no conductive layer 122 remains on the dielectric layer 124 at the step ST, over-etching is typically performed in the etching step E1 until the conductive layer 122 is etched. This removes a portion of the dielectric layer 124 (the dielectric layer 124 at the lower step ST), resulting in a top surface 124a of the dielectric layer 124 having a concave profile. Furthermore, the thickness TK2 of the portion of the dielectric layer 124 not covered by the conductive layer 122 is less than the thickness TK1 of the portion covered by the conductive layer 122. Furthermore, the bottom surface 122b of the conductive layer 122 is higher than the top surface 124a of the dielectric layer 124. According to some embodiments of the present invention, the curved profile of the sidewall 122s of the conductive layer 122 and the concave profile of the top surface 124a of the dielectric layer 124 can be continuously connected.

[0062] In some embodiments, the etching step E1 may be adjusted so that the recess RS of the stepped structure 160 has different depths according to its distance from the substrate 100 (for example, the depths defined by the top angle P1 are used for comparison). Figure 8In the lower figure, as described above, the step structure 160 can be formed by two mask layer trimming-etching processes, wherein the recess RS1-1 and the recess RS1-2 can be formed by using the mask layer 140 (refer to Figure 2-4 ) is formed by the trimming-etching process, the recess RS2-1 and the recess RS2-2 can be formed by using the mask layer 150 (refer to Figure 5-7 ) is formed by a trimming-etching process using the mask layer 140. In the trimming-etching process using the mask layer 140, the etching step E1 can be adjusted so that the recess closer to the substrate 100 has a smaller depth, that is, the depth of the recess RS1-1 is smaller than the depth of the recess RS1-2. Similarly, in the trimming-etching process using the mask layer 150, the etching step E1 can be adjusted so that the recess closer to the substrate 100 has a smaller depth, that is, the depth of the recess RS2-1 is smaller than the depth of the recess RS2-2. In other embodiments, when the recesses RS2-1, RS2-2, RS1-1 and RS1-2 are formed by a trimming-etching process using the same mask layer, the recess RS2-1 closest to the substrate 100 may have the smallest depth, and the recess RS1-2 farthest from the substrate 100 may have the largest depth.

[0063] Please refer to Figure 9 . Then, a thin film deposition process may be performed to form an insulating layer 162 on the storage stack structure 120 to cover the top surface of the storage stack structure 120 and the stepped structure 160, and to be in direct contact with the sidewalls 122s of the conductive layer 122, the sidewalls 124s of the dielectric layer 124 and the top surface 124a of the dielectric layer 124 of each step ST. Preferably, the thickness of the insulating layer 162 is greater than the depth of the recess RS to fill each recess RS. Next, an interlayer dielectric layer 164 is formed to fully cover the substrate 100 and mask the storage stack structure 120, and then a planarization process (such as a chemical mechanical polishing process) is performed to remove part of the interlayer dielectric layer 164 until the insulating layer 162 on the top surface of the storage stack structure 120 is exposed, thereby obtaining a flat surface to facilitate the subsequent fabrication of an electrical connection structure on the storage stack structure 120 and the interlayer dielectric layer 164. The insulating layer 162 and the interlayer dielectric layer 164 may each comprise a dielectric material, such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. According to one embodiment of the present invention, the insulating layer 162 and the interlayer dielectric layer 164 comprise different dielectric materials. For example, the insulating layer 162 may comprise silicon nitride, while the interlayer dielectric layer 164 may comprise silicon oxide. Furthermore, the insulating layer 162 may serve as a polishing stop layer during the chemical mechanical polishing process for the interlayer dielectric layer 164.

[0064] Please refer to Figure 10Then, conventional semiconductor fabrication processes such as patterning (e.g., lithography and etching), etching, thin film deposition, and planarization can be used to form a plurality of word line contact plugs 166 that penetrate the interlayer dielectric layer 164, the insulating layer 162, and the dielectric layer 124 and directly contact and electrically connect to the conductive layer 122 of one step ST of the staircase structure 160. The word line contact plugs 166 may comprise a conductive material such as, but not limited to, aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium-tungsten (Ti / W), titanium-titanium nitride (Ti / TiN), polysilicon, doped silicon, silicide, or other metal or non-metal conductive materials, or any combination thereof. According to one embodiment of the present invention, the word line contact plugs 166 comprise tungsten (W).

[0065] In summary, the three-dimensional memory device provided by the present invention is a memory stack structure 120 comprising alternately stacked conductive layers 122 and dielectric layers 124, which is trimmed and etched to form a staircase structure 160. A step ST having a nose portion 124n (i.e., the edge portion of the dielectric layer 124) can be produced. If alignment deviation occurs (e.g., Figure 10 The step nose portion 124n can provide an additional etching barrier to reduce the defect of short circuit between the word line contact plug 166 and the conductive layer 122 of the upper step ST.

[0066] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A three-dimensional memory device, characterized in that: include: A substrate comprising a first region and a second region; a liner layer disposed between the substrate and the memory stack structure; and The memory stack structure includes a plurality of alternating conductive layers and dielectric layers, and is disposed on the substrate and extends from the first region to the second region. The memory stack structure on the second region includes a stepped structure, wherein the steps of the stepped structure each include a conductive layer and a dielectric layer. The sidewalls of the conductive layer are recessed from the sidewalls of the dielectric layer to form a depression, exposing a portion of the bottom surface of the dielectric layer. The portion of the dielectric layer that protrudes from the sidewalls of the conductive layer in a direction parallel to the substrate surface constitutes a step nose. A plurality of word line contact plugs pass through the dielectric layer and directly contact the conductive layer, wherein one of the word line contact plugs contacts the top surface of the conductive layer of one step of the stair structure and contacts the top surface of the nose portion of the upper step at the same time.

2. The three-dimensional memory device according to claim 1, wherein: The sidewall of the conductive layer has a curved profile.

3. The three-dimensional memory device according to claim 1, wherein: An angle between the sidewall of the conductive layer and a top surface of the conductive layer is greater than 90 degrees.

4. The three-dimensional memory device according to claim 1, wherein: A top surface of the dielectric layer not covered by the conductive layer has a concave profile.

5. The three-dimensional memory device according to claim 1, wherein: The thickness of a portion of the dielectric layer not covered by the conductive layer is smaller than the thickness of a portion of the dielectric layer covered by the conductive layer.

6. The three-dimensional memory device according to claim 1, wherein: Also includes: an interlayer dielectric layer, disposed on the stepped structure; as well as A plurality of word line contact plugs pass through the interlayer dielectric layer and the dielectric layer and are respectively in direct contact with one of the conductive layers.

7. The three-dimensional memory device according to claim 6, wherein: The method further includes an insulating layer disposed between the stepped structure and the interlayer dielectric layer, wherein the insulating layer is in direct contact with the sidewalls of the conductive layer, the sidewalls of the dielectric layer, and a top surface of the dielectric layer.

8. The three-dimensional memory device according to claim 7, wherein: The thickness of the insulating layer is greater than the depth of the recess of the step so as to fill the recess.

9. The three-dimensional memory device according to claim 1, wherein: The depth of the recess of the step closest to the substrate is smaller than the depth of the recess of the step farthest from the substrate.

10. The three-dimensional memory device according to claim 1, wherein: It also includes a plurality of channel structures, which are arranged in the storage stack structure on the first area.

11. A method for manufacturing a three-dimensional memory device, characterized in that: include: providing a substrate comprising a first region and a second region; forming a memory stack structure comprising a plurality of conductive layers and a plurality of dielectric layers alternately stacked on the substrate, the memory stack structure extending from the first region to the second region; as well as performing a trim-etch process to form a staircase structure in the memory stack structure on the second region, wherein the steps of the staircase structure respectively include the conductive layer and the dielectric layer, and the sidewall of the conductive layer is recessed from the sidewall of the dielectric layer to form a recess, exposing a portion of the bottom surface of the dielectric layer, and the portion of the dielectric layer protruding from the sidewall of the conductive layer in a direction parallel to the substrate surface constitutes a nose portion of the step; A plurality of word line contact plugs are formed to pass through the dielectric layer and directly contact the conductive layer, wherein one of the word line contact plugs contacts the top surface of the conductive layer of one step of the stair structure and contacts the top surface of the nose portion of the upper step.

12. The method for manufacturing a three-dimensional memory device according to claim 11, wherein: The trim-etch process includes: Step a, forming a mask layer on the memory stack structure; Step b, etching the memory stack structure using the mask layer as an etching mask to obtain a step of the staircase structure, wherein the step includes a layer of the dielectric layer and a layer of the conductive layer; Step c, trimming the mask layer to expose a portion of the top surface of the dielectric layer at the step; and Step d, looping steps b and c to obtain multiple steps of the stair structure.

13. The method for manufacturing a three-dimensional memory device according to claim 11, wherein: The sidewall of the conductive layer has a curved profile.

14. The method for manufacturing a three-dimensional memory device according to claim 11, wherein: An angle between the sidewall of the conductive layer and a top surface of the conductive layer is greater than 90 degrees.

15. The method for manufacturing a three-dimensional memory device according to claim 11, wherein: A top surface of the dielectric layer not covered by the conductive layer has a concave profile.

16. The method for manufacturing a three-dimensional memory device according to claim 11, wherein: The thickness of a portion of the dielectric layer not covered by the conductive layer is smaller than the thickness of a portion of the dielectric layer covered by the conductive layer.

17. The method for manufacturing a three-dimensional memory device according to claim 11, wherein: Also includes: forming an interlayer dielectric layer on the stepped structure; as well as A plurality of word line contact plugs are formed, passing through the interlayer dielectric layer and the dielectric layer, and respectively directly contacting one of the conductive layers.

18. The method for manufacturing a three-dimensional memory device according to claim 17, wherein: The method further includes forming an insulating layer on the stepped structure before forming the interlayer dielectric layer, wherein the insulating layer is in direct contact with the sidewalls of the conductive layer, the sidewalls of the dielectric layer, and a top surface of the dielectric layer.

19. The method for manufacturing a three-dimensional memory device according to claim 18, wherein: The thickness of the insulating layer is greater than the depth of the recess of the step so as to fill the recess.

20. The method for manufacturing a three-dimensional memory device according to claim 11, wherein: The depth of the recess of the step closest to the substrate is smaller than the depth of the recess of the step farthest from the substrate.

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