Display panel and its manufacturing method

Abstract

A display panel and its manufacturing method are disclosed. The display panel includes a fingerprint recognition layer, an optical path layer, and a display panel body. The fingerprint recognition layer includes an array of transistors and a plurality of photosensors electrically connected to the transistors. The active layer patterns of the transistors and the photosensitive layer patterns of the photosensors are disposed in the same layer. This application saves on photomasks and fabrication processes because the amorphous silicon film layers of the transistors and photosensors can be fabricated in the same process.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and a method for manufacturing the same. Background Technology

[0002] Fingerprint recognition technology has been widely used in small and medium-sized panels. Among them, fingerprint recognition technology mainly includes capacitive, ultrasonic and optical methods.

[0003] Currently, the most mature solution is capacitive fingerprint recognition, which works by using a silicon wafer and a conductive subcutaneous electrolyte to create an electric field. The varying heights of the fingerprint ridges create different voltage differences, thus achieving accurate fingerprint measurement. However, with capacitive fingerprint recognition, when the finger is wet, the electrical properties change, and the detection performance significantly deteriorates.

[0004] Ultrasonic fingerprint recognition technology has advantages over capacitive fingerprint recognition, such as higher penetration, greater stability, and higher accuracy, but its cost is relatively higher. Optical fingerprint recognition technology utilizes the principles of light refraction and reflection. When light shines on a finger, it is reflected by the finger onto a light sensor, which then converts the light signal into an electrical signal. Because the valleys and ridges of a fingerprint reflect light differently, the light intensity received by the light sensor differs from that of the valleys and ridges, thus using different electrical signals for fingerprint recognition.

[0005] Optical fingerprint recognition technology offers good stability, strong penetration, and relatively low manufacturing costs. Currently, mobile phones and tablets equipped with optical fingerprint recognition use self-emissive organic light-emitting diode (OLED) screens. However, for mobile phones with liquid crystal display (LCD) screens, the presence of a backlight module and limitations imposed by factors such as aperture ratio during manufacturing increase the difficulty of integrating optical fingerprint recognition functionality within the LCD screen. Summary of the Invention

[0006] To address the aforementioned technical problems, this application provides a display panel and a method for manufacturing the same.

[0007] For the purposes described above, this application provides a display panel comprising:

[0008] Fingerprint recognition layer;

[0009] An optical path layer is disposed on the fingerprint recognition layer; and

[0010] The main body of the display panel is disposed on the optical path layer, wherein

[0011] The fingerprint recognition layer includes an array of transistors and a plurality of optical sensors electrically connected to the transistors.

[0012] The active layer pattern of the transistor and the photosensitive layer pattern of the photosensitive sensor are arranged on the same layer.

[0013] In embodiments of this application, the fingerprint recognition layer further includes a first metal layer and a first transparent conductive layer. The first metal layer and the first transparent conductive layer are disposed on the same layer. The first metal layer includes the gate pattern of the transistor, and the first transparent conductive layer includes the lower electrode pattern of the light sensor.

[0014] In embodiments of this application, the fingerprint recognition layer further includes a substrate layer, a first metal layer, and a first transparent conductive layer. The first metal layer and the first transparent conductive layer are both disposed on the surface of the substrate layer, and the optical path layer is disposed on another surface of the substrate layer. The first metal layer includes the gate pattern of the transistor, and the first transparent conductive layer includes the lower electrode pattern of the photosensitive sensor.

[0015] In an embodiment of this application, the fingerprint recognition layer further includes a gate insulating layer covering the surface of the first metal layer and the first transparent conductive layer, and the gate insulating layer has a first through hole corresponding to each of the lower electrode patterns, and the photosensitive layer pattern is disposed in the first through hole.

[0016] In an embodiment of this application, the active layer pattern is disposed on the surface of the gate insulating layer away from the first metal layer and corresponds to the gate pattern, wherein the orthogonal projection of the active layer pattern on the substrate layer falls within the orthogonal projection of the gate pattern on the substrate layer.

[0017] In embodiments of this application, the fingerprint recognition layer further includes an N+ amorphous silicon layer and a second metal layer. The second metal layer is disposed on the surface of the N+ amorphous silicon layer. The second metal layer includes the source / drain pattern of the transistor and the upper electrode pattern of the photosensitive sensor. The N+ amorphous silicon layer includes an ohmic contact layer pattern located between the source / drain pattern and the active layer pattern, and an ohmic contact layer pattern located between the upper electrode pattern and the photosensitive layer pattern.

[0018] In embodiments of this application, the source or drain of the transistor is connected to the lower electrode pattern through a second via on the gate insulating layer.

[0019] In embodiments of this application, the fingerprint recognition layer further includes a second transparent conductive layer disposed on the surface of the second metal layer away from the N+ amorphous silicon layer.

[0020] In embodiments of this application, the fingerprint recognition layer further includes a bonding terminal, the first metal layer further includes a wiring pattern of the bonding terminal, the first transparent conductive layer further includes a transparent conductive pattern of the bonding terminal, the transparent conductive pattern covering the wiring pattern, the second metal layer further includes a pad pattern of the bonding terminal, the pad pattern being connected to the transparent conductive pattern through a third via on the gate insulating layer, and the second transparent conductive layer further includes a protective pattern of the bonding terminal, the protective pattern covering the pad pattern.

[0021] This application also provides a method for manufacturing a display panel, comprising:

[0022] Provide substrate layer;

[0023] A first metal layer is disposed on the first surface of the substrate layer and the first metal layer is patterned to form a gate pattern.

[0024] A first transparent conductive layer is disposed on the first surface of the substrate layer and the first transparent conductive layer is patterned to form a lower electrode pattern.

[0025] A gate insulating layer is disposed on the first metal layer and the first transparent conductive layer, and the gate insulating layer is patterned to form a first via corresponding to the lower electrode pattern;

[0026] An amorphous silicon layer is disposed on the gate insulating layer;

[0027] An N+ type amorphous silicon layer is disposed on the amorphous silicon layer and the N+ type amorphous silicon layer and the amorphous silicon layer are patterned to form an active layer pattern corresponding to the gate pattern, a photosensitive layer pattern located in the first via, an ohmic contact layer pattern located on the active layer pattern, and an ohmic contact layer pattern located on the photosensitive layer pattern.

[0028] A second metal layer is disposed on the N+ type amorphous silicon layer and the second metal layer is patterned to form a source / drain pattern corresponding to the active layer pattern and an upper electrode pattern corresponding to the photosensitive layer pattern.

[0029] An insulating protective layer is disposed on the second metal layer;

[0030] The substrate layer is inverted and an optical path layer is formed on a second surface of the substrate layer, wherein the second surface is the surface of the substrate layer away from the amorphous silicon layer; and

[0031] The main body of the display panel is disposed on the optical path layer.

[0032] In the display panel and manufacturing method provided in this application, compared with the prior art, due to the inverted position of the photosensor, the transistor and the photosensor are made of amorphous silicon (a-Si) or N+ type amorphous silicon (N+ type amorphous silicon). + The a-Si film can be fabricated in the same process, thus saving on photomasks and fabrication processes. In addition, the fingerprint recognition layer of this application is flipped and bonded to the optical path layer, so the gate of the transistor can also be used as a light-shielding layer, overcoming the problem of integrating optical fingerprint recognition function inside the above-mentioned liquid crystal screen. Attached Figure Description

[0033] Figure 1 This is a first schematic diagram illustrating the manufacturing process of the display panel of this application.

[0034] Figure 2 This is a second schematic diagram illustrating the manufacturing process of the display panel of this application.

[0035] Figure 3 This is a third schematic diagram illustrating the manufacturing process of the display panel of this application.

[0036] Figure 4 This is a fourth schematic diagram illustrating the manufacturing process of the display panel of this application.

[0037] Figure 5 This is the fifth schematic diagram illustrating the manufacturing process of the display panel of this application.

[0038] Figure 6 This is the sixth schematic diagram illustrating the manufacturing process of the display panel of this application.

[0039] Figure 7 This is the seventh schematic diagram illustrating the manufacturing process of the display panel of this application.

[0040] Figure 8 This is the eighth schematic diagram illustrating the manufacturing process of the display panel of this application.

[0041] Figure 9 This is the ninth schematic diagram illustrating the manufacturing process of the display panel of this application.

[0042] Figure 10 This is the tenth schematic diagram illustrating the manufacturing process of the display panel of this application.

[0043] Figure 11 This is a schematic diagram of the display panel structure of this application.

[0044] Figure 12 This is a schematic diagram of the manufacturing method of the display panel of this application. Detailed Implementation

[0045] To make the above and other objects, features, and advantages of this application more apparent and understandable, preferred embodiments of this application will be described in detail below with reference to the accompanying drawings. Furthermore, the directional terms used in this application, such as up, down, top, bottom, front, back, left, right, inner, outer, side layer, surrounding, center, horizontal, transverse, vertical, longitudinal, axial, radial, uppermost, or lowermost, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for the purpose of explaining and understanding this application, and not for limiting this application.

[0046] In the diagram, units with similar structures are represented by the same labels.

[0047] Please see Figure 9 and Figure 11 This application provides a display panel 10, which includes:

[0048] A fingerprint recognition layer 100; an optical path layer 200 disposed on the fingerprint recognition layer 100; and a display panel body 300 disposed on the optical path layer 200, wherein the fingerprint recognition layer 100 includes a plurality of transistors A(t) arranged in an array. Figure 9 (Only one transistor is shown as an example) and multiple optical sensors B electrically connected to the multiple transistors A respectively. Figure 9 (Only one photosensitive sensor is shown as an example); the active layer pattern 105a of the transistor A and the photosensitive layer pattern 105b of the photosensitive sensor B are arranged on the same layer.

[0049] Specifically, the active layer pattern 105a of transistor A and the photosensitive layer pattern 105b of photosensor B are both made of amorphous silicon. Specifically, the fingerprint recognition layer 100 further includes an amorphous silicon layer 105, which includes the active layer pattern 105a of transistor A and the photosensitive layer pattern 105b of photosensor B.

[0050] Specifically, the display panel 10 of this application includes a fingerprint recognition layer 100, an optical path layer 200, and a display panel body 300. The display panel 10 can be a device with touch and display functions, such as a mobile phone, tablet computer, touch screen, smart wearable device, etc. The fingerprint recognition layer 100 includes an optical fingerprint recognition component. The display panel body 300 can be an organic light-emitting diode display panel, a liquid crystal display panel, or other display panels, and is not limited thereto.

[0051] To further explain, the fingerprint recognition layer 100 of the display panel 10 includes a substrate layer 101, a first metal layer 102, a first transparent conductive layer 103, a gate insulating layer 104, an amorphous silicon layer 105, an N+ type amorphous silicon layer 106, a second metal layer 107, a second transparent conductive layer 108, and an insulating protective layer 109.

[0052] In one embodiment, the fingerprint recognition circuit of the fingerprint recognition layer 100 includes a transistor A, and the optical sensor B includes a PIN sensor.

[0053] In one embodiment, the substrate layer 101 is made of a transparent material, such as glass. In other embodiments, if the fingerprint recognition layer 100 is to be applied to a flexible display panel 10, the substrate layer 101 may be made of a flexible transparent material, such as polyimide.

[0054] The first metal layer 102 can be disposed on the first surface S1 of the substrate layer 101 and can serve as the gate 102a of the transistor A.

[0055] In the embodiments of this application, the fingerprint recognition layer 100 further includes a first metal layer 102 and a first transparent conductive layer 103. The first metal layer 102 and the first transparent conductive layer 103 are disposed in the same layer. The first metal layer 102 includes the gate pattern 102a of the transistor A, and the first transparent conductive layer 103 includes the lower electrode pattern 103b of the photosensitive sensor B.

[0056] Further explanation: the first metal layer 102 can be a single-layer film formed of an opaque metal with good conductivity, such as molybdenum, tungsten, copper, titanium, or aluminum. In another embodiment, such as... Figure 2 As shown, the first metal layer 102 can also be a stacked first metal film layer 1021 and a second metal film layer 1022 formed of metals with good conductivity such as molybdenum, tungsten, copper, titanium, and aluminum. For example, the first metal film layer 1021 and the second metal film layer 1022 can be a stacked structure formed of molybdenum and tungsten, or molybdenum and copper. For example, the first metal film layer 1021 is made of molybdenum, and the second metal film layer 1022 is made of tungsten. In other embodiments, such as Figure 3 As shown, the first metal film layer 1021, the second metal film layer 1022, and the third metal film layer 1023 can be a stacked structure formed of titanium and aluminum. For example, the first metal film layer 1021 is made of titanium, the second metal film layer 1022 is made of aluminum, and the third metal film layer 1023 is made of titanium.

[0057] Specifically, such as Figure 4 As shown, a first transparent conductive layer 103 can be disposed on the first surface S1 of the substrate layer 101, and a portion of the first transparent conductive layer 103 (103a) covers a portion of the first metal layer 102 (102b). In one embodiment, the first transparent conductive layer 103 can be made of indium tin oxide and can serve as the lower electrode of a photosensor, but is not limited thereto. The first transparent conductive layer 103 can also be made of other materials, such as tin oxide (SnO2), zinc oxide (ZnO), etc., without limitation. In addition, there is a gap between the orthographic projections of the lower electrode pattern 103b and the gate pattern 102a onto the substrate layer. Specifically, as... Figure 10 and Figure 11 As shown, the lower electrode pattern 103b is located between the photosensitive layer pattern 105b and the optical path layer 200, and the gate pattern 102a is located between the active layer pattern 105a and the optical path layer 200.

[0058] In embodiments of this application, the fingerprint recognition layer 100 further includes a gate insulating layer 104, covering the surfaces of the first metal layer 102 and the first transparent conductive layer 103. (See also...) Figure 6 and Figure 7 The gate insulating layer 104 has a first through-hole 1041 and a second through-hole 1044 corresponding to each of the lower electrode patterns 103b. The photosensitive layer pattern 105b is disposed in the first through-hole 1041. Specifically, the gate insulating layer 104 also has a third through-hole 1045 corresponding to the first transparent conductive layer 103 (103a).

[0059] Specifically, such as Figure 6 As shown, a gate insulating layer 104 may be disposed on a first metal layer 102 and a first transparent conductive layer 103, and the first via 1041, the second via 1044, and the third via 1045 are defined on the gate insulating layer 104. In one embodiment, the gate insulating layer 104 includes one or more of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiNxOy), and the gate insulating layer 104 includes at least one film layer. Specifically, the gate insulating layer 104 may be a single-layer film, including only a first gate insulating film layer 1042, or it may be a double-layer film, including a first gate insulating film layer 1042 and a second gate insulating film layer 1043. The first gate insulating film layer 1042 and the second gate insulating film layer 1043 may be made of silicon nitride and silicon oxide, respectively, and form a stacked structure.

[0060] like Figure 9 As shown in the embodiments of this application, the fingerprint recognition layer 100 further includes an N+ amorphous silicon layer 106 and a second metal layer 107. The second metal layer 107 is disposed on the surface of the N+ amorphous silicon layer 106. The second metal layer 107 includes the source / drain pattern 107a of the transistor A and the upper electrode pattern 107b of the photosensitive sensor B. The N+ amorphous silicon layer 106 includes an ohmic contact layer pattern 106a located between the source / drain pattern 107a and the active layer pattern 105a, and an ohmic contact layer pattern 106b located between the upper electrode pattern 107b and the photosensitive layer pattern 105b.

[0061] Specifically, such as Figure 9As shown, in an embodiment of this application, the source / drain pattern 107a includes the source and drain of transistor A. An ohmic contact layer pattern 106a is disposed between the source and the active layer pattern 105a. An ohmic contact layer pattern 106a is also disposed between the drain and the active layer pattern 105a, but the two ohmic contact layer patterns 106a are not connected. Specifically, as... Figure 9 As shown, an ohmic contact layer pattern 106b may be disposed between the upper electrode pattern 107b and the photosensitive layer pattern 105b.

[0062] Specifically, such as Figure 6 , Figure 8 and Figure 9 As shown, in an embodiment of this application, the source or drain of transistor A is connected to the lower electrode pattern 103b through a second via 1044 on the gate insulating layer 104.

[0063] Specifically, such as Figure 6 , Figure 7 , Figure 8 and Figure 9 As shown, an amorphous silicon layer 105 can be disposed on the gate insulating layer 104, and an N+ type amorphous silicon layer 106 is disposed on the amorphous silicon layer 105. Specifically, a portion of the amorphous silicon layer 105 is disposed in the first via 1041 to serve as the photosensitive layer pattern 105b of the photosensor B; another portion of the amorphous silicon layer 105 is disposed on the gate insulating layer 104 and corresponds to the gate pattern 102a to serve as the active layer pattern 105a of the transistor A. A portion of the N+ type amorphous silicon layer 106 is disposed on the photosensitive layer pattern 105b to serve as the ohmic contact layer pattern 106b between the upper electrode pattern 107b and the photosensitive layer pattern 105b. Another portion of the N+ type amorphous silicon layer 106 is disposed on the active layer pattern 105a to serve as the ohmic contact layer pattern 106a between the source / drain pattern 107a and the active layer pattern 105a. In this embodiment, the N+ type amorphous silicon layer 106 is used as an ohmic contact layer between the semiconductor layer and the metal layer to reduce the impedance between the semiconductor layer and the metal layer.

[0064] In another embodiment, the active layer pattern 105a is disposed on the surface of the gate insulating layer 104 away from the first metal layer 102 and corresponds to the gate pattern 102a. The orthographic projection of the active layer pattern 105a on the substrate layer 101 falls within the orthographic projection of the gate pattern 102a on the substrate layer 101. Therefore, the gate pattern 102a can also serve as a light-blocking function, preventing the threshold voltage of the active layer pattern 105a from being affected by ambient light.

[0065] Specifically, such as Figure 8 and Figure 9 As shown, the second metal layer 107 can be disposed on the N+ type amorphous silicon layer 106. After the second metal layer 107 is formed, the source / drain pattern 107a of transistor A can be formed by a patterning process. In the photosensitive sensor B, the second metal layer 107 can serve as the upper electrode pattern 107b of the photosensitive sensor.

[0066] In addition, such as Figure 8 As shown, in one embodiment, the fingerprint recognition layer 100 further includes a second transparent conductive layer 108 disposed on the surface of the second metal layer 107 away from the N+ amorphous silicon layer 106.

[0067] Specifically, the second transparent conductive layer 108 can be disposed on the second metal layer 107 to prevent the second metal layer 107 from oxidizing and thus avoid affecting subsequent bonding with other devices. The second transparent conductive layer 108 can also serve as a circuit trace within the fingerprint recognition layer 100. In one embodiment, the second transparent conductive layer 108 can also be used as the upper electrode of the light sensor, instead of the second metal layer 107.

[0068] like Figure 9 As shown, the insulating protective layer 109 can be disposed on the second metal layer 107, and a fourth through hole 1091 can be formed on the insulating protective layer 109. In one embodiment, an integrated circuit, such as a control chip or a driver chip, can be bonded to the bonding terminal C of the fingerprint recognition layer 100 through the fourth through hole 1091.

[0069] like Figure 9 , Figure 10 and Figure 11 As shown, the optical path layer 200 can be disposed on the second surface S2 of the substrate layer 101, and the first surface S1 and the second surface S2 are different surfaces. Specifically, the optical path layer 200 can be disposed on the second surface S2 of the substrate layer 101, and the first surface S1 and the second surface S2 are different surfaces. Figure 9 The fingerprint recognition layer 100 shown is flipped, as... Figure 10 As shown. Next, the optical path layer 200 is disposed on the second surface S2 of the substrate layer 101. In other words, the optical path layer 200 and the film layer on the substrate layer 101 are disposed opposite each other. Specifically, the optical path layer 200 can guide the reflected light from the fingerprint into the fingerprint recognition layer 100, and the optical path layer 200 may include a light guide structure or an aperture array structure. In addition, the optical path layer 200 can be configured according to the sensing light source of the fingerprint recognition layer 100. For example, the sensing light source of the fingerprint recognition layer 100 can be disposed on the side of the optical path layer 200 or on the bottom of the fingerprint recognition layer 100. The light sensor of the fingerprint layer 100 also needs to be provided with a light-shielding structure to avoid malfunction. It can be configured according to actual needs.

[0070] like Figure 11As shown, the display panel body 300 can be disposed on the optical path layer 200 for display. Furthermore, the display panel body 300 includes, for example, a display substrate layer, a cathode layer, an anode layer, and display functional film layers. The film layers included in the display panel body 300 are configured according to the type of display panel body 300. Figure 11 It is not shown in the picture.

[0071] In this application, compared to the prior art, due to the inverted optical sensor, the transistor and the amorphous silicon (a-Si) film layer or N+ type amorphous silicon (N+) film layer of the optical sensor are... + The a-Si film can be fabricated in the same process, thus saving on photomasks and fabrication processes. In addition, the fingerprint recognition layer 100 of this application is flipped and bonded to the optical path layer, so the gate of the transistor can also be used as a light-shielding layer, overcoming the problem of integrating optical fingerprint recognition function inside the above-mentioned liquid crystal screen.

[0072] like Figure 7 and Figure 9 As shown in the embodiments of this application, the fingerprint recognition layer 100 further includes a bonding terminal C, the first metal layer 102 further includes a wiring pattern 102b of the bonding terminal C, the first transparent conductive layer 103 further includes a transparent conductive pattern 103a of the bonding terminal C, the transparent conductive pattern 103a covers the wiring pattern 102b, the second metal layer 107 further includes a pad pattern 107c of the bonding terminal C, the pad pattern 107c is connected to the transparent conductive pattern 103a through a third via 1045 on the gate insulating layer 104, and the second transparent conductive layer 108 further includes a protective pattern 108a of the bonding terminal C, the protective pattern 108a covers the pad pattern 107c.

[0073] like Figure 12 As shown, this application also provides a method for manufacturing a display panel, comprising:

[0074] S101: Provides substrate layer 101;

[0075] S102: A first metal layer 102 is disposed on the first surface S1 of the substrate layer 101 and the first metal layer 102 is patterned to form a gate pattern 102a;

[0076] S103: A first transparent conductive layer 103 is disposed on the first surface S1 of the substrate layer 101 and the first transparent conductive layer 103 is patterned to form a lower electrode pattern 103b.

[0077] S104: A gate insulating layer 104 is disposed on the first metal layer 102 and the first transparent conductive layer 103, and the gate insulating layer 104 is patterned to form a first through hole 1041 corresponding to the lower electrode pattern 103b.

[0078] S105: An amorphous silicon layer 105 is disposed on the gate insulating layer 104;

[0079] S106: An N+ type amorphous silicon layer 106 is disposed on the amorphous silicon layer 105 and the N+ type amorphous silicon layer 106 and the amorphous silicon layer 105 are patterned to form an active layer pattern 105a corresponding to the gate pattern 102a, a photosensitive layer pattern 105b located in the first via 1041, an ohmic contact layer pattern 106a located on the active layer pattern 105a, and an ohmic contact layer pattern 106b located on the photosensitive layer pattern 105b;

[0080] S107: A second metal layer 107 is disposed on the N+ type amorphous silicon layer 106 and the second metal layer 107 is patterned to form a source / drain pattern 107a corresponding to the active layer pattern 105a and an upper electrode pattern 107b corresponding to the photosensitive layer pattern 105b.

[0081] S108: An insulating protective layer 109 is disposed on the second metal layer 107;

[0082] S109: Invert the substrate layer 101 and form an optical path layer 200 on the second surface S2 of the substrate layer 101, wherein the second surface S2 is the surface of the substrate layer 101 away from the amorphous silicon layer 105; and

[0083] S110: A display panel body 300 is disposed on the optical path layer 200.

[0084] The manufacturing method of the display panel 10 in this application is described in detail below. The manufacturing method of the display panel 10 includes the following steps.

[0085] like Figure 1 As shown, in step S101: a substrate layer 101 is provided. The substrate layer 101 is made of a transparent material, such as glass. In other embodiments, if the fingerprint recognition layer 100 is to be applied to a flexible display panel 10, the substrate layer 101 may be made of a flexible transparent material, such as polyimide.

[0086] like Figure 1 As shown, in step S102: a first metal layer 102 is deposited on the first surface S1 of the substrate layer 101. The metal film layer can be formed on the first surface S1 of the substrate layer 101 through processes such as deposition, exposure, and etching. Whether to form multiple film layers can be adjusted according to actual needs.

[0087] like Figure 2 and Figure 3 As shown, further illustrating, the first metal layer 102 can be a single-layer film formed of an opaque metal with good conductivity, such as molybdenum, tungsten, copper, titanium, or aluminum. In another embodiment, as... Figure 2 As shown, the first metal layer 102 can also be a stacked first metal film layer 1021 and a second metal film layer 1022 formed of metals with good conductivity such as molybdenum, tungsten, copper, titanium, and aluminum. For example, the first metal film layer 1021 and the second metal film layer 1022 can be a stacked structure formed of molybdenum and tungsten, or molybdenum and copper. For example, the first metal film layer 1021 is made of molybdenum, and the second metal film layer 1022 is made of tungsten. In other embodiments, such as Figure 3 As shown, the first metal film layer 1021, the second metal film layer 1022, and the third metal film layer 1023 can be a stacked structure formed of titanium and aluminum. For example, the first metal film layer 1021 is made of titanium, the second metal film layer 1022 is made of aluminum, and the third metal film layer 1023 is made of titanium.

[0088] like Figure 4 As shown, in step S103: a first transparent conductive layer 103 is disposed on the first surface S1 of the substrate layer 101 and on a portion of the first metal layer 102 (102b). In one embodiment, the first transparent conductive layer 103 may be disposed on the first surface S1 of the substrate layer 101 and on a portion of the first metal layer 102 (102b) by coating.

[0089] In one embodiment, the first transparent conductive layer 103 may be made of indium tin oxide and may serve as the lower electrode of the photosensor, but is not limited thereto. The first transparent conductive layer 103 may also be made of other materials, such as tin oxide (SnO2), zinc oxide (ZnO), etc., and is not limited thereto.

[0090] like Figure 5 and Figure 6 As shown, in step S104: a gate insulating layer 104 is deposited on the first metal layer 102 and the first transparent conductive layer 103. The gate insulating layer 104 can be formed by depositing a single material or by forming a gate insulating layer 104 with a stacked structure, depending on actual needs.

[0091] In one embodiment, the gate insulating layer 104 includes one or more of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiNxOy), and the gate insulating layer 104 includes at least one film layer. Specifically, the gate insulating layer 104 may be a single-layer film, including only a first gate insulating film layer 1042, or it may be a double-layer film, including a first gate insulating film layer 1042 and a second gate insulating film layer 1043. The first gate insulating film layer 1042 and the second gate insulating film layer 1043 may be made of silicon nitride and silicon oxide, respectively, and form a stacked structure.

[0092] like Figure 5 and Figure 6 As shown, in step S104: the gate insulating layer 104 is patterned to form a first via 1041 corresponding to the lower electrode pattern 103b. The first via 1041 can be defined on the gate insulating layer 104 by etching.

[0093] like Figure 7 As shown, in step S105: an amorphous silicon layer 105 is deposited on the gate insulating layer 104. Specifically, the amorphous silicon layer 105 can be fabricated using vapor deposition of an amorphous silicon film, including methods such as vacuum evaporation, glow discharge, sputtering, and chemical vapor deposition.

[0094] like Figure 7 As shown, in step S106: an N+ type amorphous silicon layer 106 is deposited on the amorphous silicon layer 105. Specifically, after the deposition of the amorphous silicon layer 105 is completed in step S105, a high concentration of ion implantation is performed on the amorphous silicon layer 105 to form the N+ type amorphous silicon layer 106. Specifically, the N-type impurity is, for example, phosphorus.

[0095] Next, the N+ type amorphous silicon layer 106 and the amorphous silicon layer 105 are patterned to form an active layer pattern 105a corresponding to the gate pattern 102a, a photosensitive layer pattern 105b located in the first via 1041, an ohmic contact layer pattern 106a located on the active layer pattern 105a, and an ohmic contact layer pattern 106b located on the photosensitive layer pattern 105b.

[0096] In other words, the amorphous silicon layer 105 and the N+ type amorphous silicon layer 106 form the active layer pattern 105a, the photosensitive layer pattern 105b, and the ohmic contact layer patterns 106a and 106b in a single process, thereby reducing the photomask and fabrication process.

[0097] like Figure 8As shown, in step S107: a second metal layer 107 is deposited on the N+ type amorphous silicon layer 106 by means of vapor deposition or the like. After the second metal layer 107 is formed, the second metal layer 107 is patterned by means of exposure, development and etching to form a source / drain pattern 107a corresponding to the active layer pattern 105a and an upper electrode pattern 107b corresponding to the photosensitive layer pattern 105b.

[0098] like Figure 8 As shown, after step S107, the step may further include: depositing a second transparent conductive layer 108 on the second metal layer 107. In one embodiment, the deposition of the second transparent conductive layer 108 may be omitted to save on the fabrication process. Details regarding the second transparent conductive layer 108 can be found in the foregoing description and will not be repeated here. Figure 9 As shown, in step S108: an insulating protective layer 109 is disposed on the second metal layer 107 or the second transparent conductive layer 108.

[0099] like Figure 9 As shown, a fourth via 1091 can be formed on the insulating protective layer 109 by means of etching or other methods for bonding of integrated circuits.

[0100] like Figure 10 As shown, in step S109: the substrate layer 101 is inverted.

[0101] like Figure 11 As shown, the optical path layer 200 is disposed on the second surface S2 of the substrate layer 101. The first surface S1 and the second surface S2 of the substrate layer 101 are different surfaces. Specifically, the second surface S2 is the surface of the substrate layer 101 that is furthest from the amorphous silicon layer 105. In other words, the optical path layer 200 is disposed opposite to other film layers disposed on the substrate layer 101, but this is not a limitation and can be configured according to actual needs.

[0102] like Figure 11 As shown, in step S110: the display panel body 300 is disposed on the optical path layer 200. After step S110, bonding processes, testing processes, etc. may also be included.

[0103] Therefore, in summary, in the display panel 10 and its manufacturing method provided in this application, compared with the prior art, due to the inverted photosensor, the transistor and the a-Si or N-type photosensor are... + The a-Si film can be fabricated in the same process, thus saving on photomasks and fabrication processes. In addition, the fingerprint recognition layer 100 of this application is flipped and bonded to the optical path layer 200, so the gate of the transistor can also be used as a light-shielding layer.

[0104] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the function in the exemplary implementations shown in this specification. Furthermore, although a particular feature of this specification has been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of other implementations that may be desirable and advantageous for a given or particular application. Moreover, with respect to the use of the terms “comprising,” “having,” “containing,” or variations thereof in the embodiment or claims, such terms are intended to be included in a manner similar to the term “including.”

[0105] The above are merely preferred embodiments of this application. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A display panel, characterized in that, include: Fingerprint recognition layer; An optical path layer is disposed on the fingerprint recognition layer; as well as The main body of the display panel is disposed on the optical path layer, wherein... The fingerprint recognition layer includes an array of transistors and a plurality of optical sensors electrically connected to the transistors. The active layer pattern of the transistor and the photosensitive layer pattern of the photosensitive sensor are disposed on the same layer. The fingerprint recognition layer further includes a substrate layer, a first metal layer, and a first transparent conductive layer. The first metal layer and the first transparent conductive layer are both disposed on the surface of the substrate layer. The optical path layer is disposed on another surface of the substrate layer. The active layer pattern is disposed on the side of the first metal layer away from the optical path layer. The first transparent conductive layer is light-transmitting. The optical path layer is disposed on the side of the substrate layer close to the display panel body. The first metal layer and the first transparent conductive layer are disposed in the same layer. The first metal layer includes the gate pattern of the transistor, and the first transparent conductive layer includes the lower electrode pattern of the light sensor.

2. The display panel as described in claim 1, characterized in that, The fingerprint recognition layer further includes a gate insulating layer covering the surface of the first metal layer and the first transparent conductive layer, and the gate insulating layer has a first through hole corresponding to each of the lower electrode patterns, and the photosensitive layer pattern is disposed in the first through hole.

3. The display panel as described in claim 2, characterized in that, The active layer pattern is disposed on the surface of the gate insulating layer away from the first metal layer and corresponds to the gate pattern, wherein the orthogonal projection of the active layer pattern on the substrate layer falls within the orthogonal projection of the gate pattern on the substrate layer.

4. The display panel as described in claim 2, characterized in that, The fingerprint recognition layer further includes an N+ amorphous silicon layer and a second metal layer. The second metal layer is disposed on the surface of the N+ amorphous silicon layer. The second metal layer includes the source / drain pattern of the transistor and the upper electrode pattern of the photosensitive sensor. The N+ amorphous silicon layer includes an ohmic contact layer pattern located between the source / drain pattern and the active layer pattern, and an ohmic contact layer pattern located between the upper electrode pattern and the photosensitive layer pattern.

5. The display panel as described in claim 4, characterized in that, The source or drain of the transistor is connected to the lower electrode pattern through a second via on the gate insulating layer.

6. The display panel as described in claim 4, characterized in that, The fingerprint recognition layer further includes a second transparent conductive layer disposed on the surface of the second metal layer away from the N+ amorphous silicon layer.

7. The display panel as described in claim 6, characterized in that, The fingerprint recognition layer further includes a bonding terminal, the first metal layer further includes a wiring pattern of the bonding terminal, the first transparent conductive layer further includes a transparent conductive pattern of the bonding terminal, the transparent conductive pattern covers the wiring pattern, the second metal layer further includes a pad pattern of the bonding terminal, the pad pattern is connected to the transparent conductive pattern through a third via on the gate insulating layer, and the second transparent conductive layer further includes a protective pattern of the bonding terminal, the protective pattern covers the pad pattern.

8. A method for manufacturing a display panel, comprising preparing a display panel as described in any one of claims 1 to 7, wherein the method for preparing the display panel includes: Provide substrate layer; A first metal layer is disposed on the first surface of the substrate layer and the first metal layer is patterned to form a gate pattern. A first transparent conductive layer is disposed on the first surface of the substrate layer and the first transparent conductive layer is patterned to form a lower electrode pattern. A gate insulating layer is disposed on the first metal layer and the first transparent conductive layer, and the gate insulating layer is patterned to form a first via corresponding to the lower electrode pattern; An amorphous silicon layer is disposed on the gate insulating layer; An N+ type amorphous silicon layer is disposed on the amorphous silicon layer and the N+ type amorphous silicon layer and the amorphous silicon layer are patterned to form an active layer pattern corresponding to the gate pattern, a photosensitive layer pattern located in the first via, an ohmic contact layer pattern located on the active layer pattern, and an ohmic contact layer pattern located on the photosensitive layer pattern. A second metal layer is disposed on the N+ type amorphous silicon layer and the second metal layer is patterned to form a source / drain pattern corresponding to the active layer pattern and an upper electrode pattern corresponding to the photosensitive layer pattern. An insulating protective layer is disposed on the second metal layer; An optical path layer is disposed on a second surface of the substrate layer by inverting the substrate layer, wherein the second surface is the surface of the substrate layer away from the amorphous silicon layer. as well as The main body of the display panel is disposed on the optical path layer.

Images