Memory cell of non-volatile memory

Abstract

The present invention discloses a memory cell of a non-volatile memory, which includes a memory element. The memory element is a transistor, and the memory element has asymmetric spacer walls. In the memory element, a longer channel is disposed under the wider spacer wall. When the memory element performs a programming operation, more carriers are injected into the charge trapping layer of the spacer wall via the longer channel. Therefore, the memory cell of the present invention can perform the programming operation more efficiently and shorten the time of the programming operation.

Description

Technical Field

[0001] The present invention relates to a memory cell of a non-volatile memory, and more particularly to a memory device having an asymmetric spacer in the memory cell of a non-volatile memory. Background Art

[0002] Please refer to Figure 1 , which shows a schematic diagram of a memory device currently used in a non-volatile memory. This memory device is disclosed in U.S. Patent No. 7,551,494. The memory device 10 is a P-channel transistor.

[0003] As Figure 1 shown, the memory device 10 is fabricated between isolation structures 15, and the isolation structures 15 are shallow trench isolation structures (STI for short). The memory device 10 includes: an N well region 11, a gate layer 18, a gate dielectric layer 16, an oxygen-nitrogen-oxygen spacer (ONO spacer) 20, a P+ source doped region 12, and a P+ drain doped region 14.

[0004] The gate dielectric layer 16 and the gate layer 18 are stacked above the surface of the N well region 11. Furthermore, the oxygen-nitrogen-oxygen spacer 20 surrounds the side walls of the gate dielectric layer 16 and the gate layer 18. Below the surface of the N well region 11, the P+ source doped region 12 is located on one side of the oxygen-nitrogen-oxygen spacer 20, and the P+ drain doped region 14 is located on the other side of the oxygen-nitrogen-oxygen spacer 20. In other words, the gate dielectric layer 16, the gate layer 18, and the oxygen-nitrogen-oxygen spacer 20 are located above the surface of the N well region 11 between the P+ source doped region 12 and the P+ drain doped region 14.

[0005] Below the surface of the N-type well region 11, between the P-type source doping region 12 and the P-type drain doping region 14 is the channel region. The channel region includes: a first channel 19, a second channel 29, and a third channel 39. The channel lengths of the first channel 19, the second channel 29, and the third channel 39 are L1, L2, and L3, respectively. The first channel 19 is directly below the control gate layer 18, the second channel 29 is between the P-type drain doping region 14 and the first channel 19, and the third channel 39 is between the first channel 19 and the P-type source doping region 12.

[0006] Furthermore, the oxygen-nitrogen-oxygen spacer 20 includes: a silicon oxide layer 22, a silicon nitride layer 24, and a silicon oxide layer 26. The silicon oxide layer 22 contacts the sidewalls of the gate dielectric layer 16 and the control gate layer 18, and the silicon oxide layer 22 contacts the surface of the N-type well region 11 and extends to the P-type source doping region 12 and the P-type drain doping region 14. Furthermore, the silicon nitride layer 24 covers the silicon oxide layer 22, and the silicon oxide layer 26 covers the silicon nitride layer 24. Basically, the silicon nitride layer 24 is a charge-trapping layer.

[0007] Please refer to Figure 2 , which shows the bias schematic diagram of the programming operation of the existing memory element. When performing the programming operation on the memory element 10, the P-type drain doping region 14 receives the drain voltage V D , the P-type source doping region 12 is floating, the N-type well region 11 receives the ground voltage (i.e., V NW = 0V), and the control gate layer 18 receives the gate voltage V G . For example, the drain voltage V D = -3V to -5V, and the gate voltage V G = 0V to 2V. Under the above bias conditions, the first channel 19 below the control gate layer 18 will be turned off. Furthermore, electron-hole pairs will be generated at the junction between the N-type well region 11 and the P-type drain doping region 14, and the band-to-band hot electron injection (BBHE) effect will occur, causing electrons to be injected from the second channel 29 into the silicon nitride layer 24 on the drain side.

[0008] Of course, in addition to utilizing the BBHE effect, other biasing methods can also be used to perform a programming operation on the memory element 10. For example, a gate voltage V G is provided to turn on the first channel 19, and the channel hot hole induced hot electron injection (CHHIHE) effect occurs, causing electrons to be injected from the second channel 29 into the silicon nitride layer 24 on the drain side. Additionally, since the electrons are injected from the second channel 29 into the silicon nitride layer 24, the ratio between the injection channel length and the total channel length is

[0009] In other words, during the programming operation, controlling whether electrons are injected or not into the silicon nitride layer 24 above the second channel 29 can cause the memory element 10 to exhibit two different storage states. Furthermore, providing other biases can also perform an erase operation and a read operation on the memory element 10, and the detailed operating principles thereof will not be elaborated further.

[0010] When manufacturing the memory element 10 using current semiconductor processes, the oxygen-nitrogen-oxygen spacer 20 in contact with the sidewall of the control gate layer 18 will exhibit a symmetric shape. Therefore, the lengths of the second channel 29 and the third channel 39 in the memory element 10 are almost the same. Summary of the Invention

[0011] The main objective of the present invention is to propose a memory cell of a non-volatile memory, where the memory element in the memory cell has an asymmetric spacer. During the programming operation, more carriers can be injected into the charge-trapping layer of the wider spacer. Furthermore, the present invention designs a memory cell with a special structure. For example, a longer second channel is designed to increase the ratio between the injection channel length and the total channel length. Therefore, the programming operation can be performed more efficiently.

[0012] The present invention relates to a memory cell of a non-volatile memory. The memory cell has a memory element, and the memory element includes: a well region; a gate structure formed on a surface of the well region, and the gate structure includes at least one protrusion; a spacer surrounding a sidewall of the gate structure, and the spacer contacts the surface of the well region, wherein the spacer includes a first portion and a second portion; and a first doped region and a second doped region formed under the surface of the well region, and a channel region is between the first doped region and the second doped region, and the channel region includes a first channel and a second channel; wherein, the sidewall of the gate structure includes a plurality of surfaces, and a first surface of the at least one protrusion is parallel to a channel length direction in the channel region; wherein, the first channel is located under the gate structure, the second channel is located between the first channel and the second doped region, and the first portion of the spacer is located above the second channel; wherein, during a programming operation, a plurality of carriers are injected into a charge trapping layer in the first portion of the spacer via the second channel.

[0013] The present invention relates to a memory cell of a non-volatile memory. The memory cell includes: a memory element including: a well region, a first gate structure, a first spacer, a first doped region and a second doped region; the first gate structure is formed on a surface of the well region, and the first gate structure includes at least one protrusion; the first spacer surrounds a sidewall of the first gate structure, the first spacer contacts the surface of the well region, and the first spacer includes a first portion and a second portion; the first doped region and the second doped region are formed under the surface of the well region, and a channel region is between the first doped region and the second doped region, and the channel region includes a first channel and a second channel; the sidewall of the first gate structure includes a plurality of surfaces, and a first surface of the at least one protrusion is parallel to a channel length direction in the channel region; the first channel is located under the first gate structure, the second channel is located between the first channel and the second doped region, the first portion of the first spacer is located above the second channel; and a select transistor including: the well region, a second gate structure, a second spacer and a third doped region; the second gate structure is formed on the surface of the well region; the second spacer surrounds a sidewall of the second gate structure, and the second spacer contacts the surface of the well region; the third doped region is formed under the surface of the well region; a fourth channel is between the first doped region and the third doped region, and the fourth channel is located under the second gate structure; wherein, during a programming operation, a plurality of carriers are injected into a charge trapping layer in the first portion of the first spacer via the second channel of the memory element.

[0014] To have a better understanding of the above and other aspects of the present invention, the following provides preferred embodiments in conjunction with the accompanying drawings and detailed descriptions are as follows: Description of the Drawings

[0015] Figure 1 It is a schematic diagram of a storage element currently applied to non-volatile memory;

[0016] Figure 2 It is a bias schematic diagram of a programming operation for a current storage element;

[0017] Figures 3A to 3F It is a top view of the manufacturing process of a storage unit of a non-volatile memory according to the first embodiment of the present invention and a cross-sectional view taken along the A-B direction;

[0018] Figure 3G It is a bias schematic diagram when the storage unit of the first embodiment performs various operations;

[0019] Figure 4A And Figure 4B It is a schematic diagram of a first modified storage element according to the first embodiment and its bias schematic diagram when performing various operations;

[0020] Figure 4C It is a schematic diagram of a second modified storage element according to the first embodiment;

[0021] Figure 4D It is a schematic diagram of a third modified storage element according to the first embodiment;

[0022] Figure 4E It is a schematic diagram of a fourth modified storage element according to the first embodiment;

[0023] Figure 4F It is a schematic diagram of a fifth modified storage element according to the first embodiment;

[0024] Figure 5A And Figure 5B It is a top view of a storage unit of a non-volatile memory according to the second embodiment of the present invention and a cross-sectional view taken along the A-B direction;

[0025] Figure 5C It is a bias schematic diagram when the storage element in the storage unit of the second embodiment performs various operations;

[0026] Figure 5D It is a bias schematic diagram when an N-channel transistor is used as a storage element and performs various operations;

[0027] Figure 5E It is a schematic diagram of a second modified storage element according to the second embodiment;

[0028] Figure 6A AndFigure 6B Top view of the memory cell of the third embodiment of the present invention and cross-sectional view along the A-B direction; and

[0029] Figure 7A and Figure 7B Top view of the memory cell of the fourth embodiment of the present invention and cross-sectional view along the A-B direction.

[0030] Symbol description

[0031] 10: Memory element

[0032] 11: N-type well region

[0033] 12, 14: Doped region

[0034] 15: Isolation structure

[0035] 16: Gate dielectric layer

[0036] 18: Control gate layer

[0037] 19: First channel

[0038] 20: Spacer

[0039] 22, 26: Silicon oxide layer

[0040] 24: Silicon nitride layer

[0041] 29: Second channel

[0042] 39: Third channel

[0043] 300, 300a, 300c, 300d, 300e, 300f, 300g, 300h, 500, 500e: Memory element

[0044] 310, 310a, 310d, 310e, 310f, 610: Well region

[0045] 320, 340, 320a, 340a, 320c, 320d, 340d, 320e, 340e, 320f, 340f: Doped region

[0046] 322, 342, 322d, 342d, 322e, 342e, 322f, 342f, 641, 652: Metal electrode

[0047] 330, 330d, 330e, 330f, 630, 670: Spacer

[0048] 332, 336, 632, 636, 672, 676: Silicon oxide layer

[0049] 334,634,674: Silicon nitride layer

[0050] 380,660,680: Gate structure

[0051] 380a,380b,410: Protrusion

[0052] 380c,380d,411: Surface

[0053] 382,662,682: Gate dielectric layer

[0054] 384,384d,384e,384f,664,684: Control gate layer

[0055] 386: Opening

[0056] 391,691: First channel

[0057] 392,692: Second channel

[0058] 393,693: Third channel

[0059] 400,622,652: Extension

[0060] 502,502e,702: Auxiliary electrode

[0061] 504,704: Dielectric layer

[0062] 620,640,650: Doped region

[0063] 694: Third channel Detailed implementation manner

[0064] Please refer to Figures 3A to 3F , which shows the top view of the manufacturing process of the memory cell of the first embodiment of the present invention and the cross-sectional view in the A - B direction.

[0065] As Figure 3A And Figure 3BAs shown, a C-shaped gate structure 380 is formed on a well region 310. The gate structure 380 has two parallel protrusion parts 380a, 380b, and the two protrusion parts 380a, 380b have facing surfaces 380c, 380d. In other words, the two protrusion parts 380a, 380b can form a C-shaped gate structure 380 and define a notch 386. Furthermore, the gate structure 380 includes a gate dielectric layer 382 and a control gate layer 384. The gate dielectric layer 382 is first formed on the surface of the well region 310, and the control gate layer 384 then covers the gate dielectric layer 382. Among them, the control gate layer 384 is a polysilicon control gate layer, and the gate dielectric layer 382 is a silicon oxide layer.

[0066] As Figure 3C and Figure 3D shown, a spacer 330 is formed around the side wall of the gate structure 380. Among them, the spacer 330 is an ONO (oxide-nitride-oxide) spacer. The spacer 330 includes: a silicon oxide layer 332, a silicon nitride layer 334, and a silicon oxide layer 336. The silicon oxide layer 332 contacts the side wall of the gate structure 380, and the silicon oxide layer 332 contacts the surface of the well region 310. The silicon nitride layer 334 covers the silicon oxide layer 332. The silicon oxide layer 336 covers the silicon nitride layer 334. Among them, the silicon nitride layer 334 is a charge-trapping layer.

[0067] According to an embodiment of the present invention, during the process of forming the spacer 330, since the material of the spacer 330 fills and contacts three surfaces at the opening 386 of the C-shaped gate structure 380 (that is, two surfaces 380c and 380d plus the surface between the two surfaces 380c and 380d), after etching, more spacer 330 material will remain at the opening 386 of the C-shaped gate structure 380, resulting in asymmetric spacers 330 formed on both sides of the gate structure 380. In other words, the spacer 330 includes a right part and a left part, the widths of the right part and the left part are different, and the physical height of the right part will be higher than that of the left part. The right part of the spacer 330 is located between the two protrusion parts 380a, 380b and contacts three surfaces at the opening 386 of the C-shaped gate structure 380. Therefore, as Figure 3D shown, the width of the right part of the spacer 330 with different widths is greater than the width of the left part of the spacer 330.

[0068] AsFigure 3E As shown in Figure 3F FIG. 2, a source / drain doping process is performed to form a first doping region 320 and a second doping region 340 on both sides of the gate structure 380 and the spacer 330. After the metal electrodes 322 and 342 are respectively connected to the first doping region 320 and the second doping region 340, the storage element 300 is completed. Among them, the first doping region 320 and the second doping region 340 are P-type doping regions, and the well region 310 is an N-type well region. In other words, the storage unit of the non-volatile memory according to the first embodiment of the present invention includes a storage element 300, the storage element 300 is a P-channel transistor, the first doping region 320 is the source, and the second doping region 340 is the drain.

[0069] As shown in Figure 3E FIG. 3, Figure 3F a channel region is between the first doping region 320 and the second doping region 340 below the surface of the well region 310. Among them, the two surfaces 380c and 380d of the gate structure 380 are parallel to the channel length direction of the channel region. The channel region includes: a first channel 391, a second channel 392, and a third channel 393. The channel lengths of the first channel 391, the second channel 392, and the third channel 393 are L1, L2, and L3 respectively. The first channel 391 is directly below the gate structure 380 and is between the second channel 392 and the third channel 393. The second channel 392 is between the second doping region 340 and the first channel 391. The third channel 393 is between the first doping region 320 and the first channel 391. In addition, the wider spacer 330 on the right side is above the second channel 392, and the narrower spacer 330 on the left side is above the third channel 393.

[0070] In the embodiment of the present invention, the storage element 300 has a C-shaped gate structure 380. That is, among the side walls of the gate structure 380, three surfaces are adjacent to the second channel 392, and more materials of the spacer 330 can remain, resulting in a wider spacer 330. As shown in Figure 3FAs shown, the silicon oxide layer 332 of the spacer wall 330 contacts the sidewalls of the gate structure 380, and the silicon oxide layer 332 contacts the surface of the well region 310 and extends to the first doped region 320 and the second doped region 340 respectively. After covering the silicon nitride layer 334 and the silicon oxide layer 336 on the silicon oxide layer 332 and performing etching, an asymmetric spacer wall 330 can be formed. Since the spacer walls 330 with different widths are formed on both sides of the gate structure 380, the lengths of the second channel 392 and the third channel 393 will be different. According to an embodiment of the present invention, the length of the second channel 392 is greater than the length of the third channel 393, and the length of the second channel 392 is less than or equal to three times the length of the third channel 393. That is to say, the width of the right spacer wall 330 is greater than the width of the left spacer wall 330, and the width of the right spacer wall 330 is less than three times the width of the left spacer wall 330. Furthermore, because the right spacer wall 330 is wider, there is a longer silicon nitride layer 334 in the right spacer wall 330 that can store more electrons.

[0071] Based on this, since the right partial spacer wall 330 is physically higher, it can block more dopant ions during the source / drain doping process to prevent the formation of the second doped region 340 under the silicon oxide layer 332. In this way, the length of the second channel 392 can be increased, so that the storage element 300 has a longer second channel 392. Therefore, the ratio between the injection channel length and the total channel length (i.e., ) will increase. When the storage element 300 performs a programming operation, more carriers will be injected into the silicon nitride layer 334 of the spacer wall 330 via the second channel 392. Therefore, the storage element 300 of the present invention can perform the programming operation more efficiently and shorten the time of the programming operation.

[0072] Please refer to Figure 3G , which shows the bias voltage schematic diagram when the first embodiment storage unit performs various operations. Among them, the first doped region 320 receives the source line voltage V SL , the second doped region 340 receives the bit line voltage V BL , the control gate layer 384 receives the gate voltage V G , and the well region 310 receives the well voltage (V NW ). It should be noted that Figure 3E and Figure 3F are for simplifying the drawing, so the contact points connected to the control gate layer 384 to receive the gate voltage V G are omitted and not shown.

[0073] When using the band-to-band hot electron injection effect (BBHE effect) to perform a programming operation (PGM) on the storage element 300, the source line voltage V SLis floating, gate voltage V G is a voltage greater than or equal to 0V, bit line voltage V BL is -6V, well region voltage V NW is 0V. Since the gate voltage V G is greater than the bit line voltage V BL , the first channel 391 under the gate structure 380 will be turned off. Furthermore, electron-hole pairs will be generated at the junction between the well region 310 and the second doped region 340, and the BBHE effect will occur, causing electrons to be injected from the second channel 392 into the silicon nitride layer 334 on the drain side. That is, electrons are injected from the second channel 392 into the charge capture layer in the wider gap wall 330 near the second doped region 340 side.

[0074] When programming the memory element 300 using the channel hot electron injection (CHE) effect, the source line voltage V SL is 0V, the gate voltage V G is -1V, the bit line voltage V BL is -6V, the well region voltage V NW is 0V. Since the gate voltage V G is less than the source line voltage V SL , the first channel 391 under the gate structure 380 will be turned on, the channel region between the first doped region 320 and the second doped region 340 will be turned on, and a programming current will be generated. When electrons pass through the second channel 392, the CHE effect occurs, causing electrons to be injected from the second channel 392 into the silicon nitride layer 334 on the drain side. That is, electrons are injected from the second channel 392 into the charge capture layer in the wider gap wall 330 near the second doped region 340 side.

[0075] When erasing the memory element 300 using the channel hot hole injection (CHH) effect, the source line voltage V SL is 0V, the gate voltage V G is -6V, the bit line voltage V BL is -6V, the well region voltage V NW is 0V. Since the gate voltage V G is less than the source line voltage V SL, the first channel 391 under the gate structure 380 will be turned on, and the channel region between the first doped region 320 and the second doped region 340 is turned on. When holes pass through the second channel 392, the CHH effect occurs, causing the holes to be injected from the second channel 392 into the silicon nitride layer 334 on the drain side, so that the electrons and holes in the silicon nitride layer 334 combine to complete the erase operation (ERS).

[0076] When using the channel FN tunneling effect (Fowler-Nordheim Tunneling, abbreviated as FN effect) to perform the erase operation (ERS) on the memory element 300, the source line voltage V SL is +6V, the gate voltage V G is -6V, the bit line voltage V BL is +6V, and the well region voltage V NW is +6V. Since the gate voltage V G is less than the well region voltage V NW , the FN effect occurs, causing the electrons in the silicon nitride layer 334 to eject from the silicon nitride layer 334 to the well region 310 to complete the erase operation (ERS).

[0077] When using the band-to-band hot hole injection effect (abbreviated as BBHH effect) to perform the erase operation (ERS) on the memory element 300, the source line voltage V SL is floating, the gate voltage V G is -6V, the bit line voltage V BL is -6V, and the well region voltage V NW is 0V. Since the gate voltage V G and the bit line voltage V BL are -6V, the first channel 391 under the gate structure 380 will be turned off. Furthermore, electron-hole pairs will be generated at the junction between the well region 310 and the second doped region 340, and the band-to-band hot hole injection effect (BBHH effect) will occur. Therefore, holes are injected from the second channel 392 into the silicon nitride layer 334 on the drain side, so that the electrons and holes in the silicon nitride layer 334 combine to complete the erase operation (ERS).

[0078] When performing the read operation (READ) on the memory element 300, the source line voltage V SL is -1V, the gate voltage V G is -1V, the bit line voltage V BL is 0V, and the well region voltage V NWis 0V. At this time, the channel region between the first doped region 320 and the second doped region 340 is turned on, and a read current is generated. Basically, when electrons are stored in the silicon nitride layer 334 of the memory element 300, the read current is relatively large, which can be regarded as the first storage state of the memory element 300. On the contrary, when no electrons / holes are stored in the silicon nitride layer 334 of the memory element 300, the read current is relatively small, which can be regarded as the second storage state of the memory element 300. In other words, the storage state of the memory element 300 can be determined according to the magnitude of the read current.

[0079] Basically, in the above storage cell, the bias voltages provided by various operations of the memory element 300 are only examples of the present invention and are not used to limit the present invention. Those skilled in the art can modify the bias voltages of various operations and perform programming operations, erasing operations, and reading operations on the memory element 300.

[0080] In addition, the memory element in the first embodiment of the present invention is not limited to a P-channel transistor. The memory element in the first embodiment of the storage cell can also be an N-channel transistor.

[0081] Please refer to Figure 4A , which shows a first modified memory element according to the first embodiment. The first modified memory element 300a in the storage cell is an N-channel transistor. Figure 4B is a schematic diagram of the bias voltages for performing various operations on the first modified memory element. Among them, the structure of the memory element 300a is similar to that of the memory element 300, and the following is a description.

[0082] As Figure 4A shown, the memory element 300a in the storage cell includes: a well region 310a, a gate dielectric layer 382, a control gate layer 384, spacer walls 330, a first doped region 320a, and a second doped region 340a. The spacer walls 330 include: a silicon oxide layer 332, a silicon nitride layer 334, and a silicon oxide layer 336. In addition, the first doped region 320a and the second doped region 340a are N-type doped regions, and the well region 310a is a P-type well region. Similarly, a channel region is located between the first doped region 320a and the second doped region 340a below the surface of the well region 310a. The channel region includes: a first channel 391, a second channel 392, and a third channel 393.

[0083] Since the storage element 300a has a C-shaped gate structure, that is, three side surfaces of the sidewalls of the gate structure are adjacent to the second channel 392. Therefore, spacer walls 330 with different widths can be formed on both sides of the gate structure, which will result in different lengths of the second channel 392 and the third channel 393. According to an embodiment of the present invention, the length of the second channel 392 is greater than the length of the third channel 393, and the length of the second channel 392 is less than or equal to three times the length of the third channel 393.

[0084] As Figure 4B shown, the first doped region 320a receives the source line voltage V SL , the second doped region 340a receives the bit line voltage V BL , the control gate layer 484 receives the gate voltage V G , and the well region 310a receives the well region voltage V PW .

[0085] When programming the storage element 300a by using the band-to-band hot hole injection effect (BBHH effect for short), the source line voltage V SL is floating, the gate voltage V G is a voltage less than or equal to 0V, the bit line voltage V BL is +6V, and the well region voltage V PW is 0V. Since the gate voltage V G is less than the bit line voltage V BL , the first channel 391 will be turned off. Furthermore, electron-hole pairs will be generated at the junction between the well region 310a and the second doped region 340a, and the BBHH effect will occur, causing holes to be injected from the second channel 392 into the silicon nitride layer 334 on the drain side. That is to say, holes are injected from the second channel 392 into the charge trapping layer in the wider spacer wall 330 near the second doped region 340 side.

[0086] When erasing the storage element 300a by using the channel hot electron injection effect (CHE effect for short), the source line voltage V SL is 0V, the gate voltage V G is +6V, the bit line voltage V BL is +6V, and the well region voltage V PW is 0V. Since the gate voltage V G is greater than the source line voltage V SL, the first channel 391 will be turned on, and the channel region between the first doped region 320a and the second doped region 340a is turned on. When electrons pass through the second channel 392, the CHE effect occurs, causing electrons to be injected from the second channel 392 into the silicon nitride layer 334 on the drain side, causing the electrons and holes in the silicon nitride layer 334 to combine to complete the erasing operation.

[0087] When performing a READ operation on the memory element 300a, the source line voltage V SL is +1V, the gate voltage V G is +1V, the bit line voltage V BL is 0V, and the well region voltage V PW is 0V. At this time, the channel region between the first doped region 320a and the second doped region 340a is turned on, and a read current is generated. Therefore, the storage state of the memory element 300a can be determined according to the magnitude of the read current.

[0088] Furthermore, the gate structure of the memory element in the first embodiment of the present invention is not limited to a C-shaped gate structure. Those skilled in the art can also modify the C-shaped gate structure into other shaped gate structures and manufacture asymmetric spacer walls.

[0089] Please refer to Figure 4C , which shows a second variant memory element modified according to the first embodiment. Compared with Figure 3F the memory element 300 in Figure 4C the first doped region 320c in the memory element 300c further includes an extension 400, which is a lightly doped drain region (abbreviated as LDD region). That is, a lightly doped drain process (abbreviated as LDD process) is additionally performed on the side of the narrower spacer wall 300. When the extension 400 of the first doped region 320c is completed, the third channel under the narrower spacer wall 300 will disappear, causing the ratio of the injection channel length to the total channel length (i.e., ) to increase. Therefore, the memory element 300c can perform the programming operation more efficiently. It should be noted that the LDD process may not be performed on the side of the wider spacer wall 300, that is, the second channel 392 is allowed to exist without disappearing. Since the second channel 392 still exists, electrons can be injected into the silicon nitride layer 334 on the drain side through the second channel 392.

[0090] Please refer toFigure 4D , which is shown as a third variant memory element modified according to the first embodiment. The memory element 300d has an L-shaped control gate layer 384d, that is, the memory element 300d has an L-shaped gate structure. The gate structure has a protrusion 410, and the surface 411 of the protrusion 410 is parallel to the channel region length direction of the channel region. Furthermore, the spacer 330d surrounds the sidewalls of the gate structure. After the source / drain doping process, the first doped region 320d and the second doped region 340d formed in the well region 310d are located on both sides of the spacer 330d respectively. Connecting the metal electrodes 322d and 342d to the first doped region 320d and the second doped region 340d respectively completes the memory element 300d.

[0091] Basically, when the spacer 330d formation process is performed, since the material of the spacer 330d fills the corner of the L-shaped gate structure at the same time, there will be more spacer 330d material remaining at the corner of the L-shaped gate structure after etching. That is to say, the spacer 330d formed on the right side will contact the surface 411 of the protrusion 410 and contact another sidewall surface perpendicular to the surface 411 in the L-shaped gate structure. Therefore, spacers 330d with different widths are formed on the left and right sides of the L-shaped gate structure.

[0092] In addition, the cross-sectional view of the memory element 300d along the A-B line is similar to Figure 3F , which will not be elaborated here. Furthermore, since the memory element 300d has an L-shaped gate structure, the two sidewall surfaces of the gate structure will be adjacent to the second channel.

[0093] Please refer to Figure 4E , which is shown as a fourth variant memory element modified according to the first embodiment. Compared with the memory element 300 of Figure 3E , the gate structure of the memory element 300e also extends to adjacent memory elements 300g and 300h. That is, the memory elements 300e, 300g, and 300h share the control gate layer 384e, and the structures of the memory elements 300e, 300g, and 300h are exactly the same.

[0094] Similarly, more spacer 330e material will remain at the opening of the control gate layer 384e of the memory element 300e, resulting in spacers 330e with different widths formed on both sides of the gate structure. Furthermore, the first doped region 320e and the second doped region 340e formed after the source / drain doping process are located on both sides of the spacer 330e respectively. Connecting the metal electrodes 322e and 342e to the first doped region 320e and the second doped region 340e respectively completes the memory element 300e.

[0095] In addition, the cross-sectional view of the storage element 300e along the A-B line is similar to Figure 3F , which will not be elaborated here. Furthermore, since the storage element 300e has a C-shaped gate structure, three surfaces of the sidewalls of the gate structure will be adjacent to the second channel.

[0096] Please refer to Figure 4F , which shows a fifth variant storage element modified according to the first embodiment. Compared with the storage element 300 of Figure 3E , the channel width of the storage element 300f is narrower. That is to say, the present invention can design a narrower channel according to the semiconductor process specifications to reduce the size of the storage element 300f.

[0097] Similarly, more spacer 330f material will remain at the opening of the control gate layer 384f of the storage element 300f, resulting in different-width spacers 330f formed on both sides of the gate structure. Furthermore, the first doped region 320f and the second doped region 340f formed after the source / drain doping process are located on both sides of the spacer 330f respectively. Connecting the metal electrodes 322f and 342f to the first doped region 320f and the second doped region 340f respectively completes the storage element 300f.

[0098] In addition, the cross-sectional view of the storage element 300f along the A-B line is similar to Figure 3F , which will not be elaborated here. Furthermore, since the storage element 300f has a C-shaped gate structure, three surfaces of the sidewalls of the gate structure will be adjacent to the second channel.

[0099] From the above description, it can be seen that in order to make the storage element have an asymmetric spacer 330. The storage element of the present invention has a gate structure with a special shape, and there are multiple surfaces on the sidewalls of the gate structure. Designing the gate structure 380 such that at least two surfaces of the sidewalls are adjacent to the second channel makes a wider spacer formed above the second channel.

[0100] Please refer to Figure 5A and Figure 5B , which show the top view of the storage cell and the cross-sectional view in the A-B direction of the non-volatile memory according to the second embodiment of the present invention. The storage cell of the second embodiment includes a storage element 500, and this storage element 500 is designed with an assisted electrode 502 on the basis of the storage element 300 of the first embodiment to enhance the programming and erasing efficiency of the storage element 500. That is, the storage element 500 in the storage cell of the second embodiment also has an assisted electrode 502. Only the assisted electrode 502 will be introduced below, and the other structures of the storage element will not be elaborated.

[0101] The auxiliary electrode 502 is located above the gap wall 330 between the gate structure 380 and the second doped region 340. That is, the auxiliary electrode 502 is located above the wider gap wall 330. Furthermore, a dielectric layer 504 is located between the auxiliary electrode 502 and the gap wall 330, and the dielectric layer 504 can be a Resistance Protection Oxide layer (RPO layer). Additionally, for simplicity of drawing, Figure 5A the dielectric layer 504 is not shown.

[0102] Please refer to Figure 5C , which shows the bias voltage diagram when the storage element in the second embodiment storage cell performs various operations. Compared with Figure 3G , the difference is only that an auxiliary voltage V A is added. Only the auxiliary voltage V A will be described below, and other bias voltages will not be elaborated.

[0103] As Figure 5C shows, when the storage element 500 is a P-channel transistor, the auxiliary electrode 502 receives the auxiliary voltage V A . During the programming operation, the auxiliary voltage V A can control the injection of electrons into the silicon nitride layer 334. Additionally, during the erase operation, the auxiliary voltage V A can control the injection of holes into the silicon nitride layer 334, or control the withdrawal of electrons from the silicon nitride layer 334.

[0104] As Figure 5C shows, for the storage element 500 of a P-channel transistor, when using the BBHE effect to perform the programming operation (PGM), the auxiliary voltage V A is +3V. When using the CHE effect to perform the programming operation (PGM), the auxiliary voltage V A is -3V. When using the CHH effect to perform the erase operation (ERS), the auxiliary voltage V A is -3V. When using the FN tunneling effect to perform the erase operation (ERS), the auxiliary voltage V A is -6V. When using the BBHH effect to perform the erase operation (ERS), the auxiliary voltage V A is -3V. When performing the read operation, the auxiliary voltage V A is -1V.

[0105] Basically, in the above storage cell, the bias voltages provided for various operations of the storage element 500 are only examples of the present invention and are not used to limit the present invention. Those skilled in the art can modify the bias voltages of various operations and perform programming operations, erase operations, and read operations on the storage element 500.

[0106] In addition, the storage element of the second embodiment of the present invention described above is a P-channel transistor. Those skilled in the art can also modify it into a first variant storage element according to the second embodiment. For example, the first variant storage element is an N-channel transistor. Since the structure of the storage element of the N-channel transistor is the same as that of Figure 5B , it will not be elaborated here.

[0107] Please refer to Figure 5D , which shows the bias voltage schematic diagram when an N-channel transistor is used as a storage element and performs various operations. For the storage element of the N-channel transistor, when using the BBHH effect to perform the programming operation (PGM), the auxiliary voltage V A is less than or equal to 0V; when using the CHE effect to perform the erasing operation (ERS), the auxiliary voltage V A is +6V; when performing the reading operation, the auxiliary voltage V A is +1V.

[0108] Please refer to Figure 5E , which shows the second variant storage element modified according to the second embodiment. Compared with the storage element 500 of Figure 5B , the auxiliary electrode 502e of the storage element 500e is in direct contact with the spacer 330. For example, the auxiliary electrode 502e can be in direct contact with the silicon oxide layer 332, silicon nitride layer 334, and silicon oxide layer 336 of the spacer 330. Since the material of the spacer 330 is a non-conductor. Therefore, when the auxiliary electrode 502e contacts the spacer 330, the storage element 500e can still perform the programming operation, erasing operation, and reading operation. And the bias voltages of various operations are similar to those of Figure 5C and Figure 5D , and will not be elaborated here.

[0109] Of course, the present invention can also modify the storage element of the second embodiment. For example, modify the gate structure so that the storage element has an L-shaped gate structure as shown in Figure 4C , or a gate structure extending to adjacent storage elements as shown in Figure 4D . Of course, the channel width of the storage element can also be modified as shown in Figure 4E . In addition, Figure 5B and Figure 5E the auxiliary electrodes 520, 520e can also be in contact with the control gate layer 384.

[0110] Please refer to Figure 6A and Figure 6B, which shows a top view of a memory cell of the third embodiment of the present invention and a cross-sectional view taken along the A-B direction. Compared with the memory cell of the first embodiment which only has a single memory element 300, the memory cell of the third embodiment includes a memory element and a select transistor. Basically, the manufacturing process of the third embodiment is similar to that of the first embodiment, and will not be described in detail here.

[0111] The memory element includes: a well region 610, a first doped region 620, a second doped region 640, a gate structure 680, and an ONO spacer 630. The gate structure 680 includes: a gate dielectric layer 682, a control gate layer 684. The ONO spacer 630 is an oxygen-nitrogen-oxygen spacer, which includes: a silicon oxide layer 632, a silicon nitride layer 634, and a silicon oxide layer 636.

[0112] In the memory element, the first doped region 620 and the second doped region 640 are located below the surface of the well region 610, and the metal electrode 642 is in contact with the second doped region 640. The gate structure and the ONO spacer 630 are formed above the surface of the well region 610 and between the first doped region 620 and the second doped region 640. The C-shaped gate structure is in contact with the upper surface of the well region 610. The ONO spacer 630 surrounds the side wall of the gate structure. Among them, the silicon oxide layer 632 is in contact with the side wall of the gate structure, and the silicon oxide layer 632 is in contact with the surface of the well region 610 and extends to the first doped region 620 and the second doped region 640. The silicon nitride layer 634 covers the silicon oxide layer 632. The silicon oxide layer 636 covers the silicon nitride layer 634. Among them, the silicon nitride layer 334 is a charge-trapping layer.

[0113] Furthermore, the channel region is between the first doped region 620 and the second doped region 640 below the surface of the well region 610. The channel region includes: a first channel 691, a second channel 692, and a third channel 693. The first channel 691 is located directly below the gate structure, the second channel 692 is located between the second doped region 640 and the first channel 691, and the third channel 693 is located between the first doped region 620 and the first channel 691. In addition, the wider part of the ONO spacer 630 on the right side is located above the second channel 692, and the narrower part of the ONO spacer 630 on the left side is located above the third channel 693.

[0114] According to an embodiment of the present invention, since three side surfaces of the sidewalls of the C-shaped gate structure are adjacent to the second channel 692, spacer walls 630 with different widths are formed on both sides of the gate structure, such that the length of the second channel 692 is greater than the length of the third channel 693, and the length of the second channel 692 is less than or equal to three times the length of the third channel 693.

[0115] The select transistor includes: a well region 610, a first doped region 620, a third doped region 650, a gate structure 660, and a spacer wall 670. The gate structure includes: a gate dielectric layer 662, a select gate layer 664. The spacer wall 670 is an oxygen-nitrogen-oxygen spacer (ONO spacer), which includes: a silicon oxide layer 672, a silicon nitride layer 674, and a silicon oxide layer 676.

[0116] During the manufacturing process of the select transistor, a lightly doped drain (LDD) process is added, such that the first doped region 620 and the third doped region 650 each include an extension 622 and 652, and the extensions 622 and 652 are located below the spacer wall 670. Among them, the extensions 662 and 652 are lightly doped drain regions (LDD regions).

[0117] Therefore, in the select transistor, the first doped region 620 and the third doped region 650 are located below the surface of the well region 610, and the metal electrode 652 contacts the third doped region 650. The gate structure is formed above the surface of the well region 610, between the first doped region 620 and the third doped region 650. The gate structure contacts the upper surface of the well region 610. The spacer wall 670 surrounds the side wall of the gate structure and contacts the surface of the well region. Furthermore, a fourth channel 694 is located between the first doped region 620 and the second doped region 650 below the surface of the well region 610.

[0118] According to the third embodiment of the present invention, after applying an appropriate bias voltage to turn on the select transistor, programming, erasing, and reading operations can be performed on the storage element. Furthermore, since there is no channel below the spacer wall 670 of the select transistor, no carriers are injected into the spacer wall 670 of the select transistor during the programming operation.

[0119] Similarly, the storage element and the select transistor in the memory cell of the third embodiment of the present invention can both be P-channel transistors or both be N-channel transistors.

[0120] Of course, the present invention can also modify the storage element in the third embodiment. For example, modify the gate structure such that the storage element has Figure 4CThe L-shaped gate structure shown, or as Figure 4D shown, a gate structure extending to an adjacent memory element. Of course, it is also possible to, as Figure 4E shown, modify the channel width of the memory element.

[0121] Please refer to Figure 7A and Figure 7B , which shows a top view of a memory cell and a cross-sectional view in the A-B direction of a non-volatile memory according to a fourth embodiment of the present invention. The memory cell of the fourth embodiment includes a selection transistor and a memory element. An assisted electrode 702 is designed on the basis of the memory cell of the third embodiment to enhance the programming and erasing efficiency of the memory element. Only the assisted electrode 702 is introduced below, and other structures of the memory cell will not be elaborated. In addition, for the sake of simplifying the drawing, Figure 7A the dielectric layer 704 is not shown in

[0122] The assisted electrode 702 is located above the spacer wall 630 between the gate structure of the memory element and the second doped region 640. That is, the assisted electrode 702 is located above the wider spacer wall 630. Furthermore, a dielectric layer 704 is located between the assisted electrode 702 and the spacer wall 630, and the dielectric layer 704 can be a Resistance Protection Oxide layer (abbreviated as RPO layer).

[0123] According to the fourth embodiment of the present invention, after appropriately applying a bias voltage to turn on the selection transistor, programming, erasing, and reading operations can be performed on the memory element. Furthermore, since there is no channel under the spacer wall 670 of the selection transistor, no carriers will be injected into the spacer wall 670 of the selection transistor during the programming operation.

[0124] Similarly, the memory element and the selection transistor in the memory cell of the fourth embodiment of the present invention can both be P-channel transistors, or both be N-channel transistors.

[0125] Of course, the present invention can also modify the memory element in the fourth embodiment. For example, modify the gate structure so that the memory element has an L-shaped gate structure as Figure 4C shown, or a gate structure extending to an adjacent memory element as Figure 4D shown. Of course, it is also possible to, as Figure 4E shown, modify the channel width of the memory element. In addition, the assisted electrode 702 can also be in contact with the control gate layer 684. Or, the assisted electrode 702 can also be in contact with the spacer wall 630.

[0126] In summary, the present invention provides a memory cell of a non-volatile memory. The memory element in the memory cell is a transistor, and the memory element has an asymmetric spacer. In the memory element, a longer channel is provided under the wider spacer. When the memory element performs a programming operation, more carriers will be injected into the charge trapping layer of the spacer through the longer channel. Therefore, the memory cell of the present invention can perform the programming operation more efficiently and shorten the time of the programming operation.

[0127] Furthermore, the memory element of the present invention has a gate structure with a special shape. The sidewalls of the gate structure have multiple surfaces, and at least two surfaces of the sidewalls of the designed gate structure are adjacent to the second channel to form a wider spacer.

[0128] In summary, although the present invention is disclosed in combination with preferred embodiments, it is not intended to limit the present invention. Those of ordinary skill in the art to which the present invention pertains can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A memory cell of a non-volatile memory, the memory cell having a memory element, the memory element comprising: a well region; a gate structure formed on the surface of the well region, and the gate structure includes at least one protrusion; a spacer surrounding the sidewalls of the gate structure, and the spacer contacts the surface of the well region, wherein the spacer includes a first portion and a second portion; and a first doped region and a second doped region formed below the surface of the well region, and a channel region is between the first doped region and the second doped region, the channel region includes a first channel and a second channel; wherein, the sidewall of the gate structure includes a plurality of surfaces, and a first surface of the at least one protrusion is parallel to the channel length direction in the channel region; wherein, the first channel is located below the gate structure, the second channel is located between the first channel and the second doped region, and the first portion of the spacer is located above the second channel; wherein, the channel region further includes a third channel, the third channel is located between the first channel and the first doped region, the second portion of the spacer is located above the third channel, and the length of the second channel is greater than the length of the third channel; wherein, during a programming operation, a plurality of carriers are injected into a charge trapping layer in the first portion of the spacer via the second channel.

2. A memory cell of a non-volatile memory, the memory cell having a memory element, the memory element comprising: a well region; a gate structure formed on the surface of the well region, and the gate structure includes at least one protrusion; a spacer surrounding the sidewalls of the gate structure, and the spacer contacts the surface of the well region, wherein the spacer includes a first portion and a second portion; and a first doped region and a second doped region formed below the surface of the well region, and a channel region is between the first doped region and the second doped region, the channel region includes a first channel and a second channel; wherein, the sidewall of the gate structure includes a plurality of surfaces, and a first surface of the at least one protrusion is parallel to the channel length direction in the channel region; wherein, the first channel is located below the gate structure, the second channel is located between the first channel and the second doped region, and the first portion of the spacer is located above the second channel; wherein, during a programming operation, a plurality of carriers are injected into a charge trapping layer in the first portion of the spacer via the second channel; wherein, the first portion of the spacer surrounds the at least one protrusion, the first portion of the spacer has a first width, the second portion of the spacer has a second width, the first width is greater than the second width, and the first width is less than or equal to three times the second width.

3. The memory cell of the non-volatile memory according to claim 2, wherein the spacer includes a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer, the first silicon oxide layer contacts the surface of the well region and the sidewalls of the gate structure, the first silicon oxide layer is located above the second channel, the silicon nitride layer covers the first silicon oxide layer, the second silicon oxide layer covers the silicon nitride layer, and the silicon nitride layer is the charge trapping layer.

4. The memory cell of the non-volatile memory according to claim 2, wherein two surfaces of the sidewall of the gate structure are adjacent to the second channel.

5. The memory cell of the non-volatile memory according to claim 2, wherein the memory element further comprises: an auxiliary electrode and a dielectric layer, the auxiliary electrode being located above the first part of the spacer wall, and the dielectric layer being located between the auxiliary electrode and the first part of the spacer wall.

6. A memory cell of a non-volatile memory, the memory cell having a memory element, the memory element comprises: a well region; a gate structure formed on the surface of the well region, and the gate structure includes at least one protrusion; a spacer wall surrounding the sidewall of the gate structure, and the spacer wall contacts the surface of the well region, wherein the spacer wall includes a first part and a second part; and a first doped region and a second doped region formed below the surface of the well region, and a channel region is between the first doped region and the second doped region, the channel region includes a first channel and a second channel; wherein, the sidewall of the gate structure includes a plurality of surfaces, and a first surface of the at least one protrusion is parallel to the channel length direction in the channel region; wherein, the first channel is located below the gate structure, the second channel is located between the first channel and the second doped region, and the first part of the spacer wall is located above the second channel; wherein, during a programming operation, a plurality of carriers are injected into a charge trapping layer in the first part of the spacer wall via the second channel; wherein, the memory element further includes: an auxiliary electrode and a dielectric layer, the auxiliary electrode is located above the first part of the spacer wall, the dielectric layer is located between the auxiliary electrode and the first part of the spacer wall, and the auxiliary electrode contacts a control gate layer on the gate structure.

7. A memory cell of a non-volatile memory, the memory cell having a memory element, the memory element comprises: a well region; a gate structure formed on the surface of the well region, and the gate structure includes at least one protrusion; a spacer wall surrounding the sidewall of the gate structure, and the spacer wall contacts the surface of the well region, wherein the spacer wall includes a first part and a second part; and a first doped region and a second doped region formed below the surface of the well region, and a channel region is between the first doped region and the second doped region, the channel region includes a first channel and a second channel; wherein, the sidewall of the gate structure includes a plurality of surfaces, and a first surface of the at least one protrusion is parallel to the channel length direction in the channel region; wherein, the first channel is located below the gate structure, the second channel is located between the first channel and the second doped region, and the first part of the spacer wall is located above the second channel; wherein, during a programming operation, a plurality of carriers are injected into a charge trapping layer in the first part of the spacer wall via the second channel; wherein, the memory element further includes: an auxiliary electrode contacting the first part of the spacer wall.

8. The memory cell of the non-volatile memory according to claim 7, wherein the auxiliary electrode contacts a control gate layer on the gate structure.

9. The memory cell of the non-volatile memory as claimed in claim 7, wherein the gate structure includes a first protrusion and a second protrusion, the surfaces of the first protrusion and the second protrusion face each other and define an opening of the gate structure, and the spacer wall of the first portion contacts the surfaces of the first protrusion and the second protrusion.

10. A memory cell of a non-volatile memory, the memory cell comprising: a memory element, comprising: a well region, a first gate structure, a first spacer wall, a first doped region, and a second doped region; the first gate structure is formed on the surface of the well region, and the first gate structure includes at least one protrusion; the first spacer wall surrounds the sidewalls of the first gate structure, the first spacer wall contacts the surface of the well region, and the first spacer wall includes a first portion and a second portion; the first doped region and the second doped region are formed under the surface of the well region, and a channel region is between the first doped region and the second doped region, the channel region includes a first channel and a second channel; the sidewalls of the first gate structure include a plurality of surfaces, and the first surface of the at least one protrusion is parallel to the channel length direction in the channel region; the first channel is located under the first gate structure, the second channel is located between the first channel and the second doped region, and the first portion of the first spacer wall is located above the second channel; and a select transistor, comprising: the well region, a second gate structure, a second spacer wall, and a third doped region; the second gate structure is formed on the surface of the well region; the second spacer wall surrounds the sidewalls of the second gate structure, and the second spacer wall contacts the surface of the well region; the third doped region is formed under the surface of the well region; a fourth channel is between the first doped region and the third doped region, and the fourth channel is located under the second gate structure; wherein, the channel region further includes a third channel, the third channel is located between the first channel and the first doped region, the second portion of the spacer wall is located above the third channel, and the length of the second channel is greater than the length of the third channel; wherein, during a programming operation, a plurality of carriers are injected into a charge trapping layer in the first portion of the first spacer wall via the second channel of the memory element.

11. A memory cell of a non-volatile memory, the memory cell comprising: A storage element, comprising: a well region, a first gate structure, a first spacer, a first doped region, and a second doped region; the first gate structure is formed on the surface of the well region, and the first gate structure includes at least one protruding portion; the first spacer surrounds the sidewalls of the first gate structure, the first spacer contacts the surface of the well region, and the first spacer includes a first portion and a second portion; the first doped region and the second doped region are formed under the surface of the well region, and a channel region is between the first doped region and the second doped region, the channel region includes a first channel and a second channel; the sidewalls of the first gate structure include a plurality of surfaces, and a first surface of the at least one protruding portion is parallel to the channel length direction in the channel region; the first channel is located under the first gate structure, the second channel is located between the first channel and the second doped region, and the first portion of the first spacer is located above the second channel; and A select transistor, comprising: the well region, a second gate structure, a second spacer, and a third doped region; the second gate structure is formed on the surface of the well region; the second spacer surrounds the sidewalls of the second gate structure, and the second spacer contacts the surface of the well region; the third doped region is formed under the surface of the well region; a fourth channel is between the first doped region and the third doped region, and the fourth channel is located under the second gate structure; Wherein, during a programming operation, a plurality of carriers are injected into a charge trapping layer in the first portion of the first spacer via the second channel of the storage element; Wherein, the first portion of the first spacer surrounds the at least one protruding portion, the first portion of the first spacer has a first width, the second portion of the first spacer has a second width, the first width is greater than the second width, and the first width is less than or equal to three times the second width.

12. The memory cell of the non-volatile memory according to claim 11, wherein the first spacer includes a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer, the first silicon oxide layer contacts the surface of the well region and the sidewalls of the first gate structure, the first silicon oxide layer is located above the second channel, the silicon nitride layer covers the first silicon oxide layer, the second silicon oxide layer covers the silicon nitride layer, and the silicon nitride layer is the charge trapping layer.

13. The memory cell of the non-volatile memory according to claim 11, wherein two surfaces of the sidewalls of the first gate structure are adjacent to the second channel.

14. The memory cell of the non-volatile memory according to claim 11, wherein the storage element further comprises: An auxiliary electrode and a dielectric layer, the auxiliary electrode is located above the first portion of the first spacer, and the dielectric layer is located between the auxiliary electrode and the first portion of the first spacer.

15. A memory cell of a non-volatile memory, the memory cell comprises: A storage element, comprising: a well region, a first gate structure, a first spacer, a first doped region, and a second doped region; the first gate structure is formed on the surface of the well region, and the first gate structure includes at least one protrusion; the first spacer surrounds the sidewalls of the first gate structure, the first spacer contacts the surface of the well region, and the first spacer includes a first portion and a second portion; the first doped region and the second doped region are formed below the surface of the well region, and a channel region is between the first doped region and the second doped region, the channel region includes a first channel and a second channel; the sidewalls of the first gate structure include a plurality of surfaces, and a first surface of the at least one protrusion is parallel to the channel length direction in the channel region; the first channel is located below the first gate structure, the second channel is located between the first channel and the second doped region, and the first portion of the first spacer is located above the second channel; and A select transistor, comprising: the well region, a second gate structure, a second spacer, and a third doped region; the second gate structure is formed on the surface of the well region; the second spacer surrounds the sidewalls of the second gate structure, and the second spacer contacts the surface of the well region; the third doped region is formed below the surface of the well region; a fourth channel is between the first doped region and the third doped region, and the fourth channel is located below the second gate structure; Wherein, during a programming operation, a plurality of carriers are injected into a charge trapping layer in the first portion of the first spacer via the second channel of the storage element; Wherein, the storage element further includes: an auxiliary electrode and a dielectric layer, the auxiliary electrode is located above the first portion of the first spacer, the dielectric layer is located between the auxiliary electrode and the first portion of the first spacer, and the auxiliary electrode contacts a control gate layer on the first gate structure.

16. A storage cell of a non-volatile memory, the storage cell comprising: A storage element, comprising: a well region, a first gate structure, a first spacer, a first doped region, and a second doped region; the first gate structure is formed on the surface of the well region, and the first gate structure includes at least one protrusion; the first spacer surrounds the sidewalls of the first gate structure, the first spacer contacts the surface of the well region, and the first spacer includes a first portion and a second portion; the first doped region and the second doped region are formed below the surface of the well region, and a channel region is between the first doped region and the second doped region, the channel region includes a first channel and a second channel; the sidewalls of the first gate structure include a plurality of surfaces, and a first surface of the at least one protrusion is parallel to the channel length direction in the channel region; the first channel is located below the first gate structure, the second channel is located between the first channel and the second doped region, and the first portion of the first spacer is located above the second channel; and The select transistor includes: the well region, the second gate structure, the second spacer, and the third doped region; the second gate structure is formed on the surface of the well region; the second spacer surrounds the sidewalls of the second gate structure, and the second spacer contacts the surface of the well region; the third doped region is formed below the surface of the well region; a fourth channel is between the first doped region and the third doped region, and the fourth channel is located below the second gate structure; Wherein, during a programming operation, a plurality of carriers are injected via the second channel of the memory element into the charge trapping layer in the first portion of the first spacer; Wherein, the memory element further includes: an auxiliary electrode contacting the first portion of the first spacer.

17. The memory cell of the non-volatile memory according to claim 16, wherein the auxiliary electrode contacts the control gate layer on the first gate structure.

18. The memory cell of the non-volatile memory according to claim 16, wherein the first gate structure includes a first protrusion and a second protrusion, the surfaces of the first protrusion and the second protrusion face each other and define an opening of the first gate structure, and the first portion of the first spacer contacts the surfaces of the first protrusion and the second protrusion.

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