A capacitor structure and a method for forming the capacitor structure

Abstract

This disclosure relates to a capacitor structure and a method of forming a capacitor structure. A first capacitor is formed on a first side of a wafer, and a second capacitor is formed on a second side. The capacitor structure includes the first capacitor and the second capacitor. In this disclosure, trench capacitors are fabricated at both ends of an interposer, which can increase the capacitance value and thus significantly improve the power supply stability.

Description

Technical Field

[0001] This disclosure generally relates to semiconductors. More specifically, this disclosure relates to capacitor structures and methods of forming capacitor structures. Background Art

[0002] CoWoS (chip on wafer on substrate) is an integrated manufacturing technology. First, chips are connected to a silicon wafer through a CoW (chip on wafer) packaging process, and then the CoW chips are connected to a substrate to form CoWoS. Through this technology, multiple chips can be packaged together, and the bare chips on the plane are interconnected through a silicon interposer, achieving the technical effects of small packaging volume, low power consumption, and few pins. The power supply of CoWoS is provided by capacitor energy storage, and capacitors often use deep trench capacitor (DTC) technology to be manufactured.

[0003] The computing power of current chips is getting higher and higher, especially after the advent of deep learning chips. However, the capacitance values generated by current deep trench capacitor technology cannot support the requirements of high-performance computing chips. Therefore, high-capacitance trench capacitors are urgently needed. Summary of the Invention

[0004] To at least partially solve the technical problems mentioned in the background art, the solution of this disclosure provides a capacitor structure and a method of forming a capacitor structure.

[0005] In one aspect, this disclosure discloses a method of forming a capacitor structure on a wafer, the wafer including a first side and a second side opposite to the first side. The method includes: forming a first capacitor on the first side; and forming a second capacitor on the second side. Wherein the capacitor structure includes the first capacitor and the second capacitor.

[0006] In another aspect, the present disclosure discloses a capacitor structure including a first capacitor and a second capacitor on the other side. The second capacitor includes: a first conductive layer, a second dielectric layer, a second conductive layer, a first rewiring layer, a second rewiring layer, a first wafer bump, and a second wafer bump. The first conductive layer is disposed on the bottom regions and sidewalls of a plurality of deep trenches and above the surface of the wafer, with the width and depth of each deep trench corresponding to a specific ratio, and the plurality of deep trenches being spaced apart by a specific distance; the second dielectric layer is disposed above the first conductive layer; the second conductive layer is disposed above the second dielectric layer, and the second conductive layer fills the remaining portions of the plurality of deep trenches that are not filled by the first conductive layer and the second dielectric layer; the first rewiring layer is electrically connected to the first conductive layer; the second rewiring layer is electrically connected to the second conductive layer; the first wafer bump is electrically connected to the first rewiring layer; and the second wafer bump is electrically connected to the second rewiring layer. Wherein, the first wafer bump and the second wafer bump are the positive and negative electrodes of the second capacitor.

[0007] To increase the capacitance density, the solution of the present disclosure forms trench capacitors at both ends of the interposer to increase the capacitance value, thereby significantly improving the power supply stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the drawings, several embodiments of the present disclosure are shown in an exemplary but non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0009] Figure 1 shows the packaging process structure of CoW according to an embodiment of the present disclosure;

[0010] Figure 2 shows the packaging process structure of CoWoS according to an embodiment of the present disclosure;

[0011] Figure 3 is a flowchart showing a method for forming a capacitor structure according to an embodiment of the present disclosure;

[0012] Figure 4 is a flowchart showing a method for forming a first capacitor according to an embodiment of the present disclosure;

[0013] Figure 5 is a schematic diagram showing the formation of a first capacitor according to an embodiment of the present disclosure;

[0014] Figure 6 is a schematic diagram showing the formation of a first capacitor according to an embodiment of the present disclosure;

[0015] Figure 7 is a schematic diagram showing the packaging process structure of CoW according to another embodiment of the present disclosure;

[0016] Figure 8 is a flowchart showing the formation of a second capacitor in an embodiment of the present disclosure; and

[0017] Figure 9 is a packaging process structure of a CoW including a first capacitor and a second capacitor in an embodiment of the present disclosure. Detailed Description of the Invention

[0018] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0019] It should be understood that the terms "first", "second", "third", and "fourth", etc. in the claims, the description, and the drawings of the present disclosure are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "including" used in the description and claims of the present disclosure indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0020] It should also be understood that the terms used in the description of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used in the description and claims of the present disclosure, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms. It should be further understood that the term "and / or" used in the description and claims of the present disclosure refers to any combination and all possible combinations of one or more of the related listed items, and includes these combinations.

[0021] As used in this specification and the claims, the term "if" can be interpreted as "when" or "once" or "in response to a determination" or "in response to a detection" depending on the context.

[0022] The following will describe in detail the specific embodiments of the present disclosure with reference to the accompanying drawings.

[0023] Figure 1The packaging process structure of CoW is shown. In this structure, multiple through-silicon vias (TSVs) 102 are formed on a wafer 101. Through-silicon via technology is a high-density packaging technology used to replace wire bonding technology. By filling with conductive materials such as copper, tungsten, and polysilicon, vertical electrical interconnection of the through-silicon vias is achieved. This technology reduces the interconnection length through vertical interconnection, reduces signal delay and unnecessary capacitance / inductance, enables low-power, high-speed communication between chips, increases bandwidth, and realizes miniaturization of device integration.

[0024] Then, using the microbump preparation technology, microbumps 103 are formed to bond the chip to the wafer 101. The chip in the figure exemplarily shows a system-on-chip (SoC) 104 and multiple off-chip memories 105. The system-on-chip 104 is an integrated circuit with a dedicated target. In this disclosure, it can integrate one or more combined processing devices. The combined processing device can be an artificial intelligence computing unit used to support various deep learning and machine learning algorithms to meet the intelligent processing requirements in complex scenarios in fields such as computer vision, speech, natural language processing, and data mining. The off-chip memory 105 exemplarily shows a high bandwidth memory (HBM), which is a new type of memory chip that stacks multiple DDR chips together to achieve a large storage space. In practice, 2, 4, or 8 DDR chips can be stacked.

[0025] In addition to the system-on-chip 104 and the off-chip memory 105, the chips in this disclosure can also include various integrated circuits, such as various passive and active microelectronic devices, like resistors, other capacitor types (such as MIMCAP), inductors, diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused metal-oxide-semiconductor (LDMOS) transistors, high-power metal-oxide-semiconductor transistors, or other types of transistors, etc.

[0026] And CoWoS is formed by connecting a substrate on the basis of the Figure 1 CoW process. Figure 2 The packaging process structure of CoWoS is shown. First, the system-on-chip 104 and the off-chip memory 105 are filled with underfill, then solder balls 201 are placed and bonded to a substrate (such as a printed circuit board) 202, and finally, a package 203 is added to complete the process. CoWoS allows multiple chips to share the wafer 101. Generally speaking, the CoWoS technology can theoretically reduce the overall package thickness by up to 70%.

[0027] Embodiments of the present disclosure form multiple capacitors on the wafer 101 to supply power to the chip. The larger the generated capacitance value, the more stable the power supply. For deep learning chips with high power consumption, extremely large capacitance values are required. The present disclosure proposes a solution to form a capacitor structure on both the upper and lower sides of the wafer in the CoWoS process. The capacitor is a deep trench capacitor, which forms capacitance by etching multiple vertical trenches on the wafer. The more trenches, the larger the capacitance value.

[0028] An embodiment of the present disclosure is a method for forming a capacitor structure on both the upper and lower sides of a wafer, where the wafer includes a first side (upper side) and a second side (lower side) opposite to the first side. The method is as Figure 3 shown. In step 301, a first capacitor is formed on the first side; and in step 302, a second capacitor is formed on the second side. The capacitor structure includes a first capacitor and a second capacitor.

[0029] Step 301 can be understood by Figure 4 、 Figure 5 and Figure 6 and their descriptions, where Figure 4 shows the detailed process of step 301, Figure 5 and Figure 6 show its corresponding structure. The following description refers to Figure 4 、 Figure 5 and Figure 6 simultaneously.

[0030] In step 401, a first through-silicon via layer 502 and a second through-silicon via layer 503 are etched and formed on the first side of the wafer 501 using a photomask; in step 402, a first dielectric layer 504 is deposited on the first through-silicon via layer 502 and the second through-silicon via layer 503 using low-temperature chemical vapor deposition. The composition of the first dielectric layer 504 is silicon nitride. After this step is completed, a structure 51 is formed on the first side of the wafer 501.

[0031] Then, step 403 is executed to etch multiple deep trenches 505 on the first side. These deep trenches 505 are distributed between the first through-silicon via layer 502 and the second through-silicon via layer 503. In this embodiment, the notch shape of the deep trench 505 can be one of a rectangle, a trapezoid, a parallelogram, and a triangle. After this step is completed, a structure 52 is formed on the first side of the wafer 501.

[0032] In a possible case, the width W and the depth H of each deep trench 505 have a specific ratio, and the specific ratio ranges from 1:3 to 1:15. Preferably, the specific ratio ranges from 1:7 to 1:9. More preferably, the specific ratio is specifically 1:8.

[0033] In another possible case, the width W of each deep trench 505 ranges from 0.8 micrometers to 5 micrometers, and the depth H ranges from 3 micrometers to 15 micrometers. Preferably, the width W ranges from 1 micrometer to 1.2 micrometers, and the depth H ranges from 5.6 micrometers to 10.8 micrometers. More preferably, the width W is 1 micrometer and the depth H is 8 micrometers.

[0034] Each deep trench 505 is spaced apart by a specific distance D, and the specific distance D ranges from 0.5 micrometers to 4 micrometers. In this embodiment, the specific distance D is preferably 2 micrometers.

[0035] In step 404, a second dielectric layer 506 is deposited on the bottom, sidewalls, and the first dielectric layer 504 of the plurality of deep trenches 505, such that the thickness of the second dielectric layer 506 at the bottom of the deep trenches 505 is approximately 0.3 micrometers. After this step is completed, a structure 53 is formed on the first side of the wafer 501.

[0036] In step 405, the second dielectric layer 506 is polished. In this embodiment, chemical mechanical polishing (CMP) is used to polish the surface of the first side to be flat, such that the surfaces of all the through-silicon via layers ( Figure 5 only the second through-silicon via layer 503 is shown) are flush with the surface of the first side, that is, the surface of the second through-silicon via layer 503 is exposed on the first side. After this step is completed, a structure 54 is formed on the first side of the wafer 501.

[0037] In step 406, a first conductive layer 507 is deposited above the second dielectric layer 506; in step 407, a third dielectric layer 508 is deposited above the first conductive layer 507; in step 408, a second conductive layer 509 is deposited above the third dielectric layer 508. The second conductive layer 509 fills the remaining portions of the deep trenches 505 that are not filled by the first conductive layer 507 and the third dielectric layer 508, that is, the deep trenches 505 are filled by the first conductive layer 507, the third dielectric layer 508, and the second conductive layer 509. The third dielectric layer 508 is used to electrically isolate the first conductive layer 507 and the second conductive layer 509. After this step is completed, a structure 55 is formed on the first side of the wafer 501.

[0038] In step 409, a first redistribution layer 510 is deposited and electrically connected to the first conductive layer 507. More specifically, through the layout arrangement of the photomask, a fourth dielectric layer 511 is first deposited, and then the first redistribution layer 510 is deposited. The first redistribution layer 510 is electrically connected to the first through-silicon via layer 502 at the same time; in step 410, a second redistribution layer 512 is deposited and electrically connected to the second conductive layer 509. Through the layout arrangement of the photomask, the second redistribution layer 512 is first deposited, and then the fifth dielectric layer 513 is deposited. The second redistribution layer 512 is electrically connected to the second through-silicon via layer 503 at the same time. After this step is completed, a structure 56 is formed on the first side of the wafer 501.

[0039] In step 411, a first wafer bump 514 is formed on the first through-silicon via layer 502, and the first wafer bump 514 is electrically connected to the first redistribution layer 510; in step 412, a second wafer bump 515 is formed on the second through-silicon via layer 503, and the second wafer bump 515 is electrically connected to the second redistribution layer 512. Preferably, the distance D1 between the first wafer bump 514 and the second wafer bump 515 is 60 microns, and the center distance D2 is 130, 150 or 180 microns.

[0040] The first wafer bump 514 and the second wafer bump 515 adopt the C4 (controlled collapse chip connection) process and serve as the positive and negative electrodes of the first capacitor. More specifically, the charge on one side passes through the first wafer bump 514, the first redistribution layer 510 (the first through-silicon via layer 502), and is stored in the first conductive layer 507 of the deep trench 505, while the charge on the other side passes through the second wafer bump 515, the second redistribution layer 512 (the second through-silicon via layer 503), and is stored in the second conductive layer 509 on the deep trench 505. The first conductive layer 507 and the second conductive layer 509 are electrically isolated by the third dielectric layer 508. The overall structure forms a first capacitor.

[0041] Finally, the chip is attached to the first wafer bump 514 and the second wafer bump 515, and the CoW package manufacturing process structure as shown in Figure 7 is formed. The difference from the Figure 1 CoW package manufacturing process structure is that the CoW package manufacturing process structure of this embodiment forms a first capacitor 702 on the first side 701.

[0042] In this embodiment, in addition to the Figure 1 system-on-chip 104 and off-chip memory 105 in

[0043] The chip can also include other various types of chips, which will not be elaborated here. Figure 3, after performing step 301, step 302 is then executed to form a second capacitor on the second side of the wafer 501. To perform this step, the CoW package manufacturing process structure of Figure 7 is flipped so that the second side 703 of the wafer faces upward, and a second capacitor is fabricated on this side.

[0044] Step 302 can also be refined into Figure 5 , Figure 6 and Figure 8 . In step 801, a first dielectric layer 504 is deposited on the first through-silicon via layer 502 and the second through-silicon via layer 503 by low-temperature chemical vapor deposition. The composition of the first dielectric layer 504 is also silicon nitride. After this step is completed, structure 51 is formed on the second side of the wafer 501.

[0045] Then step 802 is executed to etch a plurality of deep trenches 505 on the second side. These deep trenches 505 are distributed between the first through-silicon via layer 502 and the second through-silicon via layer 503. In this embodiment, the notch shape of the deep trench 505 is one of a rectangle, a trapezoid, a parallelogram, and a triangle. After this step is completed, structure 52 is formed on the second side of the wafer 501.

[0046] In a possible case, the width W and the depth H of each deep trench 505 are in a specific ratio, and the specific ratio is between 1:3 and 1:15. Preferably, the specific ratio is between 1:7 and 1:9. More preferably, the specific ratio is specifically 1:8.

[0047] In a possible case, the width W of each deep trench 505 is between 0.8 micrometers and 5 micrometers, and the depth H is between 3 micrometers and 15 micrometers. Preferably, the width W is between 1 micrometer and 1.2 micrometers, and the depth H is between 5.6 micrometers and 10.8 micrometers. More preferably, the width W is 1 micrometer and the depth H is 8 micrometers.

[0048] Each deep trench 505 is spaced a specific distance D, and the specific distance D is between 0.5 micrometers and 4 micrometers. In this embodiment, the specific distance D is preferably 2 micrometers.

[0049] In step 803, a second dielectric layer 506 is deposited on the bottom, sidewalls, and the first dielectric layer 504 of the plurality of deep trenches 505 such that the thickness of the second dielectric layer 506 at the bottom of the deep trenches 505 is about 0.3 micrometers. After this step is completed, structure 53 is formed on the second side of the wafer 501.

[0050] In step 804, the second dielectric layer 506 is polished. In this embodiment, chemical mechanical polishing is used to polish the surface of the second side to make it flat, and all the through-silicon via layers ( Figure 5Only the surface of the second through-silicon via layer 503) is shown to be flush with the second side surface, that is, the surface of the second through-silicon via layer 503 is exposed on the second side. After this step is completed, structure 54 is formed on the second side of the wafer 501.

[0051] In step 805, a first conductive layer 507 is deposited above the second dielectric layer 506; in step 806, a third dielectric layer 508 is deposited above the first conductive layer 507; in step 807, a second conductive layer 509 is deposited above the third dielectric layer 508, and the second conductive layer 509 fills the remaining part of the deep trench 505 that is not filled by the first conductive layer 507 and the third dielectric layer 508, that is, the deep trench 505 is filled by the first conductive layer 507, the third dielectric layer 508, and the second conductive layer 509. The third dielectric layer 508 is used to electrically isolate the first conductive layer 507 and the second conductive layer 509. After this step is completed, structure 55 is formed on the second side of the wafer 501.

[0052] In step 808, a first redistribution layer 510 is deposited and electrically connected to the first conductive layer 507. More specifically, through the layout arrangement of the photomask, a fourth dielectric layer 511 is first deposited, and then the first redistribution layer 510 is deposited, where the first redistribution layer 510 is electrically connected to the first through-silicon via layer 502. In step 809, a second redistribution layer 512 is deposited and electrically connected to the second conductive layer 509. Through the layout arrangement of the photomask, the second redistribution layer 512 is first deposited, and then a fifth dielectric layer 513 is deposited, where the second redistribution layer 512 is electrically connected to the second through-silicon via layer 503. After this step is completed, structure 56 is formed on the second side of the wafer 501.

[0053] In step 810, a first wafer bump 514 is formed on the first through-silicon via layer 502, and the first wafer bump 514 is electrically connected to the first redistribution layer 510; in step 811, a second wafer bump 515 is formed on the second through-silicon via layer 503, and the second wafer bump 515 is electrically connected to the second redistribution layer 512. Preferably, the pitch D1 between the first wafer bump 514 and the second wafer bump 515 is 60 microns, and the center distance D2 is 130, 150, or 180 microns.

[0054] The first wafer bump 514 and the second wafer bump 515 also adopt the C4 process and serve as the positive and negative electrodes of the second capacitor. The charge on one side passes through the first wafer bump 514, the first redistribution layer 510 (the first through-silicon via layer 502), and is stored in the first conductive layer 507 of the deep trench 505, while the charge on the other side passes through the second wafer bump 515, the second redistribution layer 512 (the second through-silicon via layer 503), and is stored in the second conductive layer 509 of the deep trench 505. The first conductive layer 507 and the second conductive layer 509 are electrically isolated by the third dielectric layer 508.

[0055] Figure 9 Disclosed is a CoW package manufacturing structure including a first capacitor and a second capacitor. In this embodiment, a first capacitor 702 is formed on a first side 701 of a wafer, and a second capacitor 901 is formed on a second side 703. The first capacitor 702 and the second capacitor 901 are electrically connected through a through-silicon via layer. Finally, Figure 9 the chip is filled with underfill, bonded to a printed circuit board, and then packaged, thus completing a CoWoS package manufacturing structure similar to Figure 2 that shown. Due to the presence of the first capacitor 702 and the second capacitor 901, this manufacturing process provides a large capacitance value and stabilizes the power supply of the chip.

[0056] Another embodiment of the present disclosure is a capacitor structure as Figure 9 shown, which includes a first capacitor 702 located on a first side 701 of the wafer and a second capacitor 901 located on a second side 703 of the wafer, and they are electrically connected to each other. The following description refers to Figure 5 , Figure 6 and Figure 9 simultaneously. Both the first capacitor 702 and the second capacitor 901 include: a first conductive layer 507, a third dielectric layer 508, a second conductive layer 509, a first redistribution layer 510, a second redistribution layer 512, a first wafer bump 514, and a second wafer bump 515.

[0057] The first conductive layer 507 is disposed above the bottom regions and sidewalls of a plurality of deep trenches 505 and the surface of the wafer 501. In one possible case, the width W and the depth H of each deep trench 505 are in a specific ratio, and the specific ratio ranges from 1:3 to 1:15. Preferably, the specific ratio ranges from 1:7 to 1:9. More preferably, the specific ratio is specifically 1:8. In another possible case, the width W of each deep trench 505 ranges from 0.8 μm to 5 μm, and the depth H ranges from 3 μm to 15 μm. Preferably, the width W ranges from 1 μm to 1.2 μm, and the depth H ranges from 5.6 μm to 10.8 μm. More preferably, the width W is 1 μm and the depth H is 8 μm. Each deep trench 505 is spaced at a specific distance D, and the specific distance D ranges from 0.5 μm to 4 μm. In this embodiment, the specific distance D is preferably 2 μm. The notch of the deep trench 505 can be one of a rectangle, a trapezoid, a parallelogram, and a triangle.

[0058] The third dielectric layer 508 is disposed above the first conductive layer 507; the second conductive layer 509 is disposed above the third dielectric layer 508, and the second conductive layer 509 fills the remaining part of the deep trenches 505 not filled by the first conductive layer 507 and the third dielectric layer 508.

[0059] The first wiring layer 510 is electrically connected to the first conductive layer 507, the second wiring layer 512 is electrically connected to the second conductive layer 509, the first wafer bump 514 is electrically connected to the first wiring layer 510, and the second wafer bump 515 is electrically connected to the second wiring layer 512. Among them, the first wafer bump 514 and the second wafer bump 515 are the positive and negative electrodes of the first capacitor 702 and the second capacitor 901.

[0060] The solution disclosed in this disclosure improves the capacitance density of trench capacitors by arranging the first capacitor and the second capacitor on the upper and lower sides of the wafer, thereby increasing the capacitance value and significantly enhancing the power supply stability.

[0061] The foregoing can be better understood according to the following terms:

[0062] Clause A1. A method for forming a capacitor structure on a wafer, the wafer including a first side and a second side opposite to the first side, the method comprising: forming a first capacitor on the first side; and forming a second capacitor on the second side; wherein the capacitor structure includes the first capacitor and the second capacitor.

[0063] Clause A2. The method according to Clause A1, wherein the step of forming the second capacitor includes: forming a first through-silicon via layer and a second through-silicon via layer; and depositing a first dielectric layer on the first through-silicon via layer and the second through-silicon via layer.

[0064] Clause A3. The method according to Clause A2, wherein the step of forming the second capacitor further includes: etching a plurality of deep trenches on the second side, the width and depth of each deep trench corresponding to a specific ratio, the plurality of deep trenches being spaced apart by a specific distance; depositing a second dielectric layer on the bottom, sidewalls of the plurality of deep trenches, and the first dielectric layer; depositing a first conductive layer above the second dielectric layer; depositing a third dielectric layer above the first conductive layer; depositing a second conductive layer above the third dielectric layer, the second conductive layer filling the remaining portions of the plurality of deep trenches not filled by the first conductive layer and the third dielectric layer; depositing a first wiring layer electrically connected to the first conductive layer; and depositing a second wiring layer electrically connected to the second conductive layer. Among them, the first wiring layer is electrically connected to the first through-silicon via layer, and the second wiring layer is electrically connected to the second through-silicon via layer.

[0065] Clause A4. The method according to Clause A3, wherein the step of forming the second capacitor further includes: forming a first wafer bump on the first through-silicon via layer, the first wafer bump being electrically connected to the first redistribution layer; and forming a second wafer bump on the second through-silicon via layer, the second wafer bump being electrically connected to the second redistribution layer. Wherein, the first wafer bump and the second wafer bump are the positive and negative electrodes of the second capacitor.

[0066] Clause A5. The method according to Clause A4, wherein the step of forming the first wafer bump and the second wafer bump adopts the C4 process.

[0067] Clause A6. The method according to Clause A4, wherein the distance between the first wafer bump and the second wafer bump is 60 microns.

[0068] Clause A7. The method according to Clause A4, wherein the center distance between the first wafer bump and the second wafer bump is 150 microns.

[0069] Clause A8. The method according to Clause A3, wherein the plurality of deep trenches are located between the first through-silicon via layer and the second through-silicon via layer.

[0070] Clause A9. The method according to Clause A3, wherein the notch shape of the deep trench is one of a rectangle, a trapezoid, a parallelogram, and a triangle.

[0071] Clause A10. The method according to Clause A3, wherein the specific ratio is between 1:3 and 1:15.

[0072] Clause A11. The method according to Clause A10, wherein the specific ratio is between 1:7 and 1:9.

[0073] Clause A12. The method according to Clause A11, wherein the specific ratio is 1:8.

[0074] Clause A13. The method according to Clause A3, wherein the width is between 0.8 microns and 5 microns, and the depth is between 3 microns and 15 microns.

[0075] Clause A14. The method according to Clause A13, wherein the width is between 1 micron and 1.2 microns, and the depth is between 5.6 microns and 10.8 microns.

[0076] Clause A15. The method according to Clause A14, wherein the width is 1 micron and the depth is 8 microns.

[0077] Clause A16. The method according to Clause A3, wherein the specific distance is between 0.5 microns and 4 microns.

[0078] Clause A17. The method according to Clause A16, wherein the specific distance is 2 micrometers.

[0079] Clause A18. The method according to Clause A3, further comprising polishing the second dielectric layer before depositing the first conductive layer.

[0080] Clause A19. The method according to Clause A1, further comprising: mounting a system or off-chip memory on the first side chip.

[0081] Clause A20. A capacitor structure comprising a first capacitor and a second capacitor on the other side. The second capacitor includes: a first conductive layer disposed above the bottom regions and sidewalls of a plurality of deep trenches and the surface of the wafer, the width and depth of each deep trench corresponding to a specific ratio, the plurality of deep trenches being spaced a specific distance apart; a third dielectric layer disposed above the first conductive layer; a second conductive layer disposed above the third dielectric layer, the second conductive layer filling the remaining portions of the plurality of deep trenches not filled by the first conductive layer and the third dielectric layer; a first rewiring layer electrically connected to the first conductive layer; a second rewiring layer electrically connected to the second conductive layer; a first wafer bump electrically connected to the first rewiring layer; and a second wafer bump electrically connected to the second rewiring layer. Wherein, the first wafer bump and the second wafer bump are the positive and negative electrodes of the second capacitor.

[0082] Clause A21. The capacitor structure according to Clause A20, wherein the notch of the deep trench is one of a rectangle, a trapezoid, a parallelogram, and a triangle.

[0083] Clause A22. The capacitor structure according to Clause A20, wherein the specific ratio is between 1:7 and 1:9.

[0084] Clause A23. The capacitor structure according to Clause A22, wherein the specific ratio is 1:8.

[0085] Clause A24. The capacitor structure according to Clause A20, wherein the width is between 0.8 micrometers and 1.2 micrometers, and the depth is between 5.6 micrometers and 10.8 micrometers.

[0086] Clause A25. The capacitor structure according to Clause A24, wherein the width is 1 micrometer and the depth is 8 micrometers.

[0087] Clause A26. The capacitor structure according to Clause A20, wherein the specific distance is between 0.5 micrometers and 4 micrometers.

[0088] Clause A27. The capacitor structure according to Clause A26, wherein the specific distance is 2 micrometers.

[0089] The embodiments of the present disclosure have been introduced in detail above. Specific examples are used herein to illustrate the principle and implementation manner of the present disclosure. The description of the above embodiments is only for helping to understand the method and its core idea of the present disclosure; at the same time, for those of ordinary skill in the art, according to the idea of the present disclosure, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation on the present disclosure.

Claims

1. A method for forming a capacitor structure on a wafer, the wafer including a first side and a second side opposite to the first side, the method comprising: forming a first capacitor on the first side; and forming a second capacitor on the second side; wherein the capacitor structure includes the first capacitor and the second capacitor; wherein the step of forming the second capacitor includes: forming a first through-silicon via layer and a second through-silicon via layer; and depositing a first dielectric layer on the first through-silicon via layer and the second through-silicon via layer; etching a plurality of deep trenches on the second side, wherein the width and depth of each deep trench correspond to a specific ratio, and the plurality of deep trenches are spaced apart by a specific distance; depositing a second dielectric layer on the bottoms, sidewalls of the plurality of deep trenches, and the first dielectric layer; depositing a first conductive layer above the second dielectric layer; depositing a third dielectric layer above the first conductive layer; depositing a second conductive layer above the third dielectric layer, the second conductive layer filling the remaining portions of the plurality of deep trenches not filled by the first conductive layer and the third dielectric layer; depositing a first redistribution layer electrically connected to the first conductive layer; and depositing a second redistribution layer electrically connected to the second conductive layer; wherein the first redistribution layer is electrically connected to the first through-silicon via layer, and the second redistribution layer is electrically connected to the second through-silicon via layer.

2. The method according to claim 1, wherein the step of forming the second capacitor further includes: forming a first wafer bump on the first through-silicon via layer, the first wafer bump being electrically connected to the first redistribution layer; and forming a second wafer bump on the second through-silicon via layer, the second wafer bump being electrically connected to the second redistribution layer; wherein the first wafer bump and the second wafer bump are the positive and negative electrodes of the second capacitor.

3. The method according to claim 2, wherein the steps of forming the first wafer bump and the second wafer bump employ a C4 process.

4. The method according to claim 2, wherein the distance between the first wafer bump and the second wafer bump is 60 microns.

5. The method according to claim 2, wherein the center distance between the first wafer bump and the second wafer bump is 150 microns.

6. The method according to claim 1, wherein the plurality of deep trenches are located between the first through-silicon via layer and the second through-silicon via layer.

7. The method according to claim 1, wherein the notch shape of the deep trench is one of a rectangle, a trapezoid, a parallelogram, and a triangle.

8. The method according to claim 1, wherein the specific ratio is between 1:3 and 1:

15.

9. The method according to claim 8, wherein the specific ratio is between 1:7 and 1:

9.

10. The method according to claim 9, wherein the specific ratio is 1:

8.

11. The method according to claim 1, wherein the width is between 0.8 microns and 5 microns, and the depth is between 3 microns and 15 microns.

12. The method according to claim 11, wherein the width is between 1 micrometer and 1.2 micrometers, and the depth is between 5.6 micrometers and 10.8 micrometers.

13. The method according to claim 12, wherein the width is 1 micrometer and the depth is 8 micrometers.

14. The method according to claim 1, wherein the specific distance is between 0.5 micrometer and 4 micrometers.

15. The method according to claim 14, wherein the specific distance is 2 micrometers.

16. The method according to claim 1, further comprising polishing the second dielectric layer before depositing the first conductive layer.

17. The method according to claim 1, further comprising: mounting a system or off-chip memory on the first side chip attachment pad.

18. A capacitor structure, comprising a first capacitor and a second capacitor on the other side, the second capacitor comprising: a first conductive layer disposed above the bottom regions and sidewalls of a plurality of deep trenches and the surface of the wafer, the width and depth of each deep trench corresponding to a specific ratio, the plurality of deep trenches being spaced apart by a specific distance; a third dielectric layer disposed above the first conductive layer; a second conductive layer disposed above the third dielectric layer, the second conductive layer filling the remaining portions of the plurality of deep trenches not filled by the first conductive layer and the third dielectric layer; a first redistribution layer electrically connecting the first conductive layer; a second redistribution layer electrically connecting the second conductive layer; a first wafer bump electrically connecting the first redistribution layer; and a second wafer bump electrically connecting the second redistribution layer; wherein the first wafer bump and the second wafer bump are the positive and negative electrodes of the second capacitor.

19. The capacitor structure according to claim 18, wherein the notch of the deep trench is one of a rectangle, a trapezoid, a parallelogram, and a triangle.

20. The capacitor structure according to claim 18, wherein the specific ratio is between 1:7 and 1:

9.

21. The capacitor structure according to claim 20, wherein the specific ratio is 1:

8.

22. The capacitor structure according to claim 18, wherein the width is between 0.8 micrometer and 1.2 micrometers, and the depth is between 5.6 micrometers and 10.8 micrometers.

23. The capacitor structure according to claim 22, wherein the width is 1 micrometer and the depth is 8 micrometers.

24. The capacitor structure according to claim 18, wherein the specific distance is between 0.5 micrometer and 4 micrometers.

25. The capacitor structure according to claim 24, wherein the specific distance is 2 micrometers.

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