Drive control circuit

Abstract

The present invention provides a drive control circuit. According to one embodiment, the drive control circuit includes: a first transistor that supplies current to the gate of an output transistor in response to a drive signal; a second transistor that supplies current to a capacitor in response to the drive signal; a comparison circuit that compares the gate voltage of the output transistor with the voltage of the capacitor; a control signal generation circuit that generates a control signal in response to the output signal of the comparison circuit and the drive signal; and a third transistor that supplies current to the gate of the output transistor in response to the control signal.

Description

[0001] This application claims the benefit of priority of Japanese Patent Application No. 2020-154310, filed on September 15, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This embodiment generally relates to a drive control circuit. Background Art

[0003] Conventionally, there has been disclosed a technique in which, in a drive control circuit that controls the on / off of an output transistor, the driving ability of a driving element that drives the output transistor is adjusted based on a pre-stored threshold value, taking into account both the high-speed switching of the output transistor and the suppression of EMI noise. In the case of a configuration that uses the threshold value of the output transistor stored in advance, a threshold value storage circuit is required, and the circuit configuration becomes complicated. There is a need for a drive control circuit that can detect the threshold value of the output transistor and adjust the driving ability of the driving element with a simple configuration. Summary of the Invention

[0004] One embodiment of the present invention provides a drive control circuit that can detect the threshold value of an output transistor and adjust the driving ability of a driving element with a simple configuration.

[0005] According to one embodiment, the drive control circuit includes: a first drive transistor that supplies a drive current to the gate of the output transistor in response to a drive signal; a first capacitor having one end applied with a reference potential; a second drive transistor that supplies a charging current to the other end of the first capacitor in response to the drive signal; a first comparison circuit that compares the gate voltage of the output transistor with the voltage at the other end of the first capacitor and outputs a first detection signal based on the result; a first control signal generation circuit that generates a first control signal in response to the first detection signal and the drive signal; and a third drive transistor that supplies a drive current to the gate of the output transistor in response to the first control signal. Brief Description of the Drawings

[0006] Figure 1 It is a diagram showing the configuration of the drive control circuit according to the first embodiment.

[0007] Figure 2 It is a diagram for explaining the change in the gate capacitance of the output transistor.

[0008] Figure 3 It is a diagram schematically showing the voltage relationship of each node.

[0009] Figure 4 It is a diagram for explaining the relationship between the gate voltage of the output transistor and the reference voltage.

[0010] Figure 5 This is a diagram for explaining the effects of the first embodiment.

[0011] Figure 6 This is a diagram showing the configuration of the drive control circuit of the second embodiment.

[0012] Figure 7 This is a diagram for explaining the relationship between the gate voltage of the output transistor and the reference voltage. Detailed implementation mode

[0013] Hereinafter, the drive control circuit of the embodiment will be described in detail with reference to the accompanying drawings. In addition, the present invention is not limited by these embodiments.

[0014] (First embodiment)

[0015] Figure 1 This is a diagram showing the configuration of the drive control circuit of the first embodiment. This embodiment has a drive circuit 10. The drive circuit 10 outputs switching signals V S , V S1 . The switching signals V S , V S1 are provided with a so-called dead time so that the drive transistors Q11 and Q13 and Q12 and Q14 are not turned on simultaneously.

[0016] This embodiment has buffers 11 and 12. The buffer 11 shapes the waveform of the switching signal V S and supplies it to the gate of the drive transistor Q11. The buffer 12 shapes the waveform of the switching signal V S1 and supplies it to the gate of the drive transistor Q13.

[0017] The source of the drive transistor Q11 is applied with the power supply voltage VDD, and the drain is connected to the drain of the drive transistor Q13. The common connection end N1 of the drains of the drive transistors Q11 and Q13 is connected to the gate of the output transistor Q1. The drain of the output transistor Q1 is connected to the output terminal 13. The source of the drive transistor Q13 is grounded. The drive transistor Q11 supplies a drive current to the gate of the output transistor Q1 in the on state. The drive transistor Q13 discharges the charge of the gate capacitance of the output transistor Q1 in the on state.

[0018] This embodiment has a reference voltage generation circuit 40. The reference voltage generation circuit 40 has drive transistors Q12, Q14, and a capacitor C R . The capacitor C ROne end of it is grounded and a ground potential which is applied as a reference potential is applied. The source of the driving transistor Q12 is applied with the power supply voltage VDD, and the drain is connected to the drain of the driving transistor Q14. The common connection terminal N2 of the drains of the driving transistors Q12 and Q14 is connected to the non-inverting input terminal (+) of the comparison circuit 30. The on / off states of the driving transistors Q12 and Q14 are controlled by the outputs of the buffers 11 and 12 respectively. When the driving transistor Q12 is in the on state, a charging current is supplied to charge the capacitor C R When the driving transistor Q14 is in the on state, the charge of the capacitor C R is discharged.

[0019] Based on the time constant determined by the gate-source capacitance C GS of the output transistor Q1 and the driving ability of the driving transistor Q11, and the driving ability of the driving transistor Q12, the value of the capacitor C R is set. For example, it is set such that the time for charging the gate-source capacitance C GS of the output transistor Q1 to a specified voltage by the driving transistor Q11 is the same as the time for charging the capacitor C R to its specified voltage by the driving transistor Q12. Therefore, the potential at one end of the capacitor C R and the potential of the source of the output transistor Q1 do not necessarily need to be the same potential.

[0020] For example, when the value of the capacitor C R is set to 1 / 2 of the gate-source capacitance C GS of the output transistor Q1, the driving ability of the driving transistor Q12 is set to 1 / 2 of the driving ability of the driving transistor Q11. Thereby, the size of the driving transistor Q12 can be reduced and the power consumption can be lowered. In addition, the driving ability mentioned here refers to the supply ability of the driving current.

[0021] This embodiment has a comparison circuit 30. The common connection terminal N1 is connected to the inverting input terminal (-) of the comparison circuit 30. The comparison circuit 30 compares the voltage at the common connection terminal N1, that is, the gate voltage V G of the output transistor Q1, with the voltage at the common connection terminal N2, that is, the reference voltage V R at the other end side of the capacitor C of the reference voltage generation circuit 40, and outputs a detection signal V R C C according to the comparison result.

[0022] The comparison circuit 30 has, for example, a hysteresis characteristic. By making the comparison circuit 30 have a hysteresis characteristic, for example, malfunction of the comparison circuit 30 due to noise or the like can be avoided.

[0023] This embodiment has a control signal generation circuit 20. A detection signal V is supplied to the control signal generation circuit 20. C And a switch signal V S . The control signal generation circuit 20 responds to the detection signal V C And the switch signal V S And outputs a control signal V D . The control signal V D Controls the on / off of the driving transistor Q10. The control signal generation circuit 20 can be constituted by a latch circuit that responds to the detection signal V C And the switch signal V S .

[0024] The driving ability of the driving transistor Q10 is set to be higher than that of the driving transistor Q11. For example. By making the size (gate width) of the driving transistor Q10 larger than that of the driving transistor Q11, the driving ability of the driving transistor Q10 can be improved.

[0025] Use Figures 2 to 4 To illustrate the circuit operation of this embodiment. Figure 2 Represents the relationship between the gate capacitance and the gate voltage of the output transistor Q1. The horizontal axis represents the gate voltage of the output transistor Q1, and the vertical axis represents the gate capacitance. In the state where the gate voltage is lower than the threshold, the gate capacitance of the output transistor Q1 is the gate-source capacitance C GS . When the gate voltage becomes high and reaches the threshold, the gate capacitance becomes the gate-drain capacitance C GD . When the gate voltage becomes high beyond the threshold, the gate capacitance becomes C GS And C GD The sum of which is C GS +C GD .

[0026] When the gate voltage reaches the threshold, the gate capacitance of the output transistor Q1 becomes the gate-drain capacitance C GD , and a "Plateau" where the gate voltage becomes constant in the interval from V1 to V2 is generated. In this embodiment, the gate voltage of the output transistor Q1 in this plateau interval is detected as the threshold of the output transistor Q1.

[0027] The capacitor C of the reference voltage generation circuit 40 is charged by the driving current of the driving transistor Q12 R , and the reference voltage V R Rises at a certain slope. On the other hand, the gate voltage V of the output transistor Q1 G Becomes constant in the plateau generated by the threshold. Therefore, by comparing the reference voltage V R With the gate voltage V GWhen compared, it is possible to easily detect the case where the gate voltage V G reaches the threshold of the output transistor Q1.

[0028] Figure 3 is a diagram schematically showing the voltage relationships of the respective nodes. The solid line 100 in the upper part represents the switch signal V S . At timing t00, the switch signal V S is at the L level.

[0029] The next part represents the gate voltage V G and the reference voltage V R . The dashed-dotted line 101 represents the reference voltage V R , and the solid line 102 represents the gate voltage V G . The drive transistors Q11 and Q12 turn on in response to the switch signal V S , and at timing t0, the reference voltage V R and the gate voltage V G of the output transistor Q1 start to rise. At timing t1, it is detected that the reference voltage V R becomes higher than the gate voltage V G , and reaches the threshold of the output transistor Q1. At timing t2, the gate voltage V G becomes higher than the reference voltage V R .

[0030] The solid line 103 in the next part represents the detection signal V C of the comparison circuit 30. The comparison circuit 30 outputs a detection signal V R at the H level at timing t1 when the reference voltage V G becomes higher than the gate voltage V C .

[0031] The solid line 104 in the next part represents the control signal V D output by the control signal generation circuit 20. The control signal V D changes to the L level in response to the detection signal V C at the H level, turning on the drive transistor Q10. Thereby, the ability to supply drive current to the gate of the output transistor Q1 can be improved. The control signal generation circuit 20 maintains the L level until timing t3 when the switch signal V S becomes the H level.

[0032] The solid line 105 in the lower part represents the output voltage V out . When the gate voltage V G of the output transistor Q1 reaches the threshold, the gate of the output transistor Q1 is charged with the current obtained by adding the drive current of the drive transistor Q11 and the drive current of the drive transistor Q10, and the output voltage Vout The output transistor Q1 is switched to L level when the switching signal V S At the timing t3 when the voltage becomes H level, the output voltage V out becomes H level.

[0033] According to this embodiment, the gate voltage V G With reference voltage V R By comparing the gate voltage V of the output transistor Q1, it is easy to detect G When the gate voltage V G Before reaching the threshold, only the driving transistor Q11 with a smaller driving capability is activated, thereby suppressing the rush current to the gate of the output transistor Q1. In this way, EMI noise is reduced. In addition, when the gate voltage V is detected, G After reaching the threshold, the driving transistor Q10 with a higher driving capability is turned on and driven together with the driving transistor Q11, thereby increasing the driving capability. Thus, the switching speed of the output transistor Q1 can be increased.

[0034] Figure 4 Amplified gate voltage V G With reference voltage V R The single-dot chain line 101 represents the reference voltage V R , solid line 102 represents the gate voltage V G . Response to switch signal V S The driving transistor Q12 is turned on, and thus at timing t0 the capacitor C of the reference voltage generating circuit 40 is R Start charging, reference voltage V R On the other hand, the gate voltage V G The voltage also rises at timing t0 when the driving transistor Q11 is turned on, but becomes constant at timing t1 when a plateau is generated.

[0035] The timing t1 is detected by the comparison circuit 30. C The control signal V D The driving transistor Q10 with high driving capability is turned on, thereby outputting the gate voltage V G rises sharply and becomes higher than the reference voltage V at timing t2 R .

[0036] Figure 5 1 is a diagram for explaining the effect of the present embodiment. The horizontal axis represents time, and the vertical axis schematically represents the rush current to the gate of the output transistor Q1. Figure 5 A solid line 110 shows a case where the output transistor Q1 is driven using only the drive transistor having a relatively high drive capability.

[0037] When driving is performed by a driving transistor with a higher driving ability, the inrush current reaches the current value I10 in a short time from the timing t0 to t12 when the response switch signal V S turns on. Due to the higher driving ability, the peak value of the inrush current becomes a larger current value I10. The solid line 111 represents the case of this embodiment. Before the timing t1 when the gate voltage V G becomes the threshold value, driving is performed by a driving transistor Q11 with a smaller driving ability. Therefore, the inrush current is suppressed to I20. Since the inrush current is suppressed, the gate voltage V G of the output transistor Q1 rises gently. Thus, the change rate dV / dt of the gate voltage V G becomes smaller, and EMI noise is suppressed.

[0038] After the timing t1 when the threshold value is reached, the driving transistor Q10 with a higher driving ability is turned on and operates together with the driving transistor Q11 to increase the driving ability. Thus, the switching speed of the output transistor Q1 is increased. At the timing t1, since the gate voltage V G of the output transistor Q1 has already risen, the inrush current is suppressed and is also suppressed to I21 even at the timing t13.

[0039] According to this embodiment, by comparing with the reference voltage V R of the reference voltage generation circuit 40, it is possible to easily detect the situation where the gate voltage V G of the output transistor Q1 reaches the threshold value. The timing t1 for detecting the threshold value of the output transistor Q1 can be adjusted by the configuration of the reference voltage generation circuit 40. For example, by serially connecting an inductor (not shown) between the capacitor C R and the drain of the driving transistor Q14, the charging to the capacitor C R can be delayed. Thus, the rise of the reference voltage V R can be delayed, and the timing t1 for detecting that the gate voltage V G reaches the threshold value can be delayed.

[0040] For example, when the output transistor Q1 is a GaN transistor made of GaN (gallium nitride), the GaN transistor is sometimes formed by different chips and connected to the driving transistors Q11 and Q13 through specified wirings. In the case of this configuration, since the wiring has a parasitic inductor component, by connecting an inductor to the capacitor C R , the delay caused by the parasitic inductor component of the wiring can be offset.

[0041] According to this embodiment, the capacitor C of the reference voltage generation circuit 40R reference voltage V R is compared with the gate voltage V of the output transistor Q1 G to thereby detect the gate voltage V G in the flat plateau interval where it becomes flat G and use it as the threshold voltage. Therefore, it is also possible to provide the following configuration: When the value of the reference voltage V C at the time when the comparison circuit 30 outputs the detection signal V R deviates from the assumed threshold range, an abnormality is notified. For example, by responding to the detection signal V C at the H level of the comparison circuit 30 to turn off the drive transistors Q12 and Q14 of the reference voltage generation circuit 40, it is possible to cause the capacitor C R to hold the reference voltage V corresponding to the threshold of the output transistor Q1 R . By comparing the held voltage with the voltage assumed to be the threshold, it is possible to determine whether it is an abnormal state.

[0042] (Second Embodiment)

[0043] Figure 6 FIG. is a diagram showing the configuration of the drive control circuit according to the second embodiment. Components corresponding to those of the embodiments already described are given the same reference numerals, and repeated description is made only when necessary. The same applies hereinafter.

[0044] This embodiment includes a reference voltage generation circuit 41. The reference voltage generation circuit 41 includes drive transistors Q15, Q16, and a capacitor C R1 . The output signal of the buffer 11 is supplied to the gate of the drive transistor Q15, and the output signal of the buffer 12 is supplied to the gate of the drive transistor Q16. The power supply voltage VDD is applied to the source of the drive transistor Q15, and the drain is connected to the drain of the drive transistor Q16. The source of the drive transistor Q16 is grounded. One end of the capacitor C R1 is grounded and is applied with the ground potential that becomes the reference potential. The other end of the capacitor C R1 is connected to the common connection terminal N3 of the drains of the drive transistors Q15 and Q16. The drive transistor Q15 supplies a charging current in the on state to charge the capacitor C R1 . The drive transistor Q16 discharges the charge of the capacitor C R1 in the on state. The on / off of the drive transistors Q15 and Q16 are respectively controlled by the outputs of the buffers 11 and 12.

[0045] This embodiment includes a comparison circuit 31. The comparison circuit 31 compares the gate voltage V G with the reference voltage V at the common connection terminal N3 R1Compare them and output a detection signal V according to the comparison result C1 The comparison circuit 31 is such that when the reference voltage V applied to the non-inverting input terminal (+) R1 becomes higher than the gate voltage V G the detection signal V C1 is set to the H level.

[0046] This embodiment has a control signal generation circuit 21. The control signal generation circuit 21 responds to the detection signal V of the comparison circuit 31 C1 and the switch signal V S and outputs a control signal V D1 . The control signal V D1 controls the on / off of the drive transistor Q101. The driving ability of the drive transistor Q101 is set to a value higher than that of the drive transistor Q11.

[0047] Use Figure 7 to illustrate the operation of this embodiment. Figure 7 Indicates the gate voltage V G and the reference voltage V R , V R1 . The single dotted line 101 represents the reference voltage V R , and the solid line 102 represents the gate voltage V G , and the double dotted line 120 represents the reference voltage V R1 . As described in the operation of the first embodiment, the gate voltage V of the output transistor Q1 G becomes flat at the threshold. Therefore, at timing t1, the reference voltage V R becomes higher than the gate voltage V G . The comparison circuit 30 detects this voltage relationship and controls to turn on the drive transistor Q10 with higher driving ability.

[0048] Similarly, the reference voltage V shown by the double dotted line 120 R1 also becomes higher than the gate voltage V at timing t20 G . By detecting this voltage relationship by the comparison circuit 31, the comparison circuit 31 generates a detection signal V of the H level at timing t20 C1 and supplies it to the control signal generation circuit 21. The control signal generation circuit 21 responds to the detection signal V C1 and supplies a control signal V of the L level D1 to the drive transistor Q101 to turn on the drive transistor Q101. By turning on the drive transistor Q101, the solid line 102 indicating the gate voltage V G changes, but the illustration is omitted for simplicity.

[0049] In this embodiment, at the reference voltage VR1 becomes higher than the gate voltage V G At the timing t20, the driving transistor Q101 with a higher driving ability is turned on. That is, in addition to the adjustment of turning on the driving transistor Q10 with a higher driving ability according to the comparison operation between the reference voltage V R and the gate voltage V G the driving ability is adjusted by turning on the driving transistor Q101 with a higher driving ability according to the comparison operation between the reference voltage V R1 and the gate voltage V G . Therefore, extremely delicate adjustment of the driving ability can be performed.

[0050] The reference voltage generation circuit 41 can be simply constituted by the driving transistors Q15, Q16, and the capacitor C R1 . In addition, the slope of the change of the reference voltage V R1 can be adjusted by the value of the capacitor C R1 and the value of the driving current of the driving transistor Q15. Thus, by adjusting the values of the capacitors C R , C R1 and the driving ability of the driving transistors Q12, Q15, the slope of the change of the reference voltage V R of the reference voltage generation circuit 40 and the slope of the change of the reference voltage V R1 of the reference voltage generation circuit 41 can be easily adjusted. By adjusting the slopes of the changes of the reference voltages V R , V R1 , the timings t1, t20 of the detection threshold, that is, the timings for turning on the driving transistors Q10, Q101 with a higher driving ability can be adjusted.

[0051] The charging current to the capacitors C R , C R1 can be delayed, and the timing for detecting the threshold of the output transistor Q1 can be delayed. For example, by connecting an inductor (not shown) between the capacitors C R , C R1 and the common connection terminals N2, N3, the charging to the capacitors C R , C R1 can be delayed. Thereby, the rise of the reference voltages V R , V R1 can be delayed, and the timings t1, t20 at which they cross the gate voltage V G can be delayed.

[0052] The control signal generation circuits 20, 21 of the embodiment described above are configured such that, for the detection signals V C , V C1After making a response, before the timing t3 when the switch signal V S becomes the H level, output a control signal V D at the L level, V D1 . However, it may also be configured as follows: Whenever the detection signals V C and V C1 of the comparison circuits 30 and 31 change to the H level or the L level, output a control signal V D and V D1 whose output level changes. When the detection signals of the comparison circuits 30 and 31 are at the L level, it is possible to suppress the inrush current by only operating the drive transistor Q11 with a relatively small driving ability. Whenever the detection signals V C and V C1 become the H level, turn on the drive transistors Q10 and Q101 with a relatively high driving ability to increase the driving ability and accelerate the switching speed of the output transistor Q1.

[0053] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the scope equivalent thereto.

Claims

1. A drive control circuit comprising: A first drive transistor that supplies a drive current to the gate of an output transistor in response to a drive signal; A first capacitor having one end applied with a reference potential; A second drive transistor that supplies a charging current to the other end of the first capacitor in response to the drive signal; A first comparison circuit that compares the gate voltage of the output transistor with the voltage at the other end of the first capacitor and outputs a first detection signal based on the result; A first control signal generation circuit that generates a first control signal in response to the first detection signal and the drive signal; and A third drive transistor that supplies a drive current to the gate of the output transistor in response to the first control signal.

2. The drive control circuit according to claim 1, wherein the driving ability of the third drive transistor is higher than that of the first drive transistor.

3. The drive control circuit according to claim 1, wherein the size of the third drive transistor is larger than that of the first drive transistor.

4. The drive control circuit according to claim 2, wherein the value of the first capacitor is set based on a time constant determined by the gate-source capacitance of the output transistor and the driving ability of the first drive transistor, and the driving ability of the second drive transistor.

5. The drive control circuit according to claim 1, wherein the drive control circuit is set such that the time for the gate-source capacitance of the output transistor to be charged to a specified voltage by the first drive transistor is the same as the time for the first capacitor to be charged to the specified voltage by the second drive transistor.

6. The drive control circuit according to claim 1, wherein the first comparison circuit has a hysteresis characteristic.

7. The drive control circuit according to claim 1, comprising: A fourth drive transistor that discharges the charge of the gate-source capacitance of the output transistor in response to a second drive signal; and A fifth drive transistor that discharges the charge of the first capacitor in response to the second drive signal.

8. The drive control circuit according to claim 1, comprising: A second capacitor having one end applied with the reference potential; A sixth drive transistor that supplies a charging current to the other end of the second capacitor in response to the drive signal; A second comparison circuit that compares the gate voltage of the output transistor with the voltage at the other end of the second capacitor and outputs a second detection signal based on the comparison result; A second control signal generation circuit that generates a second control signal in response to the second detection signal and the drive signal; and A seventh drive transistor that supplies a drive current to the gate of the output transistor in response to the second control signal.

9. The drive control circuit according to claim 8, wherein the driving ability of the seventh drive transistor is higher than that of the first drive transistor.

10. The drive control circuit according to claim 8, wherein the size of the seventh drive transistor is larger than that of the first drive transistor.

11. The drive control circuit according to claim 1, wherein The above output transistor is a GaN transistor.

12. A drive control circuit comprising: A drive circuit that outputs a first drive signal and a second drive signal; A first drive transistor that supplies a drive current to the gate of the output transistor in response to the first drive signal; A first capacitor having one end applied with a reference potential; A second drive transistor that supplies a charging current to the other end of the first capacitor in response to the first drive signal; A first comparison circuit that compares the gate voltage of the output transistor with the voltage at the other end of the first capacitor and outputs a first detection signal based on the result; A first control signal generation circuit that generates a first control signal in response to the first detection signal and the first drive signal; A third drive transistor having a higher driving ability than the first drive transistor and supplying a drive current to the gate of the output transistor in response to the first control signal; A second capacitor having one end applied with the reference potential; A fourth drive transistor that supplies a charging current to the other end of the second capacitor in response to the first drive signal; A second comparison circuit that compares the gate voltage of the output transistor with the voltage at the other end of the second capacitor and outputs a second detection signal based on the comparison result; A second control signal generation circuit that generates a second control signal in response to the second detection signal and the first drive signal; and A fifth drive transistor having a higher driving ability than the first drive transistor and supplying a drive current to the gate of the output transistor in response to the second control signal.

13. The drive control circuit according to claim 12, wherein the drive control circuit is set such that the time for the first drive transistor to charge the gate-source capacitance of the output transistor to a specified voltage is the same as the time for the second drive transistor to charge the first capacitor to the specified voltage.

14. The drive control circuit according to claim 12, wherein the sizes of the third drive transistor and the fifth drive transistor are larger than the size of the first drive transistor.

15. The drive control circuit according to claim 12, further comprising: A sixth drive transistor that discharges the charge of the gate-source capacitance of the output transistor in response to the second drive signal; A seventh drive transistor that discharges the charge of the first capacitor in response to the second drive signal; and An eighth drive transistor that discharges the charge of the second capacitor in response to the second drive signal.

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