Degradation detection device and degradation detection method

Abstract

Embodiments relate to degradation detection devices and degradation detection methods. According to one embodiment, the degradation detection device comprises: a drive circuit that supplies a drive signal to an output transistor for controlling the on / off state of the output transistor; and an output circuit that compares an integrated value of an output current output in a state where the output transistor is off during a predetermined period with a predetermined threshold value when the output transistor changes from an on state to an off state, and outputs a signal indicating the degradation state of the output transistor based on the comparison result.

Description

[0001] Related Applications

[0002] This application benefits from the priority of Japanese patent application No. 2020-157657 filed on September 18, 2020, and the entire contents of the Japanese patent application are incorporated herein by reference. Technical Field

[0003] The present embodiment generally relates to a degradation detection device and a degradation detection method. Background Art

[0004] In the past, a technology for a power supply circuit using a GaN (gallium nitride) transistor as an output transistor has been disclosed. A switching element composed of a GaN transistor has low loss under a high withstand voltage and is therefore suitable for use in a power supply circuit that outputs a high voltage. The correlation between the charge accumulated in the GaN transistor when the GaN transistor is in the on state (hereinafter referred to as the drain charge) and the on-resistance has been studied. In order to reduce the power consumption of the power supply circuit, it is preferred to use an output transistor with a small on-resistance. The increase in the on-resistance of the output transistor is an indicator of the degradation of the output transistor. It is desired to have a degradation detection device and a degradation detection method that can easily detect the degradation state of the output transistor. Summary of the invention

[0005] In one embodiment, a degradation detection device and a degradation detection method capable of easily detecting a degradation state of an output transistor are provided.

[0006] According to one embodiment, a degradation detection device comprises: an output transistor whose main current path is connected between a power supply terminal and an output terminal; a drive circuit that supplies a drive signal to the output transistor for controlling the on / off state of the output transistor; and an output circuit that compares an integrated value of an output current output in a state where the output transistor is off during a specified period with a specified threshold value when the output transistor changes from an on state to an off state, and outputs a signal indicating the degradation state of the output transistor based on the comparison result. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a diagram showing the degradation detection device according to the first embodiment.

[0008] Figure 2 It is a diagram for explaining the degradation detection method.

[0009] Figure 3 is a flowchart showing a degradation detection method.

[0010] Figure 4 It is a diagram showing the configuration of a degradation detection device according to a second embodiment. DETAILED DESCRIPTION

[0011] Hereinafter, a degradation detection device and a degradation detection method according to the embodiments will be described in detail with reference to the drawings. Note that the present invention is not limited to these embodiments.

[0012] (First Embodiment)

[0013] Figure 1 1 is a diagram showing the structure of the degradation detection device of the first embodiment. In this embodiment, an output transistor Q1 having a source-drain path connected as a main current path is provided between a power supply terminal 11 to which a power supply voltage is applied and an output terminal 30. A DC input voltage is applied to the power supply terminal 11. The output transistor is, for example, an N-channel GaN transistor made of GaN. The main current path between the drain and source of the MOS transistor made of GaN is made of GaN.

[0014] An output transistor Q2 having a source-drain path as a main current path connected thereto is provided between the output terminal 30 and the ground. The output transistor Q2 is, for example, an N-channel GaN transistor.

[0015] This embodiment includes a drive circuit 10 that supplies a drive signal for controlling the on / off of output transistors Q1 and Q2. The drive circuit 10 supplies the drive signal to the output transistors Q1 and Q2 by turning on the output transistors Q1 and Q2 at the same time, and sets a so-called dead time so that no through current is generated between the power supply terminal 11 and the ground. Information on the timing of supplying the drive signal is supplied from the drive circuit 10 to the arithmetic processing circuit 20.

[0016] One end of the inductor L is connected to the output terminal 30. The other end of the inductor L is connected to one end of the output capacitor C and to the output terminal 40. The other end of the output capacitor C is grounded. By turning on / off the output transistors Q1 and Q2 complementarily, an inductor current I flows from the output terminal 30 to the inductor L. L , constituting a DC / DC converter that outputs a predetermined DC output voltage Vout from an output terminal 40 .

[0017] A current sensor 17 is provided between the source of the output transistor Q1 and the output terminal 30. A signal is supplied from the current sensor 17 to the isolator 13. The isolator 13 has a structure in which the input side and the output side are electrically insulated. The isolator 13 has, for example, an inductive or capacitive structure. The output signal from the isolator 13 is supplied to the AD conversion circuit 14. The AD conversion circuit 14 converts the output signal from the isolator 13 into a digital value and supplies it to the operation processing circuit 20. The operation processing circuit 20 is composed of, for example, a CPU (Central Processing Unit).

[0018] A current sensor 18 is provided between the source of the output transistor Q2 and the ground. A signal is supplied from the current sensor 18 to the isolator 15. The isolator 15 has the same structure as the isolator 13. The output signal from the isolator 15 is supplied to the AD conversion circuit 16. The AD conversion circuit 16 converts the output signal from the isolator 15 into a digital value and supplies it to the operation processing circuit 20.

[0019] The arithmetic processing circuit 20 calculates the output current I outputted in the state where the output transistor Q1 is turned off when the output transistor Q1 changes from the on state to the off state. d1 The processing circuit 20 performs integration for a predetermined period of time. d1 The integrated value of is compared with a predetermined threshold value, and based on the comparison result, a detection signal Det indicating the degradation state of the output transistor Q1 is output. d1 When the integrated value of is smaller than the threshold value, the detection signal Det of the H level indicating that degradation has occurred is output. Similarly, the arithmetic processing circuit 20 outputs the output current I outputted in the state where the output transistor Q2 is turned off when the output transistor Q2 is turned off from the on state. d2 The processing circuit 20 performs integration for a predetermined period of time. d2 The integrated value of is compared with a predetermined threshold value, and based on the comparison result, a detection signal Det indicating the deterioration state of the output transistor Q2 is output. D1 ,I D2 Indicates the drain current when each of the output transistors Q1 and Q2 is turned on.

[0020] The output current I of the output transistor Q1 is d1 The accumulation period is, for example, the period from when the drive circuit 10 supplies a drive signal to the output transistor Q1 to switch the output transistor Q1 from on to when the drive circuit 10 supplies a drive signal to the output transistor Q1 to switch the output transistor Q1 from off to on.

[0021] Similarly, the output current I of the output transistor Q2 is calculated by the calculation processing circuit 20. d2 The period for accumulation is, for example, the period from when the drive circuit 10 supplies a drive signal to the output transistor Q2 to switch the output transistor Q2 from on to off, to when the drive circuit 10 supplies a drive signal to the output transistor Q2 to switch the output transistor Q2 from off to on.

[0022] It is known from research that the on-resistance of GaN transistors is correlated with the drain charge. Therefore, when GaN transistors are used as output transistors Q1 and Q2, the on-resistance state of the output transistors Q1 and Q2 can be detected by detecting the drain charge discharged as the output current when the output transistors Q1 and Q2 change from the on state to the off state.

[0023] For example, by setting the threshold value based on the information of the initial drain charge of the output transistors Q1 and Q2, the output current I d1 ,I d2 The integrated value of is compared with the threshold value, so that the state of the on-resistance of the output transistors Q1 and Q2 can be detected. If the on-resistance of the output transistors Q1 and Q2 increases, the power consumption increases. Therefore, the information of the on-resistance of the output transistors Q1 and Q2 can become an indicator of the degradation state.

[0024] According to the first embodiment, the arithmetic processing circuit 20 is provided, which processes the output current I of the output transistors Q1 and Q2 after the output transistors Q1 and Q2 are switched from the on state to the off state. d1 ,I d2 The integration is performed for a predetermined period, and the integrated value is compared with a predetermined threshold value. The operation processing circuit 20 outputs a detection signal Det based on the comparison result. The detection signal Det indicates the state of the on-resistance of the output transistors Q1 and Q2. Therefore, through the detection signal Det, it is possible to grasp that the on-resistance of the output transistors Q1 and Q2 has increased and deteriorated. In the case where the output transistors Q1 and Q2 constitute the output transistors of the DC / DC converter, the increase in the on-resistance of the output transistors Q1 and Q2 can be used to detect the increase in the power consumption of the DC / DC converter.

[0025] Figure 2 This is a diagram for illustrating a method of detecting degradation of an output transistor. The horizontal axis represents the drain charge Qoss. The vertical axis represents the ratio of the on-resistance of the GaN transistor (= on-resistance during detection / initial on-resistance). The on-resistance and drain charge of the GaN transistor, as shown by the solid line 100, are such that when the drain charge is large, the on-resistance is small, and when the drain charge decreases, the on-resistance increases. Therefore, for example, a threshold value QTH is set based on the initial drain charge of the output transistor. When the drain charge is above the threshold value QTH, it is determined that the output transistor is not degraded. When the drain charge is less than the threshold value QTH, it can be determined that the output transistor is degraded. The drain charge of the output transistor can be detected by integrating the output current output from the output transistor after the output transistor changes from the on state to the off state.

[0026] Figure 3 1 is a flowchart showing a method for detecting degradation of an output transistor. The method is implemented in the first embodiment described above. The method for detecting the degradation state of the output transistor Q1 is described. The output transistor Q1 is turned on (S10) by a drive signal from the drive circuit 10. Then, the output transistor Q1 is turned off (S11) by a drive signal from the drive circuit 10.

[0027] The output current I is output when the output transistor Q1 is turned off. d1 The integration starts (S12). The timing of turning on / off the output transistor Q1 is detected by the information supplied from the drive circuit 10 to the arithmetic processing circuit 20. When the output transistor Q1 or Q2 is turned on (S13: Yes), the output current I of the output transistor Q1 is d1 The integration ends (S14). During the period when the output transistor Q1 is turned off (S13: No), the output current I of the output transistor Q1 continues to be output. d1 's points.

[0028] When the output current I d1 After the integration is completed, the output current I d1 The integrated value of is compared with a predetermined threshold value (S15). d1 When the integrated value of is greater than the threshold value (S15: Yes), it is determined that the output transistor Q1 has not deteriorated (S16). d1 When the integrated value of is smaller than the threshold value (S15: No), it is determined that the output transistor Q1 is degraded (S17).

[0029] When the output transistor Q1 changes from the on state to the off state, the output current I d1 By integrating, the drain charge of the output transistor Q1 can be detected. By detecting the drain charge of the output transistor Q1, the state of the on-resistance of the output transistor Q1 can be detected, and the deterioration state can be easily detected.

[0030] Similarly, regarding the output transistor Q2, after the output transistor Q2 changes from the on state to the off state, the output current I d2 By integrating and comparing the integrated value with the threshold, the state of the on-resistance of the output transistor Q2 can be detected, and the degradation state can be easily detected. Figure 3 In the flowchart shown in FIG. 1 , the output transistor Q1 is replaced by the output transistor Q2, and the output current I d1 Replaced by the output current I of the output transistor Q2 d2 process to represent it.

[0031] (Second Embodiment)

[0032] Figure 4 1 is a diagram showing the structure of the degradation detection device of the second embodiment. The same reference numerals are given to the structures corresponding to the above-mentioned embodiments, and the description is repeated only when necessary. The following is the same. This embodiment has an output transistor Q11, which has a source-drain path connected in series with the source-drain path of the output transistor Q1 as the main current path. The output transistor Q11 is, for example, a Si transistor composed of Si.

[0033] The drive circuit 10 supplies a drive signal to the gates of the output transistors Q1 and Q11. The output transistors Q1 and Q11 are controlled to be turned on / off by the drive signal from the drive circuit 10. When the output transistor Q1 is a GaN transistor, the output transistor Q1 is turned off by the drive signal of the negative voltage. In the present embodiment, the output transistor Q11 is always controlled to be in the on state.

[0034] This embodiment has a voltage / current conversion circuit 170 whose input terminal is connected to the source and drain of the output transistor Q11. The voltage / current conversion circuit 170 is composed of, for example, an OTA (Operational Trans-conductance Amplifier) ​​called a Gm unit. The voltage / current conversion circuit 170 converts the voltage generated between the source and drain of the output transistor Q11 into a current. For example, if the gain of the voltage / current conversion circuit 170 is set to gm, and the voltage between the source and drain of the output transistor Q11 is set to V DS , then the voltage / current conversion circuit 170 outputs gm×V DS The output current of the output transistor Q1 is I d1 is supplied to the output transistor Q11, through which the output current I d1 The voltage generated between the source and drain of the output transistor Q11 is converted into a current by the voltage / current conversion circuit 170. Therefore, the output of the voltage / current conversion circuit 170 is equal to the output current I of the output transistor Q1. d1 The corresponding current.

[0035] The output current of the voltage / current conversion circuit 170 is supplied to the inverting input terminal ( ) of the operational amplifier 171. The non-inverting input terminal (+) of the operational amplifier 171 is grounded. A capacitor 172 is connected between the output terminal and the inverting input terminal () of the operational amplifier 171. The operational amplifier 171 and the capacitor 172 constitute an integration circuit. Therefore, the current supplied to the inverting input terminal ( ) of the operational amplifier 171 is integrated by the integration circuit constituted by the operational amplifier 171 and the capacitor 172, and is accumulated in the capacitor 172.

[0036] The integrating circuit composed of the operational amplifier 171 and the capacitor 172 integrates the current supplied from the voltage / current conversion circuit 170 while the switch 173 connected between the two ends of the capacitor 172 is open (i.e., turned off). When the switch 173 is short-circuited (i.e., turned on), the charge accumulated in the capacitor 172 is reset. The on / off of the switch 173 is controlled by the control signal SW1 supplied from the drive circuit 10. By turning on the output transistor Q2, the output current I d1 The output transistor Q11 is supplied. When the drive circuit 10 supplies the drive signal for turning on the output transistor Q2 to the output transistor Q2, the control signal SW1 for turning off the switch 173 is supplied to the switch 173. The output signal of the operational amplifier 171 is supplied to the determination circuit 21.

[0037] This embodiment includes an output transistor Q12 having a source-drain path connected in series with a source-drain path which is a main current path of the output transistor Q2. The output transistor Q12 is, for example, a Si transistor made of Si.

[0038] The drive circuit 10 supplies a drive signal to the gates of the output transistors Q2 and Q12. The on / off of the output transistors Q2 and Q12 is controlled by the drive signal from the drive circuit 12. When the output transistor Q2 is a GaN transistor, the output transistor Q2 is turned off by the drive signal of the negative voltage. In the present embodiment, the output transistor Q12 is always controlled to be in the on state.

[0039] This embodiment has a voltage / current conversion circuit 180 whose input terminal is connected to the source and drain of the output transistor Q12. The structure of the voltage / current conversion circuit 180 is the same as that of the voltage / current conversion circuit 170. The voltage / current conversion circuit 180 converts the voltage generated between the source and drain of the output transistor Q12 into a current. The output current I of the output transistor Q2 d2 is supplied to the output transistor Q12, through which the output current I d2The voltage generated between the source and drain of the output transistor Q12 is converted into a current by the voltage / current conversion circuit 180. Therefore, the output of the voltage / current conversion circuit 180 is equal to the output current I d2 The corresponding current.

[0040] The output current of the voltage / current conversion circuit 180 is supplied to the inverting input terminal ( ) of the operational amplifier 181. The non-inverting input terminal (+) of the operational amplifier 181 is grounded. A capacitor 182 is connected between the output terminal and the inverting input terminal () of the operational amplifier 181. The operational amplifier 181 and the capacitor 182 constitute an integration circuit. Therefore, the current supplied to the inverting input terminal ( ) of the operational amplifier 181 is integrated by the integration circuit constituted by the operational amplifier 181 and the capacitor 182, and is accumulated in the capacitor 182.

[0041] The integrating circuit composed of the operational amplifier 181 and the capacitor 182 integrates the current supplied from the voltage / current conversion circuit 180 while the switch 183 connected between both ends of the capacitor 182 is in an open state. When the switch 183 is short-circuited, the charge accumulated in the capacitor 182 is reset.

[0042] The switch 183 is turned on / off by the control signal SW2 supplied from the drive circuit 10. When the drive circuit 10 supplies the drive signal for turning on the output transistor Q1 to the output transistor Q1, the control signal SW2 for turning off the switch 183 is supplied to the switch 183. The output signal of the operational amplifier 181 is supplied to the determination circuit 21.

[0043] The determination circuit 21 compares the output signal supplied from the operational amplifiers 171 and 181 with a predetermined threshold value. The threshold value is, for example, the threshold value QTH set based on the initial drain charge described above. When the value of the output signal supplied from the operational amplifiers 171 and 181 is greater than the threshold value QTH, the determination circuit 21 determines that the output transistors Q1 and Q2 are not degraded. When the value is less than the threshold value QTH, the determination circuit 21 determines that the output transistors Q1 and Q2 are degraded.

[0044] According to the present embodiment, the output current I output by the output transistors Q1 and Q2 when they are switched from the on state to the off state is d1 ,I d2 The integration circuit composed of operational amplifiers 171, 181 and capacitors 172, 182 integrates the integrated value. Then, the determination circuit 21 compares the integrated value with the threshold value QTH, and determines the degradation state of the output transistors Q1, Q2 based on the comparison result. The output current I d1 ,Id2 By integrating, the drain charge can be detected. The drain charge is correlated with the on-resistance of the output transistors Q1 and Q2. Therefore, by detecting the drain charge of the output transistors Q1 and Q2, the state of the on-resistance can be grasped, and the degradation state of the output transistors Q1 and Q2 can be easily detected.

[0045] The source-drain voltage of the output transistors Q11 and Q12 formed of Si is lower than that of the GaN transistor. Therefore, by adopting a structure for detecting the source-drain voltage of the output transistors Q11 and Q12, the voltage / current conversion circuits 170 and 180 can be simplified to have a relatively low withstand voltage.

[0046] The operational amplifiers 171 and 181 may be formed of fully differential operational amplifiers. By connecting capacitors between the inverting and non-inverting input terminals and the non-inverting and inverting output terminals of a fully differential operational amplifier (not shown), an integrating circuit can be formed.

[0047] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope or subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A degradation detection device, comprising: The output transistor, the source and the drain are connected between the power supply terminal and the output terminal; a drive circuit that supplies a drive signal for controlling on / off of the output transistor to the output transistor; and The output circuit integrates the output current discharged from the source side for a predetermined period according to the drain charge when the output transistor changes from the on state to the off state, compares the integrated value with a predetermined threshold value, outputs a signal indicating that the output transistor has not been degraded if the integrated value is larger than the predetermined threshold value, and outputs a signal indicating that the output transistor has been degraded if the integrated value is smaller than the predetermined threshold value.

2. The degradation detection device according to claim 1, wherein: The predetermined period is a period from the timing when the drive circuit supplies a drive signal to the output transistor to change the output transistor from the on state to the off state to the timing when the drive circuit supplies a drive signal to the output transistor to change the output transistor that has changed to the off state to the on state.

3. The degradation detection device according to claim 1, wherein: have: a second output transistor having a main current path connected in series with the main current path of the output transistor and supplied with the output current of the output transistor; a voltage / current conversion circuit for converting a voltage generated in a main current path of the second output transistor into a current; as well as The integrating circuit integrates the output current of the voltage / current conversion circuit.

4. The degradation detection device according to claim 1, wherein: The output transistor is a GaN transistor.

5. The degradation detection device according to claim 1, wherein: have: an inductor having one end supplied with an output current of the output transistor; and The output capacitor has one end connected to the other end of the inductor and the other end grounded.

6. A degradation detection method comprising the following steps: a step of changing an output transistor from an on state to an off state, wherein the source and the drain of the output transistor are connected between the power supply terminal and the output terminal; a step of integrating an output current discharged from a source side for a predetermined period based on a drain charge when the output transistor has been turned into an off state; and The integrated value is compared with a predetermined threshold value, and when the integrated value is larger than the predetermined threshold value, the output transistor is determined to be non-degraded, and when the integrated value is smaller than the predetermined threshold value, the output transistor is determined to be degraded.

7. The degradation detection method according to claim 6, wherein: The output transistor is a GaN transistor.

8. The degradation detection method according to claim 6, wherein: A drive circuit is provided, the drive circuit supplies a drive signal for controlling on / off of the output transistor to the output transistor, The predetermined period is a period from the timing when the drive circuit supplies a drive signal to the output transistor to switch the output transistor from on to off to the timing when the drive circuit supplies a drive signal to the output transistor to switch the output transistor from off to on.

9. The degradation detection method according to claim 6, wherein: A second output transistor is provided, the second output transistor having a main current path connected in series with the main current path of the output transistor and being supplied with the output current of the output transistor, The step of integrating includes the step of converting a voltage generated in a main current path of the second output transistor by the output current into a current.

10. The degradation detection method according to claim 6, wherein: The determination step includes the step of outputting a signal indicating that the output transistor has not deteriorated, when the integrated value is equal to or greater than the predetermined threshold value.

11. A degradation detection device comprising: A first output transistor having a main current path with one end connected to a power supply end; a second output transistor having a main current path having one end connected to the other end of the main current path of the first output transistor and the other end connected to the output end; a third output transistor having a main current path having one end connected to the other end of the main current path of the second output transistor; a fourth output transistor, one end of which is connected to the other end of the main current path of the third output transistor and the other end of which is grounded; a driving circuit for supplying a driving signal for controlling on / off of the first output transistor to the fourth output transistor to the first output transistor to the fourth output transistor; as well as A determination circuit integrates an output current discharged from a source side during a predetermined period based on a drain charge when the first output transistor is turned off when the first output transistor changes from an on state to an off state, compares the integrated value with a predetermined threshold value, outputs a signal indicating that the first output transistor has not been degraded when the integrated value is larger than the predetermined threshold value, and outputs a signal indicating that the first output transistor has been degraded when the integrated value is smaller than the predetermined threshold value.

12. The degradation detection device according to claim 11, wherein: have: a conversion circuit that converts a voltage generated in a main current path of the second output transistor into a current; and An integrating circuit comprising: an amplifier circuit, a first input terminal of which is supplied with the output current of the conversion circuit, and a second input terminal of which is grounded; and a capacitor connected between the output terminal of the amplifier circuit and the first input terminal; The output signal of the integration circuit is supplied to the determination circuit.

13. The degradation detection device according to claim 12, wherein: A switch is provided, the switch being connected between both ends of the capacitor, and the on / off state of the switch being controlled by the drive circuit.

14. The degradation detection device according to claim 11, wherein: The prescribed period is a period from the timing when the drive circuit supplies a drive signal to the first output transistor to change the first output transistor from the on state to the off state to the timing when the drive circuit supplies a drive signal to the first output transistor to change the first output transistor that has changed to the off state to the on state.

15. The degradation detection device according to claim 11, wherein: The first output transistor and the third output transistor are GaN transistors, The second output transistor and the fourth output transistor have Si transistors.

16. The degradation detection device according to claim 11, wherein: have: an inductor having one end supplied with an output current of the second output transistor; and The output capacitor has one end connected to the other end of the inductor and the other end grounded.

17. The degradation detection device according to claim 11, wherein: The driving circuit turns on / off the first output transistor and the second output transistor complementarily with respect to the third output transistor and the fourth output transistor.

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