Memory device and method of operating a memory device

Abstract

The present technology includes a memory device and a method for operating the memory device. The memory device includes: a control logic circuit configured to control a peripheral circuit so that a programming operation is performed. The control logic circuit controls the peripheral circuit so that: when a verification operation of a memory cell corresponding to an (N-1)th programming state has failed, the memory cells to be programmed to the first to (N-1)th programming states are programmed in a dual programming method using a main verification voltage and a sub-verification voltage less than the main verification voltage during the verification operation, and the memory cells to be programmed to the Nth programming state are programmed in a normal programming method using the main verification voltage during the verification operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0111857 ​​filed on September 2, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a memory device and a method of operating the memory device, and more particularly, to a memory device capable of performing a programming operation and a method of operating the memory device. Background Art

[0004] The memory device may include a volatile memory device in which stored data is destroyed when power is cut off, and a nonvolatile memory device in which stored data is maintained even if power is cut off.

[0005] Volatile memory devices may include dynamic random access memory (DRAM) and static random access memory (SRAM). Non-volatile memory devices may include read-only memory (ROM), programmable read-only memory (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), NAND FLASH, etc.

[0006] A memory device may include a memory cell array, peripheral circuits, and logic circuits.

[0007] The memory cell array may include a plurality of memory cells, and the plurality of memory cells may store data. The method of storing one bit of data in one memory cell is called a single-level cell (SLC) method, and the method of storing two or more bits of data in one memory cell is called a multi-level cell (MLC) method. According to the number of bits stored in the memory cell, the programming operation of the MLC method may be divided into a three-level cell (TLC) method or a four-level cell (QLC) method. In the TLC method, three bits of data may be stored in one memory cell, and in the QLC method, four bits of data may be stored in one memory cell. Summary of the invention

[0008] A memory device according to an embodiment of the present disclosure may include: a memory block including a plurality of pages; a peripheral circuit configured to perform a programming operation to program memory cells included in a page selected from the plurality of pages to first to Nth programming states, where 'N' is an integer greater than or equal to 2; and a control logic circuit configured to control the peripheral circuit so that the programming operation is performed. The control logic circuit may control the peripheral circuit so that: when a verification operation of a memory cell corresponding to the (N-1)th programming state fails, the memory cells to be programmed to the first to (N-1)th programming states are programmed in a dual programming method using a main verification voltage and a sub-verification voltage less than the main verification voltage during the verification operation, and the memory cells to be programmed to the Nth programming state are programmed using a normal programming method using the main verification voltage during the verification operation, and the control logic circuit may control the peripheral circuit so that: when a verification operation of a memory cell corresponding to the (N-1)th programming state has passed, the verification operation of the memory cell to be programmed to the Nth programming state is performed using the dual programming method.

[0009] A method for operating a memory device according to an embodiment of the present disclosure in a programming operation for programming memory cells to first to Nth programming states, wherein 'N' is an integer greater than or equal to 2, the method may include: performing a sub-programming operation, a sub-verification operation, and a main verification operation on memory cells to be programmed to the first to (N-1)th programming states, and performing a sub-programming operation and a main verification operation on memory cells to be programmed to the Nth programming state; and when the main verification operation of the memory cells to be programmed to the (N-1)th programming state has passed, performing a sub-programming operation, a sub-verification operation, and a main verification operation on the memory cells to be programmed to the Nth programming state.

[0010] A method of operating a memory device according to an embodiment of the present disclosure may include: programming memory cells to first to Nth programming states according to a target voltage, and performing a programming loop by mixing a normal programming method and a dual programming method until the programming operation of the memory cell whose target voltage corresponds to the (N-1)th programming state is completed, where 'N' is an integer greater than or equal to 2; and after the programming operation of the memory cell whose target voltage corresponds to the (N-1)th programming state has been completed, performing a programming loop with the dual programming method. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0012] Figure 2 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0013] Figure 3 is a diagram illustrating a memory block according to an embodiment of the present disclosure.

[0014] Figure 4 is a diagram illustrating voltages applied to bit lines according to an embodiment of the present disclosure.

[0015] Figure 5 is a diagram illustrating threshold voltage distribution of memory cells.

[0016] Fig. 6A is a diagram illustrating voltages applied to bit lines in a normal programming method.

[0017] Figure 6B is a diagram illustrating voltages applied to bit lines in a dual programming method.

[0018] Figure 7 is a flowchart illustrating a programming operation according to an embodiment of the present disclosure.

[0019] Figure 8 is a diagram illustrating an embodiment of the present disclosure for each program loop.

[0020] Fig. 9 is a diagram illustrating a memory card system to which the memory device of the present disclosure is applied.

[0021] Fig.10 is a diagram illustrating a solid state drive (SSD) system to which the memory device of the present disclosure is applied. DETAILED DESCRIPTION

[0022] Embodiments of the present disclosure provide a memory device capable of improving a threshold voltage distribution of a selected memory cell having a highest target voltage during a program operation, and a method of operating the memory device.

[0023] The present technology can improve the threshold voltage distribution of memory cells and can shorten the time to perform a programming operation.

[0024] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0025] Reference Figure 1 , the memory system 1000 may include a memory device 1100 and a controller 1200. The memory device 1100 may include a plurality of memory devices MD, and the memory devices MD may be connected to the controller 1200 through input / output lines.

[0026] The controller 1200 may communicate between the host 1500 and the memory device MD. The controller 1200 may generate a command CMD for controlling the memory device MD according to a request RQ of the host 1500, and may perform background operations to improve performance of the system 1000 even if there is no request RQ of the host 1500.

[0027] The host 1500 may generate request RQ for various operations and may output the generated request RQ to the memory system 1000. For example, the request RQ may include a program request that may control a program operation, a read request that may control a read operation, an erase request that may control an erase operation, and the like.

[0028] The host 1500 may communicate with the memory system 1000 through various interfaces, such as Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), MultiMediaCard (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0029] The memory device MD according to the present embodiment can perform a programming operation. The programming operation can be performed according to an incremental step pulse programming (ISPP) method, in which the programming voltage is gradually increased. In the present embodiment, the memory device MD can perform a programming operation of the ISPP method, in which the normal programming method and the dual programming method are selectively applied, or the normal programming method and the dual programming method are selectively mixed.

[0030] The normal programming method is a method in which, when a programming voltage is applied to a selected word line, a programming enable voltage is applied to a selected bit line, and a programming inhibit voltage is applied to an unselected bit line. The selected word line refers to a word line connected to a programming target memory cell. The selected bit line refers to a bit line connected to a memory cell whose threshold voltage is lower than a target voltage, and the unselected bit line refers to a bit line connected to a memory cell whose threshold voltage is increased to be equal to or higher than the target voltage. The programming enable voltage may be a voltage having a large potential difference from the programming voltage applied to the selected word line, and may be, for example, 0V. The programming inhibit voltage may be a voltage having a small potential difference from the programming voltage, and may be, for example, a positive voltage of 18V or higher.

[0031] The normal programming method is a method in which, when a programming voltage is applied to a selected word line, a programming enabling voltage is applied to a bit line of a memory cell connected to a threshold voltage having a large difference with a target voltage among the selected bit lines, a programming reducing voltage is applied to a bit line of a memory cell connected to a threshold voltage having a small difference with a target voltage, and a programming prohibition voltage is applied to an unselected bit line. For ease of description, a bit line connected to a memory cell having a large difference with a target voltage may be defined as a first state bit line, and a bit line connected to a memory cell having a relatively small difference with a target voltage may be defined as a second state bit line. The programming reducing voltage may be a voltage that is used to increase the threshold voltage of a memory cell connected to a second state bit line more slowly than the threshold voltage of a memory cell connected to a first state bit line. For example, the programming reducing voltage may be set to a positive voltage between the programming prohibition voltage and the programming enabling voltage.

[0032] Figure 2 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0033] Reference Figure 2 , the memory device MD may include: a memory cell array 110 in which data is stored; a peripheral circuit 200 that performs programming, reading or erasing operations; and a control logic 160 that controls the peripheral circuit 200. The control logic 160 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 160 may be a control logic circuit that operates according to an algorithm and / or a processor that executes a control logic code.

[0034] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKi in which data is stored. Each of the memory blocks BLK1 to BLKi may include a plurality of memory cells, and the memory cells may be implemented in a two-dimensional structure arranged in parallel with a substrate or in a three-dimensional structure stacked in a vertical direction on a substrate.

[0035] The peripheral circuit 200 may include a voltage generator 120 , a row decoder 130 , a page buffer group 140 , and an input / output circuit 150 .

[0036] The voltage generator 120 may generate and output an operation voltage Vop required for various operations in response to the voltage code VCD. For example, the voltage generator 120 may generate and output a program voltage, a verification voltage, a read voltage, a pass voltage, an erase voltage, etc. having various levels.

[0037] The row decoder 130 may select one of the memory blocks BLK1 to BLKi included in the memory cell array 110 according to the row address RADD and transfer the operating voltage Vop to the selected memory block.

[0038] The page buffer group 140 may be connected to the memory cell array 110 via a bit line. For example, the page buffer group 140 may include a page buffer connected to the corresponding bit line. The page buffer may be operated simultaneously in response to the page buffer control signal PBSIG, and may temporarily store data during a programming or reading operation. The verification operation performed during the programming operation and the verification operation performed during the erase operation may be performed in the same method as the read operation. During a read operation or a verification operation, the page buffer may sense the voltage of the bit line, which varies according to the threshold voltage of the memory cell. That is, it may be determined whether the threshold voltage of the memory cell is lower or higher than the read voltage or the verification voltage according to the result of the sensing operation performed in the page buffer. During the programming operation of the normal programming method, the page buffer may apply a programming enable voltage to the selected bit line, and apply a programming inhibit voltage to the unselected bit line. During the programming operation of the dual programming method, the page buffer may apply a programming enable voltage to the first state bit line, a programming reduction voltage to the second state bit line, and a programming inhibit voltage to the unselected bit line.

[0039] The input / output circuit 150 can be connected to the Figure 1 The controller 1200 of the input / output circuit 150. The input / output circuit 150 may input / output a command CMD, an address ADD, and data DATA through the input / output line. For example, the input / output circuit 150 may transmit the command CMD and the address ADD received through the input / output line to the control logic 160, and transmit the data DATA received through the input / output line to the page buffer group 140. The input / output circuit 150 may output the data DATA received from the page buffer group 140 to the controller 1200 through the input / output line.

[0040] The control logic 160 may output a voltage code VCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, the control logic 160 may include software that executes an algorithm in response to a command CMD, and hardware that is configured to output various signals according to the address ADD and the algorithm.

[0041] The control logic 160 may control the peripheral circuit 200 by selectively applying the normal program method and the dual program method according to a result of a verification operation during a program operation of a selected page among a plurality of pages included in a selected memory block.

[0042] Figure 3 is a diagram illustrating a memory block according to an embodiment of the present disclosure, and Figure 2 Among the illustrated plurality of memory blocks BLK1 to BLKi, the i-th memory block BLKi is illustrated as an example.

[0043] Reference Figure 3 , the i-th memory block BLKi may include a plurality of strings ST1 to STj (j is a positive integer). The first to j-th strings ST1 to STj may be connected between the bit lines BL1 to BLj and the source line SL. For example, the first string ST1 may be connected between the first bit line BL1 and the source line SL, the second string ST2 may be connected between the second bit line BL2 and the source line SL, and the j-th string STj may be connected between the j-th bit line BLj and the source line SL.

[0044] Each of the first to j-th strings ST1 to STj may include a source selection transistor SST, a plurality of memory cells C1 to Cn, and a drain selection transistor DST. Although not shown in the figure, a dummy cell may also be included between the memory cells C1 to Cn and the source or drain selection transistor SST or DST. The configuration of the string is specifically described below by taking the j-th string STj as an example.

[0045] The source select transistor SST included in the jth string STj can be electrically connected or disconnected between the source line SL and the first memory cell C1 according to the voltage applied to the source select line SSL. The gates of the first to nth memory cells C1 to Cn can be connected to the first to nth word lines WL1 to WLn, respectively. The drain select transistor DST can be electrically connected or disconnected between the jth bit line BLj and the nth memory cell Cn according to the voltage applied to the drain select line DSL. The gates of the source select transistors SST included in different strings ST1 to STj can be connected to the source select line SSL in common, and the gates of the first to nth memory cells C1 to Cn can be connected to the first to nth word lines WL1 to WLn, and the gates of the drain select transistors DST can be connected to the drain select line DSL in common. A group of memory cells connected to the same word line is called a page (PG), and programming and reading operations can be performed in units of page PG.

[0046] The programming operation according to the present embodiment may be performed in accordance with an incremental step pulse programming (ISPP) method of gradually increasing the programming voltage. In the programming operation of the ISPP method, a plurality of programming loops may be performed until the threshold voltage of the selected memory cell increases to the target voltage, and the programming voltage may be gradually increased each time the programming loop is performed. In each programming loop, a sub-programming operation and a verification operation may be performed, the sub-programming operation being used to increase the threshold voltage of the selected memory cell, and the verification operation being used to determine whether the threshold voltage of the selected memory cell increases to the target voltage. In the sub-programming operation, the programming voltage may be applied to the selected word line, and in the verification operation, the verification voltage may be applied to the selected word line. An operation of determining whether the verification operation is passed or failed according to the data of the memory cell sensed in the verification operation may be performed in the sub-programming operation of the next programming loop. The operation of determining whether the verification operation is passed or failed during the sub-programming operation may be a current sensing check operation.

[0047] Figure 4 is a diagram illustrating voltages applied to bit lines according to an embodiment of the present disclosure.

[0048] Reference Figure 4 , the page buffer group 140 may include first to j-th page buffers PB1 to PBj. The first to j-th page buffers PB1 to PBj may be connected to the first to j-th bit lines BL1 to BLj, respectively. When a program operation starts, the first to j-th page buffers PB1 to PBj may store bits from Figure 1 The controller 1200 of the present invention may store data outputted therefrom, and may apply a program enable voltage Val, a program reduction voltage Vde, or a program inhibition voltage Vin to the first to j-th bit lines BL1 to BLj according to the stored data. After the programming operation starts, the first to j-th page buffers PB1 to PBj may apply a program enable voltage Val, a program reduction voltage Vde, or a program inhibition voltage Vin to the first to j-th bit lines BL1 to BLj according to the data stored during the verification operation and the data sensed from the selected memory cells. The program enable voltage Val may be 0V, and the program reduction voltage Vde may be a positive voltage higher than the program enable voltage Val. The program inhibition voltage Vin may be a positive voltage higher than the program reduction voltage Vde.

[0049] In the normal programming method, the programming permission voltage Val may be applied to the selected bit line, and the programming prohibition voltage Vin may be applied to the unselected bit line. In the dual programming method, the programming permission voltage Val may be applied to the first state bit line, the programming reduction voltage Vde may be applied to the second state bit line, and the programming prohibition voltage Vin may be applied to the unselected bit line. Here, the dual programming method is taken as an example for explanation, and it is assumed that the first and second bit lines BL1 and BL2 are first state bit lines, the third and fifth bit lines BL3 and BL5 are second state bit lines, and the fourth and jth bit lines BL4 and BLj are unselected bit lines. In this case, the first and second page buffers PB1 and PB2 connected to the first and second bit lines BL1 and BL2 may output the programming permission voltage Val, the third and fifth page buffers PB3 and PB5 connected to the third and fifth bit lines BL3 and BL5 may output the programming reduction voltage Vde, and the fourth and jth page buffers PB4 and PBj connected to the fourth and jth bit lines BL4 and BLj may output the programming prohibition voltage Vin. Voltages output from the first to j-th page buffers PB1 to PBj may vary according to data sensed in a verification operation.

[0050] Figure 5 is a diagram illustrating threshold voltage distribution of memory cells.

[0051] Reference Figure 5 According to the number of bits stored in a memory cell, the programming operation can be divided into various methods. For example, a method of storing three bits of data in one memory cell is called a three-level cell (TLC) method, and a method of storing four bits of data in one memory cell is called a quad-level cell (QLC) method.

[0052] In the TLC method, the state of the memory cell can be classified into one erase state ER and any one of seven program states P1 to P7. In the QLC method, the state of the memory cell can be classified into one erase state ER and any one of fifteen program states P1 to P15.

[0053] During a programming operation, memory cells to be programmed to a first programming state P1 may be programmed to have a target voltage corresponding to the first programming state P1, and memory cells to be programmed to a second programming state P2 may be programmed to have a target voltage corresponding to the second programming state P2. In this method, the remaining memory cells may be programmed to have a target voltage corresponding to each programming state.

[0054] As the number of target voltages increases, the interval between threshold voltage distributions of memory cells to be programmed to different program states decreases. Therefore, in the present embodiment, the normal programming method and the dual programming method may be mixed.

[0055] Fig. 6A 2 is a diagram illustrating a voltage applied to a bit line in a normal programming method. The y-axis represents the number N# of cells, and the x-axis represents the voltage V.

[0056] Reference Fig. 6A In a normal programming method, a target verification voltage Vt may be set for each target voltage PV, and a selected memory cell may be programmed until a threshold voltage 61 is higher than the target verification voltage Vt.

[0057] During the programming operation, the threshold voltage 61 of the selected memory cell may be increased each time the programming voltage is applied, and the selected memory cell whose threshold voltage is increased to the target voltage PV is changed to an unselected memory cell. Therefore, the program enable voltage Val may be applied to the selected bit line Sel_BL until the threshold voltage 61 of all selected memory cells reaches the target voltage PV, and the program inhibit voltage Vin may be applied to the unselected bit line Unsel_BL. For example, among the selected memory cells, the bit line connected to the memory cell whose threshold voltage is lower than the target verification voltage Vt may become the selected bit line Sel_BL, and the bit line connected to the memory cell whose threshold voltage is equal to or greater than the target verification voltage Vt may become the unselected bit line Unsel_BL.

[0058] Figure 6B 2 is a diagram illustrating voltages applied to bit lines in a dual programming method. The y-axis represents the number N# of cells, and the x-axis represents the voltage V.

[0059] Reference Figure 6B In the dual programming method, two or more verification voltages Vs and Vt may be set for each target voltage PV, and the selected memory cell may be programmed until the threshold voltage 61 is higher than the target verification voltage Vt. In the present embodiment, a programming operation using the sub-verification voltage Vs and the target verification voltage Vt as verification voltages is described. The sub-verification voltage Vs may be set to a level lower than the target verification voltage Vt.

[0060] In the dual programming operation, after the sub-verification operation using the sub-verification voltage Vs is performed, the main verification operation using the target verification voltage Vt may be performed. Therefore, according to the results of the sub-verification operation and the main verification operation, the selected memory cells may be classified into memory cells whose threshold voltages are lower than the sub-verification voltage Vs, memory cells whose threshold voltages are between the sub-verification voltage Vs and the target verification voltage Vt, and memory cells whose threshold voltages are equal to or greater than the target verification voltage Vt.

[0061] The bit lines connected to memory cells whose threshold voltages are lower than the sub-verification voltage Vs can become the first state bit lines 1ST_BL, the bit lines connected to memory cells whose threshold voltages are between the sub-verification voltage Vs and the target verification voltage Vt can become the second state bit lines 2ST_BL, and the bit lines connected to memory cells whose threshold voltages are equal to or greater than the target verification voltage Vt can become the unselected bit lines Unsel_BL.

[0062] While the programming operation is being performed, a program enable voltage Val may be applied to the first state bit line 1ST_BL, a program reduction voltage Vde may be applied to the second state bit line 2ST_BL, and a program inhibition voltage Vin may be applied to the unselected bit line Unsel_BL until all threshold voltages of the selected memory cells are increased to the target verification voltage Vt. When a program reduction voltage Vde between the program enable voltage Val and the program inhibition voltage Vin is applied to the second state bit line 2ST_BL, the threshold voltage of the memory cell connected to the second state bit line 2ST_BL may increase more slowly than the threshold voltage of the memory cell to which the program enable voltage Val is applied. In other words, due to the difference between the program enable voltage Val and the program reduction voltage Vde, the threshold voltage change amount of the memory cell connected to the second state bit line 2ST_BL is relatively smaller than the threshold voltage change amount of the memory cell connected to the first state bit line 1ST_BL. Therefore, the following phenomenon can be prevented: the threshold voltage of the memory cell connected to the second state bit line 2ST_BL is excessively increased.

[0063] However, in the programming operation of the dual programming method, since the sub-verification operation and the main verification operation are performed, the programming operation time may increase. Therefore, in the present embodiment, the programming operation of the dual programming can be selectively performed on the selected memory cell with the highest target voltage PV. The programming operation according to the present embodiment is described below.

[0064] Figure 7 is a flowchart illustrating a programming operation according to an embodiment of the present disclosure.

[0065] Reference Figure 7, when the programming operation of the selected page starts, k (k is a positive integer) as the programming loop number is set to 1 (S71), and the kth programming loop can be performed (S72). In the kth programming loop, a sub-programming operation of applying a programming voltage to the selected word line and a verification operation of verifying the threshold voltage of the selected memory cell can be performed. The kth programming loop for programming the memory cell to the first to (n-1)th target voltages PV1 to PV(n-1) can be performed in the dual programming method DPGM, and the kth programming loop for programming the memory cell to the nth target voltage PVn can be performed in the normal programming method NPGM. For example, when k is 1, the first programming loop can be performed, and in the first programming loop, a sub-programming operation and a first verification operation for programming the memory cell to the first target voltage PV1 can be performed in the dual programming method DPGM. Subsequently, an operation for determining whether the threshold voltage of the memory cell increases to the first to (n-1)th target voltages PV1 to PV(n-1) can be performed (S73). When the threshold voltage of the memory cell does not increase to the first to (n-1)th target voltages PV1 to PV(n-1) (No), k is increased by 1 (S74), and an operation of increasing the program voltage Vpgm may be performed (S75). Subsequently, a kth program loop using the increased program voltage Vpgm may be performed (S72).

[0066] Steps S71 to S75 may be repeated until all threshold voltages of the memory cells are increased to the first to (n-1)th target voltages PV1 to PV(n-1). As steps S71 to S75 are repeated, the number of memory cells reaching the low target voltage among the first to (n-1)th target voltages PV1 to PV(n-1) may increase. Therefore, when steps S71 to S75 are repeated, a program loop for the highest nth target voltage may be performed.

[0067] In a state where the verification operation for at least one of the first to (n-1)th target voltages PV1 to PV(n-1) fails in step S73, a program loop for a target voltage lower than the nth target voltage PVn may be performed in the dual programming method DPGM, and a program loop for the nth target voltage PVn may be performed in the normal programming method NPGM in step S72. Since the program loop for the nth target voltage PVn is performed in the normal programming method NPGM, the program operation time of the selected page may be shortened.

[0068] In step S73, when it is determined that all threshold voltages of the memory cells are increased to the first to (n-1)th target voltages PV1 to PV(n-1) (Yes), for the next programming loop, k is increased by 1 (S76), and the kth programming loop for the nth target voltage PVn may be performed (S77). The kth programming loop for the nth target voltage PVn performed from step S77 may be performed in the dual programming method DPGM.

[0069] Subsequently, an operation for determining whether the threshold voltage of the memory cell increases to the nth target voltage PVn may be performed (S78). When the threshold voltage of the memory cell does not increase to the nth target voltage PVn (No), k is increased by 1 (S79), and an operation for increasing the program voltage Vpgm may be performed (S80). Subsequently, a kth programming loop using the increased program voltage Vpgm may be performed (S77).

[0070] Steps S77 to S80 may be repeated until all threshold voltages of the memory cells increase to the nth target voltage PVn, and when all threshold voltages of the memory cells increase to the nth target voltage PVn (“Yes” in step S78 ), the program operation of the selected page may be ended.

[0071] Figure 8 is a diagram illustrating an embodiment of the present disclosure for each program loop.

[0072] Reference Figure 8 , the first programming loop LP1 may be performed in the dual programming method DPGM. For example, in the first programming loop LP1, a sub-programming operation using the first programming voltage 1Vpgm and a verification operation using the first verification voltage V1 as a target voltage may be sequentially performed. Assuming that the first verification voltage V1 is a main verification voltage, the verification operation may further include a sub-verification operation using a first sub-verification voltage lower than the first verification voltage V1. For example, after performing the sub-verification operation using the first sub-verification voltage, a main verification operation using the first verification voltage V1 may be performed.

[0073] Subsequently, the second programming loop LP2 may be performed. The second programming loop LP2 may be performed in the dual programming method DPGM. For example, in the second programming loop LP2, a sub-programming operation using a second programming voltage 2Vpgm higher than the first programming voltage 1Vpgm may be performed. During the sub-programming operation, a current sensing check (CSC) operation for determining whether the verification operation performed in the first programming loop LP1 is passed or failed may be performed. In the current sensing check CSC operation, when it is determined that the first verification operation fails, in the second programming loop LP2, a first verification operation and a second verification operation using the first verification voltage V1 and the second verification voltage V2 may be performed. Since the second programming loop LP2 is performed in the dual programming method DPGM, a sub-verification operation and a main verification operation may be performed in each of the first verification operation and the second verification operation.

[0074] The third programming loop LP3 may be performed in the dual programming method DPGM. For example, in the third programming loop LP3, a sub-programming operation using a third programming voltage 3Vpgm higher than the second programming voltage 2Vpgm may be performed. During the sub-programming operation, a current sensing check CSC operation for determining whether the verification operation performed in the second programming loop LP2 is passed or failed may be performed. When it is determined that both the first verification operation and the second verification operation fail in the current sensing check CSC operation, in the third programming loop LP3, first to third verification operations using the first to third verification voltages V1 to V3 may be performed. Since the third programming loop LP3 is performed in the dual programming method DPGM, a sub-verification operation and a main verification operation may be performed in each of the first to third verification operations.

[0075] The fourth programming loop LP4 may be performed in the dual programming method DPGM. For example, in the fourth programming loop LP4, a sub-programming operation using a fourth programming voltage 4Vpgm higher than the third programming voltage 3Vpgm may be performed. During the sub-programming operation, a current sensing check CSC operation for determining whether the verification operation performed in the third programming loop LP3 is passed or failed may be performed. In the current sensing check CSC operation, when it is determined that the first verification operation of the first to third verification operations passes and the second and third verification operations fail, in the fourth programming loop LP4, second to fourth verification operations using the second verification voltage V2 to the fourth verification voltage V4 may be performed. Since the fourth programming loop LP4 is performed in the dual programming method DPGM, a sub-verification operation and a main verification operation may be performed in each of the second to fourth verification operations. The fourth to (k-5)th programming loops LP4 to LP(k-5) may be performed in the above method.

[0076] The (k-4)th programming loop LP(k-4) may be performed in the dual programming method DPGM. For example, in the (k-4)th programming loop LP(k-4), a sub-programming operation using a (k-4)th programming voltage (k-4)Vpgm higher than a (k-5)th programming voltage (k-5)Vpgm may be performed. During the sub-programming operation, a current sensing check CSC operation for determining whether a verification operation performed in the (k-5)th programming loop LP(k-5) is passed or failed may be performed. The verification operation passed in the current sensing check CSC operation may be omitted from the (k-4)th programming loop LP(k-4). In the (k-4)th programming loop LP(k-4), an (n-2)th verification operation and an (n-1)th verification operation using an (n-2)th verification voltage V(n-2) and an (n-1)th verification voltage V(n-1) may be performed.

[0077] When the (k-3)th programming loop LP(k-3) starts, a sub-programming operation using a (k-3)th programming voltage (k-3) Vpgm higher than the (k-4)th programming voltage (k-4) Vpgm may be performed. During the sub-programming operation, a current sensing check CSC operation for determining whether a verification operation performed in the (k-4)th programming loop LP(k-4) passes or fails may be determined. In the current sensing check CSC operation, when it is determined that the (n-2)th verification operation passes and the (n-1)th verification operation fails, the (n-2)th verification operation may be omitted from the (k-3)th programming loop LP(k-3). When an nth verification operation using an nth verification voltage Vn is performed from the (k-3)th programming loop LP(k-3), the (n-1)th verification operation may be performed in the dual programming method DPGM, and the nth verification operation using the nth verification voltage Pn may be performed in the normal programming method NPGM. That is, since the (n-1)th verification operation fails, the nth verification operation may be performed in the normal program method NPGM.

[0078] When the (k-2)th programming loop LP(k-2) starts, a sub-programming operation using a (k-2)th programming voltage (k-2) Vpgm higher than the (k-3)th programming voltage (k-3) Vpgm may be performed. During the sub-programming operation, a current sensing check CSC operation for determining whether a verification operation performed in the (k-3)th programming loop LP(k-3) passes or fails may be determined. In the current sensing check CSC operation, when it is determined that the (n-1)th verification operation passes and the nth verification operation fails, the (n-1)th verification operation may be omitted from the (k-2)th programming loop LP(k-2). Since the (n-1)th verification operation passes, the nth verification operation using the nth verification voltage Vn may be performed in the dual programming method DPGM.

[0079] When the (k-1)th program loop LP(k-1) starts, a sub-programming operation using a (k-1)th program voltage (k-1) Vpgm higher than a (k-2)th program voltage (k-2) Vpgm may be performed. During the sub-programming operation, a current sensing check CSC operation for determining whether a verification operation performed in the (k-2)th program loop LP(k-2) passes or fails may be determined. In the current sensing check CSC operation, when it is determined that the nth verification operation fails, the kth program loop LPk may be performed after performing the nth verification operation.

[0080] When the k-th programming loop LPk starts, a sub-programming operation using a k-th programming voltage kVpgm higher than the (k-1)-th programming voltage (k-1)Vpgm may be performed. During the sub-programming operation, a current sensing check CSC operation for determining whether a verification operation performed in the (k-1)-th programming loop LP(k-1) is passed or failed may be performed. In the current sensing check CSC operation, when it is determined that the n-th verification operation is passed, the programming operation of the selected page may be ended.

[0081] Since the above-described program operation is for helping to understand the embodiment of the present embodiment, the verification operation and the verification voltage performed in each program loop may vary according to the memory device.

[0082] According to the present embodiment described above, before the (n-1)th verification operation is passed, except for the nth verification operation, all the first to (n-1)th verification operations can be performed in the dual programming method DPGM, and only the nth verification operation can be performed in the normal programming method. After the (n-1)th verification operation is passed, the nth verification operation can be performed in the dual programming method DPGM.

[0083] Therefore, by performing the nth verification operation in the normal programming method NPGM until the (n-1)th verification operation passes, the programming operation time can be shortened. In addition, by performing the nth verification operation in the dual programming method DPGM after the nth verification operation passes, the threshold voltage distribution of the memory cell programmed to have the nth target voltage can be improved.

[0084] Fig. 9 is a diagram illustrating a memory card system to which the memory device of the present disclosure is applied.

[0085] Reference Fig. 9 , the memory card system 2000 includes a memory controller 2100 , a memory device 2200 , and a connector 2300 .

[0086] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 is configured to access the memory device 2200. For example, the memory controller 2100 may be configured to control the programming, reading, or erasing operations of the memory device 2200, or to control background operations. The memory controller 2100 is configured to provide an interface between the memory device 2200 and the host. The memory controller 2100 is configured to drive firmware for controlling the memory device 2200. The memory device 2200 may be configured to communicate with the reference Figure 2 The described memory devices MD are identical.

[0087] The memory controller 2100 may communicate with an external device through the connector 2300. The memory controller 2100 may communicate with an external device (e.g., a host) according to a specific communication standard. For example, the memory controller 2100 may be configured to communicate with an external device through at least one of various communication standards, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI-express (PCI-E), an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage device (UFS), WIFI, Bluetooth, and NVMe. For example, the connector 2300 may be defined by at least one of the various communication standards.

[0088] For example, the memory device 2200 may be composed of various nonvolatile memory devices, such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetic RAM (STT-MRAM).

[0089] The memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro or eMMC), an SD card (SD, miniSD, microSD or SDHC), and a Universal Flash Storage (UFS).

[0090] Fig.10 is a diagram illustrating a solid state drive (SSD) system to which the memory device of the present disclosure is applied.

[0091] Reference Fig.10 , the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals with the host 3100 through a signal connector 3001, and receives power through a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply device 3230, and a buffer memory 3240.

[0092] According to an embodiment of the present disclosure, the flash memories 3221 to 322n may be configured to be connected to the reference Figure 2 The described memory devices MD are identical.

[0093] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal received from the host 3100. For example, the signal may be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal may be a signal defined by at least one of interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (MCM), a peripheral component interconnect (PCI), PCI Express (PCI-E), an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0094] The auxiliary power supply device 3230 is connected to the host 3100 through the power connector 3002. The auxiliary power supply device 3230 can receive power from the host 3100 and can be charged. When the power supply from the host 3100 is not stable, the auxiliary power supply device 3230 can provide power to the SSD 3200. For example, the auxiliary power supply device 3230 can be located in the SSD 3200, or can be located outside the SSD 3200. For example, the auxiliary power supply device 3230 can be located on the mainboard and can provide auxiliary power to the SSD 3200.

[0095] The buffer memory 3240 is used as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

Claims

1. A memory device, comprising: A memory block, including a plurality of pages; a peripheral circuit that performs a programming operation to program memory cells included in a page selected from the plurality of pages to a first programming state to an Nth programming state, where 'N' is an integer greater than or equal to 2; as well as a control logic circuit, controlling the peripheral circuit so that the programming operation is performed, wherein the peripheral circuit includes a page buffer connected to the memory block through a bit line, wherein the control logic circuit controls the peripheral circuit so that: when a verification operation of a memory cell corresponding to the (N-1)th programming state has failed, the memory cells to be programmed to the first programming state to the (N-1)th programming state are programmed using a dual programming method using a main verification voltage and a sub-verification voltage less than the main verification voltage during the verification operation, and the memory cells to be programmed to the Nth programming state are programmed using a normal programming method using the main verification voltage during the verification operation, wherein the control logic circuit controls the peripheral circuit so that: when the verification operation of the memory cell corresponding to the (N-1)th programming state has passed, the verification operation of the memory cell to be programmed to the Nth programming state is performed using the dual programming method, and The page buffer included in the peripheral circuit is configured to: in the normal programming method, apply a programming enable voltage to selected bit lines among the bit lines that are connected to memory cells having a threshold voltage less than the main verification voltage, and apply a programming inhibit voltage to unselected bit lines among the bit lines that are connected to memory cells having a threshold voltage greater than or equal to the main verification voltage.

2. The memory device of claim 1 , wherein the peripheral circuit comprises: A voltage generator, generating voltages required for the programming operation and the verification operation; as well as A row decoder transmits the voltage generated by the voltage generator to the memory block.

3. The memory device of claim 1 , wherein in the dual programming method, the page buffer applies the programming enable voltage to first-state bit lines among the bit lines connected to memory cells having a threshold voltage less than the sub-verification voltage, applies a programming reduction voltage to second-state bit lines among the bit lines connected to memory cells having a threshold voltage between the sub-verification voltage and the main verification voltage, and applies the programming inhibit voltage to the unselected bit lines among the bit lines connected to the memory cells having a threshold voltage equal to or greater than the main verification voltage.

4. The memory device according to claim 3, wherein the program reduction voltage is set to a positive voltage greater than the program allowance voltage, and The program inhibition voltage is set to a positive voltage greater than the program reduction voltage. 5 . The memory device of claim 1 , wherein the control logic circuit controls the peripheral circuit so that a plurality of program loops in which a program voltage is increased are performed during the program operation.

6. A method of operating a memory device in a programming operation for programming memory cells to a first programming state to an Nth programming state, wherein 'N' is an integer greater than or equal to 2, the method comprising: performing a sub-programming operation, a sub-verification operation, and a main-verification operation on memory cells to be programmed to the first to (N-1)th programming states, and performing the sub-programming operation and the main-verification operation on memory cells to be programmed to the Nth programming state; as well as when the main verification operation of the memory cell to be programmed to the (N-1)th programming state has passed, performing the sub-programming operation, the sub-verification operation, and the main verification operation on the memory cell to be programmed to the Nth programming state, Wherein in the main verification operation, a program enable voltage is applied to a bit line connected to a memory cell sensed with a threshold voltage less than the main verification voltage, and a program inhibit voltage is applied to a bit line connected to a memory cell sensed with a threshold voltage equal to or greater than the main verification voltage.

7. The method according to claim 6, wherein when performing the sub-programming operation and the main verification operation on the memory cells to be programmed to the Nth program state, The sub-programming operation is performed using a method of applying a program voltage to a selected word line connected to the memory cell, and The main verification operation is performed using a method of sensing a threshold voltage of the memory cell using the main verification voltage. 8 . The method according to claim 7 , wherein the main verification voltage is set to a voltage for determining whether the threshold voltage of the memory cell reaches a target voltage.

9. The method according to claim 6, wherein when the sub-programming operation, the sub-verification operation, and the main verification operation are performed on the memory cells to be programmed to the Nth program state, The sub-programming operation is performed using a method of applying a program voltage to a selected word line connected to the memory cell, The sub-verification operation is performed using a method of sensing a threshold voltage of the memory cell using a sub-verification voltage, and The main verification operation is performed using a method of sensing the threshold voltage of the memory cell using the main verification voltage greater than the sub verification voltage.

10. The method of claim 9, wherein in the main verification operation, the program enable voltage is applied to bit lines connected to memory cells sensed with a threshold voltage less than the sub-verification voltage, a program reduction voltage is applied to bit lines connected to memory cells having a threshold voltage between the sub-verification voltage and the main verification voltage, and the program inhibit voltage is applied to the bit lines connected to the memory cells sensed with the threshold voltage equal to or greater than the main verification voltage.

11. The method according to claim 10, wherein the program reduction voltage is greater than the program enable voltage, and The program inhibition voltage is lower than the program reduction voltage.

12. The method according to claim 6, further comprising: A current sensing check operation for determining a result of the main verification operation is performed. 13 . The method of claim 12 , wherein the current sensing check operation is performed when the sub program operation is performed.

14. A method of operating a memory device, the method comprising: Programming memory cells to a first programming state to an Nth programming state according to a target voltage, and performing a programming loop by mixing a normal programming method and a dual programming method until a programming operation of a memory cell whose target voltage corresponds to an (N-1)th programming state is completed, wherein 'N' is an integer greater than or equal to 2; as well as After the programming operation of the memory cell having the target voltage corresponding to the (N-1)th programming state has been completed, performing the programming loop in the dual programming method, Wherein in the normal programming method, a program enable voltage is applied to selected bit lines connected to memory cells having a threshold voltage less than a main verification voltage, and a program inhibit voltage is applied to unselected bit lines connected to memory cells having a threshold voltage equal to or greater than the main verification voltage.

15. The method of claim 14, wherein the normal programming method comprises: performing a sub-programming operation of applying a programming voltage to a word line connected to the memory cell; as well as A verification operation is performed to sense the memory cell using a main verification operation to determine whether a threshold voltage of the memory cell is increased to the target voltage.

16. The method according to claim 14, wherein the dual programming method comprises: performing a sub-programming operation of applying a programming voltage to a word line connected to the memory cell; performing a verification operation of sensing the memory cell using a sub-verification operation to determine whether a threshold voltage of the memory cell is increased to a sub-target voltage that is less than the target voltage; as well as A verification operation is performed to sense the memory cell using a main verification operation to determine whether the threshold voltage of the memory cell is increased to the target voltage.

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