Method of manufacturing a semiconductor component and method of manufacturing a semiconductor device

Abstract

An embodiment provides a method for manufacturing a semiconductor component and a method for manufacturing a semiconductor device that can reduce the difference in impurity amounts. In the method for manufacturing a semiconductor component according to the embodiment, a first quality of a semiconductor substrate including a first semiconductor layer of a first conductivity type is measured. A first opening is formed in an upper surface of the first semiconductor layer. A second quality of the semiconductor substrate in which the first opening is formed is measured. When a second semiconductor layer of a second conductivity type is formed inside the first opening, an impurity concentration of the second conductivity type in the second semiconductor layer is changed according to a difference in quality between the first quality and the second quality.

Description

[0001] Related Application

[0002] This application claims priority based on Japanese Patent Application No. 2020-157540 (filing date: September 18, 2020). This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0003] Embodiments of the present invention relate to a method for manufacturing a semiconductor component and a method for manufacturing a semiconductor device. Background Art

[0004] Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used for applications such as power conversion. There are semiconductor devices having a superjunction structure in which a plurality of semiconductor regions of a first conductivity type and a plurality of semiconductor regions of a second conductivity type are alternately provided. For such a semiconductor device, it is preferable that the difference in the amount of impurities contained in the semiconductor regions of the first conductivity type and the amount of impurities contained in the semiconductor regions of the second conductivity type is small. Summary of the Invention

[0005] Embodiments of the present invention provide a method for manufacturing a semiconductor component and a method for manufacturing a semiconductor device capable of reducing the difference in the amount of impurities.

[0006] In the method for manufacturing a semiconductor component according to an embodiment, a first mass of a semiconductor substrate including a first semiconductor layer of a first conductivity type is measured. A first opening is formed on the upper surface of the first semiconductor layer. A second mass of the semiconductor substrate on which the first opening is formed is measured. When a second semiconductor layer of a second conductivity type is formed inside the first opening, the impurity concentration of the second conductivity type in the second semiconductor layer is changed according to the difference in mass between the first mass and the second mass. Brief Description of the Drawings

[0007] Figure 1 is a cross-sectional view showing a semiconductor device having a superjunction structure manufactured by the manufacturing method according to the embodiment.

[0008] Figure 2 of (a) to Figure 3 of (b) are cross-sectional views showing the method for manufacturing a semiconductor component according to the embodiment.

[0009] Figure 4 of (a) to Figure 6 is a cross-sectional view showing the method for manufacturing a semiconductor device according to the embodiment.

[0010] Figure 7 is a graph showing the characteristics of the manufacturing method of the reference example and the manufacturing method of the embodiment. Detailed Description of the Invention

[0011] Hereinafter, each embodiment of the present invention will be described with reference to the accompanying drawings.

[0012] The accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as in reality. Even when representing the same part, there are cases where the sizes and ratios thereof are represented differently according to the accompanying drawings.

[0013] In the specification and each figure of the present application, the same reference numerals are assigned to the elements that have been described before, and the detailed description is appropriately omitted.

[0014] In the following description and the accompanying drawings, n + 、n - and p + 、p, p - The marks represent the relative levels of the respective impurity concentrations. That is, the mark with “+” indicates that the impurity concentration is relatively high compared to the mark without either “+” or “-” added, and the mark with “-” indicates that the impurity concentration is relatively low compared to the mark without either one added. When both p-type impurities and n-type impurities are included in each region, these marks represent the relative levels of the net impurity concentration after these impurities are mutually compensated.

[0015] Regarding each of the embodiments described below, each embodiment can also be implemented by inverting the p-type and n-type of each semiconductor region.

[0016] Figure 1 is a cross-sectional view showing a semiconductor device having a superjunction structure manufactured by the manufacturing method of the embodiment.

[0017] Figure 1 The semiconductor device 100 shown includes an n + -type (first conductivity type) drain region 1, an n - -type drift region 2, a p - -type (second conductivity type) column region 3, a p-type substrate region 4, an n + -type source region 5, a p + -type contact region 6, a gate electrode 10, a drain electrode 21, and a source electrode 22.

[0018] In the description of the embodiment, an XYZ orthogonal coordinate system is used. The direction from the drain electrode 21 toward the n + -type drain region 1 is set as the Z direction (first direction). The two directions perpendicular to the Z direction and orthogonal to each other are set as the X direction (second direction) and the Y direction (third direction). In addition, for the sake of explanation, the direction from the drain electrode 21 toward the n +The direction of the n-type drain region 1 is called "up", and the opposite direction is called "down". These directions are based on the relative positional relationship between the drain electrode 21 and the n + -type drain region 1 and are independent of the direction of gravity.

[0019] The drain electrode 21 is provided on the lower surface of the semiconductor device 100. The n + -type drain region 1 is provided above the drain electrode 21 and is electrically connected to the drain electrode 21. The n - -type drift region 2 is provided above the n + -type drain region 1. - The n-type drift region 2 is electrically connected to the drain electrode 21 via the n + -type drain region 1. The n-type impurity concentration in the n - -type drift region 2 is lower than the n-type impurity concentration in the n + -type drain region 1.

[0020] The p - -type column region 3 is provided above the n - -type drift region 2. The n - -type drift region 2 includes n - -type column regions 2n arranged side by side with the p - -type column region 3 in the X direction. The p-type substrate region 4 is provided above the p - -type column region 3. The p-type impurity concentration in the p-type substrate region 4 is higher than the p-type impurity concentration in the p - -type column region 3. + The n-type source region 5 and the p + -type contact region 6 are provided above the p-type substrate region 4. The p + -type impurity concentration in the p-type contact region 6 is higher than the p-type impurity concentration in the p-type substrate region 4.

[0021] The gate electrode 10 is provided above the n - -type column region 2n. The gate electrode 10 faces a part of the n - -type column region 2n, the p-type substrate region 4, and the n + -type source region 5 with the gate insulating layer 10a interposed therebetween in the X direction.

[0022] The source electrode 22 is provided above the n + -type source region 5, the p + -type contact region 6, and the gate electrode 10 and is electrically connected to the n + -type source region 5 and the p + -type contact region 6. An insulating layer 15 is provided between the gate electrode 10 and the source electrode 22. The gate electrode 10 and the source electrode 22 are electrically separated.

[0023] The source electrode 22 includes, for example, a first metal layer 22a and a second metal layer 22b. The first metal layer 22a is disposed along the upper surface of the n + -type source region 5, the upper surface of the p + -type contact region 6, and the surface of the insulating layer 15. The second metal layer 22b is disposed on the first metal layer 22a.

[0024] The n - -type pillar regions 2n, the p - -type pillar regions 3, the p-type substrate region 4, the n + -type source region 5, the p + -type contact region 6, and the gate electrode 10 are provided in multiple numbers in the X direction. Multiple n - -type pillar regions 2n and multiple p - -type pillar regions 3 are alternately provided in the X direction. Multiple n - -type pillar regions 2n and multiple p - -type pillar regions 3 constitute a so-called super junction structure. Each n - -type pillar region 2n, each p - -type pillar region 3, each p-type substrate region 4, each n + -type source region 5, each p + -type contact region 6, and each gate electrode 10 extend in the Y direction.

[0025] The operation of the semiconductor device 100 will be described.

[0026] With a positive voltage applied to the drain electrode 21 with respect to the source electrode 22, a voltage higher than the threshold is applied to the gate electrode 10. A channel (inversion layer) is formed in the p-type substrate region 4. Electrons flow through the channel and the n - -type drift region 2 to the drain electrode 21. Thus, the semiconductor device 100 becomes in an on state. Then, when the voltage applied to the gate electrode 10 becomes lower than the threshold, the channel in the p-type substrate region 4 disappears, and the semiconductor device 100 becomes in an off state.

[0027] When the semiconductor device 100 is in an off state and a positive potential is applied to the drain electrode 21 with respect to the source electrode 22, the depletion layer extends along the Z direction from the pn junction surface between the n - -type pillar region 2n and the p-type substrate region 4. In addition, the depletion layer extends along the X direction from the pn junction surface between the n - -type pillar region 2n and the p - -type pillar region 3. By the extension of the depletion layer in the X direction caused by the n - -type pillar region 2n and the p - -type pillar region 3, the breakdown voltage of the semiconductor device 100 can be increased. Alternatively, the breakdown voltage of the semiconductor device 100 can be maintained unchanged while increasing the n- The n-type impurity concentration in the drift region 2 reduces the on-resistance of the semiconductor device 100.

[0028] An example of the material of each component of the semiconductor device 100 will be described.

[0029] n + type drain region 1, n - type drift region 2, p - type pillar region 3, p-type substrate region 4, n + type source region 5, and p + type contact region 6 include at least one selected from the group consisting of silicon, silicon carbide, and gallium nitride as a semiconductor material. In the case of using silicon as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity.

[0030] The gate electrode 10 includes a conductive material such as polysilicon. The gate insulating layer 10a and the insulating layer 15 include an insulating material such as silicon oxide. The drain electrode 21 and the second metal layer 22b include metals such as copper and aluminum. The first metal layer 22a includes metals that function as barrier metals such as titanium, titanium nitride, and tungsten.

[0031] A method for manufacturing a semiconductor component according to an embodiment will be described.

[0032] Figure 2 and Figure 3 is a cross-sectional view showing a method for manufacturing a semiconductor component according to an embodiment.

[0033] Prepare a semiconductor substrate Sub including an n + type semiconductor layer 1a and an n - type semiconductor layer 2a (first semiconductor layer). The n - type semiconductor layer 2a is provided on the n + type semiconductor layer 1a. The semiconductor substrate Sub may not include the n + type semiconductor layer 1a and include only the n - type semiconductor layer 2a. The direction from the n + type semiconductor layer 1a toward the n - type semiconductor layer 2a is parallel to the Z direction. The upper surface of the n - type semiconductor layer 2a is parallel to the X direction and the Y direction. By thermal oxidation or chemical vapor deposition (CVD) of the semiconductor substrate Sub, as shown in Figure 2 (a) of, an insulating layer IL1 (first layer) is formed on the upper surface of the n - type semiconductor layer 2a.

[0034] Measure the quality (first quality) of the semiconductor substrate Sub formed with the insulating layer IL1. The quality can be measured, for example, by the Metryx series of Lam Research Corporation or by an electronic balance set in an environment where the temperature and air pressure are controlled. A photoresist PR is formed on the insulating layer IL1. The insulating layer IL1 is patterned by photolithography and reactive ion etching (RIE). Thus, as shown in (b) of Figure 2 , an insulating layer IL1 having openings OP2 (second openings) is provided on the upper surface of the n - -type semiconductor layer 2a. A plurality of openings OP2 are formed in the X direction. Each opening OP2 extends in the Y direction.

[0035] Remove the photoresist PR by ashing. Measure the length of the opening OP2 in the X direction. The length is measured, for example, by a critical dimension scanning electron microscope (CD – SEM). Using the insulating layer IL1 as a mask, openings OP1 (first openings) are formed on the upper surface of the n - -type semiconductor layer 2a by RIE. The positions where the openings OP1 are formed correspond to the positions of the openings OP2. As shown in (a) of - , a plurality of openings OP1 are formed in the X direction. Each opening OP1 extends in the Y direction. Figure 3 Measure the quality (second quality) of the semiconductor substrate Sub formed with the openings OP1. The second quality includes the quality of the insulating layer IL1. As shown in (b) of

[0036] , a p Figure 3 -type semiconductor layer 3a (second semiconductor layer) is epitaxially grown inside the opening OP1. - During epitaxial growth, while heating the semiconductor substrate Sub, a first gas containing silicon and a second gas containing a p-type impurity are supplied to the processing space where the semiconductor substrate Sub is placed. For example, as the first gas, gases such as silane, chlorosilane, dichlorosilane, and trichlorosilane are used. As the second gas, gases such as diborane, triborane, and chloroborane are used. In order to suppress the deposition of silicon on the insulating layer IL1, an etching gas may be further supplied. As the etching gas, hydrochloric acid gas can be used.

[0038] When forming the p

[0037] -type semiconductor layer 3a, the p-type impurity concentration in the p - -type semiconductor layer 3a is changed according to the mass difference between the first quality and the second quality. Specifically, the larger the mass difference, the lower the p-type impurity concentration in the p - -type semiconductor layer 3a. -

[0039] As a method for changing the p-type impurity concentration in the p - -type semiconductor layer 3a, there are the following methods.

[0040] In the first method, when forming the p - -type semiconductor layer 3a, the flow rate of the second gas is adjusted. The greater the mass difference, the smaller the flow rate of the second gas. The pressure may be adjusted instead of the flow rate. For example, the greater the mass difference, the lower the pressure of the second gas in the space where the p - -type semiconductor layer 3a is formed. The greater the flow rate or the higher the pressure, the greater the supply amount of the p-type impurity to the formed semiconductor layer. Thus, the p - -type impurity concentration in the p-type semiconductor layer 3a can be changed.

[0041] In the second method, first, an impurity layer containing a p-type impurity is formed along the inner wall of the opening OP1. Then, an undoped or low p-type impurity concentration semiconductor layer is formed inside the opening OP1. After that, by heat treatment, the p-type impurity diffuses from the impurity layer to the undoped or low-concentration semiconductor layer, thereby forming the p - -type semiconductor layer 3a. When forming the impurity layer, by adjusting the flow rate of the second gas according to the mass difference, the p - -type impurity concentration in the p-type semiconductor layer 3a can be changed.

[0042] Instead of adjusting the flow rate or pressure of the second gas, the flow rate or pressure of the dilution gas or etching gas may be adjusted. As the dilution gas, hydrogen can be used.

[0043] Alternatively, in addition to adjusting the flow rate or pressure of the second gas, the flow rate or pressure of the dilution gas or etching gas can also be adjusted.

[0044] Figures 4 to 6 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment.

[0045] First, by the above-described method for manufacturing a semiconductor component, a semiconductor component including an n - -type semiconductor layer 2a and a p - -type semiconductor layer 3a is manufactured. The insulating layer IL1 is removed. By chemical mechanical polishing (CMP), the upper surfaces of the n - -type semiconductor layer 2a and the p - -type semiconductor layer 3a are planarized. P-type impurities are ion-implanted into the upper surface of the n - -type semiconductor layer 2a and the upper surface of the p - -type semiconductor layer 3a to form a p-type semiconductor region 4a (first semiconductor region). By photolithography and RIE, as shown in (a) of Figure 4 the (a) of -An opening OP3 is formed above the p-type semiconductor layer 2a. The opening OP3 penetrates the p-type semiconductor region 4a and reaches the n - -type semiconductor layer 2a. A plurality of openings OP3 are formed in the X direction. Each opening OP3 extends in the Y direction.

[0046] Through thermal oxidation, an insulating layer IL2 is formed along the inner wall of the opening OP3 and the upper surface of the p-type semiconductor region 4a. Through CVD, a conductive layer is formed on the insulating layer IL2 to fill the opening OP3. Through chemical dry etching (CDE), RIE, or wet etching, the upper surface of the conductive layer is recessed. Thus, as Figure 4 shown in (b) of, a gate electrode 10 is formed in the opening OP3.

[0047] N-type impurities are ion-implanted into the upper surface of the p-type semiconductor region 4a to form an n + -type semiconductor region 5a (second semiconductor region). Through CVD, an insulating layer IL3 is formed on the n + -type semiconductor region 5a and the gate electrode 10. Through photolithography and RIE, a part of the insulating layer IL2 and a part of the insulating layer IL3 are removed. As shown in (a) of Figure 5 , an opening OP4 is formed. Through the opening OP4, a part of the n + -type semiconductor region 5a is exposed.

[0048] Through the opening OP4, p-type impurities are ion-implanted into a part of the n + -type semiconductor region 5a to form a p + -type contact region 6. Through sputtering, a first metal layer 22a is formed along the upper surface of the n + -type semiconductor region 5a, the upper surface of the p + -type contact region 6, and the surface of the insulating layer IL3. Through sputtering, as shown in (b) of Figure 5 , a second metal layer 22b is formed on the first metal layer 22a. A source electrode 22 (first electrode) including the first metal layer 22a and the second metal layer 22b is formed.

[0049] The lower surface of the n + -type semiconductor layer 1a is ground until the n + -type semiconductor layer 1a reaches a specified thickness. Through sputtering, as shown in Figure 6 , a drain electrode 21 (second electrode) is formed on the lower surface of the n + -type semiconductor layer 1a. In the case of using a semiconductor substrate Sub that does not include the n + -type semiconductor layer 1a, the lower surface of the n - -type semiconductor layer 2a is ground. N-type impurities are ion-implanted into the ground lower surface to form an n +The semiconductor region of the type. Then, the drain electrode 21 is formed by sputtering. In this way, the semiconductor device 100 of the manufacturing embodiment is manufactured.

[0050] In Figure 6 the structure shown, the n + -type semiconductor layer 1a corresponds to the n + -type drain region 1 of the semiconductor device 100. The n - -type semiconductor layer 2a corresponds to the n - -type drift region 2. The p - -type semiconductor layer 3a corresponds to the p - -type pillar region 3. The p-type semiconductor region 4a corresponds to the p-type substrate region 4. The n + -type semiconductor region 5a corresponds to the n + -type source region 5. The insulating layer IL2 corresponds to the gate insulating layer 10a. The insulating layer IL3 corresponds to the insulating layer 15.

[0051] The order of the processes in the above manufacturing method can be appropriately changed. For example, the p-type semiconductor region 4a can be formed after the gate electrode 10 is formed. It is also possible to form the p + -type contact region 6 after the n + -type semiconductor region 5a is formed and before the insulating layer IL3 is formed. In addition, other processes can be appropriately added to the above manufacturing method. For example, an insulating layer such as a silicon nitride layer or a polyimide resin can be formed as a passivation layer on a part of the second metal layer 22b. It is also possible to form other semiconductor regions on the n - -type semiconductor layer 2a.

[0052] The effects of the embodiment will be described.

[0053] As described above, when the semiconductor device 100 is in the off state, the depletion layer extends along the pn junction surface of the n - -type pillar region 2n and the p - -type pillar region 3 in the X direction. By depleting the n - -type pillar region 2n and the p - -type pillar region 3, the breakdown voltage of the semiconductor device 100 is increased. In order to promote the depletion of the n - -type pillar region 2n and the p - -type pillar region 3, it is preferable that the difference in the amount of impurities between the amount of n-type impurities contained in the n - -type pillar region 2n and the amount of p-type impurities contained in the p - -type pillar region 3 is small. The width (length in the X direction) of the n - -type pillar region 2n, the n-type impurity concentration in the n - -type pillar region 2n, the width of the p - -type pillar region 3, and the p- The p-type impurity concentration in the shaped column region 3 is designed to reduce this difference.

[0054] n - The amount of n-type impurities in the n-type column region 2n and the p - The amount of p-type impurities in the shaped column region 3 varies according to Figure 3 the size of the opening OP1 shown in (a) of. For example, the larger the cross-sectional area of the opening OP1, the larger the cross-sectional area of the p - -type semiconductor layer 3a, and the smaller the cross-sectional area of the n - -type semiconductor layer 2a between the openings OP1. As a result, the amount of n-type impurities in the n - -type column region 2n decreases, and the amount of p-type impurities in the p - -type column region 3 increases. The more the cross-sectional area of the opening OP1 deviates from the design value, the greater the difference in the amount of impurities between the amount of n-type impurities in the n - -type column region 2n and the amount of p-type impurities in the p - -type column region 3.

[0055] In the manufacturing method of the embodiment, the first mass of the semiconductor substrate Sub when the opening OP1 is not formed and the second mass of the semiconductor substrate Sub after the opening OP1 is formed are measured. The magnitude of the mass difference between the first mass and the second mass is related to the cross-sectional area of the opening OP1. The larger the cross-sectional area of the opening OP1, the greater the mass difference. By changing the p-type impurity concentration in the p - -type semiconductor layer 3a according to the mass difference, the difference in the amount of impurities can be reduced.

[0056] For example, the mass difference (first nominal value) when the amount of n-type impurities in the n - -type column region 2n is equal to the amount of p-type impurities in the p - -type column region 3 is preset. When forming the p - -type semiconductor layer 3a, the flow rate of the second gas (nominal flow rate) is preset, and the flow rate of the second gas (nominal flow rate) is used to make the amount of n-type impurities in the n - -type column region 2n equal to the amount of p-type impurities in the p - -type column region 3. After measuring the first mass and the second mass, calculate their mass difference. Calculate the change amount (first change amount) of the mass difference based on the measurement result with respect to the first nominal value. According to the first change amount, change the flow rate of the second gas from the nominal flow rate. The greater the mass difference based on the measurement result is than the first nominal value, the smaller the flow rate of the second gas is made than the nominal flow rate. The smaller the mass difference based on the measurement result is than the first nominal value, the larger the flow rate of the second gas is made than the nominal flow rate.

[0057] For example, data representing the relationship between the first variation and the correction amount of the flow rate is preset. When the first variation is calculated, referring to this data, the correction amount corresponding to the first variation is obtained. The nominal flow rate is corrected based on the obtained correction amount. When forming the p - -type semiconductor layer 3a, the second gas is supplied at the corrected flow rate.

[0058] According to the manufacturing method of the embodiment, a semiconductor component with reduced impurity mass difference is manufactured. By using this semiconductor component, a semiconductor device 100 capable of reducing the impurity mass difference can be manufactured.

[0059] As a manufacturing method of a comparative example, a method of adjusting the p-type impurity concentration of the p - -type semiconductor layer 3a based on the analysis results of the manufactured semiconductor component or semiconductor device can be cited. Specifically, in the semiconductor component or semiconductor device, the width of the n - -type column region 2n and the width of the p - -shaped column region 3 are measured, and based on the measurement results, the p-type impurity concentration of the p - -type semiconductor layer 3a in the subsequent manufacturing process is adjusted. That is, in the manufacturing method of the comparative example, feedback control is performed on the p-type impurity concentration of the p - -type semiconductor layer 3a.

[0060] According to the manufacturing method of the embodiment, the first variation can be calculated before the formation of the p - -type semiconductor layer 3a. Based on the first variation, the p-type impurity concentration of the subsequently formed p - -type semiconductor layer 3a can be adjusted. That is, feedforward control can be performed on the p-type impurity concentration of the p - -type semiconductor layer 3a based on the first variation. By performing feedforward control on the p-type impurity concentration of the p - -type semiconductor layer 3a based on the measurement results during the manufacturing process, compared with the manufacturing method of the comparative example, the impurity mass difference can be reduced. In addition, the situation of manufacturing a semiconductor device with poor characteristics can be suppressed, and the yield of the semiconductor component and the semiconductor device can be improved.

[0061] In addition to the first variation, the p-type impurity concentration in the p - -type semiconductor layer 3a may also be changed according to the width of the opening OP2. The width of the opening OP2 is related to the width of the opening OP1 formed using the insulating layer IL1 as a mask. The wider the width of the opening OP2, the wider the width of the opening OP1, and the larger the cross-sectional area of the opening OP1.

[0062] It is preset so that the n-type impurity amount of the n - -type column region 2n is the same as the p -The p-type impurity amount in the columnar region 3 is equal, and the width (second nominal value) of the preferred opening OP2. After forming the opening OP2, the width of the opening OP2 is measured. The change amount (second change amount) of the measured width with respect to the second nominal value is calculated. Based on the first change amount and the second change amount, the flow rate of the second gas is changed from the nominal flow rate.

[0063] For example, data representing the relationship between the correction amounts for the first change amount, the second change amount, and the flow rate is preset in advance. When the first change amount and the second change amount are calculated, referring to this data, the correction amount corresponding to the first change amount and the second change amount is obtained. Based on the obtained correction amount, the flow rate of the second gas is corrected according to the nominal flow rate. When forming the p - -type semiconductor layer 3a, the second gas is supplied at the corrected flow rate.

[0064] The mass difference depends not only on the width of the opening OP1 but also on the depth of the opening OP1 (the length in the Z direction). A part of the mass difference may also be caused by the deviation of the depth of the opening OP1. When the opening OP1 becomes deeper, the length of the p - -type columnar region 3 in the Z direction becomes longer. Correspondingly, the length of the n - -type columnar region 2n arranged side by side with the p - -type columnar region 3 in the Z direction also becomes longer. Therefore, the influence of the deviation of the depth of the opening OP1 on the impurity mass difference is small. By changing the p-type impurity concentration in the p - -type semiconductor layer 3a according to the first change amount and the second change amount, the impurity mass difference can be further reduced.

[0065] When forming the opening OP1, a deviation in the etching amount occurs. If the cross-sectional area of the opening OP1 is predicted only based on the width of the opening OP2, due to the deviation of the etching amount, the accuracy is lower than the prediction based on the mass difference. Therefore, if the p-type impurity concentration in the p - -type semiconductor layer 3a is changed only according to the measurement result of the width of the opening OP2, compared with the case where the p-type impurity concentration in the p - -type semiconductor layer 3a is changed only based on the mass difference, there is a tendency for the impurity mass difference to become larger. Therefore, it is preferable to change the p-type impurity concentration in the p - -type semiconductor layer 3a according to the width of the opening OP2 and the mass difference.

[0066] Figure 7 (a) is a characteristic curve graph showing the manufacturing method of the reference example. Figure 7 (b) is a characteristic curve graph showing the manufacturing method of the embodiment.

[0067] In the manufacturing method of the embodiment, the first mass, the second mass, and the width of the opening OP2 are measured. In the manufacturing method of the reference example, only the width of the opening OP2 is measured, and the first mass or the second mass is not measured.

[0068] Figure 7 The curve graph of (a) is obtained through the following steps.

[0069] During the manufacturing process of the semiconductor device, the width of the opening OP2 is measured. The p- - type semiconductor layer 3a is formed by supplying the second gas at a nominal flow rate. Based on the electrical characteristics of the manufactured semiconductor device, the ratio of the amount of n-type impurities contained in the n- - type semiconductor layer 2a to the amount of p-type impurities contained in the p- - type semiconductor layer 3a can be calculated. Specifically, for the manufactured semiconductor device, the breakdown voltage (dielectric breakdown voltage) when no voltage is applied to the gate electrode 10 and the breakdown voltage when a voltage is applied to the gate electrode 10 are measured, and their ratio is measured. Refer to the simulation results related to this ratio obtained from past mass production data. Based on the simulation results, the ratio of the amount of n-type impurities contained in the n- - type semiconductor layer 2a to the amount of p-type impurities contained in the p- - type semiconductor layer 3a is obtained. This is taken as the measured value. The measured value can be expressed in units of % using the mathematical formula of (Np / Nn - 1). A positive sign indicates a state where the amount of p-type impurities is more than the amount of n-type impurities. A negative sign indicates a state where the amount of n-type impurities is more than the amount of p-type impurities.

[0070] Predict the amount of p-type impurities in the p- - type semiconductor layer 3a when the second gas is supplied at a nominal flow rate. Based on this prediction result, calculate the predicted value of the impurity ratio. Specifically, the predicted value of the impurity ratio is expressed as (Np1 / Nn1 - 1). Np1 is the predicted amount of p-type impurities in the p- - type semiconductor layer 3a. Nn1 is the pre-specified amount of n-type impurities in the n- - type semiconductor layer 2a. Np1 is the product of the cross-sectional area of the opening OP1 and the p-type impurity concentration in the p- - type semiconductor layer 3a. The cross-sectional area of the opening OP1 is the predicted cross-sectional area when forming the opening OP1 through the opening OP2 with the measured width. The p-type impurity concentration is the value when the second gas is supplied at a nominal flow rate. Nn1 is the product of the n-type impurity concentration in the n- - type semiconductor layer 2a and the cross-sectional area of the n- - type semiconductor layer 2a between the openings OP1. The n- -The n-type impurity concentration in the n-type semiconductor layer 2a is provided by the manufacturer supplying the semiconductor substrate Sub. Alternatively, it is also possible to measure the n-type impurity concentration in the n-type semiconductor layer 2a before processing in the semiconductor manufacturing apparatus by means of a mercury probe or CV measurement. The cross-sectional area of the n-type semiconductor layer 2a between the openings OP1 is a value obtained by subtracting the predicted cross-sectional area of the opening OP1 from the nominal values of the pitch of the gate electrodes 10 and the depth of the opening OP1. - The cross-sectional area of the n-type semiconductor layer 2a between the openings OP1 is a value obtained by subtracting the predicted cross-sectional area of the opening OP1 from the nominal values of the pitch of the gate electrodes 10 and the depth of the opening OP1. - The cross-sectional area of the n-type semiconductor layer 2a between the openings OP1 is a value obtained by subtracting the predicted cross-sectional area of the opening OP1 from the nominal values of the pitch of the gate electrodes 10 and the depth of the opening OP1.

[0071] Figure 7 The graph of (b) is obtained by the same procedure as the graph of (a). Figure 7 The graph of (b) is obtained by the same procedure as the graph of (a).

[0072] During the manufacturing process of the semiconductor device, the first mass, the second mass, and the width of the opening OP2 are measured. The p-type semiconductor layer 3a is formed by supplying a second gas at a nominal flow rate. Based on the electrical characteristics of the manufactured semiconductor device, it is possible to calculate the ratio of the amount of n-type impurities contained in the n-type semiconductor layer 2a to the amount of p-type impurities contained in the p-type semiconductor layer 3a. This is taken as the measured value. - During the manufacturing process of the semiconductor device, the first mass, the second mass, and the width of the opening OP2 are measured. The p-type semiconductor layer 3a is formed by supplying a second gas at a nominal flow rate. Based on the electrical characteristics of the manufactured semiconductor device, it is possible to calculate the ratio of the amount of n-type impurities contained in the n-type semiconductor layer 2a to the amount of p-type impurities contained in the p-type semiconductor layer 3a. This is taken as the measured value. - During the manufacturing process of the semiconductor device, the first mass, the second mass, and the width of the opening OP2 are measured. The p-type semiconductor layer 3a is formed by supplying a second gas at a nominal flow rate. Based on the electrical characteristics of the manufactured semiconductor device, it is possible to calculate the ratio of the amount of n-type impurities contained in the n-type semiconductor layer 2a to the amount of p-type impurities contained in the p-type semiconductor layer 3a. This is taken as the measured value. - During the manufacturing process of the semiconductor device, the first mass, the second mass, and the width of the opening OP2 are measured. The p-type semiconductor layer 3a is formed by supplying a second gas at a nominal flow rate. Based on the electrical characteristics of the manufactured semiconductor device, it is possible to calculate the ratio of the amount of n-type impurities contained in the n-type semiconductor layer 2a to the amount of p-type impurities contained in the p-type semiconductor layer 3a. This is taken as the measured value.

[0073] Predict the amount of n-type impurities in the n-type semiconductor layer 2a and the amount of p-type impurities in the p-type semiconductor layer 3a when the second gas is supplied at a flow rate corresponding to the first change amount and the second change amount. The predicted value of the impurity amount ratio represented by (Np1 / Nn1 - 1). - Predict the amount of n-type impurities in the n-type semiconductor layer 2a and the amount of p-type impurities in the p-type semiconductor layer 3a when the second gas is supplied at a flow rate corresponding to the first change amount and the second change amount. The predicted value of the impurity amount ratio represented by (Np1 / Nn1 - 1). - Predict the amount of n-type impurities in the n-type semiconductor layer 2a and the amount of p-type impurities in the p-type semiconductor layer 3a when the second gas is supplied at a flow rate corresponding to the first change amount and the second change amount. The predicted value of the impurity amount ratio represented by (Np1 / Nn1 - 1).

[0074] In Figure 7 of (a) and Figure 7 of (b), the horizontal axis represents the predicted value of the impurity amount ratio, and the vertical axis represents the measured value of the impurity amount ratio. The solid line represents the line where the predicted value and the measured value are the same. Comparing the results of Figure 7 of (a) and Figure 7 of (b), it can be seen that for the manufacturing method of the embodiment, the deviation of the measured value from the predicted value is smaller than that of the manufacturing method of the reference example. Specifically, for the manufacturing method of the reference example, the coefficient of determination R of the predicted value with respect to the measured value 2 is 0.53. For the manufacturing method of the embodiment, the coefficient of determination R of the predicted value with respect to the measured value 2 is 0.84. The smaller the deviation of the predicted value from the measured value, the more the difference in the amount of impurities can be reduced when performing feedforward control on the p-type impurity concentration of the p-type semiconductor layer 3a. According to the manufacturing method of the embodiment, compared with the manufacturing method of the reference example, the difference in the amount of impurities can be reduced. Thus, for example, the yield can be improved. - is 0.84. The smaller the deviation of the predicted value from the measured value, the more the difference in the amount of impurities can be reduced when performing feedforward control on the p-type impurity concentration of the p-type semiconductor layer 3a. According to the manufacturing method of the embodiment, compared with the manufacturing method of the reference example, the difference in the amount of impurities can be reduced. Thus, for example, the yield can be improved.

[0075] The calculations of the above-mentioned quality difference, the first change amount, the second change amount, the acquisition of the correction amount, the correction of the flow rate of the second gas, etc. are performed by a general-purpose or dedicated computer. Alternatively, these processes can also be performed by a person.

[0076] In the manufacturing method of the above-described embodiment, other processes can also be appropriately added. For example, the formation of the n-type semiconductor layer and the set of processes shown in (a) to (b) of can be performed multiple times to form regions corresponding to the n-type pillar region 2n and the p-type pillar region 3. Also in this case, the quality is measured after the formation of the insulating layer IL1 and after the formation of the opening in the n-type semiconductor layer, and the p-type impurity concentration in the p-type semiconductor layer is adjusted based on the quality difference. Thereby, for example, a semiconductor device 100 with a small difference in impurity amount is manufactured. - and Figure 2 of (a) to Figure 3 of (b) to form regions corresponding to the n-type pillar region 2n and the p-type pillar region 3. Also in this case, the quality is measured after the formation of the insulating layer IL1 and after the formation of the opening in the n-type semiconductor layer, and the p-type impurity concentration in the p-type semiconductor layer is adjusted based on the quality difference. Thereby, for example, a semiconductor device 100 with a small difference in impurity amount is manufactured. - type pillar region 2n and p - type pillar region 3 equivalent regions. Also in this case, after the formation of the insulating layer IL1 and after the formation of the opening in the n-type semiconductor layer, the quality is measured, and based on the quality difference, the p-type impurity concentration in the p-type semiconductor layer is adjusted. Thereby, for example, a semiconductor device 100 with a small difference in impurity amount is manufactured. - type semiconductor layer opening are measured respectively, and according to the quality difference, the p-type impurity concentration in the p-type semiconductor layer is adjusted. Thus, for example, a semiconductor device 100 with a small difference in impurity amount is manufactured. - type semiconductor layer. Thus, for example, a semiconductor device 100 with a small difference in impurity amount is manufactured.

[0077] As mentioned above, several embodiments of the present invention have been illustrated, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, changes, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalents. In addition, the above-described embodiments can be implemented in combination with each other.

[0078] Description of Reference Numerals

[0079] 1: n + type drain region, 1a: n + type semiconductor layer, 2: n - type drift region,

[0080] 2a: n - type semiconductor layer, 2n: n - shaped pillar region, 3: p - shaped pillar region,

[0081] 3a: p - type semiconductor layer, 4: p-type substrate region, 4a: p-type semiconductor region,

[0082] 5: n + type source region, 5a: n + type semiconductor region, 6: p + type contact region,

[0083] 10: Gate electrode, 10a: Gate insulating layer, 15: Insulating layer, 21: Drain electrode,

[0084] 22: Source electrode, 22a: First metal layer, 22b: Second metal layer,

[0085] 100: Semiconductor device, IL1 - IL3: Insulating layer, OP1 - OP4: Opening,

[0086] PR: Photoresist, Sub: Semiconductor substrate.

Claims

1. A method for manufacturing a semiconductor component, measuring a first quality of a semiconductor substrate including a first semiconductor layer of a first conductivity type, forming a first opening on an upper surface of the first semiconductor layer, measuring a second quality of the semiconductor substrate having the first opening formed therein, when forming a second semiconductor layer of a second conductivity type inside the first opening, varying an impurity concentration of the second conductivity type in the second semiconductor layer according to a mass difference between the first quality and the second quality, thereby reducing a mass difference in impurity amounts between the impurity amount included in the first semiconductor layer of the first conductivity type and the impurity amount included in the second semiconductor layer of the second conductivity type.

2. The method for manufacturing a semiconductor component according to claim 1, wherein, in the formation of the first opening, forming a first layer having a second opening thereon above the upper surface, the second opening being provided corresponding to a position where the first opening is formed, measuring a length of the second opening in a first direction along the upper surface, using the first layer as a mask to form the first opening, when forming the second semiconductor layer, further varying the impurity concentration of the second conductivity type in the second semiconductor layer according to the length.

3. The method for manufacturing a semiconductor component according to claim 1 or 2, wherein, the second semiconductor layer is formed by supplying a first gas containing a semiconductor material and a second gas containing an impurity of the second conductivity type to the semiconductor substrate, when forming the second semiconductor layer, varying the impurity concentration of the second conductivity type in the second semiconductor layer by varying a flow rate or pressure of the second gas according to the mass difference.

4. The method for manufacturing a semiconductor component according to claim 1 or 2, wherein, a plurality of the first openings are formed in a first direction along the upper surface.

5. The method for manufacturing a semiconductor component according to claim 1 or 2, wherein, the first semiconductor layer and the second semiconductor layer include at least one selected from the group consisting of silicon, silicon carbide, and gallium nitride.

6. A method for manufacturing a semiconductor device, implementing the method for manufacturing a semiconductor component according to any one of claims 1 to 5, forming a first semiconductor region of a second conductivity type on the upper surface of the first semiconductor layer and on the upper surface of the second semiconductor layer, forming a gate electrode above the first semiconductor layer, forming a second semiconductor region of a first conductivity type on the upper surface of the first semiconductor region, forming a first electrode electrically connected to the second semiconductor region above the second semiconductor region, forming a second electrode electrically connected to the first semiconductor layer below the first semiconductor layer.

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