Electronic package and manufacturing method thereof

Abstract

The invention relates to an electronic package and a manufacturing method thereof, which comprises stacking an electronic structure as an integrated voltage stabilizer on an electronic component to facilitate electrical transmission in close coordination with the electronic component.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, in particular to an electronic package and a manufacturing method and an electronic structure thereof. Background Art

[0002] With the booming electronics industry, electronic products are gradually moving towards multi-functionality and high performance. For example, integrated voltage regulators (IVRs) are embedded in high-performance processors to improve efficiency, such as switching frequency, reduce power consumption, improve reliability, and even reduce manufacturing costs. Furthermore, current chip packaging technologies include flip-chip packaging modules such as chip scale package (CSP), direct chip attached (DCA), or multi-chip module (MCM), as well as chip stacking technology that integrates chips into three-dimensional integrated circuits (3D ICs).

[0003] Figure 1 FIG. 1 is a cross-sectional view of a 3D chip stacking packaging structure 1. Figure 1 As shown, the packaging structure 1 includes a silicon interposer (TSI) 1a having a silicon plate 10 and a plurality of conductive through-silicon vias (TSVs) 101 formed therein, and a redistribution layer (RDL) electrically connected to the conductive through-silicon vias 101 is formed on the surface of the silicon plate 10. Specifically, the redistribution layer includes a dielectric layer 11 and a circuit layer 12 formed on the dielectric layer 11, and the circuit layer 12 is electrically connected to the conductive through-silicon vias 101, and an insulating protective layer 13 is formed on the dielectric layer 11 and the circuit layer 12, and the insulating protective layer 13 exposes a portion of the circuit layer 12 to combine with a plurality of solder bumps 14.

[0004] In addition, another insulating protective layer 15 can be first formed on the silicon plate 10, and the insulating protective layer 15 exposes the end surfaces of the conductive silicon vias 101 to combine multiple solder bumps 16 on the end surfaces of the conductive silicon vias 101, and the solder bumps 16 are electrically connected to the conductive silicon vias 101. Among them, an under bump metallurgy (UBM) 160 for receiving the solder bumps 16 can be optionally formed on the end surfaces of the conductive silicon vias 101.

[0005] In addition, the package structure 1 further includes a package substrate 19 on which the silicon interposer 1 a is disposed via the solder bumps 16 , so that the package substrate 19 is electrically connected to the conductive TSVs 101 and the solder bumps 16 are covered with an underfill 191 .

[0006] In addition, the package structure 1 further includes a plurality of system-on-chip (SOC) semiconductor chips 17 disposed on the solder bumps 14 so that the semiconductor chips 17 are electrically connected to the circuit layer 12. The solder bumps 14 are covered with an underfill 171, and a packaging material 18 is formed on the package substrate 19 so that the packaging material 18 covers the semiconductor chips 17 and the silicon interposer 1a.

[0007] In subsequent applications, the package structure 1 may form a plurality of solder balls 192 on the bottom side of the package substrate 19 to be mounted on a circuit board 1 ′.

[0008] In early commercial products, a voltage regulator (IVR) 1b' was directly mounted on the circuit board. However, this method would result in the end product's volume failing to meet the requirements of being thin and light. In addition, the voltage regulator 1b' was too far away from the package structure 1, causing the signal transmission path of the semiconductor chip 17 electrically connected to it to be too long, resulting in a decrease in electrical performance and an increase in power consumption.

[0009] Therefore, the industry has integrated the voltage regulator 1 b into the lower side of the package substrate 19 to shorten the transmission distance between the voltage regulator 1 b and the semiconductor chip 17 , thereby reducing the surface area and volume of the circuit board 1 ′.

[0010] However, as the consumer market demands, the functional requirements of today's terminal products are becoming increasingly diverse. Therefore, more and more semiconductor chips 17 are placed on the package substrate 19, and the demand for the corresponding regulator 1b has increased significantly. As a result, there is no extra space on the lower side of the package substrate 19 to configure more regulators 1b. As a result, the single package structure 1 can no longer meet the requirements of today's terminal products such as being light, thin, short, low power consumption, and high electrical performance.

[0011] Furthermore, although the voltage regulator 1 b can be integrated into the semiconductor chip 17 , the package structure 1 needs to be redesigned, which not only increases the manufacturing cost but also increases the size of the semiconductor chip 17 , making it difficult to meet the demand for miniaturization.

[0012] Therefore, how to overcome the various problems of the above-mentioned known technologies has become a difficult problem that needs to be overcome urgently in the industry. Summary of the Invention

[0013] In view of the above-mentioned various deficiencies of the prior art, the present invention provides an electronic package and a manufacturing method thereof, so as to facilitate electrical transmission between electronic components in close proximity.

[0014] The electronic package of the present invention includes: an electronic structure, which includes an electronic body having a first side and a second side opposite to each other, and a conductor formed on the first side of the electronic body; an electronic component, which is combined with the conductor of the electronic structure; a conductive column, which is arranged on the electronic component to electrically connect the electronic component to the conductive column and the conductor; and a coating layer, which is formed on the electronic component to coat the electronic structure and the conductive column.

[0015] The present invention also provides a method for manufacturing an electronic package, comprising: providing an electronic body having a first side and a second side opposite to each other; forming a conductor on the first side of the electronic body to form an electronic structure; arranging the electronic structure with its conductor on an electronic component, and forming a plurality of conductive columns on the electronic component to electrically connect the conductive columns and the conductor; and forming a coating layer on the electronic component to coat the electronic structure and the conductive columns.

[0016] In the aforementioned electronic package and its manufacturing method, the electronic body comprises a base and a circuit portion formed on the base, such that the base defines the second side and the circuit portion defines the first side. The base has a plurality of conductive through-holes electrically connected to the circuit portion and exposing the second side. For example, the conductor is formed on the second side of the electronic body, and an insulating layer is formed on the second side of the electronic body, such that the insulating layer covers the conductor on the second side.

[0017] In the aforementioned electronic package and its manufacturing method, the surface of the coating layer is flush with the end surface of the conductive column.

[0018] In the aforementioned electronic package and its manufacturing method, the end surface of the conductive column is exposed outside the surface of the coating layer.

[0019] In the aforementioned electronic package and its manufacturing method, the conductor is electrically connected to the electronic component via the conductive bump.

[0020] The aforementioned electronic package and its manufacturing method further include forming a plurality of conductive elements on the cladding layer, and electrically connecting the plurality of conductive elements to the conductive pillars.

[0021] The aforementioned electronic package and method of manufacturing the same may further include forming a circuit structure on the cladding layer and electrically connecting the circuit structure to the conductive pillar. For example, the method may further include forming a plurality of conductive elements on the circuit structure and electrically connecting the plurality of conductive elements to the circuit structure. Alternatively, the circuit structure may be a fan-in or fan-out configuration.

[0022] As can be seen from the above, the electronic package and its manufacturing method of the present invention mainly stack the electronic structure on the electronic component to closely match the electronic component. Therefore, compared with the known technology, the present invention does not require redesigning the electronic package, thereby significantly saving production costs and does not require increasing the size of the electronic component, which is conducive to meeting the needs of miniaturization and facilitating the presentation of high electrical performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a cross-sectional schematic diagram of the packaging structure.

[0024] Figures 2A to 2G FIG. 1 is a cross-sectional view of a first embodiment of a method for manufacturing an electronic package according to the present invention.

[0025] Figure 2G' To correspond Figure 2G Schematic cross-sectional view of other embodiments.

[0026] Figure 2H for Figure 2G A cross-sectional schematic diagram of the subsequent process.

[0027] Figures 3A to 3F FIG. 1 is a cross-sectional view of a second embodiment of a method for manufacturing an electronic package according to the present invention.

[0028] Description of Reference Numerals

[0029] 1: Package structure

[0030] 1': Circuit board

[0031] 1a: Silicon interposer

[0032] 1b,1b': Voltage Regulator

[0033] 10: Silicon plate

[0034] 101: Conductive silicon vias

[0035] 11,260: Dielectric layer

[0036] 12: Circuit layer

[0037] 13,15: Insulation protective layer

[0038] 14,16: Solder bumps

[0039] 160: Underbump Metal Layer

[0040] 17: Semiconductor chips

[0041] 171,191: Primer

[0042] 18: Packaging material

[0043] 19:Packaging substrate

[0044] 192: Solder ball

[0045] 2,2',3: Electronic packaging

[0046] 2a: Whole wafer

[0047] 2b,3b: electronic structure

[0048] 21,31: electronic host

[0049] 21': base

[0050] 21”: Line Department

[0051] 21a, 31a: First side

[0052] 21b, 31b: Second side

[0053] 210: Conductive perforation

[0054] 211: passivation layer

[0055] 212: Circuit layer

[0056] 22: Conductive bump

[0057] 23: Conductive column

[0058] 23b: End face

[0059] 24: Binding layer

[0060] 25: coating layer

[0061] 25a: first surface

[0062] 25b: Second surface

[0063] 26: Line structure

[0064] 261: Line redistribution layer

[0065] 27: Conductive element

[0066] 270:Metal column

[0067] 28: Insulation layer

[0068] 280a: first conductor

[0069] 280b: Second conductor

[0070] 29: Electronic components

[0071] 29a: Action surface

[0072] 29b: Non-active surface

[0073] 290,310:Electrode pads

[0074] 3a: Stacking components

[0075] 38: Conductor

[0076] 8: Wiring board

[0077] 9: Loading plate

[0078] 90: Release layer

[0079] 91: Adhesive layer

[0080] L, S: cutting path. DETAILED DESCRIPTION

[0081] The following describes the embodiments of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0082] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment in size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, terms such as "on", "first", "second", "one", etc. quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0083] Figures 2A to 2G FIG. 1 is a cross-sectional view of a first embodiment of a method for manufacturing an electronic package 2 according to the present invention.

[0084] like Figure 2A As shown, a full-panel wafer 2 a is provided, which includes a plurality of electronic bodies 21 arranged in an array, and the electronic body 21 has a first side 21 a and a second side 21 b opposite to each other.

[0085] In this embodiment, the electronic body 21 is an active component, such as a semiconductor chip, which has a silicon base 21' and a circuit portion 21" formed on the base 21', and the base 21' has a plurality of conductive through-holes 210 exposed from the base 21', such as conductive through-silicon vias (TSVs), to electrically connect the circuit portion 21". For example, the circuit portion 21" includes at least one passivation layer 211 and a circuit layer 212 combined with the passivation layer 211, so that the circuit layer 212 is electrically connected to the conductive through-hole 210. Specifically, the base 21' defines the second side 21b, and the circuit portion 21" defines the first side 21a. It should be understood that there are many structural embodiments of the active component having the conductive through-hole 210, and there is no special limitation.

[0086] like Figure 2B As shown, a thinning process is performed, such as by grinding, to remove part of the material of the second side 21 b (or the base 21 ′) of the electronic body 21 , so that the conductive through-hole 210 is exposed outside the second side 21 b .

[0087] like Figure 2C As shown, a plurality of first conductive bodies 280 a and second conductive bodies 280 b are formed on the first side 21 a and the second side 21 b of the electronic body 21 , so that the first conductive bodies 280 a and the second conductive bodies 280 b are electrically connected to the circuit layer 212 and the conductive through-via 210 .

[0088] In this embodiment, the exposed ends of each conductive through-hole 210 contact the first conductive body 280a and the second conductive body 280b respectively. For example, the first conductive body 280a and the second conductive body 280b are metal pillars such as copper pillars.

[0089] Furthermore, an insulating layer 28 may be formed on the second side 21b of the electronic body 21, such that the insulating layer 28 covers the second conductive bodies 280b. For example, the second conductive bodies 280b are not exposed from the insulating layer 28, and the first conductive bodies 280a are combined with the conductive bumps 22. Specifically, the conductive bumps 22 are metal bumps such as copper pillars or solder balls.

[0090] In addition, a singulation process may be performed along the cutting path L to obtain a plurality of electronic structures 2 b , which serve as an integrated voltage regulator (IVR).

[0091] like Figure 2D As shown, an electronic component 29 is provided on a carrier board 9 , and a plurality of conductive pillars 23 are formed on the electronic component 29 so as to arrange at least one electronic structure 2 b on the electronic component 29 .

[0092] In this embodiment, the electronic component 29 is an active component, a passive component, or a combination thereof. The active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 29 is a semiconductor chip, such as a system-on-chip (SOC) type functional chip, having an active surface 29 a and an inactive surface 29 b opposite to each other. The active surface 29 a has a plurality of electrode pads 290, and the inactive surface 29 b is disposed on the carrier board 9.

[0093] In addition, the carrier plate 9 is, for example, a plate made of semiconductor material (such as silicon or glass), on which a release layer 90 (or adhesive layer) may be formed as required, so that the electronic component 29 can be disposed on the release layer 90 .

[0094] In addition, the conductive pillar 23 is disposed on a portion of the electrode pad 290 of the electronic component 29 and electrically connected to the electrode pad 290 . The conductive pillar 23 is made of a metal material such as copper or a solder material.

[0095] In addition, the electronic structure 2b is bonded to another portion of the electrode pads 290 of the electronic component 29 via a plurality of conductive bumps 22 to electrically connect the electrode pads 290. For example, a bonding layer 24 such as a primer can be used to cover the conductive bumps 22 and the first conductor 280a as needed.

[0096] like Figure 2E As shown, a cladding layer 25 is formed on the active surface 29a of the electronic component 29, so that the cladding layer 25 covers the electronic structure 2b, the bonding layer 24, and the conductive pillars 23. The cladding layer 25 has a first surface 25a and a second surface 25b opposite each other, and the first surface 25a is bonded to the active surface 29a of the electronic component 29. Next, a planarization process is performed to align the second surface 25b of the cladding layer 25 with the end surface 23b of the conductive pillar 23 and the insulating layer 28 of the electronic structure 2b (or the end surface of the second conductive body 280b). This allows the end surface 23b of the conductive pillar 23 and the insulating layer 28 of the electronic structure 2b (or the end surface of the second conductive body 280b) to be exposed outside the second surface 25b of the cladding layer 25.

[0097] In this embodiment, the coating layer 25 is an insulating material, such as an epoxy resin encapsulation colloid, and can be formed on the electronic component 29 by lamination or molding.

[0098] In addition, the planarization process removes part of the material of the conductive pillar 23 , part of the material of the insulating layer 28 (or the second conductor 280 b ) of the electronic structure 2 b , and part of the material of the cladding layer 25 by grinding.

[0099] In addition, if the bonding layer 24 is not formed, the coating layer 25 may cover the conductive bumps 22 and the first conductive body 280 a .

[0100] like Figure 2F As shown, a circuit structure 26 is formed on the second surface 25 b of the cladding layer 25 , and the circuit structure 26 is electrically connected to the conductive pillars 23 and the second conductor 280 b of the electronic structure 2 b .

[0101] In this embodiment, the circuit structure 26 includes multiple second dielectric layers 260 and multiple redistribution layers (RDLs) 261 disposed on the multiple dielectric layers 260. The outermost dielectric layer 260 can serve as a solder mask, so that the outermost RDL 261 is partially exposed. Alternatively, the circuit structure 26 can include only a single dielectric layer 260 and a single RDL 261.

[0102] In addition, the material forming the circuit redistribution layer 261 is copper, and the material forming the dielectric layer 260 is a dielectric material such as poly(p-oxadiazole) (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

[0103] Additionally, a plurality of conductive elements 27, such as solder balls, may be formed on the outermost redistribution layer 261 to electrically connect the conductive pillars 23 and / or the second conductor 280b. For example, the circuit structure 26 may be configured in a fan-in configuration so that the layout of the conductive elements 27 does not exceed the area of the active surface 29a of the electronic component 29.

[0104] like Figure 2G As shown, the carrier plate 9 and the release layer 90 thereon are removed to expose the electronic components 29, and then Figure 2F The cutting path S shown is used to perform a singulation process to obtain the electronic package 2 .

[0105] In this embodiment, if Figure 2H As shown, in the subsequent process, these conductive elements 27 can be connected to the upper side of a wiring board 8, such as an organic material board (such as a packaging substrate with a core layer and a circuit portion or a coreless packaging substrate with a circuit portion) or an inorganic material board (such as a silicon board), and the lower side of the wiring board 8 can be connected to an electronic device such as a circuit board (not shown).

[0106] In addition, in another embodiment, if Figure 2G'The electronic package 2' shown may omit the circuit structure 26 as needed. For example, the conductive elements 27 may be attached to the second conductive body 280b of the electronic structure 2b and the conductive pillar 23 to electrically connect the second conductive body 280b and the conductive pillar 23. Specifically, the conductive elements 27 may be bonded to the second conductive body 280b and the conductive pillar 23 via metal pillars 270, such as copper pillars.

[0107] Therefore, the manufacturing method of the present invention stacks the electronic structure 2b serving as an IVR on the electronic component 29 to facilitate coordination with the electronic components 29 with different functions. Therefore, compared to the known method of integrating the IVR into the SOC, the manufacturing method of the present invention does not require redesigning the electronic package 2, 2', thereby significantly saving production costs and eliminating the need to increase the size of the electronic component 29 to meet the demand for miniaturization.

[0108] In addition, compared to the conventional method of integrating IVR into a circuit board or a package substrate, the electrical transmission distance between the electronic structure 2b of the present invention and the electronic component 29 can be minimized (without passing through the package substrate or circuit board), thereby reducing losses and shrinking the size of the electronic package 2, 2', and improving electrical performance.

[0109] Figures 3A to 3F 2 is a cross-sectional view of a second embodiment of the method for manufacturing an electronic package 3 of the present invention. The difference between this embodiment and the first embodiment lies in the embodiment of the electronic structure 3b. The other processes are substantially the same, so the similarities will not be repeated below.

[0110] like Figure 3A As shown, an electronic structure 3 b is provided, which has a plurality of conductive bodies 38 for combining with the conductive bumps 22 to serve as an integrated voltage regulator (IVR).

[0111] In this embodiment, the electronic structure 3b is an active component, such as a semiconductor chip, and its electronic body 31 has a first side 31a and a second side 31b opposite to each other. The first side 31a has a plurality of electrode pads 310 for combining with the conductor 38, and the electronic body 31 does not have the conductive through hole 210.

[0112] like Figure 3B As shown, the electronic structure 3b is provided on the electronic component 29 with the conductive bump 22 to form a stacked assembly 3a, and a plurality of conductive pillars 23 are formed on the electronic component 29. Thereafter, a singulation process is performed to obtain a plurality of stacked assemblies 3a.

[0113] In this embodiment, the electronic structure 3b is flip-chip bonded to a portion of the electrode pads 290 of the electronic component 29 via a plurality of conductive bumps 22 to electrically connect the electrode pads 290. For example, a bonding layer 24 such as a primer can be used to cover the conductive bumps 22 and the conductor 38 as needed.

[0114] like Figure 3C As shown, the stack assembly 3 a is placed on a carrier plate 9 with the inactive surface 29 b of the electronic component 29 thereof.

[0115] In this embodiment, the carrier plate 9 is, for example, a plate made of semiconductor material (such as silicon or glass), on which a release layer 90 and an adhesive layer 91 may be sequentially formed as needed, so that the electronic component 29 is disposed on the adhesive layer 91 .

[0116] like Figure 3D As shown, a coating layer 25 is formed on the adhesive layer 91 of the carrier plate 9 so that the coating layer 25 covers the stacked assembly 3a. The coating layer 25 has a first surface 25a and a second surface 25b opposite to each other, and the first surface 25a is bonded to the adhesive layer 91. Then, through a flattening process, the second surface 25b of the coating layer 25 is aligned with the end surface 23b of the conductive pillar 23 and the second side 31b of the electronic body 31 of the electronic structure 3b, so that the end surface 23b of the conductive pillar 23 is exposed on the second surface 25b of the coating layer 25.

[0117] In this embodiment, the coating layer 25 is an insulating material, such as an epoxy resin encapsulation colloid, and can be formed on the adhesive layer 91 by lamination or molding.

[0118] In addition, the planarization process removes part of the material of the conductive pillar 23 and part of the material of the cladding layer 25 (and even part of the material of the electronic body 31 ) by grinding.

[0119] like Figure 3E As shown, a circuit structure 26 is formed on the cladding layer 25, and the circuit structure 26 is electrically connected to the conductive pillars 23, and a plurality of conductive elements 27 such as solder balls are formed on the outermost circuit redistribution layer 261, so that the plurality of conductive elements 27 are electrically connected to the circuit redistribution layer 261.

[0120] In this embodiment, the circuit structure 26 is a fan-out configuration, so that the layout range of the conductive elements 27 exceeds the area of the active surface 29 a of the electronic element 29 .

[0121] like Figure 3F As shown, the carrier plate 9 and the release layer 90 and the adhesive layer 91 thereon are removed to expose the inactive surface 29b of the electronic component 29. Figure 3E The cutting path S shown is used for singulation process to complete the electronic package 3 of the present invention, and the electronic package 3 can be connected to an electronic device (omitted) such as a packaging structure or other structure (such as a circuit board or an interposer) through the conductive elements 27 in subsequent processes.

[0122] Therefore, the manufacturing method of the present invention stacks the electronic structure 3b serving as the IVR on the electronic component 29 to facilitate coordination with the electronic components 29 with different functions. Therefore, compared to the known method of integrating the IVR into the SOC, the manufacturing method of the present invention does not require redesigning the electronic package 3, thereby significantly saving production costs and eliminating the need to increase the size of the electronic component 29 to meet miniaturization requirements.

[0123] In addition, compared to the known method of integrating the IVR into a circuit board or a packaging substrate, the electrical transmission distance between the electronic structure 3b of the present invention and the electronic component 29 can be minimized (without passing through the packaging substrate or circuit board), thereby reducing losses and shrinking the size of the electronic package 3, and improving electrical performance.

[0124] The present invention further provides an electronic package 2 , 2 ′, 3 , comprising: an electronic structure 2 b , 3 b , an electronic component 29 , a plurality of conductive pillars 23 , and a coating layer 25 .

[0125] The electronic structure 2b, 3b includes an electronic body 21, 31 having a first side 21a, 31a and a second side 21b, 31b opposite to each other, and a first conductor 280a (or conductor 38) is formed on the first side 21a, 31a of the electronic body 21, 31.

[0126] The electronic component 29 is combined with the first conductive body 280a (or the conductive body 38) of the electronic structure 2b, 3b.

[0127] The conductive post 23 is disposed on the electronic component 29 so that the electronic component 29 is electrically connected to the conductive post 23 and the first conductor 280 a or the conductor 38 .

[0128] The coating layer 25 is formed on the electronic component 29 to cover the electronic structures 2 b and 3 b and the conductive pillars 23 .

[0129] In one embodiment, the electronic body 21 has a base 21′ and a circuit portion 21″ formed on the base 21′, such that the base 21′ defines the second side 21b, and the circuit portion 21″ defines the first side 21a. The base 21′ has a plurality of conductive through-holes 210 electrically connected to the circuit portion 21″ and exposing the second side 21b. For example, a second conductor 280b is further formed on the second side 21b of the electronic body 21, and an insulating layer 28 is formed on the second side 21b of the electronic body 21, so that the insulating layer 28 covers the second conductor 280b.

[0130] In one embodiment, the second surface 25 b of the cladding layer 25 is flush with the end surface 23 b of the conductive pillar 23 .

[0131] In one embodiment, the end surface 23 b of the conductive pillar 23 is exposed from the second surface 25 b of the cladding layer 25 .

[0132] In one embodiment, the first conductive body 280 a (or the conductive body 38 ) is electrically connected to the electronic component 29 via the conductive bump 22 .

[0133] In one embodiment, the electronic package 2 ′ further includes a plurality of conductive elements 27 formed on the coating layer 25 , such that the plurality of conductive elements 27 are electrically connected to the conductive pillars 23 .

[0134] In one embodiment, the electronic packages 2 and 3 further include a circuit structure 26 formed on the cladding layer 25, such that the circuit structure 26 is electrically connected to the conductive pillars 23. Furthermore, the electronic packages 2 and 3 further include a plurality of conductive elements 27 formed on the circuit structure 26, such that the plurality of conductive elements 27 are electrically connected to the circuit structure 26. For example, the circuit structure 26 is configured in a fan-in or fan-out configuration.

[0135] In summary, the electronic package and its manufacturing method of the present invention stack the electronic structure on the electronic component to closely match the electronic component. Therefore, the present invention does not need to redesign the electronic package, thereby significantly saving production costs and does not need to increase the size of the electronic component, thereby meeting the needs of miniaturization and facilitating the presentation of high electrical performance.

[0136] Furthermore, by embedding the electronic structure serving as an IVR in the coating layer, the electronic package can be applied to a server or base station processor.

[0137] The above embodiments are intended only to illustrate the principles and effects of the present invention and are not intended to limit the present invention. Any skilled artisan may modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as set forth in the appended claims.

Claims

1. An electronic package, characterized in that: include: An electronic structure includes an electronic body having a first side and a second side opposite to each other, and a first conductor and a second conductor formed on the first side and the second side of the electronic body respectively; an electronic component incorporating a first electrical conductor of the electronic structure; a conductive post disposed on the electronic component so as to electrically connect the electronic component to the conductive post and the first conductor; as well as The covering layer is formed on the electronic component to cover the electronic structure and the conductive column.

2. The electronic package according to claim 1, wherein: The electronic body has a base and a circuit portion formed on the base, so that the base defines the second side, and the circuit portion defines the first side. The base has a plurality of conductive through holes electrically connected to the circuit portion and exposing the second side.

3. The electronic package according to claim 2, wherein: An insulating layer covering the second conductor is formed on the second side of the electronic body.

4. The electronic package according to claim 1, wherein: The surface of the cladding layer is flush with the end surface of the conductive column.

5. The electronic package according to claim 1, wherein: The end surface of the conductive column is exposed outside the surface of the cladding layer.

6. The electronic package according to claim 1, wherein: The first conductor is electrically connected to the electronic component via a conductive bump.

7. The electronic package according to claim 1, wherein: The electronic package also includes a plurality of conductive elements formed on the covering layer, and the plurality of conductive elements are electrically connected to the conductive pillar.

8. The electronic package according to claim 1, wherein: The electronic package also includes a circuit structure formed on the covering layer, and the circuit structure is electrically connected to the conductive column.

9. The electronic package according to claim 8, wherein: The electronic package also includes a plurality of conductive elements formed on the circuit structure, and the plurality of conductive elements are electrically connected to the circuit structure.

10. The electronic package according to claim 8, wherein The circuit structure is a fan-in configuration or a fan-out configuration.

11. A method for manufacturing an electronic package, characterized in that: include: Providing an electronic body having a first side and a second side opposite to each other; forming a first conductor and a second conductor on the first side and the second side of the electronic body respectively to form an electronic structure; The electronic structure is provided on an electronic component with its first conductive body, and a plurality of conductive pillars are formed on the electronic component, so that the electronic component is electrically connected to the conductive pillars and the first conductive body; as well as A coating layer is formed on the electronic component to cover the electronic structure and the conductive column.

12. The method for manufacturing an electronic package according to claim 11, wherein: The electronic body has a base and a circuit portion formed on the base, so that the base defines the second side, and the circuit portion defines the first side. The base has a plurality of conductive through holes electrically connected to the circuit portion and exposing the second side.

13. The method for manufacturing an electronic package according to claim 12, wherein: An insulating layer covering the second conductor on the second side is formed on the second side of the electronic body.

14. The method for manufacturing an electronic package according to claim 11, wherein: The surface of the cladding layer is flush with the end surface of the conductive column.

15. The method for manufacturing an electronic package according to claim 11, wherein: The end surface of the conductive column is exposed outside the surface of the cladding layer.

16. The method for manufacturing an electronic package according to claim 11, wherein: The first conductor is electrically connected to the electronic component via a conductive bump.

17. The method for manufacturing an electronic package according to claim 11, wherein: The manufacturing method further includes forming a plurality of conductive elements on the cladding layer, and electrically connecting the plurality of conductive elements to the conductive pillar.

18. The method for manufacturing an electronic package according to claim 11, wherein: The manufacturing method further includes forming a circuit structure on the cladding layer, and electrically connecting the circuit structure to the conductive column.

19. The method for manufacturing an electronic package according to claim 18, wherein: The manufacturing method further includes forming a plurality of conductive elements on the circuit structure, and electrically connecting the plurality of conductive elements to the circuit structure.

20. The method for manufacturing an electronic package according to claim 18, wherein: The circuit structure is a fan-in configuration or a fan-out configuration.

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