Memory device and method of manufacturing the same

Abstract

The present invention discloses a memory device and a manufacturing method thereof. The memory device includes a laminate structure and a stepped structure. The laminate structure includes a first sub-laminate structure and a second sub-laminate structure. The stepped structure is electrically connected to the laminate structure. The stepped structure includes a first sub-stepped structure and a second sub-stepped structure. The first sub-stepped structure and the second sub-stepped structure each include a first stepped portion and a second stepped portion. The first sub-laminate structure and the second sub-laminate structure are respectively connected to the first stepped portion of the first sub-stepped structure and the first stepped portion of the second sub-stepped structure.

Description

Technical Field

[0001] The invention relates to a memory device and a manufacturing method thereof. Background Art

[0002] In recent years, the size of semiconductor devices has been gradually reduced. In semiconductor technology, the reduction of feature size, speed, performance, density and cost per integrated circuit are all very important goals. In practical applications, while the size of the device is reduced, the electrical properties of the device must still be maintained to meet commercial needs. Summary of the invention

[0003] The invention relates to a memory device and a manufacturing method thereof.

[0004] According to one aspect of the present invention, a memory device is provided, which includes a stacked body structure and a stepped structure. The stacked body structure includes a first sub-stacked body structure and a second sub-stacked body structure. The stepped structure is electrically connected to the stacked body structure. The stepped structure includes a first sub-stacked structure and a second sub-stacked structure. The first sub-stacked structure and the second sub-stacked structure each include a first stepped portion and a second stepped portion. The first sub-stacked body structure and the second sub-stacked body structure are respectively connected to the first stepped portion of the first sub-stacked structure and the first stepped portion of the second sub-stacked structure.

[0005] According to another aspect of the present invention, a method for manufacturing a memory device is provided, which includes the following steps. Multiple conductive layers and multiple insulating layers are stacked alternately in a vertical direction to form a stacked structure. The stacked structure includes a first stacked portion, a second stacked portion and another first stacked portion arranged in a first direction. The first stacked portion and the other first stacked portion are respectively on opposite sides of the second stacked portion. The first stacked portion and the other first stacked portion are in a stepped contact area. The second stacked portion is in a memory array area. The first stacked portion and the other first stacked portion are etched using multiple photoresist layers to form a stepped structure. In the stepped contact area, the dimensions of the photoresist layers in the first direction and / or a second direction are different from each other. The first direction, the second direction and the vertical direction are perpendicular to each other. The memory device includes a stacked body structure and a stepped structure. The stacked body structure includes a first sub-stacked body structure and a second sub-stacked body structure. The first sub-stacked body structure and the second sub-stacked body structure include the second stacked portion. The stepped structure is electrically connected to the laminate structure and includes a first sub-stepped structure and a second sub-stepped structure. The first sub-stepped structure and the second sub-stepped structure each include a first stepped portion and a second stepped portion. The first sub-laminate structure and the second sub-laminate structure are respectively connected to the first stepped portion of the first sub-stepped structure and the first stepped portion of the second sub-stepped structure.

[0006] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 4 is a schematic top view of a memory device according to an embodiment.

[0008] Figure 2 FIG. 4 is a schematic top view of a memory device according to another embodiment.

[0009] 3A to 3T A method for manufacturing a memory device according to an embodiment is illustrated.

[0010]

Explanation of symbols

[0011] 1~96: Conductive step layer

[0012] 100: Laminated structure

[0013] 101: First laminate body

[0014] 102: Second laminated body

[0015] 110: First sub-laminate structure

[0016] 111: First laminate body

[0017] 112: Second laminated body

[0018] 120: Second sub-laminate structure

[0019] 121: First laminate body

[0020] 122: Second laminated body

[0021] 130: The third sub-laminate structure

[0022] 131: First laminate body

[0023] 132: Second laminated body

[0024] 140: Fourth sub-laminate structure

[0025] 141: First laminate body

[0026] 142: Second laminated body

[0027] 200: Ladder structure

[0028] 210: First sub-ladder structure

[0029] 211: First step

[0030] 212: Second step

[0031] 220: Second sub-ladder structure

[0032] 221: First step

[0033] 222: Second step

[0034] 230: The third sub-ladder structure

[0035] 231: First step

[0036] 232: Second step

[0037] 240: The fourth sub-ladder structure

[0038] 241: First step

[0039] 242: Second step

[0040] 300: Columnar element

[0041] 410, 420: Insulation components

[0042] 500: Dielectric components

[0043] 610, 620, 630, 640: word line driver

[0044] 700: Laminated structure

[0045] 701, 701-1, 701-2: First laminated part

[0046] 701G1~701G11:Inner laminated part

[0047] 701K1~701K11:Outer laminated part

[0048] 701P1~701P3, 701Q1~701Q3: Laminated area

[0049] 702: Second laminated part

[0050] 707: Conductive layer

[0051] 708: Insulation layer

[0052] 7011: First sub-laminate

[0053] 7012: Second sub-laminate

[0054] C: Stepped contact area

[0055] D1: First direction

[0056] D2: Second direction

[0057] E, F: Step size

[0058] H1, H2, T1, T11, T12, T21, T22: Dimensions

[0059] M: Memory array area

[0060] PR1~, PR15: Photoresist layer

[0061] Z: vertical direction DETAILED DESCRIPTION

[0062] The following are some embodiments for illustration. It should be noted that the present invention does not show all possible embodiments, and other embodiments not proposed in the present invention may also be applicable. Furthermore, the dimensional ratios in the drawings are not drawn in proportion to the actual product. Therefore, the description and the illustrated contents are only used to describe the embodiments, and are not used to limit the scope of protection of the present invention. In addition, the descriptions in the embodiments, such as local structures, process steps and material applications, etc., are only for illustrative purposes and are not intended to limit the scope of protection of the present invention. The steps and structural details of the embodiments can be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present invention. The following is an illustration of the same / similar elements represented by the same / similar symbols.

[0063] Please refer to Figure 1 , which is a schematic top view of a memory device according to an embodiment. The memory device includes a stacked structure 100 and a stepped structure 200. The stepped structure 200 is electrically connected to the stacked structure 100. The stepped structure 200 and the stacked structure 100 include conductive layers and insulating layers that are alternately stacked in a vertical direction Z. The stepped structure 200 is electrically connected to the conductive layer of the stacked structure 100. The vertical direction Z, the first direction D1, and the second direction D2 may be perpendicular to each other.

[0064] In one embodiment, the stepped structure 200 and the stacked structure 100 have 96 conductive layers. The conductive layer of the stepped structure 200 has 96 conductive stepped layers arranged in a stepped manner, such as Figure 1 As shown. The conductive layer of the stepped structure 200 includes, from bottom to top, a conductive step layer 1 of the first level (bottom level), a conductive step layer 2 of the second level, a conductive step layer 3 of the third level, ... to a conductive step layer 94 of the ninety-fourth level, a conductive step layer 95 of the ninety-fifth level, and a conductive step layer 96 of the ninety-sixth level (top level). The stepped structure 200 has 96 stepped units, respectively having a conductive step layer 1, a conductive step layer 2, a conductive step layer 3 ... to a conductive step layer 94, a conductive step layer 95, and a conductive step layer 96. The stepped unit has a step size E in the first direction D1, and has a step size F in the second direction D2. However, the present invention is not limited thereto.

[0065] The stacked structure 100 may include a first sub-stacked structure 110, a second sub-stacked structure 120, a third sub-stacked structure 130, and a fourth sub-stacked structure 140. The first sub-stacked structure 110, the second sub-stacked structure 120, the third sub-stacked structure 130, and the fourth sub-stacked structure 140 are in the memory array region M. The first sub-stacked structure 110, the second sub-stacked structure 120, the third sub-stacked structure 130, and the fourth sub-stacked structure 140 may be arranged in the second direction D2. In this embodiment, the first sub-stacked structure 110, the second sub-stacked structure 120, the third sub-stacked structure 130, and the fourth sub-stacked structure 140 each have the same size T1 in the second direction D2. For example, the sub-laminate structure (e.g., the first sub-laminate structure 110, the second sub-laminate structure 120, the third sub-laminate structure 130, and the fourth sub-laminate structure 140) includes a first laminate body 101. That is, the first sub-laminate structure 110 includes a first laminate body 111. The second sub-laminate structure 120 includes a first laminate body 121. The third sub-laminate structure 130 includes a first laminate body 131. The fourth sub-laminate structure 140 includes a first laminate body 141. The first laminate body 101 (the first laminate body 111, the first laminate body 121, the first laminate body 131, the first laminate body 141) may have a uniform size T1 in the second direction D2.

[0066] The memory cell is defined in the first stack body portion 101 of the first sub-stack structure 110, the second sub-stack structure 120, the third sub-stack structure 130 and the fourth sub-stack structure 140. For example, a columnar element 300 may be formed in the stack structure 100. The columnar element 300 extends through the stack structure 100 in the vertical direction Z. In one embodiment, the columnar element 300 includes a channel column. The storage material layer is configured between the channel column and the conductive layer. The memory cell of the NAND flash memory array is defined in the storage material layer at the intersection of the channel column and the conductive layer. The conductive layer is used as a word line. The channel column is electrically connected to the bit line. In one embodiment, the NAND chip may be a capture layer design. In one embodiment, the NAND chip may be a floating gate design. In one embodiment, the NAND chip may be an array under circuit design.

[0067] The stepped structure 200 may include a first sub-stepped structure 210, a second sub-stepped structure 220, a third sub-stepped structure 230, and a fourth sub-stepped structure 240. The first sub-stepped structure 210, the second sub-stepped structure 220, the third sub-stepped structure 230, and the fourth sub-stepped structure 240 are in the stepped contact region C. The first sub-stepped structure 210 includes a first stepped portion 211 and a second stepped portion 212. The step levels (i.e., the 49th to the 96th levels) of the first stepped portion 211 are higher than the step levels (i.e., the first to the 48th levels) of the second stepped portion 212. The first sub-stacked body structure 110 is connected to the first stepped portion 211 of the first sub-stepped structure 210. The first stepped portion 211 of the first sub-stepped structure 210 is electrically connected between the second stepped portion 212 of the first sub-stepped structure 210 and the first sub-laminate structure 110 .

[0068] The second sub-stair-shaped structure 220 includes a first step-shaped portion 221 and a second step-shaped portion 222. The step levels (i.e., the 49th to the 96th levels) of the first step-shaped portion 221 are higher than the step levels (i.e., the first to the 48th levels) of the second step-shaped portion 222. The second sub-laminated body structure 120 is connected to the first step-shaped portion 221 of the second sub-stair-shaped structure 220. The first step-shaped portion 221 of the second sub-stair-shaped structure 220 is electrically connected between the second step-shaped portion 222 of the second sub-stair-shaped structure 220 and the second sub-laminated body structure 120.

[0069] The first sub-laminate body structure 110 is between the first stepped portion 211 of the first sub-stepped structure 210 and the second stepped portion 222 of the second sub-stepped structure 220. The second sub-laminate body structure 120 is between the second stepped portion 212 of the first sub-stepped structure 210 and the first stepped portion 221 of the second sub-stepped structure 220. The dimension H1 of the first sub-stepped structure 210 in the second direction D2 may be greater than the dimension T1 of the first sub-laminate body structure 110. For example, the dimension H1 may be approximately twice the dimension T1.

[0070] The relationship between the third sub-laminate structure 130, the fourth sub-laminate structure 140, the third sub-step-shaped structure 230 and the fourth sub-step-shaped structure 240 is similar to the relationship between the first sub-laminate structure 110, the second sub-laminate structure 120, the first sub-step-shaped structure 210 and the second sub-step-shaped structure 220. For example, the third sub-step-shaped structure 230 may include a first step-shaped portion 231 and a second step-shaped portion 232. The fourth sub-step-shaped structure 240 may include a first step-shaped portion 241 and a second step-shaped portion 242. The third sub-laminate structure 130 is connected to the first step-shaped portion 231 of the third sub-step-shaped structure 230. The fourth sub-laminate structure 140 is connected to the first step-shaped portion 241 of the fourth sub-step-shaped structure 240. Other structural features can be deduced by analogy.

[0071] The conductive layers of the first sub-laminate structure 110 and the first sub-staircase structure 210 may be electrically insulated from the conductive layers of the second sub-laminate structure 120 and the second sub-staircase structure 220 by the insulating element 410. The insulating element 410 is between the first sub-laminate structure 110 and the second step-shaped portion 222 of the second sub-staircase structure 220, between the first sub-laminate structure 110 and the second sub-staircase structure 120, and between the second sub-laminate structure 120 and the second step-shaped portion 212 of the first sub-staircase structure 210. The relationship between the insulating element 420 and the third sub-laminate structure 130, the fourth sub-laminate structure 140, the third sub-staircase structure 230, and the fourth sub-staircase structure 240 can be deduced in the same manner. The insulating element 410 and the insulating element 420 may have shape.

[0072] The conductive layers of the first sub-stepped structure 210, the second sub-stacked structure 120, and the second sub-stepped structure 220 may be electrically insulated from the conductive layers of the third sub-stepped structure 230, the third sub-stepped structure 130, and the fourth sub-stepped structure 240 by the dielectric element 500. The dielectric element 500 may be between the second step-shaped portion 212 of the first sub-stepped structure 210 and the first step-shaped portion 231 of the third sub-stepped structure 230, between the insulating element 410 and the third sub-stepped structure 130, between the second sub-stepped structure 120 and the third sub-stepped structure 130, between the second sub-stepped structure 120 and the third sub-stepped structure 130, between the second sub-stepped structure 120 and the insulating element 420, and between the first step-shaped portion 221 of the second sub-stepped structure 220 and the second step-shaped portion 242 of the fourth sub-stepped structure 240.

[0073] The conductive layers (word lines) of the first sub-stacked structure 110 and the first sub-stacked structure 210 can be electrically connected to the word line driver 610 through the conductive staircase layers 1-96 of the first sub-stacked structure 210 and the conductive plugs (not shown) thereon. The conductive layers (word lines) of the second sub-stacked structure 120 and the second sub-stacked structure 220 can be electrically connected to the word line driver 620 through the conductive staircase layers 1-96 of the second sub-stacked structure 220 and the conductive plugs (not shown) thereon. The conductive layers (word lines) of the third sub-stacked structure 130 and the third sub-stacked structure 230 can be electrically connected to the word line driver 630 through the conductive staircase layers 1-96 of the third sub-stacked structure 230 and the conductive plugs (not shown) thereon. The conductive layers (word lines) of the fourth sub-stacked structure 140 and the fourth sub-staircase structure 240 can be electrically connected to the wordline driver 640 through the conductive staircase layers 1-96 of the fourth sub-staircase structure 240 and the conductive plugs (not shown) thereon. That is, the first sub-staircase structure 210, the second sub-staircase structure 220, the third sub-staircase structure 230 and the fourth sub-staircase structure 240 can be referred to as effective staircase structures. In the embodiment, there is no dummy staircase structure (whose conductive layer is electrically floating) disposed between the first sub-staircase structure 210 and the third sub-staircase structure 230, and there is no dummy staircase structure disposed between the second sub-staircase structure 220 and the fourth sub-staircase structure 240. Therefore, the density of effective memory devices on the wafer can be increased. The memory cells of one block defined in each of the first sub-stack structure 110, the second sub-stack structure 120, the third sub-stack structure 130 and the fourth sub-stack structure 140 can be selected or controlled by one of the corresponding word line drivers 610, 620, 630 or 640, or erased simultaneously.

[0074] Please refer to Figure 2 , which is a schematic top view of a memory device according to another embodiment. Figure 2 The memory device and Figure 1 The differences between the memory devices are described as follows. The first sub-stacked body structure 110, the second sub-stacked body structure 120, the third sub-stacked body structure 130 and the fourth sub-stacked body structure 140 each further include a second stacked body portion 102 connected to the first stacked body portion 101. The first stacked body portion 111 of the first sub-stacked body structure 110 is connected to the second stacked body portion 112. The first stacked body portion 121 of the second sub-stacked body structure 120 is connected to the second stacked body portion 122. The first stacked body portion 131 of the third sub-stacked body structure 130 is connected to the second stacked body portion 132. The first stacked body portion 141 of the fourth sub-stacked body structure 140 is connected to the second stacked body portion 142.

[0075] For example, the second laminated body 112 of the first sub-laminate structure 110 is between the first laminated body 121 of the second sub-laminate structure 120 and the second stepped portion 212 of the first sub-stepped structure 210. The second laminated body 122 of the second sub-laminate structure 120 is between the first laminated body 111 of the first sub-laminate structure 110 and the second stepped portion 222 of the second sub-stepped structure 220. The second laminated body 112 of the first sub-laminate structure 110 is connected to the second stepped portion 212 of the first sub-stepped structure 210, thereby providing a shorter electrical connection path to the first sub-stepped structure 210 and reducing resistance. The second laminated body 122 of the second sub-laminate structure 120 is connected to the second stepped portion 222 of the second sub-stepped structure 220, thereby providing a shorter electrical connection path to the second sub-stepped structure 220 and reducing resistance. The relationship between the third sub-laminate structure 130, the fourth sub-laminate structure 140, the third sub-staircase structure 230 and the fourth sub-staircase structure 240 is similar to the relationship between the first sub-laminate structure 110, the second sub-laminate structure 120, the first sub-staircase structure 210 and the second sub-staircase structure 220. Therefore, the other structural features of the second laminated body portion 132 of the third sub-laminate structure 130 and the second laminated body portion 142 of the fourth sub-laminate structure 140 and the relationship between them and other elements can be inferred by analogy.

[0076] The first sub-laminate structure 110, the second sub-laminate structure 120, the third sub-laminate structure 130 and the fourth sub-laminate structure 140 each have different sizes in the second direction D2. For example, the first sub-laminate structure 110, the second sub-laminate structure 120, the third sub-laminate structure 130 and the fourth sub-laminate structure 140 independently have an L shape. The dimension T11 of the portion of the first sub-laminate structure 110 away from the first sub-step-shaped structure 210 in the second direction D2 (equal to the dimension T1 of the first laminated body 111 in the second direction D2) is smaller than the dimension T12 of the portion close to the first sub-step-shaped structure 210 in the second direction D2 (i.e., the sum of the dimension T1 of the first laminated body 111 in the second direction D2 and the dimension of the second laminated body 112 in the second direction D2). The dimension H1 of the first sub-step-like structure 210 in the second direction D2 may be smaller than the dimension T11 of the portion of the first sub-stack-like structure 110 away from the first sub-step-like structure 210 in the second direction D2. For example, the dimension H1 may be approximately twice the dimension T11. The dimension H1 of the first sub-step-like structure 210 may be equal to the dimension T12 of the portion of the first sub-stack-like structure 110 close to the first sub-step-like structure 210 in the second direction D2. Similar to the above, the dimension T21 of the portion of the second sub-stack-like structure 120 away from the second sub-step-like structure 220 in the second direction D2 (equal to the dimension T1 of the first stack body 121 in the second direction D2) is smaller than the dimension T22 of the portion close to the second sub-step-like structure 220 in the second direction D2 (i.e., the sum of the dimension T1 of the first stack body 121 in the second direction D2 and the dimension of the second stack body 122 in the second direction D2). The dimension H2 of the second sub-stair-shaped structure 220 in the second direction D2 may be greater than the dimension T21 of the portion of the second sub-stair-shaped structure 120 away from the second sub-stair-shaped structure 220 in the second direction D2. For example, the dimension H2 may be approximately twice the dimension T21. The dimension H2 of the second sub-stair-shaped structure 220 may be equal to the dimension T22 of the portion of the second sub-stair-shaped structure 120 close to the second sub-stair-shaped structure 220 in the second direction D2. The dimension characteristics of the third sub-stacked structure 130 and the fourth sub-stacked structure 140 can be deduced by analogy.

[0077] In this embodiment, the step levels (i.e., the 49th to the 96th level) of the first step-shaped portion 211 of the first sub-step-shaped structure 210 are higher than the step levels (i.e., the 1st to the 48th level) of the second step-shaped portion 212. The step levels (i.e., the 1st to the 48th level) of the first step-shaped portion 221 of the second sub-step-shaped structure 220 are lower than the step levels (i.e., the 49th to the 96th level) of the second step-shaped portion 222. The step levels (i.e., the 49th to the 96th level) of the first step-shaped portion 231 of the third sub-step-shaped structure 230 are higher than the step levels (i.e., the 1st to the 48th level) of the second step-shaped portion 232. The step levels (i.e., the 1st to the 48th level) of the first step-shaped portion 241 of the fourth sub-step-shaped structure 240 are lower than the step levels (i.e., the 49th to the 96th level) of the second step-shaped portion 242. However, the present invention is not limited thereto. The number and configuration of the step levels can be adjusted according to the actual process or actual product requirements.

[0078] The insulating element 410 is between the first laminate body portion 111 of the first sub-laminate body structure 110 and the second laminate body portion 122 of the second sub-laminate body structure 120, between the first laminate body portion 111 of the first sub-laminate body structure 110 and the first laminate body portion 121 of the second sub-laminate body structure 120, and between the second laminate body portion 112 of the first sub-laminate body structure 110 and the first laminate body portion 121 of the second sub-laminate body structure 120. The relationship between the insulating element 420 and the third sub-laminate body structure 130 and the fourth sub-laminate body structure 140 can be deduced in the same manner.

[0079] The conductive layers of the first sub-stepped structure 210 , the first sub-stacked structure 110 , the second sub-stacked structure 120 and the second sub-stepped structure 220 may be electrically insulated from the conductive layers of the third sub-stepped structure 230 , the third sub-stacked structure 130 , the fourth sub-stacked structure 140 and the fourth sub-stepped structure 240 by the dielectric element 500 . The dielectric element 500 may be between the second stepped portion 212 of the first sub-stepped structure 210 and the first stepped portion 231 of the third sub-stepped structure 230, between the second stacked portion 112 of the first sub-stacked structure 110 and the first stacked portion 131 of the third sub-stacked structure 130, between the insulating element 410 and the first stacked portion 131 of the third sub-stacked structure 130, between the first stacked portion 121 of the second sub-stacked structure 120 and the first stacked portion 131 of the third sub-stacked structure 130, between the first stacked portion 121 of the second sub-stacked structure 120 and the insulating element 420, between the first stacked portion 121 of the second sub-stacked structure 120 and the second stacked portion 142 of the fourth sub-stacked structure 140, and between the first stepped portion 221 of the second sub-stepped structure 220 and the second stepped portion 242 of the fourth sub-stepped structure 240.

[0080] 3A to 3T A method for manufacturing a memory device according to an embodiment is shown, which includes a manufacturing step of performing a plurality of yellow light photolithography processes using photoresist layers with different distributions on a stacked structure 700 to form a stepped structure.

[0081] Please refer to Figure 3A . Conductive layers 707 and insulating layers 708 may be alternately stacked along a vertical direction Z on a substrate (not shown) to form a stacked structure 700. In this embodiment, the stacked structure 700 may include 96 conductive layers 707, which are insulated from each other by insulating layers 708. The stacked structure 700 includes a first stacked portion 701 and a second stacked portion 702 arranged in a first direction D1. The first stacked portion 701 includes a first stacked portion 701-1 and a first stacked portion 701-2, respectively, on opposite sides of the second stacked portion 702. The first stacked portion 701-1 and the first stacked portion 701-2 are in a stepped contact region C. The second stacked portion 702 is in a memory array region M. The second stacked portion 702 may be a stacked body structure 100. In one embodiment, a photoresist layer (not shown) may be formed to cover the insulating layer 708 (e.g., the top insulating layer) of the second stacked portion 702, and an etching step may be performed using the photoresist layer (not shown) as an etching mask to remove the exposed insulating layer 708 (e.g., the top insulating layer) of the first stacked portion 701, thereby exposing the ninety-sixth level of the conductive layer 707 (e.g., the conductive step layer 96) of the first stacked portion 701. The photoresist layer may then be removed.

[0082] Please refer to Figure 3B . A photoresist layer PR1 is formed on the stacked structure 700. The photoresist layer PR1 covers the second stacked portion 702 and the first sub-stacked portion 7011 of the first stacked portion 701 (including the first stacked portion 701-1 and the first stacked portion 701-2), and exposes the ninety-sixth level conductive layer (i.e., conductive step layer 96) of the second sub-stacked portion 7012 of the first stacked portion 701. Using the photoresist layer PR1 as an etching mask, the 48th level conductive layer of the second sub-stacked portion 7012 is etched downward from the ninety-sixth level conductive layer (i.e., conductive step layer 96) of the second sub-stacked portion 7012 to expose the forty-eighth level conductive layer (i.e., conductive step layer 48). The photoresist layer PR1 can then be removed. In this way, a conductive layer such as the conductive step layer 48 is formed. Figure 3C The semiconductor structure shown.

[0083] Please refer to Figure 3D , forming a photoresist layer PR2 on the stacked structure 700. The photoresist layer PR2 covers the second stacked portion 702, and extends in the first direction D1 to cover a portion of the first stacked portion 701. That is, the photoresist layer PR2 covers the inner stacked portion 701G1 of the first stacked portion 701 that is closer to the second stacked portion 702, and exposes the outer stacked portion 701K1 that is farther away from the second stacked portion 702. Using the photoresist layer PR2 as an etching mask, etch down 4 levels from the ninety-sixth level of the conductive layer (i.e., the conductive step layer 96) and the forty-eighth level of the conductive layer (i.e., the conductive step layer 48) of the exposed outer stacked portion 701K1 to expose the ninety-second level of the conductive layer (i.e., the conductive step layer 92) and the forty-fourth level of the conductive layer (i.e., the conductive step layer 44), respectively. Then, the step size E of the photoresist layer PR2 (previous photoresist layer) in the first direction D1 can be reduced to form Figure 3E The photoresist layer PR3 (subsequent photoresist layer) shown may not reduce the size of the photoresist layer PR2 in the second direction D2, so the size of the photoresist layer PR3 in the second direction D2 is the same as the size of the photoresist layer PR2 in the second direction D2.

[0084] Please refer to Figure 3E , the photoresist layer PR3 is on the stacked structure 700. The photoresist layer PR3 covers the second stacked portion 702 and the inner stacked portion 701G2 of the first stacked portion 701, and exposes the outer stacked portion 701K2 of the first stacked portion 701. Using the photoresist layer PR3 as an etching mask, 4 layers are etched downward from the conductive layer (i.e., the conductive step layer 96, the conductive step layer 92, the conductive step layer 48, and the conductive step layer 44) of the exposed outer stacked portion 701K2. In this way, a structure such as Figure 3F The semiconductor structure shown in FIG. 1 can then be reduced by reducing the step size E of the photoresist layer PR3 (previous photoresist layer) in the first direction D1 to form Figure 3GThe photoresist layer PR4 (subsequent photoresist layer) shown may not reduce the size of the photoresist layer PR3 in the second direction D2, so the size of the photoresist layer PR4 in the second direction D2 is the same as the size of the photoresist layer PR3 in the second direction D2.

[0085] Please refer to Figure 3G , the photoresist layer PR4 is on the stacked structure 700. The photoresist layer PR4 covers the second stacked portion 702 and the inner stacked portion 701G3 of the first stacked portion 701, and exposes the outer stacked portion 701K3 of the first stacked portion 701. The photoresist layer PR4 is used as an etching mask to etch the conductive layer (e.g. Figure 3F The conductive step layers 96, 92, 88, 48, 44, 40) shown in FIG. 1 are etched downward by 4 levels to form a Figure 3G The conductive step layers 92, 88, 84, 44, 40, 36 of the outer stack portion 701K3 are shown. Then, the step size E of the photoresist layer PR4 (previous photoresist layer) in the first direction D1 can be reduced to form Figure 3H The photoresist layer PR5 (subsequent photoresist layer) shown may not reduce the size of the photoresist layer PR4 in the second direction D2, so the size of the photoresist layer PR5 in the second direction D2 is the same as the size of the photoresist layer PR4 in the second direction D2.

[0086] Please refer to Figure 3H , the photoresist layer PR5 is on the stacked structure 700. The photoresist layer PR5 covers the second stacked portion 702 and the inner stacked portion 701G4 of the first stacked portion 701, and exposes the outer stacked portion 701K4 of the first stacked portion 701. Using the photoresist layer PR5 as an etching mask, 4 levels are etched downward from the conductive layer (i.e., the conductive step layers 96, 92, 88, 84, 48, 44, 40, 36) of the exposed outer stacked portion 701K4 to form a structure as shown in FIG. Figure 3H The conductive step layers 92, 88, 84, 80, 44, 40, 36, 32 of the outer stack portion 701K4 are shown. Then, the step size E of the photoresist layer PR5 (previous photoresist layer) in the first direction D1 can be reduced to form Fig. 3I The photoresist layer PR6 (subsequent photoresist layer) shown may not reduce the size of the photoresist layer PR5 in the second direction D2, so the size of the photoresist layer PR6 in the second direction D2 is the same as the size of the photoresist layer PR5 in the second direction D2.

[0087] Please refer to Fig. 3I, the photoresist layer PR6 is on the stacked structure 700. The photoresist layer PR6 covers the second stacked portion 702 and the inner stacked portion 701G5 of the first stacked portion 701, and exposes the outer stacked portion 701K5 of the first stacked portion 701. Using the photoresist layer PR6 as an etching mask, 4 levels are etched downward from the exposed conductive layer (i.e., the conductive step layers 96, 92, 88, 84, 80, 48, 44, 40, 36, 32) to form the following structure: Fig. 3I The conductive step layers 92, 88, 84, 80, 76, 44, 40, 36, 32, 28 of the outer stack portion 701K5 are shown. Then, the step size E of the photoresist layer PR6 (previous photoresist layer) in the first direction D1 can be reduced to form Figure 3J The photoresist layer PR7 (subsequent photoresist layer) shown may not reduce the size of the photoresist layer PR6 in the second direction D2, so the size of the photoresist layer PR7 in the second direction D2 is the same as the size of the photoresist layer PR6 in the second direction D2.

[0088] Please refer to Figure 3J , the photoresist layer PR7 is on the stacked structure 700. The photoresist layer PR7 covers the second stacked portion 702 and the inner stacked portion 701G6 of the first stacked portion 701, and exposes the outer stacked portion 701K6 of the first stacked portion 701. Using the photoresist layer PR7 as an etching mask, 4 levels are etched downward from the conductive layer (i.e., the conductive step layers 92, 88, 84, 80, 76, 44, 40, 36, 32, 28) of the exposed outer stacked portion 701K6 to form a structure as shown in FIG. Figure 3J The conductive step layers 92, 88, 84, 80, 76, 72, 44, 40, 36, 32, 28, 24 of the outer stack portion 701K6 are shown. Then, the step size E of the photoresist layer PR7 (previous photoresist layer) in the first direction D1 can be reduced to form Figure 3K The photoresist layer PR8 (subsequent photoresist layer) shown may not reduce the size of the photoresist layer PR7 in the second direction D2, so the size of the photoresist layer PR8 in the second direction D2 is the same as the size of the photoresist layer PR7 in the second direction D2.

[0089] Please refer to Figure 3K , the photoresist layer PR8 is on the stacked structure 700. The photoresist layer PR8 covers the second stacked portion 702 and the inner stacked portion 701G7 of the first stacked portion 701, and exposes the outer stacked portion 701K7 of the first stacked portion 701. Using the photoresist layer PR8 as an etching mask, 4 levels are etched downward from the conductive layer (i.e., the conductive step layers 92, 88, 84, 80, 76, 72, 44, 40, 36, 32, 28, 24) of the exposed outer stacked portion 701K7 to form a structure as shown in FIG. Figure 3KThe conductive step layers 92, 88, 84, 80, 76, 72, 68, 44, 40, 36, 32, 28, 24, 20 of the outer stack portion 701K7 are shown. Then, the step size E of the photoresist layer PR8 (previous photoresist layer) in the first direction D1 can be reduced to form Figure 3L The photoresist layer PR9 (subsequent photoresist layer) shown may not reduce the size of the photoresist layer PR8 in the second direction D2, so the size of the photoresist layer PR9 in the second direction D2 is the same as the size of the photoresist layer PR8 in the second direction D2.

[0090] Please refer to Figure 3L , the photoresist layer PR9 is on the stacked structure 700. The photoresist layer PR9 covers the second stacked portion 702 and the inner stacked portion 701G8 of the first stacked portion 701, and exposes the outer stacked portion 701K8 of the first stacked portion 701. Using the photoresist layer PR9 as an etching mask, 4 levels are etched downward from the conductive layer (i.e., the conductive step layers 92, 88, 84, 80, 76, 72, 68, 44, 40, 36, 32, 28, 24, 20) of the exposed outer stacked portion 701K8 to form a structure as shown in FIG. Figure 3L The conductive step layers 92, 88, 84, 80, 76, 72, 68, 64, 44, 40, 36, 32, 28, 24, 20, 16 of the outer stack portion 701K8 are shown. Then, the step size E of the photoresist layer PR9 (previous photoresist layer) in the first direction D1 can be reduced to form Figure 3M The photoresist layer PR10 (subsequent photoresist layer) shown may not reduce the size of the photoresist layer PR9 in the second direction D2, so the size of the photoresist layer PR10 in the second direction D2 is the same as the size of the photoresist layer PR9 in the second direction D2.

[0091] Please refer to Figure 3M , the photoresist layer PR10 is on the stacked structure 700. The photoresist layer PR10 covers the second stacked portion 702 and the inner stacked portion 701G9 of the first stacked portion 701, and exposes the outer stacked portion 701K9 of the first stacked portion 701. Using the photoresist layer PR10 as an etching mask, 4 levels are etched downward from the conductive layer (i.e., the conductive step layers 92, 88, 84, 80, 76, 72, 68, 64, 44, 40, 36, 32, 28, 24, 20, 16) of the exposed outer stacked portion 701K9 to form a structure as shown in FIG. Figure 3M The conductive step layers 92, 88, 84, 80, 76, 72, 68, 64, 60, 44, 40, 36, 32, 28, 24, 20, 16, 12 of the outer stack portion 701K9 are shown. Then, the step size E of the photoresist layer PR10 (previous photoresist layer) in the first direction D1 can be reduced to form Figure 3NThe photoresist layer PR11 (subsequent photoresist layer) shown may not reduce the size of the photoresist layer PR10 in the second direction D2, so the size of the photoresist layer PR11 in the second direction D2 is the same as the size of the photoresist layer PR10 in the second direction D2.

[0092] Please refer to Figure 3N , the photoresist layer PR11 is on the stacked structure 700. The photoresist layer PR11 covers the second stacked portion 702 and the inner stacked portion 701G10 of the first stacked portion 701, and exposes the outer stacked portion 701K10 of the first stacked portion 701. Using the photoresist layer PR11 as an etching mask, 4 levels are etched downward from the conductive layer (i.e., the conductive step layers 92, 88, 84, 80, 76, 72, 68, 64, 60, 44, 40, 36, 32, 28, 24, 20, 16, 12) of the exposed outer stacked portion 701K10 to form a structure as shown in FIG. Figure 3N The conductive step layers 92, 88, 84, 80, 76, 72, 68, 64, 60, 56, 44, 40, 36, 32, 28, 24, 20, 16, 12, 8 of the outer stack portion 701K10 are shown. Then, the step size E of the photoresist layer PR11 (previous photoresist layer) in the first direction D1 can be reduced to form Fig.3O The photoresist layer PR12 (subsequent photoresist layer) shown may not reduce the size of the photoresist layer PR11 in the second direction D2, so the size of the photoresist layer PR12 in the second direction D2 is the same as the size of the photoresist layer PR11 in the second direction D2.

[0093] Please refer to Fig.3O , the photoresist layer PR12 is on the stacked structure 700. The photoresist layer PR12 covers the second stacked portion 702 and the inner stacked portion 701G11 of the first stacked portion 701, and exposes the outer stacked portion 701K11 of the first stacked portion 701. Using the photoresist layer PR12 as an etching mask, 4 levels are etched downward from the conductive layer (i.e., the conductive step layers 92, 88, 84, 80, 76, 72, 68, 64, 60, 56, 44, 40, 36, 32, 28, 24, 20, 16, 12, 8) of the exposed outer stacked portion 701K11 to form a Fig.3O The conductive step layers 92, 88, 84, 80, 76, 72, 68, 64, 60, 56, 52, 44, 40, 36, 32, 28, 24, 20, 16, 12, 8, 4 of the stacked portion 701K11 are shown. The photoresist layer PR12 can then be removed. Thus, a structure such as Figure 3P The semiconductor structure shown.

[0094] Please refer to Figure 3Q, a photoresist layer PR13 is formed on the stacked structure 700. The photoresist layer PR13 covers the second stacked portion 702, and extends in the first direction D1 to cover a portion of the first stacked portion 701. That is, the photoresist layer PR13 covers the stacked portion region 701P1 of the first sub-stacked portion 7011 and the second sub-stacked portion 7012 of the first stacked portion 701, and exposes the stacked portion region 701Q1 of the first sub-stacked portion 7011 and the second sub-stacked portion 7012. Using the photoresist layer PR13 as an etching mask, one layer is etched downward from the exposed conductive layer to form a structure as shown in FIG. Figure 3Q The stacked layer region 701Q1 shown has a conductive step layer configuration. Then, the step size F of the photoresist layer PR13 (previous photoresist layer) in the second direction D1 can be reduced to form Figure 3R The photoresist layer PR14 (subsequent photoresist layer) shown may not reduce the size of the photoresist layer PR13 in the first direction D1, so the size of the photoresist layer PR14 in the first direction D1 is the same as the size of the photoresist layer PR13 in the first direction D1.

[0095] Please refer to Figure 3R , a photoresist layer PR14 is formed on the stacked structure 700. The photoresist layer PR14 covers the second stacked portion 702 and the stacked portion region 701P2 of the first sub-stacked portion 7011 and the second sub-stacked portion 7012 of the first stacked portion 701, and exposes the stacked portion region 701Q2. Using the photoresist layer PR14 as an etching mask, one layer is etched downward from the exposed conductive layer to form a Figure 3R The stacked region 701Q2 shown has a conductive step layer configuration. Then, the step size F of the photoresist layer PR14 (previous photoresist layer) in the second direction D1 can be reduced to form Figure 3S The photoresist layer PR15 (subsequent photoresist layer) shown may not reduce the size of the photoresist layer PR14 in the first direction D1, so the size of the photoresist layer PR15 in the first direction D1 is the same as the size of the photoresist layer PR14 in the first direction D1.

[0096] Please refer to Figure 3S , a photoresist layer PR15 is formed on the stacked structure 700. The photoresist layer PR15 covers the stacked portion region 701P3 of the second stacked portion 702 and the first sub-stacked portion 7011 and the second sub-stacked portion 7012 of the first stacked portion 701, and exposes the stacked portion region 701Q3. Using the photoresist layer PR15 as an etching mask, one layer is etched downward from the exposed conductive layer to form a Figure 3S The conductive step layer configuration of the stacked layer region 701Q3 shown in FIG. 1 can then be removed from the photoresist layer PR15. Thus, a structure such as Figure 3T The semiconductor structure shown includes a similar Figure 1The laminate structure 100 and the stepped structure 200.

[0097] According to the above manufacturing method, the first stacked portion 701 is etched using photoresist layers with different distributions as etching masks to form the stepped structure 200. For example, in the stepped contact region C, the photoresist layers have different sizes in the first direction D1 and / or the second direction D2. Figure 3B The photoresist layer PR1, Figure 3Q Photoresist layer PR13, Figure 3R The photoresist layer PR14 and Figure 3S The photoresist portion of the photoresist layer PR15 in the stepped contact region C has the same size in the first direction D1 and different sizes in the second direction D2. Figure 3D The photoresist layer PR2, Figure 3E and Figure 3F The photoresist layer PR3, Figure 3G The photoresist layer PR4, Figure 3H The photoresist layer PR5, Fig. 3I The photoresist layer PR6, Figure 3J The photoresist layer PR7, Figure 3K Photoresist layer PR8, Figure 3L The photoresist layer PR9, Figure 3M Photoresist layer PR10, Figure 3N The photoresist layer PR11 and Fig.3O The photoresist portion of the photoresist layer PR12 in the stepped contact region C has the same size in the second direction D2 and has different sizes in the first direction D1. Other possible interpretations of the so-called differently distributed photoresist layers can also be understood with reference to the drawings.

[0098] The present invention is not limited to the above manufacturing method. For example, other types of photoresist layer configurations, etching sequences and other process parameters may be used depending on actual process experience.

[0099] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory device, wherein: include: A laminate structure, comprising a first sub-laminate structure and a second sub-laminate structure; and a stepped structure electrically connected to the laminate structure and comprising a first sub-stepped structure and a second sub-stepped structure, wherein the first sub-stepped structure and the second sub-stepped structure each comprise a first stepped portion and a second stepped portion, the first sub-laminate structure and the second sub-laminate structure are respectively connected to the first stepped portion of the first sub-stepped structure and the first stepped portion of the second sub-stepped structure, wherein the first sub-step-shaped structure and the second sub-step-shaped structure are disposed on opposite sides of the stacked structure; and The stacked structure penetrates through and is located between the first sub-step-shaped structure and the second sub-step-shaped structure.

2. The memory device according to claim 1, wherein: The first sub-stack structure and the first sub-step-shaped structure are arranged in a first direction. The first sub-stack structure has a consistent size in a second direction. The first direction is perpendicular to the second direction.

3. The memory device according to claim 1, wherein: The first sub-stack structure and the first sub-step-shaped structure are arranged in a first direction. The first sub-stack structure has different sizes in a second direction. The first direction is perpendicular to the second direction.

4. The memory device according to claim 3, wherein: A dimension of a portion of the first sub-stacked structure away from the first sub-step-shaped structure in the second direction is smaller than a dimension of another portion of the first sub-step-shaped structure close to the first sub-step-shaped structure in the second direction.

5. The memory device according to claim 1, wherein: The first sub-laminate structure is between the first stepped portion of the first sub-stepped structure and the second stepped portion of the second sub-stepped structure, The second sub-stacked structure is between the second stepped portion of the first sub-stacked structure and the first stepped portion of the second sub-stacked structure.

6. The memory device according to claim 1, wherein: The first sub-laminate structure and the second sub-laminate structure independently have an L-shape.

7. The memory device according to claim 1, wherein: The step levels of the first stepped portions are higher than the step levels of the second stepped portions.

8. The memory device according to claim 1, wherein: The invention also includes an insulating element, wherein the first sub-laminate structure and the first sub-step-shaped structure are electrically insulated from the second sub-laminate structure and the second sub-step-shaped structure by the insulating element.

9. The memory device according to claim 8, wherein: The insulating element has a shape.

10. The memory device according to claim 1, wherein: The first sub-stacked body structure and the second sub-stacked body structure each include a first stacked body portion and a second stacked body portion.

11. The memory device according to claim 10, wherein: The second stacking body portion of the first sub-stacked body structure is between the first stacking body portion of the second sub-stacked body structure and the second stepped portion of the first sub-stepped structure.

12. The memory device according to claim 10, wherein: The second laminated body portion of the first sub-laminated body structure is connected to the second stepped portion of the first sub-stepped structure, and the second laminated body portion of the second sub-laminated body structure is connected to the second stepped portion of the second sub-stepped structure.

13. The memory device according to claim 12, wherein: The first stacked body portion of the first sub-stacked body structure is connected to the first stepped portion of the first sub-stepped structure, and the first stacked body portion of the second sub-stacked body structure is connected to the first stepped portion of the second sub-stepped structure.

14. The memory device according to claim 13, wherein: The step level of the first stepped portion of one of the first sub-stepped structure and the second sub-stepped structure is higher than the step level of the second stepped portion of the first sub-stepped structure, or is lower than the step level of the second stepped portion of the first sub-stepped structure.

15. A method for manufacturing a memory device, wherein: include: A plurality of conductive layers and a plurality of insulating layers are alternately stacked along a vertical direction to form a stacked structure, wherein the stacked structure includes a first stacked portion, a second stacked portion and another first stacked portion arranged in a first direction, the first stacked portion and the another first stacked portion are respectively on opposite sides of the second stacked portion, the first stacked portion and the another first stacked portion are in a stepped contact region, and the second stacked portion is in a memory array region; and The first stacked portion and the other first stacked portion are etched using a plurality of photoresist layers to form a stepped structure, wherein in the stepped contact region, the photoresist layers have different sizes in the first direction and / or a second direction, and the first direction, the second direction and the vertical direction are perpendicular to each other. The memory device comprises: A laminate structure, comprising a first sub-laminate structure and a second sub-laminate structure, wherein the first sub-laminate structure and the second sub-laminate structure include the second laminate portion; and The stepped structure is electrically connected to the laminate structure and includes a first sub-stepped structure and a second sub-stepped structure, wherein the first sub-stepped structure and the second sub-stepped structure each include a first stepped portion and a second stepped portion, and the first sub-laminate structure and the second sub-laminate structure are respectively connected to the first stepped portion of the first sub-stepped structure and the first stepped portion of the second sub-stepped structure.

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