Semiconductor device and method for manufacturing the same

Abstract

The embodiment provides a semiconductor device capable of reducing on-resistance and a method for manufacturing the same. The semiconductor device of the embodiment comprises a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, an insulating portion, a conductive portion, a gate electrode, and a second electrode. The insulating portion is arranged side by side with a portion of the first semiconductor region, the second semiconductor region, and the third semiconductor region in a second direction perpendicular to the first direction from the first electrode toward the first semiconductor region. The insulating portion includes a plurality of first insulating portions and a plurality of second insulating portions alternately arranged along the first direction. The outer diameter of each first insulating portion in the second direction is longer than the outer diameter of each second insulating portion in the second direction. The conductive portion is arranged in the insulating portion and is arranged side by side with the first semiconductor region in the second direction. The gate electrode is arranged in the insulating portion and is arranged side by side with the second semiconductor region in the second direction.

Description

[0001] Related Applications

[0002] This application claims the priority of Japanese Patent Application No. 2020-157500 (filing date: September 18, 2020) as a basic application, and the present application incorporates all the contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0004] Semiconductor devices such as Metal Oxide Semiconductor Field Effect Transistor (MOSFET) are used for power conversion and the like. It is desirable that the on-resistance of the semiconductor device is low. Summary of the invention

[0005] Embodiments of the present invention provide a semiconductor device capable of reducing on-resistance and a method for manufacturing the same.

[0006] A semiconductor device according to an embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, an insulating portion, a conductive portion, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode and electrically connected to the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The insulating portion is arranged side by side with a part of the first semiconductor region, the second semiconductor region, and the third semiconductor region in a second direction perpendicular to the first direction from the first electrode toward the first semiconductor region. The insulating portion includes a plurality of first insulating portions and a plurality of second insulating portions alternately arranged along the first direction. The outer diameter of each of the first insulating portions in the second direction is longer than the outer diameter of each of the second insulating portions in the second direction. The conductive portion is provided in the insulating portion and is arranged side by side with the first semiconductor region in the second direction. The gate electrode is provided in the insulating portion and is arranged side by side with the second semiconductor region in the second direction. The second electrode is provided on the third semiconductor region and electrically connected to the third semiconductor region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a perspective cross-sectional view showing a semiconductor device according to an embodiment.

[0008] Figure 2(a) and (b) are cross-sectional views showing the manufacturing process of the semiconductor device according to the first embodiment.

[0009] Figure 3 (a) and (b) are cross-sectional views showing the manufacturing process of the semiconductor device according to the first embodiment.

[0010] Figure 4 It is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

[0011] Figure 5 (a) and (b) are cross-sectional views showing the shapes of openings formed in the semiconductor layer.

[0012] Figure 6 This is a cross-sectional view showing a portion of a semiconductor device according to an embodiment.

[0013] Figure 7 is a cross-sectional view showing a portion of another semiconductor device according to an embodiment.

[0014] Figure 8 is a cross-sectional view showing a portion of another semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0016] The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between parts, etc. are not necessarily the same as in reality. Even when the same part is shown, the sizes and ratios of each other may be shown differently in the drawings.

[0017] In the present specification and each drawing, the same reference numerals are given to the same elements as those already described, and detailed description thereof will be appropriately omitted.

[0018] In the following description and drawings, n + 、n － and p + , p marks indicate the relative level of each impurity concentration. That is, a mark marked with "+" indicates that the impurity concentration is relatively high compared to a mark without either "+" or "-", and a mark marked with "-" indicates that the impurity concentration is relatively low compared to a mark without either "+" or "-". These marks indicate the relative level of the net impurity concentration after these impurities compensate for each other when both p-type impurities and n-type impurities are included in each region.

[0019] Each embodiment described below may be implemented by inverting the p-type and n-type of each semiconductor region.

[0020] Figure 1 It is a perspective cross-sectional view showing a semiconductor device according to an embodiment.

[0021] The semiconductor device 100 of the embodiment is a MOSFET. Figure 1 As shown, including n － p-type (first conductivity type) drift region 1 (first semiconductor region), p-type (second conductivity type) base region 2 (second semiconductor region), n + Type source region 3 (third semiconductor region), p + Type contact region 4 (fourth semiconductor region), n + The type drain region 5 (fifth semiconductor region), the insulating portion 10, the conductive portion 20, the gate electrode 25, the drain electrode 31 (first electrode) and the source electrode 32 (second electrode).

[0022] In the description of the embodiment, an XYZ coordinate system is used. － The direction of the drift region 1 is defined as the Z direction (first direction). A direction perpendicular to the Z direction is defined as the X direction (second direction). A direction perpendicular to the X direction and the Z direction is defined as the Y direction (third direction). － The direction of the type drift region 1 is called "up", and the opposite direction is called "down". These directions are based on the drain electrode 31 and the n － The relative position relationship of the drift region 1 is independent of the direction of gravity.

[0023] The drain electrode 31 is provided on the lower surface of the semiconductor device 100. + The type drain region 5 is provided on the drain electrode 31 and is electrically connected to the drain electrode 31. － The drift region 1 is located at n + The type drain region 5 is above. － The n-type impurity concentration in the drift region 1 is n + The n-type impurity concentration in the type drain region 5 is low. － Type drift region 1 via n + The type drain region 5 is electrically connected to the drain electrode 31.

[0024] The p-type base region 2 is provided on the n － Type drift region 1. + Type source region 3 and p + The p-type contact region 4 is provided on the p-type base region 2. + The p-type impurity concentration in the p-type contact region 4 is higher than the p-type impurity concentration in the p-type base region 2 .

[0025] The insulating portion 10 is aligned with the n－ A portion of the p-type drift region 1, a p-type base region 2, and an n-type + The conductive portion 20 is provided in the insulating portion 10. At least a portion of the conductive portion 20 is aligned with the n-type source region 3 in the X direction. － The gate electrode 25 is arranged in parallel with the p-type base region 2 in the X direction. The conductive portion 20 may also be arranged in parallel with the gate electrode 25 in the X direction.

[0026] The source electrode 32 is provided at n + Type source region 3 and p + Type contact area 4, with n + Type source region 3 and p + The conductive portion 20 is electrically connected to the source electrode 32. The upper end of the conductive portion 20 is in contact with the source electrode 32, and the conductive portion 20 is electrically connected to the source electrode 32. The gate electrode 25 is electrically separated from the conductive portion 20 and the source electrode 32 by the insulating portion 10. Alternatively, the conductive portion 20 may be in contact with the gate electrode 25 in the insulating portion 10 and electrically connected to the gate electrode 25. In this case, the conductive portion 20 is electrically separated from the source electrode 32.

[0027] The insulating portion 10 includes a plurality of first insulating portions 11 and a plurality of second insulating portions 12 alternately arranged in the Z direction. An outer diameter Lx1 of the first insulating portion 11 in the X direction is longer than an outer diameter Lx2 of the second insulating portion 12 in the X direction.

[0028] In other words, the side wall of the opening 10op includes a plurality of concave portions 10r and a plurality of convex portions 10p alternately arranged in the Z direction. The insulating portion 10 is arranged inside the opening 10op. The concave portion 10r extends from the insulating portion 10 toward the n direction. － The drift region 1 is concave along the XY plane. The convex portion 10p extends from n － The type drift region 1 protrudes along the XY plane toward the insulating portion 10. The dimension of the opening 10op in the X direction at the position where the recessed portion 10r is provided is longer than the dimension of the opening 10op in the X direction at the position where the raised portion 10p is provided.

[0029] The insulating portion 10 further includes a third insulating portion 13. The third insulating portion 13 is disposed on the plurality of first insulating portions 11 and the plurality of second insulating portions 12. The third insulating portion 13 is connected to the p-type base region 2 and the n-type base region 2 in the X direction. + The gate electrode 25 is arranged in the third insulating portion 13. The sidewall of the third insulating portion 13 is parallel to the Z direction.

[0030] The conductive portion 20 includes a plurality of first conductive portions 21 and a plurality of second conductive portions 22 alternately arranged in the Z direction. The length Lx3 of the first conductive portion 21 in the X direction is longer than the length Lx4 of the second conductive portion 22 in the X direction. For example, a plurality of first insulating portions 11 are respectively arranged around the plurality of first conductive portions 21 along the X-Y plane (first plane). A plurality of second insulating portions 12 are respectively arranged around the plurality of second conductive portions 22 along the X-Y plane.

[0031] The conductive portion 20 further includes a third conductive portion 23. The third conductive portion 23 is provided on the plurality of first conductive portions 21 and the plurality of second conductive portions 22. The third insulating portion 13 is provided around the third conductive portion 23 along the XY plane. At least a portion of the third conductive portion 23 is aligned with the gate electrode 25 in the X direction.

[0032] For example Figure 1 As shown, the p-type base region 2 and n + Type source region 3, p + The p-type contact region 4, the insulating portion 10, the conductive portion 20, and the gate electrode 25 are provided in plurality in the X direction. + Type source region 3, each p + The type contact region 4, each insulating portion 10, each conductive portion 20, and each gate electrode 25 extend in the Y direction. － In the drift region 1, portions having a relatively long length in the X direction and portions having a relatively short length in the X direction are alternately arranged along the Z direction.

[0033] The operation of the semiconductor device 100 will be described.

[0034] When a positive voltage relative to the source electrode 32 is applied to the drain electrode 31, a voltage higher than the threshold is applied to the gate electrode 25. A channel (inversion layer) is formed in the p-type base region 2. As a result, the semiconductor device 100 is turned on. In the on state, electrons pass through the channel and n － The p-type drift region 1 flows toward the drain electrode 31. Thereafter, when the voltage applied to the gate electrode 25 becomes lower than the threshold, the channel in the p-type base region 2 disappears, and the semiconductor device 100 enters the off state.

[0035] When the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 31 relative to the source electrode 32 increases. Due to the potential difference between the drain electrode 31 and the conductive portion 20, the depletion layer extends from the insulating portion 10 to the n － The interface of drift region 1 is oriented toward n －The type drift region 1 is diffused. The diffusion of the depletion layer can improve the withstand voltage of the semiconductor device 100. Alternatively, the n-type drift region 1 is diffused while maintaining the withstand voltage of the semiconductor device 100. － The n-type impurity concentration in the n-type drift region 1 is reduced, thereby reducing the on-resistance of the semiconductor device 100 .

[0036] An example of the material of each component of the semiconductor device 100 is described.

[0037] n － type drift region 1, p-type base region 2, n + Type source region 3, p + Type contact area 4, and n + The n-type drain region 5 includes silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity. The insulating portion 10 includes an insulating material. The insulating portion 10 is preferably an insulating material including an oxide or a nitride. For example, the insulating portion 10 includes silicon oxide, silicon nitride, or silicon oxynitride. The conductive portion 20 and the gate electrode 25 include conductive materials such as polycrystalline silicon. N-type or p-type impurities can also be added to the conductive portion 20 and the gate electrode 25. The drain electrode 31 and the source electrode 32 include metals such as titanium, tungsten, or aluminum.

[0038] Figure 2 to Figure 4 It is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

[0039] Prepare to include + Type semiconductor layer 5a and n － The semiconductor substrate S of the semiconductor layer 1a is made of silicon. － The semiconductor layer 1a is provided on n + On top of the n-type semiconductor layer 5a. － The p-type semiconductor layer 1a is ion-implanted with p-type impurities, and the p-type impurities are activated by heat treatment to form a p-type semiconductor region 2a. － The direction from the p-type semiconductor layer 1a to the p-type semiconductor region 2a is along the Z direction. － A portion of the semiconductor layer 1a is removed, such as Figure 2 As shown in (a), an opening OP is formed. A plurality of openings OP are formed in the X direction. Each opening OP extends in the Y direction.

[0040] In the process of forming the opening OP, first, an opening penetrating the p-type semiconductor region 2a is formed by reactive ion etching (RIE). Then, the n-type semiconductor region at the bottom of the opening is removed by using the Bosch process. － type semiconductor layer 1a. In the Bosch process, the formation of the protective film, anisotropic etching and isotropic etching are repeatedly performed. As a result, a plurality of recesses R and a plurality of protrusions P alternately arranged along the Z direction are formed in a portion of the side wall of the opening OP. The recesses R are recessed from the inside of the opening OP toward the outside along the X-Y plane. The protrusions P protrude from the outside of the opening OP toward the inside along the X-Y plane. The dimension D1 of the opening OP in the X direction at the position where the recesses R are formed is longer than the dimension D2 of the opening OP in the X direction at the position where the protrusions P are formed.

[0041] By thermal oxidation of the semiconductor substrate S, an insulating layer 10a is formed along the inner wall of the opening OP and the upper surface of the p-type semiconductor region 2a. By chemical vapor deposition (CVD), an insulating layer 10b is formed along the insulating layer 10a. The insulating layer 10b includes silicon oxide. By CVD, a conductive layer is formed on the insulating layer 10b to bury the opening OP. By chemical dry etching (CDE) or wet etching, such as Figure 2 As shown in (b), the upper surface of the conductive layer is retreated to form the conductive portion 20.

[0042] Insulating layers 10a and 10b are formed in the opening OP in which portions with different outer diameters in the X direction are alternately arranged in the Z direction. A portion of the insulating layer 10a and a portion of the insulating layer 10b formed at the position of the concave portion correspond to the first insulating portion 11. Another portion of the insulating layer 10a and another portion of the insulating layer 10b formed at the position of the convex portion correspond to the second insulating portion 12. The difference between the dimensions D1 and D2 is reduced by thermal oxidation. The opening OP is formed in such a manner that the difference between the dimensions D1 and D2 is larger than the difference between the outer diameter of the first insulating portion 11 in the X direction and the outer diameter of the second insulating portion 12 in the X direction.

[0043] By CDE or wet etching, remove the － The upper part of the insulating layer 10a and the upper part of the insulating layer 10b above the vicinity of the interface between the p-type semiconductor layer 1a and the p-type semiconductor region 2a. － A portion of the p-type semiconductor layer 1a and the p-type semiconductor region 2a are exposed. － An insulating layer 10c is formed on the surface of the p-type semiconductor layer 1a and the p-type semiconductor region 2a. A conductive layer is formed on the insulating layer 10c. The upper surface of the conductive layer is retreated by CDE or wet etching. Figure 3 As shown in FIG. 2 ( a ), a gate electrode 25 is formed around the upper portion of the conductive portion 20 .

[0044] Ion implantation of n-type impurities and p-type impurities is sequentially performed on the upper surface of the p-type semiconductor region 2a, and each impurity is activated by heat treatment to form an n-type semiconductor region 2a. + Type source region 3 and p + The insulating layer 10d is formed on the insulating layer 10c and the gate electrode 25 by CVD. Figure 3 As shown in (b), the insulating layers 10c and 10d are polished to n by chemical mechanical polishing (CMP). + Type source region 3 and p + The contact area 4 is exposed.

[0045] By RIE, a portion of the insulating layer 10c is removed to expose the upper end of the conductive portion 20. + Type source region 3, p + The source electrode 32 is formed on the type contact region 4 and the conductive portion 20. + The lower surface of the semiconductor layer 5a is ground to n + until the semiconductor layer 5a reaches a predetermined thickness. Figure 4 As shown, by sputtering, in n + The drain electrode 31 is formed on the lower surface of the type semiconductor layer 5a. As described above, the semiconductor device 100 of the embodiment is manufactured.

[0046] The effects of the embodiment will be described.

[0047] It is preferred that the n － The drift region 1 generates tensile stress in the Z direction. － The tensile stress in the Z direction is generated in the drift region 1, then n － The lattice spacing of the semiconductor material contained in the drift region 1 is expanded. As a result, the mobility of carriers is improved.

[0048] Figure 5 (a) and Figure 5 (b) is a cross-sectional view showing the shape of an opening formed in the semiconductor layer.

[0049] Figure 5 (a) shows a semiconductor layer SL1 in which an opening OP1 is formed. Figure 5 (b) shows a semiconductor layer SL2 in which an opening OP2 is formed. The width of the upper end of the opening OP1 is the same as the width of the upper end of the opening OP2. The inclination of the side wall of the opening OP1 is greater than the inclination of the side wall of the opening OP2. Therefore, the width W1 of the bottom of the opening OP1 is narrower than the width W2 of the bottom of the opening OP2.

[0050] The inventors have discovered the following phenomenon. When an insulator is formed inside each of the openings OP1 and OP2, the compressive stress of the insulator inside the opening OP1 is greater than the compressive stress of the insulator inside the opening OP2. The insulator inside the openings OP1 and OP2 generates tensile stress in the semiconductor layers SL1 and SL2. The tensile stress ST1 generated in the semiconductor layer SL1 is greater than the tensile stress ST2 generated in the semiconductor layer SL2. The narrower the width of the opening, the greater the tensile stress generated in the semiconductor layer when the insulator is formed in the opening.

[0051] Figure 6 This is a cross-sectional view showing a portion of a semiconductor device according to an embodiment.

[0052] Based on the above insights, the inventors Figure 2 As shown in (a), an opening OP is formed. A plurality of concave portions and a plurality of convex portions are formed on the sidewall of the opening OP. In other words, a plurality of openings having a smaller width than the opening OP are formed on the sidewall of the opening OP. By forming an insulating layer in the opening OP, as shown in Figure 6 As shown, an insulating portion 10 including a plurality of first insulating portions 11 and a plurality of second insulating portions 12 is formed.

[0053] Near the outer periphery of each first insulating portion 11, － When the semiconductor device 100 is in the on state, carriers flow to the n-type drift region 1 through a channel near the boundary between the insulating portion 10 and the p-type base region 2. － type drift region 1. Due to the n － The drift region 1 generates a tensile stress ST in the Z direction, which causes the flow to n － The mobility of carriers in the type drift region 1 is effectively improved. As a result, the on-resistance of the semiconductor device 100 is reduced.

[0054] In order to further increase n － In order to reduce the tensile stress ST generated in the drift region 1, it is preferred that the insulating portion 10 includes an oxide or a nitride. For example, the insulating portion 10 is formed by thermal oxidation or atomic layer deposition (ALD) of oxide. Alternatively, the insulating portion 10 can also be formed by plasma CVD using monosilane, ammonia and nitrogen. Thus, the compressive stress of the insulating portion 10 can be further increased.

[0055] The first insulating portion 11 and the second insulating portion 12 may also be provided at positions aligned with the p-type base region 2 in the X direction. Figure 6As shown, the third insulating portion 13 is provided at a position aligned with the p-type base region 2 in the X direction. The sidewall 13a of the third insulating portion 13 is parallel to the Z direction.

[0056] For example, when the first insulating portion 11 and the second insulating portion 12 are arranged side by side with the p-type base region 2 in the X direction, the boundary surface between the p-type base region 2 and the insulating portion 10 is curved in a concave-convex manner in the Z direction. An undesirable surface orientation may occur at the boundary surface of the p-type base region 2, and a current path may be generated at the boundary surface. As a result, there is a possibility that the leakage current of the semiconductor device 100 increases. In addition, by forming the channel formed in the p-type base region 2 in a concave-convex curved manner, the channel length becomes longer than when the channel is formed along the Z direction. As a result, the on-resistance of the semiconductor device 100 increases.

[0057] The third insulating portion 13 can control the plane orientation at the boundary surface of the p-type base region 2, thereby suppressing an increase in leakage current of the semiconductor device 100. In addition, since the channel length is formed along the Z direction, an increase in on-resistance of the semiconductor device 100 can be suppressed.

[0058] Preferably, the plurality of first insulating portions 11 are respectively provided around the plurality of first conductive portions 21 along the X-Y plane. The plurality of second insulating portions 12 are respectively provided around the plurality of second conductive portions 22 along the X-Y plane. According to this configuration, compared with the case where the first insulating portion 11 is provided around the second conductive portion 22 and the second insulating portion 12 is provided around the first conductive portion 21, n can be reduced. － The distance between the drift region 1 and the first conductive portion 21 in the X direction is n － When the semiconductor device 100 is in the off state, the depletion layer from the first insulating portion 11 and the n-type drift region 11 can be reduced. － The diffusion and depletion layer from the boundary of the drift region 1 is formed from the second insulating portion 12 and the n － The difference in diffusion from the boundary of the type drift region 1 is reduced. Thus, the withstand voltage of the semiconductor device 100 can be improved.

[0059] For example, the sum of the length Lz1 of the first insulating portion 11 in the Z direction and the length Lz2 of the second insulating portion 12 in the Z direction is longer than 0.1 times and shorter than 0.3 times the length Lz3 of the insulating portion 10 in the Z direction. The length Lx2 of the second insulating portion 12 in the X direction is longer than 0.7 times and shorter than 0.95 times the length Lx1 of the first insulating portion 11 in the X direction.

[0060] Figure 7 as well as Figure 8is a cross-sectional view showing a portion of another semiconductor device according to an embodiment.

[0061] You can also Figure 7 As in the semiconductor device 110 shown in the figure, the first insulating portion 11 is not provided below the conductive portion 20, but only the second insulating portion 12 is provided. Preferably, one or more first insulating portions 11 are provided below the conductive portion 20 as in the semiconductor device 100.

[0062] If only the second insulating portion 12 is provided below the conductive portion 20, the compressive stress in the X direction generated in the insulating portion 10 below the conductive portion 20 increases. As a result, a tensile stress along the X direction is generated at the lower end of the conductive portion 20. As a result, Figure 7 As shown in FIG. 1 , a corner portion CP having a large curvature is formed at the lower end of the conductive portion 20. The greater the curvature of the corner portion CP, the greater the curvature of the corner portion CP. － When a voltage is applied between the drift region 1 and the conductive portion 20, the electric field intensity near the corner CP increases, and the possibility of dielectric breakdown occurring near the corner CP and the semiconductor device 100 being broken increases.

[0063] By providing one or more first insulating portions 11 below the conductive portion 20, the compressive stress of the insulating portion 10 below the conductive portion 20 can be reduced. This can reduce the curvature of the corner portion CP and reduce the possibility of damage to the semiconductor device 100.

[0064] exist Figure 8 In the semiconductor device 120 shown, the width (length in the X direction) of one first insulating portion 11 is narrower than the width of the other first insulating portion 11 . The one first insulating portion 11 is located below the other first insulating portion 11 .

[0065] Likewise, the width of one second insulating portion 12 is narrower than the width of the other second insulating portion 12. The one second insulating portion 12 is located below the other second insulating portion 12.

[0066] For example, the width of each first insulating portion 11 and the width of each second insulating portion 12 become narrower as they go downward. － The width of the drift region 1 becomes wider as it goes downward.

[0067] When the semiconductor device 120 is switched from the on state to the off state, the depletion layer is － The pn junction surface of the p-type drift region 1 and the p-type base region 2 diffuses. － The width of the drift region 1 increases as it moves downward, so n －The amount of n-type impurities contained in the drift region 1 increases as it moves downward. Therefore, the more the depletion layer diffuses downward, the slower the diffusion rate of the depletion layer. For example, regarding the relationship between the voltage Vds of the drain electrode 31 relative to the source electrode 32 and the output capacity Coss, the output capacity Coss changes slowly relative to the voltage Vds. As a result, the noise generated when the semiconductor device 120 is switched to the off state can be reduced.

[0068] In addition, the width of one first conductive portion 21 is narrower than the width of the other first conductive portion 21. The one first conductive portion 21 is located below the other first conductive portion 21.

[0069] The width of one second conductive portion 22 is narrower than the width of the other second conductive portion 22. The one second conductive portion 22 is located below the other second conductive portion 22.

[0070] For example, the width of each first conductive portion 21 and the width of each second conductive portion 22 become shorter toward the bottom.

[0071] This can suppress the width of each first conductive portion 21 and the width of each second conductive portion 22 in the Z direction, as compared to the case where the width of each first conductive portion 21 and the width of each second conductive portion 22 are constant. － The thickness of the insulating portion 10 in the X direction between the drift region 1 and the conductive portion 20 varies in the Z direction. For example, it is possible to suppress the occurrence of dielectric breakdown due to the thickness of the insulating portion 10 becoming thinner at the bottom of the insulating portion 10 .

[0072] Several embodiments of the present invention are illustrated above, but these embodiments are proposed as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, changes, etc. can be made without departing from the scope of the main purpose of the invention. These embodiments and their modifications are included in the scope and main purpose of the invention, and are included in the invention described in the claims and the scope of their equivalents. In addition, the aforementioned embodiments can be implemented in combination with each other.

Claims

1. A semiconductor device comprising: a first electrode; A first semiconductor region of a first conductivity type, disposed on the first electrode and electrically connected to the first electrode; A second semiconductor region of a second conductivity type, disposed on the first semiconductor region; A third semiconductor region of the first conductivity type, disposed on the second semiconductor region; an insulating portion arranged side by side with a portion of the first semiconductor region, the second semiconductor region, and the third semiconductor region in a second direction perpendicular to the first direction from the first electrode toward the first semiconductor region, the insulating portion comprising a plurality of first insulating portions and a plurality of second insulating portions alternately arranged along the first direction, an outer diameter of each of the first insulating portions in the second direction being longer than an outer diameter of each of the second insulating portions in the second direction; a conductive portion, disposed in the insulating portion and arranged side by side with the first semiconductor region in the second direction; a gate electrode, disposed in the insulating portion and arranged side by side with the second semiconductor region in the second direction; as well as The second electrode is disposed on the third semiconductor region and is electrically connected to the third semiconductor region.

2. The semiconductor device according to claim 1, The insulating portion further includes a third insulating portion disposed on the plurality of first insulating portions and the plurality of second insulating portions, The side surface of the third insulating portion is parallel to the first direction, The gate electrode is disposed in the third insulating portion.

3. The semiconductor device according to claim 1 or 2, One or more first insulating portions among the plurality of first insulating portions are provided below the conductive portion.

4. The semiconductor device according to claim 1 or 2, The conductive portion includes a plurality of first conductive portions and a plurality of second conductive portions alternately arranged in the first direction, The length of each of the first conductive portions in the second direction is longer than the length of each of the second conductive portions in the second direction. The plurality of first insulating portions are respectively arranged around the plurality of first conductive portions along a first plane perpendicular to the first direction, The plurality of second insulating portions are respectively arranged around the plurality of second conductive portions along the first surface.

5. The semiconductor device according to claim 1 or 2, One of the plurality of first insulating portions is located below another of the plurality of first insulating portions. An outer diameter of the one of the plurality of first insulating portions in the second direction is shorter than an outer diameter of the other of the plurality of first insulating portions in the second direction.

6. A semiconductor device comprising: a first electrode; A first semiconductor region of a first conductivity type, disposed on the first electrode and electrically connected to the first electrode; A second semiconductor region of a second conductivity type, disposed on the first semiconductor region; A third semiconductor region of the first conductivity type, disposed on the second semiconductor region; an opening, arranged in parallel with a portion of the first semiconductor region, the second semiconductor region, and the third semiconductor region in a second direction perpendicular to the first direction from the first electrode toward the first semiconductor region, wherein a sidewall of the opening comprises a plurality of concave portions and a plurality of convex portions alternately arranged along the first direction, each of the concave portions being recessed from the opening toward the first semiconductor region along the second direction, and each of the convex portions being protruded from the first semiconductor region toward the opening along the second direction; a conductive portion, disposed in the opening and arranged side by side with the first semiconductor region in the second direction; a gate electrode, disposed in the opening and arranged side by side with the second semiconductor region in the second direction; as well as The second electrode is disposed on the third semiconductor region and is electrically connected to the third semiconductor region.

7. A method for manufacturing a semiconductor device, forming a semiconductor region of a second conductivity type on an upper surface of the semiconductor layer of the first conductivity type, removing a portion of the semiconductor region and a portion of the semiconductor layer to form an opening, forming a conductive portion and a gate electrode in the opening via an insulating layer, Another semiconductor region of the first conductivity type is formed on the semiconductor region, wherein: In the process of forming the opening, a plurality of concave portions and a plurality of convex portions are formed on side walls of the opening and are alternately arranged in a first direction from the semiconductor layer toward the semiconductor region.

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