Transistor and method of forming transistor

Abstract

A transistor includes a top source / drain region, a bottom source / drain region, a channel region vertically between the top and bottom source / drain regions, and a gate laterally adjacent to the channel region in an operational manner. An upper material is directly above a lower material. The upper material is in at least one of the top source / drain region, the bottom source / drain region, and the channel region. The lower material is in at least one of the top source / drain region, the bottom source / drain region, and the channel region. The upper material includes 1 atomic percent to 10 atomic percent of elemental form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more inert elements. The lower material includes 0 atomic percent to less than 1 atomic percent of elemental form H and 0.1 total atomic percent to 10 total atomic percent of one or more inert elements. Other embodiments are disclosed, including methods.

Description

Technical Field

[0001] Embodiments disclosed herein relate to transistors and methods of forming transistors. Background Art

[0002] Memory is a type of integrated circuit and is used in computer systems to store data. Memory can be fabricated in one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). Sense lines can interconnect memory cells in a conductive manner along the columns of the array, and access lines can interconnect memory cells in a conductive manner along the rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for a long period of time without power. Non-volatile memory is generally specified as memory with a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of a few milliseconds or less. In any case, the memory cell is configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered to be "0" or "1". In other systems, at least some individual memory cells may be configured to store information at more than two levels or states.

[0004] A field effect transistor is an electronic component that can be used in a memory cell. These transistors include a pair of conductive source / drain regions with a semiconductive channel region between them. A conductive gate is adjacent to the channel region and is separated from the channel region by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate. Field effect transistors are of course also used in integrated circuits in addition to and / or in addition to memory circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a diagrammatic cross-sectional view of a transistor according to an embodiment of the present invention.

[0006] Figure 2 is a diagrammatic cross-sectional view of a transistor according to an embodiment of the present invention.

[0007] Figure 3is a diagrammatic cross-sectional view of a transistor according to an embodiment of the present invention.

[0008] Figure 4 is a diagrammatic cross-sectional view of a transistor according to an embodiment of the present invention.

[0009] Figure 5 is a diagrammatic cross-sectional view of a transistor according to an embodiment of the present invention.

[0010] Figure 6 is a diagrammatic cross-sectional view of a transistor according to an embodiment of the present invention.

[0011] Figure 7 is a diagrammatic cross-sectional view of a transistor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0012] Embodiments of the present invention encompass methods of forming one or more transistors and one or more transistors independent of the manufacturing method. A transistor manufactured according to a method embodiment may have any of the properties described herein in the structural embodiments. Figure 1 1 is a first example transistor 14 as part of a construction 10 according to an embodiment of the present invention. Construction 10 includes a base substrate 11 having any one or more of a conductive / conductor / conductive, semiconductive / semiconducting, or insulating / insulator / insulating (i.e., electrically herein) material 12. Various materials have been vertically formed above base substrate 11. The materials may be Figure 1 Next to, vertically inwardly of, or vertically outwardly of the depicted material. For example, other partially fabricated or fully fabricated components of an integrated circuit may be disposed somewhere above, around, or within base substrate 11. Only one transistor 14 is shown, but construction 10 may include multiple transistors of the same or different constructions, such as fabricated in an array including one or more transistors according to the present invention.

[0013] Transistor 14 includes a top source / drain region 16, a bottom source / drain region 18, a channel region 20 vertically disposed between the top source / drain region 16 and the bottom source / drain region 18, respectively, and a gate 22 (i.e., a conductive material) operatively laterally adjacent to the channel region 20. A gate insulator 24 (e.g., silicon dioxide and / or silicon nitride) is between the gate 22 and the channel region 20. For simplicity and clarity, the example components depicted are only shown at the bottom. Figure 1 The source / drain region and the channel region may be, for example, extended to Figure 138 and 40. The source / drain regions 16 and 20 may be in the form of coextensive longitudinal extensions in the plane of the page and extending out of the plane of the page. Alternatively, and by way of example only, such example source / drain regions and channel regions may be circular, rectangular, elliptical, triangular, etc. in a horizontal cross-section (not shown). The gate insulator 24 and / or gate 22 may surround such structures at the periphery, or alternatively, by way of example only, only partially surround such structures or only on one side in a vertical cross-section (not shown). The top source / drain regions 16 and channel regions 20 may be considered to have a top interface 38, and the bottom source / drain regions 18 and channel regions 20 may be considered to have a bottom interface 40. Interfaces 38 and / or 40 are shown as being flat and horizontal, but other oriented interfaces may be used, such as diagonal, jagged and / or wavy interfaces, combinations of straight and curved sections, etc. By way of example only, regions 16, 18, and 20 may include one or more of silicon in elemental form, germanium in elemental form, a mixture of silicon and germanium, etc.

[0014] Ideally, the top source / drain region 16, the bottom source / drain region 18, and the channel region 20 have grains and grain boundaries therebetween (none shown). Ideally, each of these regions is completely crystalline. In this document, "crystalline" without a numerical percentage or other quantitative adjective preceding it is a material, region, and / or structure that is at least 90% crystalline by volume (i.e., having at least 90% grains by volume). Two or three of the regions 16, 18, 20 may have the same or different average crystal grain size (i.e., by volume) from one another.

[0015] The transistor includes an upper material directly above the lower material. Ideally, the upper material is directly against the lower material. The upper material is in at least one of the top source / drain region, the bottom source / drain region, and the channel region. The lower material is also in at least one of the top source / drain region, the bottom source / drain region, and the channel region. In one embodiment, the upper and lower materials are in the same one of the top source / drain region, the bottom source / drain region, and the channel region. In another embodiment, the upper and lower materials are in different ones of the top source / drain region, the bottom source / drain region, and the channel region. In one embodiment, the maximum thickness of each of the upper and lower materials is 50 angstroms to 2,000 angstroms. In one embodiment, the maximum thickness of the lower material is less than the maximum thickness of the upper material.

[0016] Figure 1Shown is an example embodiment in which the top source / drain region 16 includes material 52, the channel region 20 includes material 54, and the bottom source / drain region includes material 50, wherein material 50 includes upper material 30 and lower material 32 (as mentioned above). The example upper material 30 and lower material 32 are directly against each other along a continuous interface 36. Alternatively, the upper material 30 and lower material 32 may not be directly against each other continuously across the depicted cross section (not shown) or may not be directly against each other (not shown). In any case, any of the materials 52, 54 and 50 may be undoped or doped with a dopant that modifies conductivity (e.g., phosphorus, arsenic, etc.). Example primary materials for each of the materials 52, 54 and 50 include single crystal silicon or polycrystalline silicon, including such materials as mixtures and / or alloys with germanium. Other characteristics of the upper material 30 and lower material 32 according to different embodiments of the present invention are described below.

[0017] Figure 1 An example embodiment is shown in which the upper material 30 and the lower material 32 are in the bottom source / drain region 18 . Figure 2 An example alternative embodiment configuration 10a is shown including a transistor 14a in which upper material 30 and lower material 32 include material 54a of channel region 20, and bottom source / drain region 18 includes material 50a. Like reference numerals from the above described embodiments have been used where appropriate, with the suffix "a" indicating certain configuration differences. Figure 3 Another example alternative embodiment configuration 10b is shown, which includes a transistor 14b, wherein the upper material 30 and the lower material 32 include material 52b in the top source / drain region 16. The same reference numerals from the embodiments described above have been used where appropriate, with the suffix "b" indicating certain construction differences. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used Figure 2 and 3 In the embodiment of .

[0018] Figures 1 to 3 An embodiment is shown where upper material 30 and lower material 32 are only in one of top source / drain region 16, bottom source / drain region 18, and channel region 20. Alternatively, such material may be in any two or all three of top source / drain region 16, bottom source / drain region 18, and channel region 20.

[0019] Figure 4 An alternative embodiment configuration 10c is shown including transistor 14c. The same reference numerals from the embodiments described above have been used where appropriate, with certain configuration differences indicated by a suffix "c" or a different reference numeral. By way of example only, Figure 4An embodiment is shown where the upper material 30 and the lower material 32 are in the same one of the top source / drain region, the bottom source / drain region, and the channel region (in the bottom source / drain region 18 as shown), but do not cover all thicknesses of such the same region. As an example, Figure 4 The bottom source / drain region 18 is shown as comprising material 50c with upper material 30 and lower material 32 sandwiched between upper material 55 and lower material 55 (e.g., doped semiconductor material). The example relationship of materials 55, 30, and 32 may alternatively or additionally be in either or both of the channel region 20 and the top source / drain region 16.

[0020] Figure 5 An example alternative embodiment configuration 10d of transistor 14d is shown where upper material 30 covers all of top source / drain regions 16, and lower material 32 covers all of channel region 20. Like reference numerals from the above described embodiments have been used where appropriate, with certain configuration differences indicated by the suffix "d". Figure 6 Another example alternative construction 10e is shown including a transistor 14e in which an upper material 30 is included in the channel region 20 and a lower material 32 is included in the bottom source / drain region 18. The same reference numerals from the embodiments described above have been used where appropriate, with the suffix "e" indicating certain construction differences. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used Figure 5 and 6 In the embodiment of .

[0021] Figure 7 Another example alternative embodiment configuration 10f is shown including transistor 14f. The same reference numerals from the embodiments described above have been used where appropriate, with certain construction differences indicated by the suffix "f" or different reference numerals. The upper material 30 of the example transistor 14f is in the bottom of the top source / drain region 16, and the lower material 32 is in the top of the channel region 20. The example material 52f of the top source / drain region 16 includes a material 56 (e.g., a doped semiconductor material) atop the upper material 30, and the material 54f of the channel region 20 includes a lower material 32 atop a suitable material 58 (e.g., a doped or undoped semiconductor material). As an alternative example, materials 30 and 32 may be in the bottom of the channel region 20 and the top of the bottom source / drain region 18, respectively (not shown). In addition and in any case, any interface 36 between materials 30 and 32 does not have to coincide with interfaces 38 and 40.

[0022] In one embodiment, the upper material 30 includes 1 atomic percent to 10 atomic percent of the elemental form H and 0 to less than 0.1 total atomic percent of one or more inert elements (i.e., any of He, Ne, Ar, Dr, Xe, Rn, and Og), and the lower material 32 includes 0 to less than 1 atomic percent of the elemental form H and 0.1 to 10 total atomic percent of the one or more inert elements. In one such embodiment, the upper material 30 includes 1 to 4 atomic percent of the elemental form H (in one embodiment, the total atoms of the elemental form H do not exceed 1x10 -6 ), and in one embodiment, the upper material comprises 0 total atomic percent to no more than 1x10 -6 In one embodiment, the lower material 32 includes 0.1 to 4 total atomic percent of one or more inert elements (in one embodiment, the total atomic percent of the one or more inert elements does not exceed 1x10 -6 ), and in one embodiment, the lower material includes 0 atomic percent to no more than 1x10 -6 Total atoms of the elemental form H. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0023] In one embodiment, the upper material 30 includes 0 atomic percent to less than 1 atomic percent of the elemental form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more inert elements, and the lower material 32 includes 0 atomic percent to less than 1 atomic percent of the elemental form H and 0.1 total atomic percent to 10 total atomic percent of one or more inert elements. In one such embodiment, the upper material 30 includes 0 atomic percent to no more than 1x10 -6 total atoms of elemental form H, and in one embodiment, the upper material comprises 0 total atomic percent to no more than 1x10 -6 In one embodiment, the lower material 32 includes 0 atomic percent to no more than 1x10 -6 In one embodiment, the lower material comprises 0.1 to 4 total atomic percent of one or more inert elements (in one embodiment, the total atomic percent of the one or more inert elements does not exceed 1x10 -6 Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0024] In one embodiment, the upper material 30 includes 0 atomic percent to less than 1 atomic percent of the elemental form H and 0.1 total atomic percent to 10 total atomic percent of one or more inert elements, and the lower material 32 includes 1 atomic percent to 10 atomic percent of the elemental form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more inert elements. In one such embodiment, the upper material 30 includes 0 atomic percent to no more than 1x10 -6 In one embodiment, the upper material comprises 0.1 to 4 total atomic percent of one or more inert elements (in one embodiment, the total atomic percent of the one or more inert elements does not exceed 1x10 -6 In one embodiment, the lower material 32 includes 1 atomic percent to 4 atomic percent of elemental form H (in one embodiment, the total atoms of elemental form H do not exceed 1x10 -6 ), and in one embodiment, the lower material comprises 0 total atomic percent to no more than 1x10 -6 Total atoms of one or more inert elements. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0025] The amount of elemental form H and the amount of one or more inert elements may be used to modify the conductivity of the upper material 30 and / or lower material 32 having conductivity-modifying dopants and / or may be artifacts therein.

[0026] Embodiments of the present invention encompass methods and transistors that are independent of manufacturing methods as identified above. However, such methods may have any of the properties described above in the structural embodiments. Similarly, the structural embodiments described above may be incorporated into and form any of the properties described below with respect to the method embodiments. The example method can be used to form at least a portion of a vertical transistor, the portion including at least a portion of a top source / drain region, at least a portion of a bottom source / drain region, or at least a portion of a channel region vertically located between the top and bottom source / drain regions. The example method includes forming a lower material (e.g., 32) above a substrate (e.g., 11), wherein the lower material is amorphous with a volume up to 20% crystalline. In this document, "amorphous" without a numerical percentage or other quantitative adjective in front is a material, region, and / or structure that is at least 90% amorphous by volume. The upper material (e.g., 30) is formed on top of the lower material (and ideally directly against the lower material) and is also amorphous with a volume up to 20% crystalline. Material 30 and material 32 may be formed using the same technique (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc.) or using different such or other techniques. Ideally, each of material 30 and material 32 is completely amorphous. Regardless, the upper and lower materials are annealed to each be crystalline, and ideally completely crystalline.

[0027] In one embodiment, the annealing of the upper material and the annealing of the lower material are performed simultaneously. In another embodiment, the annealing of the upper material and the annealing of the lower material are performed at different time periods. In one embodiment, the annealing of at least one of the upper material and the lower material comprises laser annealing. By way of example only, the laser annealing may use a wavelength between 200 nanometers and 700 nanometers, 0.1 J / cm 2 To 2J / cm 2 The power (ideally 0.5 J / cm 2 To 2J / cm 2 ), a pulse width of 5 nanoseconds to 250 nanoseconds, 1 to 100 laser shots, and a substrate temperature of room temperature to 450°C. The laser power used for any annealing can be varied at the option of the technician to control the surface roughness of the interface being laser annealed and the granularity of the layer. In addition, the substrate temperature can be changed for different laser shots, such as laser power and / or pulse width. Laser annealing can cause the annealed material to melt. Any material that is laser annealed prior to such laser annealing can be doped to different concentrations. In any case, in one embodiment, annealing activates dopants that increase conductivity that are present in the upper and lower materials. In one embodiment, the maximum temperature when the lower material is formed is lower than the maximum temperature when the upper material is formed. In one embodiment, the lower material is formed by physical vapor deposition and the upper material is formed by chemical vapor deposition.

[0028] In one embodiment, upper material 30 is formed to include 1 atomic percent to 10 atomic percent of elemental form H and 0 to less than 0.1 total atomic percent of one or more inert elements, and lower material 32 includes 0 to less than 1 atomic percent of elemental form H and 0.1 to 10 total atomic percent of one or more inert elements. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0029] In one embodiment, upper material 30 includes 0 atomic percent to less than 1 atomic percent of elemental form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more inert elements, and lower material 32 includes 0 atomic percent to less than 1 atomic percent of elemental form H and 0.1 total atomic percent to 10 total atomic percent of one or more inert elements. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0030] In one embodiment, upper material 30 includes 0 atomic percent to less than 1 atomic percent of elemental form H and 0.1 total atomic percent to 10 total atomic percent of one or more inert elements, and lower material 32 includes 1 atomic percent to 10 atomic percent of elemental form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more inert elements. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0031] One or more method embodiments of the present invention are motivated by the desire to fabricate vertical transistors at lower temperatures (e.g., below 500° C.) and at low or lower thermal budgets. This may be significant in the fabrication of integrated circuits that form multiple stacks of circuits one above the other, where processing of the higher stack should not cause melting or other adverse phenomena in one or more stacks below the higher stack. Thermal budget constraints may limit the allowable deposition temperature and time at said temperature (e.g., less than 1 minute at 500° C. and less than 60 minutes at 450° C.). In addition, the deposition rate at the lower temperature may be low to prevent sufficient deposition before the thermal budget is exceeded.

[0032] Plasma enhanced chemical vapor deposition is also a technique by which lower deposition temperatures can be achieved compared to thermal chemical vapor deposition. Elemental silicon is a common required primary material for vertical transistors and other transistors. Deposition can be performed using silanes (materials containing silicon and hydrogen), such as monosilane, disilane, trisilane, tetrasilane, or neopentasilane. Plasma enhanced chemical vapor deposition using silanes can produce elemental hydrogen that is incorporated into the deposited layer. In addition, the presence of hydrogen in the resulting silicon-containing layer has an adverse effect on the adhesion of the deposited layer to the underlying substrate material. According to some embodiments of the present invention, a lower hydrogen content (e.g., less than 1 atomic percent) in the underlying material can improve adhesion to the underlying material.

[0033] Physical vapor deposition is another technique by which materials can be deposited onto a substrate at a desired lower temperature, but the structural properties of such deposited materials may be less than ideal compared to materials deposited using plasma enhanced chemical vapor deposition. Physical deposition uses a target that is substantially composed of the desired material to be deposited. The target is physically bombarded (e.g., sputtered) with one or more inert gases that physically move the target material so that it is physically deposited on a substrate positioned near the target. Some of the inert gas (i.e., inert element) may be incorporated into the material physically deposited on the substrate. Inert elements incorporated into a physical-vapor deposited layer may undesirably create void spaces in the upper portion of the layer compared to its lower portion, which may be disadvantageous. Therefore, and in possible some embodiments, a deposited layer having less inert elements in its outermost portion compared to its lower portion may reduce void formation.

[0034] In some embodiments, the presence of one or more inert elements and / or elemental hydrogen can prevent diffusion of undesirable dopants in and / or within different regions of the substrate and, for example, can help achieve very low or undoped channel regions when desired.

[0035] The above-described processing or construction may be considered to be associated with an array of components formed as a single stack or a single stack of such components or within a single stack or a single stack, the single stack or a single stack being above or as part of the underlying base substrate (although a single stack / stack may have multiple stacks). Control and / or other peripheral circuits for operating or accessing such components within the array may also be formed at any location as part of the finished construction, and in some embodiments may be below the array (e.g., CMOS under the array). In any case, one or more additional such stacks / stacks may be disposed or manufactured above and / or below the stacks / stacks shown in the figures or described above. In addition, the arrays of components may be the same or different relative to each other in different stacks / stacks. Intermediate structures may be disposed between vertically adjacent stacks / stacks (e.g., additional circuits and / or dielectric layers). In addition, different stacks / stacks may be electrically coupled relative to each other. Multiple stacks / stacks may be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / stacks may be manufactured substantially simultaneously.

[0036] The assemblies and structures discussed above can be used in integrated circuits / circuitry systems and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, transportation vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0037] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "top", "bottom", "above", "below", "under", "under", "upward", and "downward" generally refer to the vertical direction. "Horizontal" refers to the general direction along the main substrate surface and can be relative to the substrate processed during manufacturing (i.e., within 10 degrees), and vertical is a direction generally orthogonal thereto. Reference to "just horizontal" refers to a direction along the main substrate surface (i.e., not at an angle to the surface) and the substrate can be processed during manufacturing. In addition, "vertical" and "horizontal" as used herein are generally perpendicular directions relative to each other and have nothing to do with the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "vertically extending" refer to a direction inclined at least 45° from just horizontal. In addition, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending", etc., relative to a field effect transistor, refer to the orientation of the channel length of the transistor, and in operation, the current flows between the source / drain regions along the orientation. For a bipolar junction transistor, "extending vertically", "extending vertically", "extending horizontally", "extending horizontally", etc., refer to the orientation of the substrate length along which current flows between the emitter and the collector in operation. In some embodiments, any component, part, and / or region extending vertically extends vertically or within 10° of vertical.

[0038] Furthermore, "directly above," "directly below," and "directly beneath" require at least some lateral overlap (i.e., horizontally) of the two stated regions / materials / components relative to each other. And, the use of "above" without a preceding "directly" requires only that some portion of the stated region / material / component that is above another stated region / material / component is vertically outside of the other stated region / material / component (i.e., regardless of whether there is any lateral overlap of the two stated regions / materials / components). Similarly, the use of "under" and "below" without a preceding "directly" requires only that some portion of the stated region / material / component that is below another stated region / material / component is vertically inside of the other stated region / material / component (i.e., regardless of whether there is any lateral overlap of the two stated regions / materials / components).

[0039] Any of the materials, regions, and structures described herein may be uniform or non-uniform, and in any case may be continuous or discontinuous over any material overlying it. When one or more example compositions are provided for any material, the material may include, consist essentially of, or consist of such one or more compositions. In addition, unless otherwise stated, each material may be formed using any suitable existing or future developed technology, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0040] In addition, "thickness" (without a directional adjective in front) used alone is defined as the average straight-line distance perpendicularly passing through a given material or region from the closest surface of an adjacent material or adjacent region with different compositions. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, then unless otherwise indicated, the thickness refers to the average thickness, and such materials or regions will have a certain minimum thickness and a certain maximum thickness due to the variable thickness. As used herein, "different compositions" only require that those parts of the two stated materials or regions that can directly abut against each other are chemically and / or physically different, such as when the materials or regions are not uniform. If the two stated materials or regions do not directly abut against each other, then in the case where such materials or regions are not homogeneous, "different compositions" only require that those parts of the two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, when the stated materials, regions or structures have at least a certain physical touch relative to each other, the material, region or structure "directly abuts" another material, region or structure. In contrast, the words “over,” “on,” “adjacent to,” “along,” and “against” without being preceded by “directly” encompass “directly against” as well as configurations in which one or more intervening materials, one or more regions, or one or more structures are such that the stated materials, regions, or structures are not in physical contact with each other.

[0041] Herein, the regions-material-components are "electrically coupled" relative to each other if, in normal operation, electrical current is able to flow continuously from one region-material-component to another region-material-component, and the flow occurs primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be between the region-material-components and electrically coupled to the region-material-components. In contrast, when the region-material-components are referred to as being "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0042] The components of any of the conductive / conductor / conductive materials herein may be metallic materials and / or conductively doped semiconductive / semiconductive / semiconductive materials. "Metallic material" is any one or combination of elemental metals, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0043] As used herein, "selective" with respect to etching, etching, removal, deposition, forming, and / or formation is such action that one stated material is acted upon relative to another stated material in a volume ratio of at least 2:1. In addition, selectively depositing, selectively growing, or selectively forming is to deposit, grow, or form one material relative to another stated material or materials in a volume ratio of at least 2:1 for at least the first 75 angstroms of deposition, growth, or formation.

[0044] Unless otherwise indicated, the use of "or" herein includes either or both.

[0045] in conclusion

[0046] In some embodiments, a transistor includes a top source / drain region, a bottom source / drain region, a channel region vertically between the top and bottom source / drain regions, and a gate laterally adjacent to the channel region in an operational manner. The upper material is directly above the lower material. The upper material is in at least one of the top source / drain region, the bottom source / drain region, and the channel region. The lower material is in at least one of the top source / drain region, the bottom source / drain region, and the channel region. The upper material includes 1 atomic percent to 10 atomic percent of elemental form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more inert elements. The lower material includes 0 atomic percent to less than 1 atomic percent of elemental form H and 0.1 total atomic percent to 10 total atomic percent of one or more inert elements.

[0047] In some embodiments, a transistor includes a top source / drain region, a bottom source / drain region, a channel region vertically between the top and bottom source / drain regions, and a gate laterally adjacent to the channel region in an operational manner. The upper material is directly above the lower material. The upper material is in at least one of the top source / drain region, the bottom source / drain region, and the channel region. The lower material is in at least one of the top source / drain region, the bottom source / drain region, and the channel region. The upper material includes 0 atomic percent to less than 1 atomic percent of the elemental form H, and 0 total atomic percent to less than 0.1 total atomic percent of one or more inert elements. The lower material includes 0 atomic percent to less than 1 atomic percent of the elemental form H and 0.1 total atomic percent to 10 total atomic percent of one or more inert elements.

[0048] In some embodiments, a transistor includes a top source / drain region, a bottom source / drain region, a channel region vertically between the top and bottom source / drain regions, and a gate laterally adjacent to the channel region in an operational manner. The upper material is directly above the lower material. The upper material is in at least one of the top source / drain region, the bottom source / drain region, and the channel region. The lower material is in at least one of the top source / drain region, the bottom source / drain region, and the channel region. The upper material includes 0 atomic percent to less than 1 atomic percent of elemental form H and 0.1 total atomic percent to 10 total atomic percent of one or more inert elements. The lower material includes 1 atomic percent to 10 atomic percent of elemental form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more inert elements.

[0049] In some embodiments, a method is used to form at least a portion of a vertical transistor, wherein the portion includes at least a portion of a top source / drain region, at least a portion of a bottom source / drain region, or at least a portion of a channel region vertically between the top and bottom source / drain regions. The method includes forming a lower material above a substrate, wherein the lower material is crystalline with an amorphous volume up to 20%. The lower material includes 0 atomic percent to less than 1 atomic percent of elemental form H and 0.1 total atomic percent to 10 total atomic percent of one or more inert elements. An upper material is formed on top of the lower material. The upper material is crystalline with an amorphous volume up to 20%. The upper material includes 1 atomic percent to 10 atomic percent of elemental form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more inert elements. The upper and lower materials are annealed to each be crystalline.

[0050] In some embodiments, a method is used to form at least a portion of a vertical transistor, wherein the portion includes at least a portion of a top source / drain region, at least a portion of a bottom source / drain region, or at least a portion of a channel region vertically between the top and bottom source / drain regions. The method includes forming a lower material above a substrate, wherein the lower material is crystalline with an amorphous volume up to 20%. The lower material includes 0 atomic percent to less than 1 atomic percent of elemental form H and 0.1 total atomic percent to 10 total atomic percent of one or more inert elements. An upper material is formed on top of the lower material. The upper material is crystalline with an amorphous volume up to 20%. The upper material includes 0 atomic percent to less than 1 atomic percent of elemental form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more inert elements. The upper and lower materials are annealed to each be crystalline.

[0051] In some embodiments, a method is used to form at least a portion of a vertical transistor, wherein the portion includes at least a portion of a top source / drain region, at least a portion of a bottom source / drain region, or at least a portion of a channel region vertically between the top and bottom source / drain regions. The method includes forming a lower material above a substrate, wherein the lower material is crystalline with an amorphous volume up to 20%. The lower material includes 1 atomic percent to 10 atomic percent of elemental form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more inert elements. An upper material is formed on top of the lower material. The upper material is crystalline with an amorphous volume up to 20%. The upper material includes 0 atomic percent to less than 1 atomic percent of elemental form H and 0.1 total atomic percent to 10 total atomic percent of one or more inert elements. The upper and lower materials are annealed to each be crystalline.

Claims

1. A transistor comprising: Upper material, comprising: 1 atomic percent to 10 atomic percent H in elemental form; and 0 to less than 0.1 total atomic percent of one or more inert elements; The lower material directly below the upper material comprises: 0 atomic percent to less than 1 atomic percent of elemental form H; and 0.1 to 10 atomic percent of one or more inert elements; At least one of a top source / drain region, a bottom source / drain region, and a channel region of the transistor includes the upper material, and at least one of the top source / drain region, the bottom source / drain region, and the channel region includes the lower material; and A gate is operatively laterally adjacent to the channel region.

2. The transistor of claim 1, wherein the upper material directly abuts against the lower material.

3. The transistor of claim 1, wherein the upper material comprises 1 atomic percent to 4 atomic percent H in elemental form. 4 . The transistor of claim 1 , wherein the lower material comprises 0.1 to 4 total atomic percent of the one or more inert elements.

5. The transistor of claim 1, wherein the upper material comprises 0 total atomic percent to no more than 1×10 -6 total atoms of the one or more inert elements.

6. The transistor of claim 1, wherein the lower material comprises 0 atomic percent to no more than 1×10 -6 total atoms of the element in form H.

7. The transistor of claim 1 wherein the upper and lower materials are in the same one of the top source / drain region, the bottom source / drain region, and the channel region.

8. The transistor of claim 7 wherein the upper and lower materials are in the top source / drain region.

9. The transistor of claim 7 wherein the upper and lower materials are in the channel region.

10. The transistor of claim 7 wherein the upper and lower materials are in the bottom source / drain region.

11. The transistor of claim 1 wherein the upper and lower materials are in different ones of the top source / drain region, the bottom source / drain region, and the channel region.

12. The transistor according to claim 11, wherein The upper material directly abuts against the lower material; The upper material is in the bottom of the top / source drain region; and The lower material is in a top portion of the channel region.

13. The transistor according to claim 12, wherein: The upper material directly abuts against the lower material; The upper material is in the bottom of the channel region; and The lower material is in the top of the bottom source / drain region.

14. The transistor of claim 1, wherein a maximum thickness of each of the upper and lower materials is 50 angstroms to 2,000 angstroms.

15. The transistor of claim 1, wherein a maximum thickness of the lower material is smaller than a maximum thickness of the upper material.

16. A transistor comprising: Upper material, comprising: 0 atomic percent to less than 1 atomic percent of elemental form H; and 0 total atomic percent to less than 0.1 total atomic percent of one or more inert elements; and The lower material directly below the upper material comprises: 0 atomic percent to less than 1 atomic percent of elemental form H; and 0.1 to 10 atomic percent of one or more inert elements; At least one of a top source / drain region, a bottom source / drain region, and a channel region of the transistor includes the upper material, and at least one of the top source / drain region, the bottom source / drain region, and the channel region includes the lower material; and A gate is operatively laterally adjacent to the channel region. The transistor of claim 16 , wherein the upper material is directly against the lower material.

18. A transistor comprising: Upper material, comprising: 0 atomic percent to less than 1 atomic percent of elemental form H; and 0.1 to 10 atomic percent of one or more inert elements; and The lower material directly below the upper material comprises: 1 atomic percent to 10 atomic percent H in elemental form; and 0 to less than 0.1 total atomic percent of one or more inert elements; At least one of a top source / drain region, a bottom source / drain region, and a channel region of the transistor includes the upper material, and at least one of the top source / drain region, the bottom source / drain region, and the channel region includes the lower material; and A gate is operatively laterally adjacent to the channel region. The transistor of claim 18 , wherein the upper material is directly against the lower material.

20. A method for forming at least a portion of a vertical transistor, the portion comprising at least a portion of a top source / drain region, at least a portion of a bottom source / drain region, or at least a portion of a channel region vertically between the top and bottom source / drain regions, the method comprising: A lower material is formed over the substrate, the lower material being amorphous with up to 20% volume crystalline, the lower material comprising: 0 atomic percent to less than 1 atomic percent of elemental form H; and 0.1 to 10 atomic percent of one or more inert elements; An upper material is formed on top of the lower material, the upper material being amorphous with up to 20% crystalline volume, the upper material comprising: 1 atomic percent to 10 atomic percent H in elemental form; and 0 total atomic percent to less than 0.1 total atomic percent of one or more inert elements; and The upper and lower materials are annealed to make each crystalline.

21. The method of claim 20, wherein the upper material is formed directly against the lower material.

22. The method of claim 20, wherein the annealing of the upper material and the annealing of the lower material are performed simultaneously.

23. The method of claim 20, wherein the annealing of the upper material and the annealing of the lower material are performed at different time periods.

24. The method of claim 20, wherein the annealing of at least one of the upper material and the lower material comprises laser annealing.

25. The method of claim 20, wherein the annealing activates conductivity-enhancing dopants in the upper and lower materials.

26. The method of claim 20, wherein a maximum temperature when the lower material is formed is lower than a maximum temperature when the upper material is formed.

27. The method of claim 20, wherein the lower material is formed by physical vapor deposition and the upper material is formed by chemical vapor deposition.

28. A method for forming at least a portion of a vertical transistor, the portion comprising at least a portion of a top source / drain region, at least a portion of a bottom source / drain region, or at least a portion of a channel region vertically between the top and bottom source / drain regions, the method comprising: A lower material is formed over the substrate, the lower material being amorphous with up to 20% volume crystalline, the lower material comprising: 0 atomic percent to less than 1 atomic percent of elemental form H; and 0.1 to 10 atomic percent of one or more inert elements; An upper material is formed on top of the lower material, the upper material being amorphous with up to 20% crystalline volume, the upper material comprising: 0 atomic percent to less than 1 atomic percent of elemental form H; and 0 total atomic percent to less than 0.1 total atomic percent of one or more inert elements; and The upper and lower materials are annealed to make each crystalline.

29. The method of claim 28, wherein the upper material is formed directly against the lower material.

30. A method for forming at least a portion of a vertical transistor, the portion comprising at least a portion of a top source / drain region, at least a portion of a bottom source / drain region, or at least a portion of a channel region vertically between the top and bottom source / drain regions, the method comprising: A lower material is formed over the substrate, the lower material being amorphous with up to 20% volume crystalline, the lower material comprising: 1 atomic percent to 10 atomic percent H in elemental form; and 0 to less than 0.1 total atomic percent of one or more inert elements; An upper material is formed on top of the lower material, the upper material being amorphous with up to 20% crystalline volume, the upper material comprising: 0 atomic percent to less than 1 atomic percent of elemental form H; and 0.1 to 10 atomic percent of one or more inert elements; and The upper and lower materials are annealed to make each crystalline.

31. The method of claim 30, wherein the upper material is formed directly against the lower material.

Images