Strained enhancement mode sic power semiconductor device and method of manufacture

Abstract

A SiC transistor device is disclosed, comprising: a SiC semiconductor substrate having a top surface and a bottom surface; a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface; a source structure formed in the top surface of the SiC epitaxial layer, the source structure having a top surface; a source contact structure electrically coupled to the top surface of the source structure; a gate structure comprising a gate oxide, a metal gate, and a gate insulator; a first backside metal contact on the bottom surface of the SiC semiconductor substrate; a stress inducing layer on the first backside metal contact; a second backside metal contact on the stress inducing layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a SiC (silicon carbide) power semiconductor device and a process flow for fabricating a SiC power semiconductor device. The fabrication method utilizes stress-induced inversion channel mobility enhancement. BACKGROUND

[0002] This section provides background information relating to the present disclosure and is not necessarily prior art.

[0003] 4H-SiC is the preferred polytype for power electronics devices (i.e., SiC power devices such as, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs)) due to advances in 4H-SiC growth technology and its attractive electronic properties such as a larger bandgap and higher carrier mobility than other available wafer-scale polytypes (e.g., 6H-SiC or 3C-SiC). While those SiC power devices are already commercially available, there is still much room for improvement, especially with respect to inversion channel mobility, in order to further reduce on-resistance. However, for higher voltage ratings > 3 kV, the drift layer resistance R drift dominates R on , the reduction of which is essential in commercially more relevant voltage ratings (≤ 1.7 kV) (e.g., for electric and hybrid electric vehicles (EV / HEV), photovoltaic inverters, and power supplies) in order to significantly reduce on-state power loss and switching loss. Here, R on is still far above the ideal value as shown, for example, by the distance of 900 V to 3.3 kV devices from the SiC limit line in Figure 1 . Higher voltage devices (such as, for example, 10 kV or 15 kV) are much closer to the SiC limit than lower voltage devices. In this regard, low inversion channel mobility represents one of the major challenges that can have a significant impact on device cost and, thus, on the widespread adoption of SiC power devices. Improving inversion channel mobility using improved gate stacks and SiC / oxide interfaces has shown limited success but is considered one of the most important milestones in the development and commercialization of SiC power MOSFETs. In the late 90s, the introduction of nitric oxide (NO) post-oxidation for 6H-SiC and its application to 4H-SiC MOSFETs in 2001 enabled a huge increase in inversion layer electron mobility because the introduction of N near the interface via NO annealing reduced the interface defect density D it . However, in addition to the current process level of NO annealed power devices, there is a strong demand for higher mobility devices, especially in order to expand SiC power devices (particularly SiC MOSFETs) into the low / mid voltage rating market.

[0004] Further advantages are

[0005] (i) the gate can be driven at lower voltages, resulting in a smaller gate oxide field, which improves threshold stability and oxide long-term reliability, and

[0006] (ii) there is no need to aggressively scale the transistor channel length in order to reduce channel resistance, thus avoiding short channel effects.

[0007] US 6,563,152 B2 discloses a method for forming a strained layer on the underside of a channel in a MOS transistor to create mechanical stress in the channel to increase the mobility of carriers in the channel, and a device fabricated by such a method. Embodiments of the disclosed device include a transistor having a strained layer formed on the underside of the channel to create mechanical stress in the channel to increase the mobility of carriers in the channel. Embodiments of the disclosed device allow a greater amount of mechanical stress to be created in the channel, and thus allow a greater increase in the mobility of carriers in the channel, than other methods of straining the channel, such as forming a strained layer on the upper surface of the channel. The strained layer disclosed in US 6,563,152 B2 is embedded within the substrate, and requires the construction of several removal steps.

[0008] US 2009 / 0289284 Al discloses a method and semiconductor device forming a high shrinkage stress silicon nitride layer for use as a contact etch stop layer (CESL) or capping layer in stress management techniques (SMT) that provides increased tensile stress to the channel of nFET devices to enhance carrier mobility. A spin-on polysilazane based dielectric material is applied to a semiconductor substrate and baked to form a film layer. The film layer is cured to remove hydrogen from the film, which causes shrinkage in the film when the film recrystallizes into silicon nitride. The resulting silicon nitride stress layer introduces an increased level of tensile stress to the transistor channel region.

[0009] US 2017 / 194438 exhibits a silicon carbide semiconductor device including a silicon carbide semiconductor structure; an insulated gate structure including a gate insulating film contacting the silicon carbide semiconductor structure and a gate electrode formed on the gate insulating film; an interlayer insulating film covering the insulated gate structure; a metal layer provided on the interlayer insulating film for absorbing or blocking hydrogen; and a main electrode provided on the metal layer and electrically connected to the silicon carbide semiconductor structure.

[0010] EP 3 024 017 Al discloses a technique for ensuring reliability of a gate insulating film in a semiconductor device using a semiconductor material having a larger band gap than silicon and, for example, represented by a SiC power MOSFET, which is about the same as in a SiC power MOSFET. To achieve this object, in the SiC power MOSFET, a gate electrode is formed in contact with a gate insulating film, and is formed by a polysilicon film PF1 having a thickness equal to or smaller than 200 nm and a polycrystalline silicon film PF2 formed in contact with the polysilicon film PF1 and having any thickness.

[0011] From EP 2 477 213 Al a method of manufacturing a semiconductor device is known, the method comprising the steps of forming a semiconductor layer made of SiC on a SiC substrate, forming a film on the semiconductor layer, and forming a recess in the film. The semiconductor device comprising a chip with an interlayer insulating film comprises a recess formed in the interlayer insulating film to traverse the chip. SUMMARY

[0012] This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features.

[0013] The subject disclosure provides a SiC transistor device comprising: a SiC semiconductor substrate, the SiC semiconductor substrate having a top surface and a bottom surface; a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface and a bottom surface; a source structure formed in the top surface of the SiC epitaxial layer, the source structure having a top surface and a bottom surface; a source contact structure electrically coupled to the top surface of the source structure; a gate structure comprising a gate oxide, a metal gate, and a gate insulator; a first backside metal contact on the bottom surface of the SiC semiconductor substrate; a stress inducing layer on the first backside metal contact; a second backside metal contact on the stress inducing layer.

[0014] According to another aspect of the subject disclosure, the second backside metal contact of the SiC transistor device comprises at least one of titanium (Ti), nickel (Ni), or silver (Ag).

[0015] According to another aspect of the subject disclosure, the SiC transistor device comprises a second stress inducing layer on the gate structure.

[0016] According to another aspect of the subject disclosure, the SiC transistor device comprises a structured and electrically insulating second stress inducing layer on the top surface of the SiC epitaxial layer.

[0017] The subject disclosure also provides a SiC transistor device, comprising: a SiC semiconductor substrate having a top surface and a bottom surface; a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface and a bottom surface; a source structure formed in the top surface of the SiC epitaxial layer, the source structure having a top surface and a bottom surface; a source contact structure electrically coupled to the top surface of the source structure; a gate structure comprising a gate oxide, a metal gate, and a gate insulator; a first contact layer electrically contacting the source contact structure; a second contact layer electrically contacting the metal gate; a first backside metal contact on the bottom surface of the SiC semiconductor substrate; a stress inducing layer on the gate structure, wherein the stress inducing layer induces a tensile stress or a compressive stress in a range of 500 MPa to 2000 MPa depending on the manufacturing process.

[0018] The subject disclosure also provides a SiC transistor device, comprising: a SiC semiconductor substrate having a top surface and a bottom surface; a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface and a bottom surface; a source structure formed in the top surface of the SiC epitaxial layer, the source structure having a top surface and a bottom surface; a structured and electrically insulating stress inducing layer on the top surface of the SiC epitaxial layer; a source contact structure electrically coupled to the top surface of the source structure through the structured stress inducing layer; a gate structure comprising a metal gate; a first contact layer electrically contacting the source contact structure; a second contact layer electrically contacting the metal gate; a first backside metal contact on the bottom surface of the SiC semiconductor substrate, wherein the stress inducing layer induces a tensile stress or a compressive stress in a range of 500 MPa to 2000 MPa depending on the manufacturing process.

[0019] According to another aspect of the subject disclosure, the first contact layer and / or the second contact layer is at least partially covered with a passivation layer.

[0020] According to another aspect of the subject disclosure, the substrate and the SiC epitaxial layer are n-type 4H-SiC.

[0021] According to another aspect of the subject disclosure, the thickness of the stress inducing layer and / or the thickness of the second stress inducing layer is in a range of 1 nm to 1000 nm.

[0022] According to another aspect of the subject disclosure, the stress inducing layer and / or the second stress inducing layer comprises SiN.

[0023] According to another aspect of the subject disclosure, the stress inducing layer and / or the second stress inducing layer comprises SiN.

[0024] According to another aspect of the present subject disclosure, the stress inducing layer induces a tensile stress or a compressive stress in the range of 500 MPa to 2000 MPa depending on the manufacturing process.

[0025] According to another aspect of the present subject disclosure, the SiC transistor device is an Insulated Gate Bipolar Transistor (IGBT).

[0026] According to another aspect of the present subject disclosure, a method of manufacturing a SiC transistor device is disclosed, the method comprising the steps of: forming a SiC semiconductor substrate having a top surface and a bottom surface; epitaxially forming a SiC epitaxial layer on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface and a bottom surface; forming a source structure in the top surface of the SiC epitaxial layer, the source structure having a top surface and a bottom surface; forming a source contact structure electrically coupled to the top surface of the source structure; forming a gate structure on the top surface of the SiC epitaxial layer, wherein the gate structure comprises a gate oxide, a metal gate; forming a first backside metal contact on the bottom surface of the SiC semiconductor substrate; forming a stress inducing layer on the first backside metal contact; structuring the stress inducing layer; forming a second backside metal contact on the structured stress inducing layer.

[0027] According to another aspect of the present subject disclosure, a method of manufacturing a SiC transistor device is disclosed, the method comprising the steps of: forming a SiC semiconductor substrate having a top surface and a bottom surface; epitaxially forming a SiC epitaxial layer on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface and a bottom surface; forming a source structure in the top surface of the SiC epitaxial layer, the source structure having a top surface and a bottom surface; forming a source contact structure electrically coupled to the top surface of the source structure; forming a gate structure on the top surface of the SiC epitaxial layer, wherein the gate structure comprises a metal gate; forming a first contact layer electrically contacting the source contact structure; forming a second contact layer electrically contacting the metal gate; forming a first backside metal contact on the bottom surface of the SiC semiconductor substrate; forming a stress inducing layer at the gate structure, wherein the stress inducing layer induces a tensile stress or a compressive stress in the range of 500 MPa to 2000 MPa depending on the manufacturing process.

[0028] According to another aspect of the present subject disclosure, a method of manufacturing a SiC transistor device is disclosed, the method comprising the steps of: forming a SiC semiconductor substrate having a top surface and a bottom surface; epitaxially forming a SiC epitaxial layer on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface and a bottom surface; forming a source structure in the top surface of the SiC epitaxial layer, the source structure having a top surface and a bottom surface; forming an electrically insulating stress inducing layer on the top surface of the SiC epitaxial layer; structuring the electrically insulating stress inducing layer; forming a source contact structure electrically coupled to the top surface of the source structure through the structured electrically insulating stress inducing layer; forming a gate structure on the electrically insulating stress inducing layer, wherein the gate structure comprises a metal gate; forming a first contact layer electrically contacting the source contact structure; forming a second contact layer electrically contacting the metal gate; forming a first backside metal contact on the bottom surface of the SiC semiconductor substrate, wherein the stress inducing layer induces a tensile stress or a compressive stress in the range of 500 MPa to 2000 MPa depending on the manufacturing process.

[0029] According to another aspect of the present subject disclosure, a method of manufacturing a SiC transistor device is disclosed, the method comprising the steps of: forming a SiC semiconductor substrate having a top surface and a bottom surface; epitaxially forming a SiC epitaxial layer on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface and a bottom surface; forming a source structure in the top surface of the SiC epitaxial layer, the source structure having a top surface and a bottom surface; forming a source contact structure electrically coupled to the top surface of the source structure; forming a gate structure on the top surface of the SiC epitaxial layer, wherein the gate structure comprises a metal gate; forming a first stress inducing layer at the gate structure; forming a first backside metal contact on the bottom surface of the SiC semiconductor substrate; forming a second stress inducing layer on the first backside metal contact; structuring the second stress inducing layer; forming a second backside metal contact on the structured second stress inducing layer.

[0030] According to another aspect of the present subject disclosure, a method of fabricating a SiC transistor device is disclosed, the method comprising the steps of: forming a SiC semiconductor substrate having a top surface and a bottom surface; epitaxially forming a SiC epitaxial layer on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface and a bottom surface; forming a source structure in the top surface of the SiC epitaxial layer, the source structure having a top surface and a bottom surface; forming an electrically insulating first stress inducing layer on the top surface of the SiC epitaxial layer; structuring the electrically insulating first stress inducing layer; forming a source contact structure electrically coupled to the top surface of the source structure; forming a gate structure on the top surface of the SiC epitaxial layer, wherein the gate structure comprises a metal gate; forming a first backside metal contact on the bottom surface of the SiC semiconductor substrate; forming a second stress inducing layer on the first backside metal contact; structuring the second stress inducing layer; forming a second backside metal contact on the structured second stress inducing layer.

[0031] Further areas of applicability will become apparent from the description provided herein. The detailed description and specific examples in this summary are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0032] The drawings described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

[0033] Figure 1 Performance of a 4H-SiC power MOSFET at the current state of the art is shown.

[0034] Figure 2A Electrical characterization of a processed lateral SiC MOSFET is shown.

[0035] Figure 2B Electrical characterization of a strain-free lateral SiC MOSFET is shown.

[0036] Figure 2C Electrical characterization of a lateral SiC MOSFET exposed to tensile strain is shown.

[0037] Figures 3A to 3F Schematic of process integration of a backside SiN stressor layer is shown.

[0038] Figure 4A And Figure 4B Device with a frontside SiN stressor layer is shown.

[0039] Figure 5A And Figure 5BDevices with front and back side SiN stressor layers are shown. DETAILED DESCRIPTION

[0040] Examples of embodiments will now be described more fully with reference to the accompanying drawings.

[0041] Example embodiments are provided so as to convey the subtleties of the present disclosure to those skilled in the art, and to fully disclose the range of the present disclosure to those skilled in the art. Numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art, however, that the embodiments of the present disclosure can be practiced without employing specific details, and that the embodiments of the present disclosure can be implemented in many different ways, and that the scope of the present disclosure is not to be construed as being limited to one or more specific embodiments. In some example embodiments, well-known processes, well-known device structures, and well-known technologies are not described in detail.

[0042] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "including," and "having" are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order

[0043] It will also be understood that additional or alternative steps can be employed.

[0044] When an element or layer is referred to as being "on," "engaged to," "connected to," or "coupled to" another element or layer, it can be directly on, engaged, connected, or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly engaged to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.). As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] Although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can be only used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as "first," "second," and other numerical terms when used herein do not connote a sequential or chronological order, unless explicitly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.

[0046] For ease of description, spatial relative terms, such as "inner," "outer," "beneath," "below," "lower," "above," "upper," and the like, can be used herein to describe the relationship of one element or feature to another in the orientation depicted in the figures. Unless otherwise specified by the context, spatial relative terms can be intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0047] According to one embodiment of the present invention, a stressor layer (e.g., a SiN stressor layer) is formed on the backside of the fully processed wafer to improve the performance of the SiC transistor device. In Figures 2A to 2C , electrical characterization of a lateral SiC MOSFET processed differently is presented, which illustrates the advantage of the additional SiN stressor. The transfer characteristics of the MOSFET using the conventional process are shown in Figure 2A , which exhibit an I 5 / I on / I off ratio of approximately 10 DS and a sub-threshold slope of 1236 mV / decade (at V DS = 1 V). As depicted in the inset scheme, after the last processing step, the SiO2 layer 21 on the backside is still present, which leads to a wafer bow and thus to a compressive strain surface (i.e., the channel) of the MOSFET. However, by removing this residual backside layer (relieving the compressive stress) (e.g., by etching), the off-state current is reduced by almost two orders of magnitude and the sub-threshold slope is reduced to 644 mV / decade (at V DS = 1 V), see Figure 2BFinally, for the MOSFET with the additional SiN stressor layer 22 on the backside inducing tensile stress, a further reduction of the subthreshold slope to 377 mV / decade is observed, which is more than three times lower compared to the conventional process shown in Figure 2A . According to experiments performed by the inventors, the stress depends on the stoichiometry of the stressor layer material, in particular on the N content in the SiN layer.

[0048] An example of the integration of this backside stressor layer process into the existing vertical SiC power MOSFET processing platform is presented in Figures 3A to 3F . However, similar processes can also be applied to fabricate SiC IGBTs or SiC diodes. - - A 4H-SiC epitaxial layer 32 is grown on top of the n + - 4H-SiC (0001) substrate 31 and acts as drift layer material. However, the substrate can also be a Si substrate or a SiC substrate with another crystal structure like e.g. 6H-SiC or 3C-SiC. After the standard implantation steps have been completed (such as p-channel 33, p-well 34 and n ++ ohmic contact 35 (source) Figure 3A ) the gate stack is processed, which at least includes gate oxide 36, metal gate 37 and gate isolation 40 Figure 3B , Figure 3C . After the subsequent formation of front side silicide contact 38 and backside silicide contact 39 (see Figure 3C ) a silicon nitride based (SiN based) stressor layer 41 is formed on the backside of the wafer Figure 3D . An example of a method to fabricate the silicon nitride based (SiN based) stressor layer 41 on the backside is e.g. PE-CVD, LP-CVD or ALD. The thickness of the stressor layer 41 (stress inducing layer) is in the range of 1 nm to 1000 nm. The stress induced by the stressor layer 41 is in the range of 500 MPa to 2000 MPa, in a particular embodiment 1000 MPa. Depending on the application of the layer e.g. on the frontside or backside, the stressor layer is formed to induce tensile stress to the channel of the device. The device fabrication is finalized with the formation of a second backside metal contact 42 (see Figures 3E to 3F ) which includes the following steps: structuring the SiN layer (see Figure 3E ) to finally electrically contact the first backside metal contact 39 with the second backside metal contact 42. The backside metal contacts 39, 42 can be e.g. titanium (Ti), nickel (Ni), aluminum (Al), silver (Ag), titanium nitride (TiN), tantalum nitride (TaN) or copper (Cu).

[0049] Some advantages of this backside stressor layer 41 are improved interface defect density of the 4H-SiC / oxide interface (by I on / I off increased ratio and decreased subthreshold slope) and improved interface quality resulting in less carrier scattering. Thus, enhanced inversion layer electron mobility and hence lower R on on-state power losses and switching losses, especially for commercially highly relevant voltage classes (< 1.7 kV).

[0050] In another embodiment as shown in, e.g. Figure 4A In another embodiment as shown in, e.g.

[0051] In another embodiment as disclosed in Figure 4B In another embodiment as disclosed in Figure 4A In this embodiment, the SiN-based stressor layer 41 would not extend over the entire gate structure as shown in, e.g.

[0052] In another embodiment, the stressor layer is not formed to cover the entire front surface, but only as stressor lines.

[0053] To avoid inhomogeneous stress distribution, e.g. due to varying thickness of the stressor layer, in another embodiment a planarization layer can be formed to planarize the surface before applying the stressor layer. In another example, the planarization layer is a passivation layer.

[0054] In an alternative embodiment, the SiN-based stressor layer can also be an electrically conductive stressor, such as, e.g., titanium nitride (TiN). This embodiment has the advantage that the above-mentioned second backside metal contact formation and preceding structuring steps can be omitted.

[0055] In other embodiments as disclosed in, e.g. Figure 5A and Figure 5B In other embodiments as disclosed in, e.g. Figure 5AAs shown in FIG. 1, the stressor layer 51 on the front side can extend over the gate structure. Alternatively and similarly to Figure 4B , Figure 5B The SiN-based stressor layer 51 on the front side of the embodiment shown in FIG. 1 can be formed on the top surface of the SiC epitaxial layer 32 and can act as a gate dielectric. SiN can provide stress of varying types (tensile or compressive) and varying amounts depending on the time and manner of application. Thus, by forming a stressor layer on the top side and the bottom side of the device, the overall stress level can be adjusted depending on the requirements of the remaining elements and the desired application of the SiC transistor device.

[0056] The foregoing description of embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Separate elements or features of a particular embodiment are generally not limited to that particular embodiment unless specifically recited therein, and the individual features can be mutually adapted or used in other embodiments, even if not specifically stated or described herein. It is intended to be within the scope of this disclosure. It also can be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.

Claims

1. A SiC transistor device, comprising: SiC semiconductor substrate (31), the SiC semiconductor substrate having a top surface and a bottom surface; A SiC epitaxial layer (32) is formed on the top surface of the SiC semiconductor substrate (31), the SiC epitaxial layer (32) having a top surface; A source structure (35) is formed in the top surface of the SiC epitaxial layer (32), the source structure (35) having a top surface; A source contact structure, wherein the source contact structure is electrically coupled to the top surface of the source structure (35); A gate structure comprising a gate oxide (36), a metal gate (37), and a gate insulating portion (40). A first back-side metal contact (39) on the bottom surface of the SiC semiconductor substrate (31). Its features are: A first stress-inducing layer (41) on the first back-side metal contact (39), wherein the first stress-inducing layer (41) is formed to induce tensile stress in the channel of the device, and the first stress-inducing layer (41) is structured. as well as A second back-side metal contact (42) on the structured first stress-inducing layer (41), wherein the first back-side metal contact (39) is in electrical contact with the second back-side metal contact (42).

2. The SiC transistor device according to claim 1, wherein, The second back-side metal contact (42) includes at least one of titanium (Ti), nickel (Ni), aluminum (Al) or silver (Ag).

3. The SiC transistor device according to any one of claims 1 or 2, further comprising: A second stress-induced layer (51) on the gate structure.

4. The SiC transistor device according to any one of claims 1 or 2, further comprising: A structured and electrically insulating second stress-induced layer (51) on the top surface of the SiC epitaxial layer (32).

5. The SiC transistor device according to claim 1 or 2, further comprising: A first contact layer, wherein the first contact layer is in electrical contact with the source contact structure; as well as The second contact layer is electrically connected to the metal gate (37).

6. The SiC transistor device according to claim 4, wherein, The source contact structure is electrically coupled to the top surface of the source structure (35) through a structured second stress-induced layer.

7. The SiC transistor device according to claim 5, wherein, The first contact layer and / or the second contact layer are at least partially covered by a passivation layer.

8. The SiC transistor device according to claim 1 or 2, wherein, The SiC semiconductor substrate (31) and the SiC epitaxial layer (32) are n-type 4H-SiC.

9. The SiC transistor device according to claim 3, wherein, The thickness of the first stress-inducing layer (41) and / or the thickness of the second stress-inducing layer (51) are in the range of 1 nm to 1000 nm.

10. The SiC transistor device according to claim 3, wherein, The first stress-inducing layer (41) and / or the second stress-inducing layer (51) comprise SiN.

11. The SiC transistor device according to claim 3, wherein, The first stress-inducing layer (41) and / or the second stress-inducing layer (51) comprise TiN.

12. The SiC transistor device according to claim 1 or 2, wherein, The first stress-inducing layer (41) induces tensile stress in the range of 500 MPa to 2000 MPa.

13. The SiC transistor device according to claim 3, wherein, The second stress-inducing layer (51) induces tensile stress in the range of 500 MPa to 2000 MPa, depending on the manufacturing process.

14. The SiC transistor device according to claim 1 or 2, wherein, The SiC transistor device is a metal-oxide-semiconductor field-effect transistor (MOSFET).

15. The SiC transistor device according to claim 1 or 2, wherein, The SiC transistor device is an insulated gate bipolar transistor (IGBT).

16. A method for manufacturing a SiC transistor device, comprising: A SiC semiconductor substrate is formed, the SiC semiconductor substrate having a top surface and a bottom surface; A SiC epitaxial layer is epitaxially formed on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface; A source structure is formed in the top surface of the SiC epitaxial layer, the source structure having a top surface; A source contact structure is formed, wherein the source contact structure is electrically coupled to the top surface of the source structure; A gate structure is formed on the top surface of the SiC epitaxial layer, wherein the gate structure includes a gate oxide and a metal gate. A first back-side metal contact is formed on the bottom surface of the SiC semiconductor substrate; A stress-inducing layer is formed on the first back-side metal contact; The stress-induced layer is structured; and A second back-side metal contact is formed on a structured stress-induced layer, wherein the first back-side metal contact is in electrical contact with the second back-side metal contact. The stress-inducing layer is formed to induce tensile stress in the channel of the device.

17. The method according to claim 16, wherein, The stress-inducing layer induces tensile stress in the range of 500 MPa to 2000 MPa.

18. A method for manufacturing a SiC transistor device, comprising: A SiC semiconductor substrate is formed, the SiC semiconductor substrate having a top surface and a bottom surface; A SiC epitaxial layer is epitaxially formed on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface; A source structure is formed in the top surface of the SiC epitaxial layer, the source structure having a top surface; A source contact structure is formed, wherein the source contact structure is electrically coupled to the top surface of the source structure; A gate structure is formed on the top surface of the SiC epitaxial layer, wherein the gate structure includes a metal gate; A first stress-induced layer is formed at the gate structure, extending and covering the surface of the gate structure; A first back-side metal contact is formed on the bottom surface of the SiC semiconductor substrate; A second stress-inducing layer is formed on the first back-side metal contact; The second stress-inducing layer is structured; and A second back-side metal contact is formed on a structured second stress-inducing layer, wherein the first back-side metal contact is in electrical contact with the second back-side metal contact. The first stress-inducing layer and the second stress-inducing layer are formed to induce tensile stress in the channel of the device.

19. The method according to claim 18, wherein, Both the first stress-inducing layer and the second stress-inducing layer induce tensile stress in the range of 500 MPa to 2000 MPa.

20. A method for manufacturing a SiC transistor device, comprising: A SiC semiconductor substrate is formed, the SiC semiconductor substrate having a top surface and a bottom surface; A SiC epitaxial layer is epitaxially formed on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface; A source structure is formed in the top surface of the SiC epitaxial layer, the source structure having a top surface; An electrically insulating first stress-induced layer is formed on the top surface of the SiC epitaxial layer; The first stress-inducing layer of the electrical insulation is structured; A source contact structure is formed, wherein the source contact structure is electrically coupled to the top surface of the source structure; A gate structure is formed on the top surface of the SiC epitaxial layer, wherein the gate structure includes a metal gate; A first back-side metal contact is formed on the bottom surface of the SiC semiconductor substrate; A second stress-inducing layer is formed on the first back-side metal contact; The second stress-inducing layer is structured; and A second back-side metal contact is formed on a structured second stress-inducing layer, wherein the first back-side metal contact is in electrical contact with the second back-side metal contact. The first stress-inducing layer and the second stress-inducing layer are formed to induce tensile stress in the channel of the device; and The first stress-induced layer is planarly formed on the top surface of the SiC epitaxial layer to serve as a gate dielectric.

21. The method according to claim 20, wherein, Both the first stress-inducing layer and the second stress-inducing layer induce tensile stress in the range of 500 MPa to 2000 MPa.

Images