A heterogeneous many-core architecture cpu shared array steering selection strategy

Abstract

The application discloses a CPU shared array guide dimension selection method on a heterogeneous many-core architecture, which adjusts a matrix guide dimension as follows and stores it in a CPU shared space: S1, when applying for the CPU shared space, the first address of the applied space, namely, src 128B, is controlled to be pair boundary, so that the source address is always 128B pair boundary when taking data from a core DMA; S2, ld=64*(6a+1) is selected, a is the minimum integer value satisfying 64*(6a+1)>=N, so that the storage control utilization is the highest when accessing the memory from the core DMA, and the DMA stride satisfies the 128B pair boundary; S3, if ld%31==0 is obtained in S2, a=a+1 is taken, so that the body conflict problem is avoided; S4, a M*N double-precision matrix is stored in the CPU shared space with the ld obtained in S3 as the guide dimension and with src as the first address in the row-major order. The application balances the memory access amount on each storage control when taking data from the core DMA, realizes load balancing, and avoids the storage control body conflict.

Description

Technical Field

[0001] This invention relates to a CPU shared array bootstrapping dimension selection strategy on a heterogeneous many-core architecture, belonging to the field of high-performance computing technology. Background Technology

[0002] The most prominent advantage of heterogeneous many-core processors is their high performance, making them particularly suitable for high-performance computing. They are primarily used in large-scale practical systems such as ultra-large-scale parallel machines. However, they also suffer from limited memory access bandwidth. In scientific computing, matrix operations are a common tool. In supercomputing based on heterogeneous many-core processors, during matrix operations, slave cores typically need to use step-wise DMA to achieve batch data exchange between the LDM and the chip's shared memory space. However, an inappropriate step size can significantly reduce memory access performance, which becomes a bottleneck limiting the performance of heterogeneous many-core processors.

[0003] Matrix operations, due to their massive computational demands and long processing times, are often performed using parallel algorithms to improve efficiency. Simultaneously, to reduce communication, some data is placed in shared memory. On heterogeneous many-core processors, parallelism is achieved by dividing the matrix into blocks and distributing them to various slave cores for computation. Data in the chip's shared memory space can be shared across the entire processor; placing data in the shared memory space reduces communication. Slave cores often use step-based DMA to achieve batch exchange of matrix data between the LDM and the chip's shared memory space to obtain the required matrix blocks. The choice of step size affects the utilization of each memory controller, and an inappropriate step size can lead to volume conflicts, significantly impacting memory access performance. The step size is determined by both the matrix block size and the matrix bootstrap dimension.

[0004] The disadvantages of existing technologies are: 1. The addressing method of the chip's shared address space leads to an imbalance in the amount of memory accessed by each memory controller due to the step characteristics; 2. When two memory access addresses meet specific conditions, a volume conflict will occur; 3. Inappropriate DMA parameters, such as source address or step not being aligned to the 128B boundary, will lead to performance degradation.

[0005] The heterogeneous many-core chip integrates multiple core groups, each including one general-purpose master core, a memory controller, a protocol processing unit, and an 8x8 slave core array. Main memory uses virtual addresses, divided into core group private space and core group shared space. The addressing method for the shared space is shown in the attached figure. Figure 2 As shown, taking a chip with four core groups as an example, the shared address space is managed by different core groups based on the remainder when divided by 2048. In the example, remainders of 0-511 are managed by core group 0; remainders of 512-1023 by core group 1; remainders of 1024-1535 by core group 2; and remainders of 1536-2047 by core group 3. The more memory controllers used during memory access, the more efficient the bandwidth utilization.

[0006] Step mod (512 * 4) Storage control utilization data 0 4 512 2 1024 4 1536 1

[0007] For convenience, consider the case where the step size is 512B. When the remainder when the step size is divided by 2048 is 1536, all memory access processes utilize only one memory controller. When the step size is divisible by 2048, the memory access process utilizes all four memory controllers. In these two cases, the memory access bandwidth will differ by nearly four times.

[0008] The number of core groups will vary on different heterogeneous many-core chips, but a similar derivation can be made using the example above. Let's notate as follows: Denote the shared space address as k units, managed by different core groups; denote the number of core groups as n. When considering DMA, the chip's shared space addressing is similar. Figure 1 With memory access starting from 0, the data volume being large enough, and the vector block size being k bytes, an ideal scenario is that the step is divisible by (k * n) in order to utilize all memory control as much as possible.

[0009] The most crucial component in DRAM is the memory array, which is an array (2M rows × 2N columns) composed of basic dynamic memory cells. Due to physical implementation considerations, large-capacity memories cannot be implemented using a single super-large array; instead, multiple smaller arrays are used. Such an array is called a bank. DDR3 chips have 8 banks, while DDR4 chips have 8 or 16 banks. Furthermore, compared to previous DDR memories, DDR4 adds a bank group (bg) structure above the bank level, with 4 banks forming one bg. Bank groups primarily affect memory access timing parameters; the command latency within a group uses one parameter (the larger one), while the command latency between groups uses another timing parameter. (Appendix) Figure 3 This is a schematic diagram of a storage array.

[0010] DDR4 addresses are divided into row address (ROW), column address (COL), and bank address (BANK). The bank address is further divided into bankgroup address (BG) and bank address (BA) within the bank group. Considering two consecutive memory accesses, the memory controller uses a certain mapping... When physical addresses are translated to DDR4 addresses, if the two mapped DDR4 addresses are on different rows within the same entity, memory access operations cannot be parallelized and must be performed serially, leading to a decrease in memory access performance, a phenomenon known as a body conflict. In the above problem scenario, when the row-major matrix guiding dimension is a multiple of 31, DMA access to a certain block of the matrix will generate a body conflict, causing performance degradation. Summary of the Invention

[0011] The purpose of this invention is to provide a CPU shared array bootstrap dimension selection strategy on a heterogeneous many-core architecture, so as to achieve optimal performance when retrieving matrix block data from the core DMA.

[0012] To achieve the above objectives, the technical solution adopted by the present invention is: to provide a CPU shared array bootstrap dimension selection strategy on a heterogeneous many-core architecture, for a double-precision matrix of size M×N, N%64 == 0, M%m == 0, row-major order, bootstrap dimension ld, and block size m×64;

[0013] mark meaning k=512 The chip's shared address space is measured in kilobytes and is managed by different memory controllers. n=6 Number of core groups stride=(ld-64)*8B DMA step size, in bytes block=64 * 8B DMA step vector block size, in bytes src Matrix starting address disp The offset of the source address relative to the first address of the matrix during DMA, in bytes. ld The matrix guide dimension is expressed in terms of the number of matrix elements. ;

[0015] After adjusting the matrix bootstrap dimension as follows, the matrix is ​​stored in a specified address in the CPU shared memory based on the adjusted bootstrap dimension parameters, for use by the slave core's DMA memory access:

[0016] S1. When requesting CPU shared space, control the starting address of the requested space, i.e., src, to be aligned to the boundary 128B, so that the source address is always aligned to the boundary 128B when fetching from the core DMA.

[0017] S2. Select ld = 64 * (6a+1), where a is the smallest integer value that satisfies 64 * (6a+1)>= N, so that the memory control utilization is the highest and the DMA step size satisfies the 128B limit when accessing memory from the core DMA.

[0018] S3. If ld%31==0 obtained in S2, take a=a+1 so that the body conflict problem is avoided.

[0019] S4 is an M×N double-precision matrix, row-major, with ld obtained from S3 as the bootstrap dimension and src as the starting address, stored in the CPU shared space.

[0020] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art:

[0021] This invention proposes a bootstrap dimension selection strategy for processors with heterogeneous many-core architectures. By adjusting the bootstrap dimension of the matrix, the memory access volume on each memory controller is balanced when retrieving data from the core DMA, thus achieving load balancing and avoiding memory controller conflicts. At the same time, the DMA parameters are optimized so that the DMA memory access to the chip's shared space array can reach the theoretical bandwidth, thereby reducing the waiting time for retrieving matrix block data from the core and improving computational efficiency. Attached Figure Description

[0022] Appendix Figure 1 This is a schematic diagram of DMA read / write operations with step-by-step navigation to main memory;

[0023] Appendix Figure 2Example diagram of quad-core chip - shared space addressing method;

[0024] Appendix Figure 3 This is a schematic diagram of a storage array;

[0025] Appendix Figure 4 This is a schematic diagram of matrix data transmission. Detailed Implementation

[0026] Example: This invention provides a CPU shared array bootstrap dimension selection strategy on a heterogeneous many-core architecture. For a double-precision matrix of size M×N, N%64 == 0, M%m == 0, row-major order (the matrix is ​​stored in the form of a one-dimensional array), bootstrap dimension is ld, and block size is m×64.

[0027] mark meaning k=512 The chip's shared address space is measured in kilobytes and is managed by different memory controllers. n=6 Number of core groups stride=(ld-64)*8B DMA step size, in bytes block=64 * 8B DMA step vector block size, in bytes src Matrix starting address disp The offset of the source address relative to the first address of the matrix during DMA, in bytes. ld The matrix guide dimension is expressed in terms of the number of matrix elements. ;

[0029] After adjusting the matrix bootstrap dimension as follows, the matrix is ​​stored in a specified address in the CPU shared memory based on the adjusted bootstrap dimension parameters, for use by the slave core's DMA memory access:

[0030] S1. When requesting CPU shared space, control the starting address of the requested space, i.e., src, to be aligned to the boundary 128B. At this time, since the block size is 64, the source address is always aligned to the boundary 128B when fetching from the core DMA.

[0031] S2. In order to improve memory control utilization, ld = 64 * (6a+1) is selected, where a is the smallest integer value that satisfies 64 * (6a+1)>= N, so that memory control utilization is maximized when accessing memory from the core DMA and the DMA step size satisfies the 128B limit.

[0032] S3. To avoid body conflict, if ld%31==0 obtained in S2, take a=a+1, so that the body conflict problem is avoided.

[0033] S4 is an M×N double-precision matrix, row-major, with ld obtained from S3 as the bootstrap dimension and src as the starting address, stored in the CPU shared space.

[0034] Further explanation of the above embodiments is as follows:

[0035] The actual problem scenario is as follows: the size of the double-precision matrix is ​​MxN, N%64 == 0, M%m == 0, row-major order (the matrix is ​​stored in the form of a one-dimensional array), the guiding dimension is ld, and the block size is mx64; during the operation, a certain block is obtained from the core for DMA each time.

[0036] mark meaning k=512 The chip's shared address space is measured in kilobytes and is managed by different memory controllers. n=6 Number of core groups stride=(ld-64)*8B DMA step size, in bytes block=64 * 8B DMA step vector block size, in bytes src Matrix starting address disp The offset of the source address relative to the first address of the matrix during DMA, in bytes. ld The matrix guide dimension is expressed in terms of the number of matrix elements.

[0037] The relevant hardware requirements are as follows:

[0038] 1. Heterogeneous many-core chips: Each CPU contains 6 core groups, and the CPU shared space is in units of 512B, managed by different memory controllers.

[0039] 2. When fetching from the core DMA, the performance is optimal when the source address and destination address are aligned to a 128-byte boundary and the step size is a multiple of 128 bytes.

[0040] 3. In the above-mentioned problem scenarios, when the guiding dimension of the row-major matrix is ​​a multiple of 31, DMA fetching of a certain block of the matrix will cause volume conflicts, resulting in performance degradation.

[0041] As shown in the attached diagram Figure 4 .

[0042] After adjusting the matrix bootstrap dimension as follows, the matrix is ​​stored in a specified address in the CPU shared memory based on the adjusted bootstrap dimension parameters, for use by the slave core's DMA memory access:

[0043] 1. When requesting CPU shared space, control the starting address of the requested space, i.e., src, to be aligned to the 128B boundary, so that the source address is always aligned to the 128B boundary when fetching from the core DMA.

[0044] 2. Select ld = 64 * (6a+1), where a is the smallest integer value that satisfies 64 * (6a+1)>= N, so that the memory control utilization is maximized when accessing memory from the core DMA and the DMA step size satisfies the 128B limit.

[0045] 3. If ld%31 obtained in step 2 is 0, then take a = a + 1 to avoid the volume conflict problem;

[0046] 4. An M×N double-precision matrix, row-major, with ld obtained in S3 as the bootstrap dimension and src as the starting address, stored in the CPU shared space.

[0047] At this point, the optimal performance is achieved by retrieving a specific block of the matrix from the core using DMA each time.

[0048] When adopting the above-mentioned boot dimension selection strategy for CPU shared array on heterogeneous many-core architecture, a boot dimension selection strategy suitable for processors on heterogeneous many-core architecture is proposed. By adjusting the boot dimension length, the memory access volume on each memory controller is balanced to achieve load balancing and avoid memory controller conflicts. At the same time, DMA parameters are optimized so that DMA memory access to the chip shared space array can reach the theoretical bandwidth.

[0049] To facilitate a better understanding of this invention, the terms used herein will be briefly explained below:

[0050] Heterogeneous many-core chip: A high-performance heterogeneous central processing unit that integrates a small number of general-purpose master cores that perform management, communication and computing functions and a large number of simplified slave cores that perform computing functions on a single chip; a chip integrates multiple core groups, each core group including one general-purpose master core, a memory controller, a protocol processing unit and an 8x8 slave core array; the general-purpose master core runs a general-purpose operating system and is mainly responsible for the management and control functions of the entire chip, as well as some computing functions and communication functions between the chip and the outside world; the slave cores play a role in accelerating computing.

[0051] Chip shared space: On heterogeneous many-core chips, the main memory address space uses virtual addresses, divided into core group private space and core group shared space; between different core groups, the same private space address is mapped to different memory spaces, and the same shared space address is mapped to the same memory space.

[0052] Guided dimension: The size of the first dimension of a matrix when it is actually stored in memory. When stored in column-major order, it is the number of rows in the matrix; when stored in row-major order, it is the number of columns in the matrix.

[0053] LDM (Local Data Memory): Local storage space for slave cores on heterogeneous many-core chips.

[0054] From the kernel DMA (Direct Memory Access): The DMA mechanism enables batch data exchange between LDM and main memory; DMA has the following key parameters: DMA behavior, source address and destination address of data, vector block size (unit: bytes), step size (unit: bytes), data volume (unit: bytes), etc. Figure 1 simply describes DMA read and write to main memory with step.

[0055] Padding: Pads the boundaries of a matrix by adding values ​​to the matrix's boundaries to increase its size.

[0056] Bank conflict: A bank refers to a shared memory module that is divided into several storage modules of a fixed size. If two addresses requested by a memory fall into the same storage bank, a bank conflict will occur.

[0057] DRAM (Dynamic Random Access Memory): Dynamic random access memory.

[0058] DDR: short for Double Data-Rate Synchronous DRAM, which doubles the speed of DRAM by using two clock edges as control signals.

[0059] PA (Physical Address): Physical address.

[0060] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method for selecting the bootstrap dimension of a CPU shared array on a heterogeneous many-core architecture, characterized in that: For a double-precision matrix of size M×N, N%64 == 0, M%m == 0, row-major order, guiding dimension ld, and block size m×64; During computation, a specific block of computation is retrieved from the core via DMA each time, and the meanings of the markings are agreed upon as follows: k=512 means that the chip's shared address space is in units of k bytes and is managed by different memory controllers; n=6, meaning the number of core groups; stride=(ld-64)*8B, which means the stride size during DMA, in bytes; block=64 * 8B means the size of the step vector block during DMA, in bytes; src means the starting address of the matrix; disp means the offset of the source address relative to the first address of the matrix during DMA, in bytes; ld means the size of the matrix guiding dimension, and the unit is the number of matrix elements; After adjusting the matrix bootstrap dimension as follows, the matrix is ​​stored in a specified address in the CPU shared memory based on the adjusted bootstrap dimension parameters, for use by the slave core's DMA memory access: S1. When requesting CPU shared space, control the starting address of the requested space, i.e., src, to be aligned to the boundary 128B, so that the source address is always aligned to the boundary 128B when fetching from the core DMA. S2. Select ld = 64 * (6a+1), where a is the smallest integer value that satisfies 64 * (6a+1) >= N, so that the memory control utilization is the highest and the DMA step size satisfies the 128B limit when accessing memory from the core DMA. S3. If ld%31==0 obtained in S2, take a=a+1 so that the body conflict problem is avoided. S4 is an M×N double-precision matrix, row-major, with ld obtained from S3 as the bootstrap dimension and src as the starting address, stored in the CPU shared space.

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