Integrated Circuit Simulation Design Method and Device, Computing Device, and Storage Medium

Abstract

The present invention discloses an integrated circuit simulation design method and apparatus, a computing device, and a storage medium. The integrated circuit simulation design method according to an embodiment of the present invention includes using an original S-parameter matrix to represent a port network; performing reduction processing on the original S-parameter matrix to obtain a reduced S-parameter matrix; performing simulation design according to the reduced S-parameter matrix, wherein the reduction processing includes obtaining the reduced S-parameter matrix according to the original S-parameter matrix and reduced ports, and the reduced ports include at least one of a short-circuited port, a floating port, and a grounded port. The integrated circuit simulation design method and apparatus, the computing device, and the storage medium according to an embodiment of the present invention can reduce the scale of the S-parameter matrix, reduce the amount of computation and storage, and improve work efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit simulation, and particularly relates to an integrated circuit simulation design method and device, a computing device, and a storage medium. Background Art

[0002] The S-parameter is a model characterizing network characteristics. In high-frequency simulation, the S-parameter matrix is commonly used to represent the port network, and it has wide applications in the fields of radio frequency, microwave, and signal integrity. The S-parameter is the abbreviation of scattering parameter, which is the ratio of the scattered voltage to the incident voltage wave entering the device under test (DUT), and it reflects the signal relationship between each port in the circuit.

[0003] In the prior art, the S-parameter matrix is obtained from the S-parameters arranged according to the incident and detection port orders. For example, Sij represents that the incident port is j and the detection port is i. i = j represents reflection, and i ≠ j represents transmission. Therefore, for an n-port network, there are n×n parameter values. In the case of a large number of ports, the scale of the S-parameter matrix is very large, and subsequent operations need to face the processing of large matrices, occupying a large amount of time and space for operations.

[0004] Therefore, it is desirable to have a new integrated circuit simulation design method and device, a computing device, and a storage medium that can overcome the above problems. Summary of the Invention

[0005] In view of the above problems, the purpose of the present invention is to provide an integrated circuit simulation design method and device, a computing device, and a storage medium, so as to reduce the scale of the S-parameter matrix, reduce the amount of computation and storage, and improve work efficiency.

[0006] According to one aspect of the present invention, there is provided an integrated circuit simulation design method, including using an original S-parameter matrix to represent a port network; performing reduction processing on the original S-parameter matrix to obtain a reduced S-parameter matrix; and performing simulation design according to the reduced S-parameter matrix, wherein the reduction processing includes obtaining the reduced S-parameter matrix according to the original S-parameter matrix and reduced ports, and the reduced ports include at least one of a short-circuited port, a floating port, and a grounded port.

[0007] Preferably, obtaining the reduced S-parameter matrix according to the original S-parameter matrix and reduced ports includes converting the original S-parameter matrix into admittance parameters or impedance parameters; reducing the admittance parameters or the impedance parameters to obtain an intermediate parameter matrix; and converting the intermediate parameter matrix into the reduced S-parameter matrix.

[0008] Preferably, the use of the original S-parameter matrix to represent the port network includes reading a multi-port snp file and converting the multi-port snp file into the original S-parameter matrix; the integrated circuit simulation design method further includes converting the reduced S-parameter matrix into an snp file.

[0009] Preferably, the reduced port is a short-circuited port; obtaining the reduced S-parameter matrix according to the original S-parameter matrix and the reduced port includes converting the original S-parameter matrix into an admittance parameter matrix; obtaining the port network relationship regarding the admittance parameter and obtaining the expansion matrix regarding the admittance parameter; combining the short-circuited ports, reducing the expansion matrix regarding the admittance parameter to obtain a reduced admittance parameter matrix; and converting the reduced admittance parameter matrix into the reduced S-parameter matrix.

[0010] Preferably, the reduced port is a floating port; obtaining the reduced S-parameter matrix according to the original S-parameter matrix and the reduced port includes converting the original S-parameter matrix into an admittance parameter matrix; obtaining the port network relationship regarding the admittance parameter and obtaining the expansion matrix regarding the admittance parameter; deleting the floating port, reducing the expansion matrix regarding the admittance parameter to obtain a reduced admittance parameter matrix; and converting the reduced admittance parameter matrix into the reduced S-parameter matrix.

[0011] Preferably, there are multiple floating ports; in the expansion matrix regarding the admittance parameter, the multiple floating ports are rearranged, the floating ports are arranged in ascending order at the back of the matrix, and the remaining ports are arranged in ascending order at the front of the matrix.

[0012] Preferably, the reduced port is a grounded port; obtaining the reduced S-parameter matrix according to the original S-parameter matrix and the reduced port includes converting the original S-parameter matrix into an impedance parameter matrix; obtaining the port network relationship regarding the impedance parameter and obtaining the expansion matrix regarding the impedance parameter; deleting the grounded port, reducing the expansion matrix regarding the impedance parameter to obtain a reduced impedance parameter matrix; and converting the reduced impedance parameter matrix into the reduced S-parameter matrix.

[0013] Preferably, there are multiple grounded ports; in the expansion matrix regarding the impedance parameter, the multiple grounded ports are rearranged, the grounded ports are arranged in ascending order at the back of the matrix, and the remaining ports are arranged in ascending order at the front of the matrix.

[0014] Preferably, the reduced ports include at least one of the ground port, the short - circuit port, and the floating port; obtaining the reduced S - parameter matrix according to the original S - parameter matrix and the reduced ports includes converting the original S - parameter matrix into an admittance - parameter matrix; combining the short - circuit port and / or deleting the floating port, reducing the expansion matrix of the admittance parameters to obtain a reduced admittance - parameter matrix; converting the reduced admittance - parameter matrix into an impedance - parameter matrix; deleting the ground port, reducing the expansion matrix of the impedance parameters to obtain a reduced impedance - parameter matrix; and converting the reduced impedance - parameter matrix into a reduced S - parameter matrix.

[0015] Preferably, the reduced ports include a short - circuit port and a floating port: obtaining the reduced S - parameter matrix according to the original S - parameter matrix and the reduced ports includes obtaining the number of ports of the short - circuit port; obtaining the number of ports of the floating port; comparing the number of ports of the short - circuit port and the number of ports of the floating port; and when the number of ports of the short - circuit port is greater than or equal to the number of ports of the floating port, reducing the short - circuit port first and then the floating port; when the number of ports of the short - circuit port is less than the number of ports of the floating port, reducing the floating port first and then the short - circuit port.

[0016] According to another aspect of the present invention, there is provided an integrated - circuit simulation design device, including an acquisition module for acquiring a port network represented by an original S - parameter matrix; a reduction module for performing a reduction process on the original S - parameter matrix to obtain a reduced S - parameter matrix; and a simulation module for performing a simulation design according to the reduced S - parameter matrix, wherein the reduction module obtains the reduced S - parameter matrix according to the original S - parameter matrix and the reduced ports; the reduced ports include at least one of a short - circuit port, a floating port, and a ground port.

[0017] Preferably, the reduction module includes a conversion unit for converting the original S - parameter matrix into an admittance parameter or an impedance parameter; and a reduction unit for reducing the admittance parameter or the impedance parameter to obtain an intermediate parameter matrix, wherein the conversion unit is further used to convert the intermediate parameter matrix into the reduced S - parameter matrix.

[0018] Preferably, the reduction unit includes a sorting sub - unit for rearranging a plurality of floating ports when there are multiple floating ports, arranging the floating ports in ascending order behind the matrix, and arranging the remaining ports in ascending order in front of the matrix; and / or for rearranging a plurality of ground ports when there are multiple ground ports, arranging the ground ports in ascending order behind the matrix, and arranging the remaining ports in ascending order in front of the matrix.

[0019] Preferably, the reduction module includes a judgment unit configured to judge whether the reduction ports include the ground port and / or the short - circuit port and / or the floating port. Wherein, when at least one of the ground port, the short - circuit port and the floating port exists simultaneously, the reduction module first reduces the short - circuit port and / or the floating port, and then reduces the ground port.

[0020] Preferably, the reduction module includes a comparison unit configured to compare the number of ports of the short - circuit port and the number of ports of the floating port. Wherein, when the number of ports of the short - circuit port is greater than or equal to the number of ports of the floating port, the reduction module first reduces the short - circuit port and then reduces the floating port; when the number of ports of the short - circuit port is less than the number of ports of the floating port, the reduction module first reduces the floating port and then reduces the short - circuit port.

[0021] According to another aspect of the present invention, there is provided a computing device, including a processor; a memory for storing one or more programs, wherein when the one or more programs are executed by the processor, the processor implements the integrated circuit simulation design method as described above.

[0022] According to still another aspect of the present invention, there is provided a computer - readable storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the integrated circuit simulation design method as described above is implemented.

[0023] The integrated circuit simulation design method, device, computing device and storage medium according to the embodiments of the present invention can obtain a reduced S - parameter matrix according to the original S - parameter matrix and the reduction ports, thereby reducing the scale of the S - parameter matrix, reducing the amount of computation and storage, and improving work efficiency.

[0024] The integrated circuit simulation design method, device, computing device and storage medium according to the embodiments of the present invention convert the original S - parameter matrix into admittance parameters or impedance parameters, then reduce the admittance parameters or impedance parameters to obtain an intermediate parameter matrix, and convert the intermediate parameter matrix into a reduced S - parameter matrix. The reduced S - parameter matrix can maintain the functional characteristics of the original S - parameter matrix without affecting subsequent simulation work.

[0025] The integrated circuit simulation design method, device, computing device and storage medium according to the embodiments of the present invention perform sorting processing on the floating ports and the ground ports when there are multiple floating ports and ground ports, and the reduction method is simple and efficient.

[0026] The integrated circuit simulation design method, device, computing device and storage medium according to the embodiments of the present invention directly read the snp file and convert the snp file into the original S - parameter matrix, and the method is simple and efficient.

[0027] An integrated circuit simulation design method, device, computing device, and storage medium according to an embodiment of the present invention, when there are both short - circuit interfaces and floating ports, compare the number of ports of the short - circuit interfaces and the floating ports, first reduce the one with more port numbers, and then reduce the one with fewer port numbers, thereby reducing the computational amount of reduction. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above - mentioned and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0029] Figure 1 Shows a flowchart of a method for integrated circuit simulation design according to an embodiment of the present invention;

[0030] Figure 2 Shows a flowchart of a method for integrated circuit simulation design with partial port short - circuit according to an embodiment of the present invention;

[0031] Figure 3 Shows a flowchart of a method for integrated circuit simulation design with partial port floating according to an embodiment of the present invention;

[0032] Figure 4 Shows a flowchart of a method for integrated circuit simulation design with partial port grounding according to an embodiment of the present invention;

[0033] Figure 5 Shows a flowchart of a method for integrated circuit simulation design according to an embodiment of the present invention;

[0034] Figure 6 Shows a flowchart of a method for integrated circuit simulation design according to an embodiment of the present invention;

[0035] Figure 7 Shows a flowchart of a method for integrated circuit simulation design according to an embodiment of the present invention;

[0036] Figure 8 Shows a schematic structural diagram of an integrated circuit simulation design device according to an embodiment of the present invention;

[0037] Figure 9 Shows a schematic structural diagram of a computing device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] The various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are denoted by the same or similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well - known parts may not be shown in the figures.

[0039] The specific embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Many specific details of the present invention are described below, such as the structure, materials, dimensions, processing techniques and technologies of components, in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention can be implemented without these specific details.

[0040] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "above" or "over" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the component is flipped, this layer or region will be "below" or "beneath" the other layer or region.

[0041] The inventors found that in the prior art, S-parameters are usually stored in the format of an snp file, where n represents the number of ports of the network. For example, for a two-port network, an S-parameter file in the s2p file format is obtained. The existing number of ports is usually very large, and the scale of the S-parameter matrix is extremely large. Subsequent operations will face the processing of large matrices, and the time and space occupied by the operations will double. But in fact, most of the time not all ports are used. Some ports are floating or grounded, or short-circuited to other ports, and these ports that are not really used will cause waste, and the large-sized S-parameter matrix will affect the efficiency of the simulation work.

[0042] To solve the above problems, the inventors proposed a new integrated circuit simulation design method and device. More specifically, it is a method and device for reducing the S-parameter matrix in the case where some ports are grounded, floating, and short-circuited.

[0043] Figure 1 The method flow chart of the integrated circuit simulation design method according to an embodiment of the present invention is shown. As Figure 1 shown, the integrated circuit simulation design method according to an embodiment of the present invention includes the following steps:

[0044] In step S101, an original S-parameter matrix is used to represent the port network;

[0045] An original S-parameter matrix is used to represent the port network. Optionally, an snp file is read to obtain (acquire) the original S-parameter matrix. Optionally, a multi-port snp file is read and converted into an original S-parameter matrix.

[0046] In step S102, the original S-parameter matrix is reduced to obtain a reduced S-parameter matrix;

[0047] Reduce the original S-parameter matrix to obtain a reduced S-parameter matrix. Specifically, obtain the reduced S-parameter matrix according to the original S-parameter matrix and the reduced ports, where the reduced ports include at least one of a short-circuited port, a floating port, and a grounded port.

[0048] In step S103, perform simulation design according to the reduced S-parameter matrix.

[0049] Perform integrated circuit simulation settings according to the reduced S-parameter matrix. Optionally, convert the reduced S-parameter matrix into an snp file and perform simulation design.

[0050] In an alternative embodiment of the present invention, obtaining the reduced S-parameter matrix according to the original S-parameter matrix and the reduced ports includes: converting the original S-parameter matrix into admittance parameters (Y-parameters) or impedance parameters (Z-parameters); reducing the admittance parameters or impedance parameters to obtain an intermediate parameter matrix; and converting the intermediate parameter matrix into a reduced S-parameter matrix. Optionally, convert the original S-parameter matrix into a Y-parameter matrix or a Z-parameter matrix to obtain the network relationship I = Y∙U or U = Z∙I, perform operations and transformations (i.e., reduction work) on the original Y or Z parameter matrix according to the corresponding voltage or current conditions to obtain a new Y-parameter matrix or Z-parameter matrix (i.e., the intermediate parameter matrix), and then convert it (the intermediate parameter matrix) back into an S-parameter matrix to obtain the reduced S-parameter matrix.

[0051] According to the integrated circuit simulation design method of the embodiments of the present invention, directly process the snp file, reduce the redundant ports of floating, grounding, or short-circuiting, and perform reduction operations after converting the S-parameter matrix into a Y or Z parameter matrix for the three different cases of floating, grounding, or short-circuiting, so as to reduce the number of S-parameter ports and thus reduce the scale of the S-parameter matrix, and the reduced S-parameter matrix can maintain the functional characteristics of the original S-parameter matrix without affecting subsequent simulation work.

[0052] Figure 2 The flowchart of the integrated circuit simulation design method with partial port short-circuiting according to the embodiments of the present invention is shown. In the case where the reduced port is a short-circuited port (the short-circuited port can be one or more), the integrated circuit simulation design method includes the following steps:

[0053] In step S201, convert the original S-parameter matrix into an admittance parameter matrix;

[0054] Convert the original S-parameter matrix into an admittance parameter (Y-parameter) matrix. The conversion formula is as shown in formula (1):

[0055] Formula (1)

[0056] Among them, Y is the admittance parameter matrix; Z0 is the port characteristic impedance (it is assumed that the characteristic impedances are all equal); I is the current; S is the original S-parameter matrix.

[0057] In step S202, the port network relationship regarding the admittance parameters is obtained, and the expansion matrix regarding the admittance parameters is obtained;

[0058] After conversion, the n-port network relationship is obtained. The port network relationship is shown in formula (2):

[0059] Formula (2)

[0060] Among them, I is the current; U is the voltage; Y is the admittance parameter matrix.

[0061] The expansion matrix gives formula (3):

[0062] Formula (3)

[0063] In step S203, the shorted ports are merged, and the expansion matrix regarding the admittance parameters is reduced to obtain the reduced admittance parameter matrix;

[0064] The shorted ports are merged, and the expansion matrix regarding the admittance parameters is reduced to obtain the reduced admittance parameter matrix.

[0065] In a specific embodiment, it is assumed that ports i and j are shorted and merged into a new port m, then the current and voltage relationships are as shown in formulas (4) and (5).

[0066] U m =U i =U j Formula (4)

[0067] I m =I i =I j Formula (5)

[0068] The transformation is to first add the i-th and j-th columns of the Y matrix to obtain formula (6):

[0069]

[0070] Formula (6)

[0071]

[0072]

[0073] Then add the i-th and j-th rows of the Y matrix to obtain formula (7):

[0074]

[0075]

[0076] Formula (7)

[0077]

[0078]

[0079] Then the original n - order Y matrix becomes a new (reduced) matrix of order n - 1 (reduced admittance parameter matrix), that is, Formula (8):

[0080] Formula (8)

[0081] In step S204, convert the reduced admittance parameter matrix into a reduced S - parameter matrix;

[0082] Convert the reduced admittance parameter matrix into a reduced S - parameter matrix. The reduced S - parameter matrix is obtained according to Formula (9).

[0083] Formula (9)

[0084] Where S is the reduced S - parameter matrix; I is the current; Y is the reduced admittance parameter matrix; Z0 is the characteristic impedance.

[0085] Figure 3 The method flow chart of the integrated circuit simulation design method with some ports floating according to the embodiment of the present invention is shown. In the case where the reduced ports are floating ports (the floating ports can be one or more), the integrated circuit simulation design method includes the following steps:

[0086] In step S301, convert the original S - parameter matrix into an admittance parameter matrix;

[0087] Convert the original S - parameter matrix into an admittance parameter (Y - parameter) matrix. For example, convert it according to the above - mentioned Formula (1).

[0088] In step S302, obtain the port network relationship regarding the admittance parameter and obtain the expansion matrix regarding the admittance parameter;

[0089] Obtain the port network relationship regarding the admittance parameter and obtain the expansion matrix regarding the admittance parameter. Optionally, the port network relationship is as shown in the above - mentioned Formula (2). Among them, the current corresponding to the floating port is 0, but the voltage is not necessarily 0.

[0090] In a specific embodiment, there are multiple floating ports (for example, n - i ports). In the expansion matrix regarding admittance parameters, the multiple floating ports are rearranged. The floating ports are arranged in ascending order at the back of the matrix, and the remaining ports are arranged in ascending order at the front of the matrix (for example, if the original matrix has 8 ports and the original row arrangement order is 12345678; ports 3 and 5 are floating ports, then the row order after rearrangement becomes 12467835), and formula (10) is obtained.

[0091] Formula (10)

[0092] Wherein, I is the current; U is the voltage; ports 1 to port i are non - floating terminals; ports j to port n are floating terminals; j = i + 1.

[0093] In step S303, the floating ports are deleted, and the expansion matrix regarding admittance parameters is reduced to obtain the reduced admittance parameter matrix.

[0094] By deleting the floating ports and reducing the expansion matrix regarding admittance parameters, the reduced admittance parameter matrix is obtained. Specifically, in the above formula (10), I i and U i are respectively the i - order current and voltage column vectors corresponding to the i non - floating ports, and then formulas (11), (12), and (13) can be obtained.

[0095] Formula (11)

[0096] Formula (12)

[0097] Formula (13)

[0098] Through the above operations, the reduced admittance parameter matrix is obtained, that is, a new i - order matrix Y after deleting multiple (n - i) floating ports is obtained i .

[0099] In step S304, the reduced admittance parameter matrix is converted into a reduced S - parameter matrix.

[0100] The reduced admittance parameter matrix is converted into a reduced S - parameter matrix. For example, the reduced S - parameter matrix is obtained according to the above formula (9).

[0101] Figure 4 The flowchart of the integrated circuit simulation design method with some ports grounded according to an embodiment of the present invention is shown. In the case where the reduced ports are grounded ports (the grounded ports can be one or more), the integrated circuit simulation design method includes the following steps:

[0102] In step S401, the original S-parameter matrix is converted into an impedance parameter matrix;

[0103] The original S-parameter matrix is converted into an impedance parameter (Z-parameter) matrix. The conversion formula is shown in formula (14).

[0104] Formula (14)

[0105] Where Z is the impedance parameter matrix; Z0 is the characteristic impedance; I is the current; S is the original S-parameter matrix.

[0106] In step S402, the port network relationship regarding the impedance parameters is obtained, and the expansion matrix regarding the impedance parameters is obtained;

[0107] The port network relationship regarding the impedance parameters is obtained, and the expansion matrix regarding the impedance parameters is obtained.

[0108] After conversion, the n-port network relationship is obtained. The port network relationship is shown in formula (15):

[0109] Formula (15)

[0110] Where U is the voltage; I is the current; Z is the impedance parameter matrix.

[0111] The expansion matrix results in formula (16):

[0112] Formula (16)

[0113] Where the voltage corresponding to the grounded port is 0.

[0114] In a specific embodiment, there are multiple grounded ports (for example, i - r). In the expansion matrix regarding the impedance parameters, the multiple grounded ports are rearranged, with the grounded ports arranged in ascending order at the back of the matrix, and the remaining ports arranged in ascending order at the front of the matrix (for example, if the original matrix has 8 ports and the original row arrangement order is 12345678; ports 3 and 5 are the grounded ports, then the row arrangement order after rearrangement becomes 12467835), resulting in formula (17).

[0115] Formula (17)

[0116] Where ports 1 to r are non-grounded terminals; ports t to i are grounded terminals; t = r + 1.

[0117] In step S403, the grounded ports are deleted, and the expansion matrix regarding the impedance parameters is reduced to obtain the reduced impedance parameter matrix.

[0118] Delete the grounding ports, reduce the expansion matrix of the impedance parameters, and obtain the reduced impedance parameter matrix. Specifically, I r and U r are respectively the r-order current and voltage column vectors corresponding to the r non-grounding ports, and then the formulas (18), (19), and (20) can be obtained.

[0119] Formula (18)

[0120] Formula (19)

[0121] Formula (20)

[0122] Through the above operations, the reduced impedance parameter matrix is obtained, that is, a new r-order matrix Z r .

[0123] In step S404, convert the reduced impedance parameter matrix into a reduced S-parameter matrix.

[0124] Convert the reduced impedance parameter matrix into a reduced S-parameter matrix. The reduced S-parameter matrix is obtained according to formula (21).

[0125] Formula (21)

[0126] where Z0 is the characteristic impedance; Z is the reduced impedance parameter matrix; I is the current; and S is the reduced S-parameter matrix.

[0127] Figure 5 Fig. shows the flowchart of the integrated circuit simulation design method according to an embodiment of the present invention. The reduced ports include at least one of the grounding port, the short-circuit port, and the floating port (the grounding port must be included, and at least one of the short-circuit port and the floating port is included). Obtaining the reduced S-parameter matrix according to the original S-parameter matrix and the reduced ports includes the following steps:

[0128] In step S501, convert the original S-parameter matrix into an admittance parameter matrix;

[0129] Convert the original S-parameter matrix into an admittance parameter matrix. The specific conversion method can refer to the above text.

[0130] In step S502, merge the short-circuit ports and / or delete the floating ports, reduce the expansion matrix of the admittance parameters, and obtain the reduced admittance parameter matrix;

[0131] Merge the short - circuited ports and / or delete the floating ports, reduce the expansion matrix with respect to the admittance parameters, perform the reduction of the short - circuited and / or floating ports, and obtain the reduced admittance parameter matrix. The specific reduction method can refer to the above text. It should be noted that when the reduced ports only include short - circuited ports or floating ports, only the short - circuited ports or floating ports are reduced. When the reduced ports include both short - circuited ports and floating ports, both the short - circuited ports and floating ports need to be reduced.

[0132] In step S503, convert the reduced admittance parameter matrix into an impedance parameter matrix;

[0133] Convert the reduced admittance parameter matrix into an impedance parameter matrix. The conversion formula is as shown in formula (22).

[0134] Formula (22)

[0135] where Z is the impedance parameter matrix; Y is the admittance parameter matrix.

[0136] In step S504, delete the grounded ports, reduce the expansion matrix with respect to the impedance parameters, and obtain the reduced impedance parameter matrix;

[0137] Delete the grounded ports, reduce the expansion matrix with respect to the impedance parameters, and obtain the reduced impedance parameter matrix. The specific reduction method can refer to the above text.

[0138] In step S505, convert the reduced impedance parameter matrix into a reduced S - parameter matrix.

[0139] Convert the reduced impedance parameter matrix into a reduced S - parameter matrix. The specific reduction method can refer to the above text.

[0140] Figure 6 The method flow chart of the integrated circuit simulation design method according to the embodiment of the present invention is shown. The reduced ports include short - circuited ports and floating ports. Obtaining the reduced S - parameter matrix according to the original S - parameter matrix and the reduced ports includes the following steps:

[0141] Step S601: Obtain the number of ports of the short - circuited ports; obtain the number of ports of the floating ports;

[0142] Respectively obtain the number of ports of the short - circuited ports and the floating ports.

[0143] Step S602: Compare the number of ports of the short - circuited ports with the number of ports of the floating ports;

[0144] Compare the number of ports of the short - circuited ports with the number of ports of the floating ports.

[0145] Step S603: When the number of short - circuited ports is greater than or equal to the number of floating ports, first reduce the short - circuited ports and then reduce the floating ports; when the number of short - circuited ports is less than the number of floating ports, first reduce the floating ports and then reduce the short - circuited ports.

[0146] When the number of short - circuited ports is greater than or equal to (greater than) the number of floating ports, first reduce the short - circuited ports and then reduce the floating ports; when the number of short - circuited ports is less than (less than or equal to) the number of floating ports, first reduce the floating ports and then reduce the short - circuited ports. Specifically, taking the case where the number of short - circuited ports is greater than the number of floating ports as an example, after converting the original S - parameter matrix into an admittance - parameter matrix, first merge the short - circuited ports, reduce the expanded matrix of the admittance parameters to obtain an intermediate reduced admittance - parameter matrix; then delete the floating ports and reduce the intermediate reduced admittance - parameter matrix to obtain a reduced admittance - parameter matrix.

[0147] Figure 7 The method flow chart of the integrated - circuit simulation design method according to an embodiment of the present invention is shown. As Figure 7 shown, the integrated - circuit simulation design method according to an embodiment of the present invention includes the following steps:

[0148] In step S701, read the snp file to obtain the original S - parameter matrix;

[0149] Read the snp file to obtain the original S - parameter matrix.

[0150] In step S702, determine whether there is a grounded port;

[0151] Determine whether there is a grounded port. If there is a grounded port, execute step S703; if there is no grounded port, execute step S707.

[0152] If there is a grounded port, perform the following steps:

[0153] In step S703, convert the original S - parameter matrix into a Z - parameter matrix;

[0154] Convert the original S - parameter matrix into a Z - parameter matrix. The conversion method can refer to that described above.

[0155] In step S704, reduce according to the input grounded port;

[0156] Reduce according to the input grounded port. The reduction method can refer to that described above.

[0157] In step S705, convert the reduced Z - parameter matrix into a reduced S - parameter matrix;

[0158] Convert the reduced Z-parameter matrix into a reduced S-parameter matrix. The conversion method can be referred to the foregoing description.

[0159] In step S706, write the reduced S-parameter matrix into an snp file and save it.

[0160] Write the reduced S-parameter matrix into an snp file and save it. The specific method can be referred to the foregoing description.

[0161] In the case of no grounded port, perform the following steps:

[0162] In step S707, convert the original S-parameter matrix into a Y-parameter matrix;

[0163] Convert the original S-parameter matrix into a Y-parameter matrix. The conversion method can be referred to the foregoing description.

[0164] In step S708, determine whether there is a floating port;

[0165] Determine whether there is a floating port. In the case of having a floating port, perform step S709; in the case of no floating port, perform step S711.

[0166] In the case of having a floating port, perform the following steps:

[0167] In step S709, reduce according to the input floating port;

[0168] Reduce according to the input floating port. The reduction method can be referred to the foregoing description.

[0169] In step S710, convert the reduced Y-parameter into a reduced S-parameter matrix;

[0170] Convert the reduced Y-parameter into a reduced S-parameter matrix. The reduction method can be referred to the foregoing description.

[0171] In step S706, write the reduced S-parameter matrix into an snp file and save it.

[0172] Write the reduced S-parameter matrix into an snp file and save it. The specific method can be referred to the foregoing description.

[0173] In the case of no floating port, perform the following steps:

[0174] In step S711, reduce according to the input shorted port;

[0175] Reduce according to the input shorted port. The reduction method can be referred to the foregoing description.

[0176] In step S710, convert the reduced Y-parameter into a reduced S-parameter matrix;

[0177] Convert the reduced Y-parameters to a reduced S-parameter matrix. The reduction method can be referred to the foregoing description.

[0178] In step S706, write the reduced S-parameter matrix into an snp file and save it.

[0179] Write the reduced S-parameter matrix into an snp file and save it. The specific method can be referred to the foregoing description.

[0180] In a specific embodiment of the present invention, for an original S-parameter matrix with 44 ports and 601 frequencies, the port conditions and reduction conditions are shown in Table 1 below.

[0181] Table 1

[0182] Port Condition Simulation Time (s) Original S-parameter Matrix Reduced S-parameter Matrix 39 Ports Floating 16 3 39 Ports Grounded 18 2 30 Ports Short-circuited in Pairs 15 8

[0183] For an original S-parameter matrix with 64 ports and 401 frequencies, the port conditions and reduction conditions are shown in Table 2 below.

[0184] Table 2

[0185] Port Condition Simulation Time (s) Original S-parameter Matrix Reduced S-parameter Matrix 59 Ports Floating 29 2 59 Ports Grounded 23 1 50 Ports Short-circuited in Pairs 30 14

[0186] In a specific embodiment of the present invention, it includes the following specific implementation steps:

[0187] Step 1: Read the touchstone file and convert the file in snp format to an original S-parameter matrix.

[0188] Step 2: Input the positions of the shorted, floating or grounded ports.

[0189] Step 3: Convert the S-parameter matrix to a Y- or Z-parameter matrix. For the cases of shorting and floating, convert the S-parameter matrix to a Y-parameter matrix. For the case of grounding, convert the S-parameter matrix to a Z-parameter matrix. If there are both grounded and shorted or floating ports at the same time, the latter should be considered first, that is, first convert the S-parameter matrix to a Y-parameter matrix.

[0190] Step 4: Perform the reduction operation. If there are both shorted and floating ports at the same time, reduce the Y-parameter matrix successively. If there are ports in all three cases at the same time, after reducing the shorted and floating ports, directly convert the obtained Y-parameter matrix to a Z-parameter matrix to perform the reduction of the grounded ports.

[0191] Step 5: Convert the reduced Y- or Z-parameter matrix back to an S-parameter matrix. If there are both shorted and floating ports at the same time, reduce both types of ports and then convert the matrix back to an S-parameter matrix.

[0192] Step 6: Write the new S-parameter matrix into a new snp file and save it.

[0193] According to the integrated circuit simulation design method of an embodiment of the present invention, the reduced S-parameter matrix has the performance of the original S-parameter matrix, that is, the obtained fewer-port S-parameter matrix can be used to characterize the original circuit network relationship, and the reduction operation will not change the matrix behavior of the original S-parameter matrix; the number of ports of the reduced S-parameter matrix is less than that of the original S-parameter matrix, and the scale of the S-parameter matrix will be reduced. For the original S-parameter matrix with a large number of ports, a large scale, and a large number of short-circuited, floating, or grounded ports, after reduction by the present invention, a relatively small-scale S-parameter matrix is obtained. Using this small-scale S-parameter matrix will greatly reduce the storage capacity and improve the efficiency of subsequent work. When using alps for transient simulation experiments, it can be seen that the simulation time is reduced by more than half:

[0194] Figure 8 The structural schematic diagram of the integrated circuit simulation design device according to an embodiment of the present invention is shown. As Figure 8 shown, the integrated circuit simulation design device according to an embodiment of the present invention includes an acquisition module 10, a reduction module 20, and a simulation module 30. The integrated circuit simulation design device according to an embodiment of the present invention is, for example, used to implement the above-mentioned integrated circuit simulation design method.

[0195] Specifically, the acquisition module 10 is used to acquire the port network represented by the original S-parameter matrix.

[0196] The reduction module 20 is used to perform reduction processing on the original S-parameter matrix to obtain a reduced S-parameter matrix. Specifically, the reduction module 20 obtains the reduced S-parameter matrix according to the original S-parameter matrix and the reduced ports. The reduced ports include at least one of short-circuited ports, floating ports, and grounded ports.

[0197] The simulation module 30 is used to perform simulation design according to the reduced S-parameter matrix.

[0198] In an optional implementation of the present invention, the reduction module 20 includes a conversion unit and a reduction element. The conversion unit is used to convert the original S-parameter matrix into admittance parameters or impedance parameters. The reduction element is used to reduce the admittance parameters or impedance parameters to obtain an intermediate parameter matrix. The conversion unit is also used to convert the intermediate parameter matrix into a reduced S-parameter matrix. Optionally, the reduction element includes a sorting sub-unit. The sorting sub-unit is used to re-arrange multiple floating ports when there are multiple floating ports, with the floating ports arranged in ascending order behind the matrix, and the remaining ports arranged in ascending order in front of the matrix; and / or used to re-arrange multiple grounded ports when there are multiple grounded ports, with the grounded ports arranged in ascending order behind the matrix, and the remaining ports arranged in ascending order in front of the matrix

[0199] In an alternative embodiment of the present invention, the reduction module includes a judgment unit. The judgment unit is used to judge whether the reduction ports include a ground port and / or a short - circuit port and / or a floating port. When there is at least one of a ground port, a short - circuit port and a floating port simultaneously, the reduction module first reduces the short - circuit port and / or the floating port, and then reduces the ground port.

[0200] In an alternative embodiment of the present invention, the reduction module includes a comparison unit. The comparison unit is used to compare the number of short - circuit ports and the number of floating ports. When the number of short - circuit ports is greater than or equal to the number of floating ports, the reduction module first reduces the short - circuit ports and then reduces the floating ports; when the number of short - circuit ports is less than the number of floating ports, the reduction module first reduces the floating ports and then reduces the short - circuit ports.

[0201] Figure 9 The structural schematic diagram of a computing device according to an embodiment of the present invention is shown. Referring to Figure 9 , the present disclosure also presents a block diagram of an exemplary computing device suitable for implementing the embodiments of the present disclosure. It should be understood that Figure 9 the shown computing device is merely an example and should not impose any limitation on the functions and usage scope of the embodiments of the present disclosure.

[0202] As Figure 9 shown, the computing device 200 is presented in the form of a general - purpose computing device. The components of the computing device 200 may include, but are not limited to: one or more processors or processing units 210, a memory 220, and a bus 201 connecting different system components (including the memory 220 and the processing unit 210).

[0203] The bus 201 represents one or more of several types of bus structures, including a memory bus or a memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus structures. For example, these architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

[0204] The computing device 200 typically includes a variety of computer - system - readable media. These media can be any available media that can be accessed by the computing device 200, including volatile and non - volatile media, removable and non - removable media.

[0205] System memory 220 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 221 and / or cache memory 222. Computing device 200 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 223 may be used for reading and writing on non-removable, non-volatile magnetic media ( Figure 9 not shown, commonly referred to as a "hard disk drive"). Although Figure 9 not shown in [reference], a disk drive for reading and writing on removable non-volatile disks (such as "floppy disks") and an optical disk drive for reading and writing on removable non-volatile optical disks (such as CD-ROM, DVD-ROM or other optical media) may be provided. In these cases, each drive may be connected to bus 201 through one or more data media interfaces. Memory 220 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present disclosure.

[0206] A program / utility 224 having a set (at least one) of program modules 2241 may be stored, for example, in memory 220. Such program modules 2241 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 2241 generally perform the functions and / or methods described in the embodiments of the present disclosure.

[0207] Furthermore, computing device 200 may also be communicatively connected to a display 300 for displaying the filtered and sorted results. The display 300 may include, but is not limited to, a liquid crystal display (LCD), a light emitting diode (LED) display, and a plasma display. In some embodiments, the display 300 may also be a touch screen.

[0208] Further, the computing device 200 may also communicate with one or more devices that enable a user to interact with the computing device 200, and / or communicate with any device that enables the computing device 200 to communicate with one or more other computing devices (such as a network card, a modem, etc.). Such communication may be performed through the input / output (I / O) interface 230. Also, the computing device 200 may communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through the network adapter 240. As shown in the figure, the network adapter 240 communicates with other modules of the computing device 200 through the bus 201. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the computing device 200, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0209] The processing unit 210 executes various functional applications and data processing by running programs stored in the system memory 220.

[0210] According to another aspect of the present invention, there is provided a computer-readable storage medium having stored thereon a computer program (or computer-executable instructions), which when executed by a processor is used to execute the integrated circuit simulation design device provided by the embodiments of the present disclosure. The method includes:

[0211] Using the original S-parameter matrix to represent the port network;

[0212] Performing reduction processing on the original S-parameter matrix to obtain a reduced S-parameter matrix;

[0213] Performing simulation design according to the reduced S-parameter matrix,

[0214] wherein, the reduction processing includes:

[0215] Obtaining the reduced S-parameter matrix according to the original S-parameter matrix and the reduced ports,

[0216] wherein, the reduced ports include at least one of a shorted port, a floating port, and a grounded port.

[0217] The computer storage medium of the embodiments of the present disclosure may adopt any combination of one or more computer-readable media. The computer-readable media may be computer-readable signal media or computer-readable storage media. The computer-readable storage media may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (a non-exhaustive list) of the computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, the computer-readable storage media may be any tangible medium that contains or stores a program, and the program may be used by or in combination with an instruction execution system, apparatus, or device.

[0218] The computer-readable signal media may include data signals propagated in a baseband or as part of a carrier wave, which carry computer-readable program codes. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal media may also be any computer-readable media other than the computer-readable storage media, and the computer-readable media may send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device.

[0219] The program codes contained on the computer-readable media may be transmitted by any appropriate media, including but not limited to wireless, wire, optical fiber, RF, etc., or any suitable combination of the above.

[0220] The computer program codes for performing the operations of the embodiments of the present disclosure may be written in one or more programming languages or combinations thereof. The programming languages include object-oriented programming languages (such as Java, Smalltalk, C++), and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program codes may be executed entirely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or computing device. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network - including a local area network (LAN) or a wide area network (WAN) - or may be connected to an external computer (for example, by using an Internet service provider to connect through the Internet).

[0221] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising said element.

[0222] As described above in the embodiments of the present invention, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. These embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modified use based on the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. An integrated circuit simulation design method, characterized in that, Including: Using the original S-parameter matrix to represent the port network; Performing reduction processing on the original S-parameter matrix to obtain a reduced S-parameter matrix; Performing simulation design according to the reduced S-parameter matrix, wherein the reduction processing includes: Obtaining the reduced S-parameter matrix according to the original S-parameter matrix and the reduced ports, wherein the reduced ports include at least one of a shorted port, a floating port, and a grounded port; The obtaining the reduced S-parameter matrix according to the original S-parameter matrix and the reduced ports includes: Converting the original S-parameter matrix into an admittance parameter matrix; Merging the shorted port and / or deleting the floating port, reducing the expansion matrix with respect to the admittance parameters to obtain a reduced admittance parameter matrix; Converting the reduced admittance parameter matrix into an impedance parameter matrix; Deleting the grounded port, reducing the expansion matrix with respect to the impedance parameters to obtain a reduced impedance parameter matrix; and Converting the reduced impedance parameter matrix into a reduced S-parameter matrix.

2. The integrated circuit simulation design method according to claim 1, characterized in that, The obtaining the reduced S-parameter matrix according to the original S-parameter matrix and the reduced ports includes: Converting the original S-parameter matrix into admittance parameters or impedance parameters; Reducing the admittance parameters or the impedance parameters to obtain an intermediate parameter matrix; and Converting the intermediate parameter matrix into the reduced S-parameter matrix.

3. The integrated circuit simulation design method according to claim 1, characterized in that, The using the original S-parameter matrix to represent the port network includes: Reading a multi-port snp file and converting the multi-port snp file into the original S-parameter matrix; The integrated circuit simulation design method further includes: Converting the reduced S-parameter matrix into an snp file.

4. The integrated circuit simulation design method according to claim 1, characterized in that, The reduced port is a shorted port; the obtaining the reduced S-parameter matrix according to the original S-parameter matrix and the reduced ports includes: Converting the original S-parameter matrix into an admittance parameter matrix; Obtaining the port network relationship with respect to the admittance parameters and obtaining the expansion matrix with respect to the admittance parameters; Merging the shorted port, reducing the expansion matrix with respect to the admittance parameters to obtain a reduced admittance parameter matrix; and Converting the reduced admittance parameter matrix into the reduced S-parameter matrix.

5. The integrated circuit simulation design method according to claim 1, characterized in that, The reduced port is a floating port; the obtaining the reduced S-parameter matrix according to the original S-parameter matrix and the reduced ports includes: Converting the original S-parameter matrix into an admittance parameter matrix; Obtaining the port network relationship with respect to the admittance parameters and obtaining the expansion matrix with respect to the admittance parameters; Deleting the floating port, reducing the expansion matrix with respect to the admittance parameters to obtain a reduced admittance parameter matrix; and Converting the reduced admittance parameter matrix into the reduced S-parameter matrix.

6. The integrated circuit simulation design method according to claim 5, characterized in that, There are multiple floating ports; in the expansion matrix with respect to the admittance parameters, the multiple floating ports are rearranged, the floating ports are sorted in ascending order at the back of the matrix, and the remaining ports are sorted in ascending order at the front of the matrix.

7. The integrated circuit simulation design method according to claim 1, wherein The reduced port is a grounded port; the obtaining the reduced S-parameter matrix according to the original S-parameter matrix and the reduced ports includes: Converting the original S-parameter matrix into an impedance parameter matrix; Obtain the port network relationship regarding the impedance parameters and obtain the expansion matrix regarding the impedance parameters; Delete the grounded ports, reduce the expansion matrix regarding the impedance parameters, and obtain the reduced impedance parameter matrix; and Convert the reduced impedance parameter matrix into the reduced S-parameter matrix.

8. The integrated circuit simulation design method according to claim 7, wherein There are multiple grounded ports; in the expansion matrix regarding the impedance parameters, the multiple grounded ports are rearranged, the grounded ports are arranged in ascending order at the back of the matrix, and the remaining ports are arranged in ascending order in front of the matrix.

9. The integrated circuit simulation design method according to claim 1, wherein The reduced ports include shorted ports and floating ports: obtaining the reduced S-parameter matrix according to the original S-parameter matrix and the reduced ports includes: Obtain the number of ports of the shorted ports; Obtain the number of ports of the floating ports; Compare the number of ports of the shorted ports and the number of ports of the floating ports; and When the number of ports of the shorted ports is greater than or equal to the number of ports of the floating ports, first reduce the shorted ports and then reduce the floating ports; when the number of ports of the shorted ports is less than the number of ports of the floating ports, first reduce the floating ports and then reduce the shorted ports.

10. An integrated circuit simulation design device, wherein Includes: An acquisition module for acquiring the port network represented by the original S-parameter matrix; A reduction module for performing reduction processing on the original S-parameter matrix to obtain a reduced S-parameter matrix; And A simulation module for performing simulation design according to the reduced S-parameter matrix, wherein the reduction module obtains the reduced S-parameter matrix according to the original S-parameter matrix and the reduced ports; The reduced ports include at least one of shorted ports, floating ports, and grounded ports; Obtaining the reduced S-parameter matrix according to the original S-parameter matrix and the reduced ports includes: Convert the original S-parameter matrix into an admittance parameter matrix; Combine the shorted ports and / or delete the floating ports, reduce the expansion matrix regarding the admittance parameters, and obtain the reduced admittance parameter matrix; Convert the reduced admittance parameter matrix into an impedance parameter matrix; Delete the grounded ports, reduce the expansion matrix regarding the impedance parameters, and obtain the reduced impedance parameter matrix; and Convert the reduced impedance parameter matrix into a reduced S-parameter matrix.

11. The integrated circuit simulation design device according to claim 10, wherein The reduction module includes: A conversion unit for converting the original S-parameter matrix into admittance parameters or impedance parameters; and A reduction element for reducing the admittance parameters or the impedance parameters to obtain an intermediate parameter matrix, wherein the conversion unit is further used to convert the intermediate parameter matrix into the reduced S-parameter matrix.

12. The integrated circuit simulation design device according to claim 11, wherein The reduction element includes: A sorting sub-unit for rearranging the multiple floating ports when there are multiple floating ports, arranging the floating ports in ascending order at the back of the matrix, and arranging the remaining ports in ascending order in front of the matrix; and / or For rearranging the multiple grounded ports when there are multiple grounded ports, arranging the grounded ports in ascending order at the back of the matrix, and arranging the remaining ports in ascending order in front of the matrix.

13. The integrated circuit simulation design device according to claim 10, whereinThe reduction module includes: A judging unit, configured to judge whether the reduction port includes the grounding port and / or the shorting port and / or the floating port. Wherein, when at least one of the grounding port, the shorting port, and the floating port exists simultaneously, the reduction module first reduces the shorting port and / or the floating port, and then reduces the grounding port.

14. The integrated circuit simulation design device according to claim 10, wherein, The reduction module includes: A comparing unit, configured to compare the number of ports of the shorting port and the number of ports of the floating port. Wherein, when the number of ports of the shorting port is greater than or equal to the number of ports of the floating port, the reduction module first reduces the shorting port and then reduces the floating port; when the number of ports of the shorting port is less than the number of ports of the floating port, the reduction module first reduces the floating port and then reduces the shorting port.

15. A computing device, wherein, Comprising: A processor; A memory, configured to store one or more programs. Wherein, when the one or more programs are executed by the processor, the processor implements the integrated circuit simulation design method according to any one of claims 1 to 9.

16. A computer-readable storage medium having a computer program stored thereon, wherein, When the program is executed by the processor, it implements the integrated circuit simulation design method according to any one of claims 1 to 9.

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